KENWOOD ~ SERVICE MANUAL TS-Ma0S RRS HF TRANSCEIVER CONTENTS SPECIFICATIONS 2 PACKING 88 CIRCUIT DESCRIPTION 4 ADJUSTMENT.......... . . . a 89 SEMICONDUCTORS 27° LEVEL DIAGRAM 101 PARTS LIST oun 35 BLOCK DIAGRAM 103 PC BOARD SCHEMATIC DIAGRAM OPTION SWITCH UNIT 69 PS-50 sssstnntuniniienianenees 10M FILTER UNIT .csssstsstsnseseese 70, 71 8-430 109 PLL UNIT 72,73 vst et RF UNIT ssc secne 78, 1S $P-A30 vtsstnmtnstntentesienenseeens WA, CONTROL UNIT .ssssnennienesests 78, 77 MB-430 114 DISPLAY UNIT. ssssssestsstsestes 76, 77 AT-440 114 FINAL UNIT 78 YK-88S/SN 114 iF UNIT 78,79 YK-B8C/CN eer th) AT UNIT vssrcnniannntannennannnnenne 80 SCHEMATIC DIAGRAM 113 DISASSEMBLY «.....:cssssessseesstessnennnteesseeis BF15-4408 (GENERAL) Transmitter frequency range: Receive frequency range: Mode: Antenna impedance: Power requirement: Power consumption: RX no signal input: v Frequency configuration: RX unit TX unit: (A1,A3J,A3,FSK) (F3) Semiconductors: Dimensions: (TRANSMITTER) Ratead final power input: Carrier supression: Unwanted sidebande supression: content: ‘Maximum frequency ‘Microphone impedance: SPECIFICATIONS 160m BAND 1.8 ~ 2 0MH2 80m BAND 3.5 ~ 4 0MHz 40m BAND 7.0 ~ 7.3MHz 30m BAND" 10,1 ~ 10.16MH2 20m BAND 14.0 ~ 14.35MH2 17m BAND 18.068 ~ 18.168MHz 18m BAND 21.0 ~ 21.45MHz 12m BAND 24.89 ~ 24.99MHe 10m BAND 28.0 ~ 29.7MHz 100kH2 ~ 3OMHe ANICW), A3JISSB), ASIAMD, FIIFSK), F3(FM) 80 Ohm (TX: 20-150 Ohm with AT) 12.0 ~ 16.0V DC Approx. 1.9 Approx. 208 1st IF 45,05MHz, 2nd IF 8.83MHz, 3rd IF 455kH2 1st IF 455kH2, 2nd IF 8.83MH2, 3rd IF 45.06MH2. 1st IF 36.22MMz, 2nd IF 45,05MH2 CW, SSB, AM, FSK, FM Triple conversion superheterodyne FM: Double conversion superheterodyne 75-4408 TS-4408 (with AT) 187 174 22 22 49 58 287 277 TS-440S TS-4405 (with ATI Wimmi 270 (279) 270 (279) Himm) 96 (708) 96 108) Dim) 313 (335) 313 (335) Weightikgh 63 73 The numbers in the parenthesis include protections [Band ——M02*] a ay, FF Ay 1.8~28 MHz _| 200 W PEP 110 w PEP. More than 4048, More than 5048 Less than — 4048 400 ~ 2600He (648) a bkHe 8000 ~ 50013-4405 (RECEIVER) ‘Sensitivity: Frea, ey 100 ~ 150kHz | 150 ~ S00KH2 | 0.5 ~ 1.6MHz.| 1.6 ~ 30MHz SSB,CW.FSK_ Less than Less than| Less than ‘Less than (SINi048) 2.5uV (8c8y) 1u¥ (048, 4uV (12dBh 0.254 (~ 12084) Less than Less than Less than ‘Less than AM SINTOGB) | sev 128dBu) | 134 (2248n) | 40KV (3248))__| 2.54 184341 ‘Less than FM (1208 SINADI - - = peTV=aten ‘Squelch sensitivity: (Threshold) Fre, 01 50 ~ 5 a 100 ~ 150kHz | 150 ~ S0oKH2 | 0.5 ~16MHz | 1.6 ~ 30MHz esx. | L258 than ‘Less than Less than Less than SSB.CWAMFSK | ooyv (26480) | TOnV (2048) | 20xV (26dBy1__| 2a (6dB) Less than mu ~ 0.32aV (= 1008) Image ratio: 50dB or more [100kH2 ~ 1.6MH2) 70dB or more 1.6 ~ 30MH2) '50d8 or more {FM 3rd image ratio) F rejection: 5048 or more {100kH2 ~ 1.6MHz) 7048 or more |1.6MHz ~ 30MH2) Selectivity: ha 608, 6008 SB,CW.FSK | More than 2kHz Less than 4.4K AM More than 4kHe Less than 18kH2 (— 5008) FM More than 12kH2 Less than 25kH2 (— 5048) FF SHIFT variable ran £0.9kH2 oF more RIT/XIT variable range: 2 TikH2 or more ‘Audio output power: 1.5W oF more {with 88 load, 10% distortion) ‘Audio output impedance 4 ~ 160 (Speaker and headphone! (FREQUENCY STABILITY) Frequency accuracy: (RIT/XIT OFF) More than £10 x 10% Frequency stability: More than 410 x 10* {10°C to 50°C! (RIT/XIT OFF: at receive) Reference oscillator frequency: 36MM2 Note: Circuit and ratings subject to change without notice due to developments in technology,TS-4405 CIRCUIT 1. Overview ‘+ The TS-440 is a triple conversion type transceiver, incor porating @ general coverage receiver, which uses 45.05 MHz as the fist IF, 8.83 MHz as the second IF, and 455 kHz as the third IF + The TS-440 is compact, but allows for installation of an ‘optional interna automatic antenna tuner operating in the amateur band from 3.5 MHz to 28 MHz and enables @ ‘wide range of antennas to be used. ‘+ The TS-440 also contains a microprocessor-contrlled dig ital PLL circuit which controls frequency in 10 Hz steps Using a single crystal oscillator to implement high accurs- ‘ey and stable frequency control ‘+ The TS-440 has the following major features: (1) Selectable VFOs; VFO-A and VFO.B (2) Direct frequency input using a numeric keypad (3) 100-channel memory containing frequency band, _and mode information (channel 90 to 9 for spi fro 2. Frequency Elements The TS-440 utilizes a triple conversion transmitter and DESCRIPTION quency memory! Memory scan in 10 channel groups and two types of program scan RTTY (AFSK) mode available Squelch circuit operational in all modes Dual fiters available to improve selectivity and SIN ratio (optional fiter required) IF shift, audio notch, IF filter switching, and RF ATT functions for convenient interference reduction Large heat sink and cooling fan {100 W) enabling up to one-hour continious transmit operation Full and semi break-in circuits for CW External computer controllable (optional interface re. quired) Many easy-to-read meter functions such as the received signal strength (s meter, transmitter power, 'SWR, and ALC level @) 6 6) a ic (9) (10) a 2) sox~ Yee xs rx wxe 283MM RK MKS -SSBHHE sea ost 3 ars inrur Ex free ow. de sic eur veo ner wo secon ers te oie am, Em, FS ru cere (FM MOD) '9.08~75.090m2 auneun > — ewe -48.0792~ 75.0492MH2 AMT,EMT © 458i08 Use.ow :ase.siHe LSO,FSK | 488.50He Fig. 1 Frequency configur The overall frequency configuration of the TS-440is shown in Figure 1. The incoming received signal (fn) 's applied to the ANT terminal. This signal is mixed with the local oscilla tor signal {fyco) iy RX MIX 1 t0 obtain the first IF frequen- cy. This signal is then mixed with the HET Oscillator signal fuer) in RX MIX 2, to obtain the 2nd IF frequency. The resulting signal is then mixed with the second local oscilla tor frequency {fio} to obtain the rd IF frequency. The sig nal is then combined with the CAR signal for detection. fix is expressed mathematically as follows ft = fvo ~ ther — fio ~ fean 118-4405 CIRCUIT DESCRIPTION waa ‘arsessora Fig. 2. PLL frequency configuration ‘As shown in figure 2, all received frequencies excluding the local oscilator frequency f.o are generated in the PLL circuit, The frequencies generated in these loops are expressed as follows: ero fucos _ 4 = dl vcos: 9 Aveo = Bp favo wees 2 i + fucos _ 4 “fs10 _ Kk veos: Meet 4 oo -. Wueot = 7365 foro = 8 i 4 fucos _ 4 151° L veos: Seo = 4 2 feos = 3355 fo 4 tacos + OOP 4 MeO Ty vco2: ae, M 450 M fucoa _ fucos fvcor foro — {econ _ fvcos ‘ 1800 50 20" © feor = ho = fw + MS agg cor: — 10.4 n 8 fucor = 2 fsro + fio + tere ~ “HO? 6 2 "0 Based on these formulas, the frequencies fvco, fuer, and fea are expressed as folows: (se L fvco=fveor= 172 ~ 1800 * 3600000 0000 +) fuer = fucos = 2 fs10 8 i wom tay 72 ~ 180000 * 3600000 ~ 41 * * fsr0 fa received frequency is determined by the reference frequen. Cy fro and frequency division data I to N. Further analysis fof formula 10 shows the following 1) Basically, frequency division data Ito N contain no er- ror because they are controlled by the microproces sor according to the operating frequency. li) The accuracy of the operating frequency is equal to that of the reference frequency, because all frequen: cies other than fsro in formula 10. are determined by the microprocessor. ii) The operating frequency does not change evenit kor fio changes. When f= 14 MHz (USB model in formula 10, fy and fero have the following relationship:TS-4405 CIRCUIT DESCRIPTION 11800, J = 7244, K = 19800, L=9299, M=41 fy = 0.388 foro 4" When fy =30 MHz (USB mode} in formula 10, fw and {exo have the following relationship: 1= 1800, fin 7284, 0.833 fer 19800, L= 3239, M=73 12 Since the precision of the reference crystal oscilator used in the TS-440 is 10 ppm (~ 10 to 50°C) and the receiver systom has the characteristics shown in itomsi) and i, the {otal accuracy is stable at any point from 30 kHz to 30 MHz ‘The maximum amount of frequency shift is only. +/— 300 Hz (see formula 12). The characteristic shown in item i enables variable band functions such as IF shift to be im plemented, using the microprocessor. The microprocessor also is used to set carrier points by adjusting fean, and to set and adjust the amount of IF shift. So far received frequencies in the SSB mode have been dis 3. Receiver Circuit Description cussed. For receive modes other than SSB, and in transmit ‘mode, operating frequency is determined by the reference frequency end frequency division data, In CW receive mode, fyco is shifted down 800H2 and used {8 fico. In AM or FM receive mode, fea generation is stopped. In FM receive mode, fuer is modulated by adding ‘audio signals to VCOS from the microphone. FSK (RTTY) is transmitted in LSB mode and uses AFSK by adding audio sig nals externally The type of frequency displayed differs, depending on the mode, as shown in Table 1 Mode Displayed frequency USB, LSB, FSK | Carrier point frequency ow ‘Transmission cari frequency AM, FM FF filter center frequency Table 1 Displayed frequencies GO 242. aan {}; © OO pes18-4405 CIRCUIT DESCRIPTION Signals from the ANT pin are fed into the RAT pin of the RF Unit via the transmit/eceive switching relay. The signals then go tothe 10 BPFs through the approx. 20 dB attenuator cir cuit, the first stage of the first IF trap circuit, and the low pass fiters (which pass only 5OOkH2z or less). The signal then {goes through the second stage of the first IF trap circuit, and is mixed with the VCO signal and converted into the first IF signal of 45.05 MHz in the first mixer, consisting of 03 and 4 (2SK 126-5). The VCO circuit consists of Q21 to 024 (28C2668Y) and oscilates in four bands from 45.05 MHz to 75.05 MHz. Oscillator frequencies are controlled by DC signals from the PLL unit, The fst IF signal of 45.05 MHe is passed through the MCF (1), which is used in both receive and transmit, and is am plified by the first F amplifier 05 (3SK74l). In the second mixer, consisting of Q6 and Q7 (2SK128), the first IF signal is mixed with the heterodyne oscillator signal (36.22 MHz) from the PLL cicuit, amplified by Q12 (2SC2688Y) to ob: tain the second IF signal (8.83 MHz). The second IF signal of 8.83 MHz goes through the gate of the noise blanker. In ‘modes other than FM, the signal then goes through the MCF {F2) and is fed into the IF unit through butfer amplifiers OB and Q9 (28C2668Y). 1) Selectivity circuit Figure 4 is a selectivity circuit diagram. In auto mode, the ‘appropriata bandwidth filter is automatically selected accord- ing to mode. When an optional filter is used, two fiers are available. Tables 2 and 3 shows the various combinations When the optional 8.83 MH2 fter is connected, the second IF signal is then fed from the IF unit into the optional iter. In the third mixer, consisting of Q1 and Q2 (3SK 73GR), the second IF signal is mixed with 8.375 MHz signal generated by IF unit’s heteradyne oscillator circuit, consisting of Q53 ‘and O54 {28C2458Y), and converted into the third IF signal (455 kHz). The third IF signal is then amplified by 05 (BSK73GR). A diode switch is used to route the signal to either the FM or SSB circuits. In SSB mode, the third IF signal goes through the SSB cer- ‘mic filter XFS), In AM mode, the third IF signal goes through the AM ceramic filter (XF4). In either made, the third IF sig nalis then amplified by Q7 and 8 (3SK73GR) and detected. In FM mode, the third IF signal goes through the FM ceramic, filter (XF5). The signal is then sent to the FM IF, IC2 (MC '3367) for amplification and detection. IC2 also contains an FM noise squelch circuit, ‘The detected SSB/AM signal is passed through the notch ci- cuit, consisting of hybrid IC IC1 (BX6124) and squelch gate 12 (2SC24598L). The signal then goes through the AF volume control and is amplified to the appropriate level by ‘AF amplifier IC7 (UPC2002V). of bandwidth available when optional fters are used. in FM ‘mode, the selectivity switch does not operate and a single dedicated FM fier is used. Optional filters operate only in receive and are separate from the filters used in transmit AUTO SELECTIVITY CONTROL. toon secron Fig. 4 Selectivity control circuit MANUAL SELECTWITY CONTROL.18-4405 CIRCUIT Filter selective DESCRIPTION ‘AUTO MODE MANUAL MODE WITHOUT OPTION | OPTION INSTALLED WITHOUT OPTION | OPTION INSTALLED. ove | aeawiie | s5seHe | 6.eawHe | 4S5KH2 sevect | geamne | assuie | @6amee | 455ure sse_| Through _|_ CF XPT cra mines) Perera xF2 Cal ew | Tivoun | crt xF2 crt mt xP crt ‘am_| twrough | _cF2 | Through | oF? m2_| Tough | Crt | Trough | cra re ce xF2 Gal w | through | _ce2 | thvougn | cr? Fm_| Through | — | Through | — XF1: YK-68S of YK-885N XPT: YK-88S o& YK-88SN XF2: YK-BBC oF YK-BBCN, XF2: YK-B8C oF YK-BBCN Tobe 2 Table 3 Trem Rating Tem Rating [center requency fo 25.05 Me Center Requeney fo a5 ete Center frequency devation [Toa t kHe at 308) 6 a bandwith 2 ee OF MO ss bandwith E06 Kee oF more at 348 40 6B bandnath 75 He or ls {xc20t spurious! Final mpadance 2 k's 10 Ik. characteristic ‘Table 4 MCF (L71-0259-05) (RF UNIT F1) em ating 650 KHaROS eH £3 KH oF mow at 3 GB ‘Genter faqueney fo Pace bandvadth ‘Atervation bandwith “12 ke or oss at 18 6 ‘Guaranteed attenuation | 20 a8 or more within fox. Fipple 0.5 oB or ss nserton os 1.0 68 or oss Fal mpesenee 2.5 ARIS oF Table 6 MCF (L72-0260-05) (RF unit F2) ‘Aitenuation bandidih [£28 Wie or ess a1 10 68 Insertion oss G8 or ss Figg 0.7 a8 or ess Guaranteed attenuation | 35 dB or more carer orearer eed Iouthin 455442 = 100KH2) CGuarenieed attenuation [30 dB or more with a ME Input an output mpesanes [2.0 Mi ‘Table 5 Coramic filter (L72-0355-05) (IF UNIT CF2) Ther Rating 55 Kiet He ‘Genter reaueney fo 6-08 bandwicth 50 8 bandwidth “25 kHe oF more 112.5 eH or less Ripe 3 08 or ese Ivuthin 455 Keak Ke) Insertion los 6 aD or hse (Guaranteed attenuation twuthin 455 wha TOOK 135 Bor more Input and output mpecance [20 a Table 7 Ceramic fiter (L72-0315-06) (IF unit CF3) rem Rating ‘Center frequency 10 465 eeaO.2 Ke oE 6 8 bandwith (otal) 11-13 aie Tem ing 60-48 bandh “4.5 Hie or loss Center frequency fo 830 WHE ‘Guaranteed attenuation | 60-48 or more ‘Ateruation bandwidth 1250 ke or more at 3.68 (at .1=1 Miz) Guaranteed attenuation | 35 dB or more at 9.285 Mi Sourous (600-700 wet | 40 68 or more 45 08 or move at 974 Mie poe with bondveath 2 a or oss 0160 68 insertion 655 5.dl or ess Insertion 1a38| 2a or ess Rieple 1.0 68 or eas Temperate = 10°C +5056 Input and cutput mpedance [330 @ Input and output impedance [2 wf Max. voltage (D0) 50.v din ‘Table 8 Coramic fiter (L72-0356.06) (IF UNIT CF1) ‘Table 9 Ceramic fiter (L72-0351-05) (IF unit CF4)18-4405 CIRCUIT DESCRIPTION 2) AF notch circuit (es lex7io!-asie Le zs we X41-1610-000874) . ar er Fig. 5 NOTCH circuit ‘The hybrid IC1 in the IF unit is an audio notch circuit. Figure 5 shows its equivalent circuit, This cicuit forms state variable bandpass filter, also known as a bi-quad fiter, The notch frequency can be changed using the notch control vari able resistor. Since the circuit consists ofthe hybrid IC, sta ble attenuation characteristics can be obtained electrically and thermally. The range of variable notch frequencies is 400 Hz to 2600 He, The notch frequency is determined by the following two formulas, 1) fue RO 2) RGVA12 +R13)2R10-811 2 Ita variable resistor is used for resistor NOTCH VR, the notch fraqueney can be controlled according to formula 1), The notch frequency range is from 400 to 2600 Hz, and at- ‘enuation is from 25 to 50 dB.TS-4408 10 CIRCUIT DESCRIPTION 3. Transmitter Circuit Descrip' ca 044 mic yretisana gop SERS ASS CEL aan cra MAIC AMP) MCF PROC 146 ou 915,14 f os SG ri sete ate LPF LPF Fig. 6 Transmitter ci In $SB, CW, AM, or FSK mode, the transmitter system uses triple conversion. In FM mode, the transmitter system uses double conversion using PLL modulation ‘Audio signals from the microphone are applied to the MIC pin (connector (21) of the IF unit and are separated into SSB ‘modulation and VOX signals. The SSB signal is amplified ap prox. 8 dB by IC4 yPC1158HZ). AFSK audio signals from the AFSK IN pin (back panel) are also applied to IC4. it configuration IC4 functions as a SPEECH processor. Output from ICé is distributed to the MIC GAIN control (front panell and FM ci cuit (RF unit). In SSB mode, the signal applied to the MIC GAIN controls sent back to the IF unt (connector (23) MV2), amplified by Q44 (2SC2459), and supplied to the balanced modulator IC5 (AN12). In FM or CW mode, Q44 does not ‘operate because a cut-off voltage is supplied to its emitter via diodes 082 and D46. The signal converted to 455 kHzTS-4405 CIRCUIT DESCRIPTION DSB by IC4 goes through the SSB transmit switching diodes 117 and D18, filter switching diodes D 14 and D 12, and SSB ‘ceramic filter CF 1, to obtain the SSB signal. The SSB signal then goes through the transmit switching diode D36 and is {ed into the transmit first mixer, IC6, where the SSB signal is mixed with the output from the 8.375 MHz oscillator in the F unit, and converted to 8.83 MHz. In CW or FM mode, ‘the carter signal from the PLL unit does not go through IC5 BM oF the 455 kHe filter. These carrior signale are applied 10 IC6 via switching diodes D53 and 054, The output signal {rom IC6 goes through the MCF to remove spurious compo: rents, and is amplified by the IF amplifier 046 (3SK73) and sent to the RF unit. Q46 provides ALC control and CW keying Inthe transmitter second mixer, consisting of 11 and 012, (GSK 122), the 8.83 MHe transmit IF signal input to the RF Unit is mixed with HET oscillator signal (36.22 MHz} from th PLL unit and converted to 45,08 MH2 signals, The 45.05 MHz signal goes through 023 and the MCF to remove any spurious components, The 45.05 MHz signal then goes through D27 and is supplied to the transmit third mixer con sisting of 13 and Q 14 (3SK122). In the third mixer the sig ral is mixed with VCO signal (021 t0 024) amplified by 12 (28C2668) and converted to the required transmit frequen cy (1.8 t0 29.7 MH). The signal from the third mixer goes through the low pass filters C156, C158, C159, and L89, and is amplified by the wide band amplifier Q18 (28C2670}. ‘The signal then goes through the wide band transformer T19 and low pass fiters C164, C165, and L9O, and is further am plified by wide band amplifier 016 (28C2538). The signal from the Q16 goes through the output trensformer T20 end is used as the drive output. In FM mode, the PLL VCO is directly modulated. The audio signal from IF unit IC4 (UPC 1158H2_ is fed into the RF unit Via the FMI pin. lo the RF unit, the audio signal is amplified by 036 (28C2459} and 037 (28C2603}, and goes through the limiter circuit consisting of 038 (UPC4558C) and low pass fiter circuit, and is sent to the PLL unit via the FMD pin, Inthe PLL unit, the 36.22 MHz VCO is modulated. 039 (28C2603) is a switching circuit to prevent the modulated signals from being emitted from the PLL unit in a made other than FM. For "'S"" model radios the output from the RF unit is ‘amplified to a 100 W power level by Q1 (2SC2075), 2 and Q3 (2SC2509), and Q4 and QS (2SC2879) in the final unit. The 100 W output goes through the LPFs which differ by bands, and is sent 2s output to the antenna via the AT unit and transmitireceive switching relay. SWR and ALC detection is performed at the output of the LPFS. 1) Antenna tuner ‘The antenna tuner operates when the AUTO/THRU switch isin the AUTO position and the AT TUNE switch is ON. The ‘antenna tuneris driven in the CW mode and power is reduced to 50 W by the microcomputer regardless of the mode select fed before the AT TUNE switch was turned ON. The range of operating frequencies is determined by a microcomputer program, and is from 3.5 MHz to 30 MHz, ‘+ AT unit operation Power transmitted by the final unit passes through the cur rent and voltage detecting transformers L1 and L2 using toroidal cores. Current and voltage components detected by the transformers are supplied to pins 9 and 13 of ICZ for wave shaping and their phases are compared by IC3 010131. The output from pin 3 of IC3 depends upon the phase of the voltage and current waveforms applied 10 IC3. The signal from IC3 pin 3 is sent to pins 10 and 16 of buffer IC IC3 HD10125. Output from pins 12 and 13 of IC3 goes through level shift Zener diodes D5 and DB to control the input circuit of motor drive IC ICS BA6109U2. The output signal is used to drive moter MT to adjust the variable capacitor VC1 so that the phase difference between voltage and current components is reduced ‘The current and voltage components output from the cur rent and voltage detecting transformers is also supplied to the voltage comparator IC1 NJM29020. The compa: rator output is used by motor drive IC IC6 BAG109U2 to drive motor M2 to adjust variable capacitor VC2 so that the amplitude difference is reduced. That is, the phase con- trol variable capacitor VC1 is controlled so that the cur- rent isin phase with the voltage and the voltage control variable capacitor VC2 is controled so that the amount of amplitude difference between the current and voltage is reduced (SWR1, an SWR of 1 to 1, is obtained when the current and voltage are in phase and the amount of amplitude difference is 0). VC1 and VC2 are designed to ‘operate independently of each other, but since phase difference affects the amount of amplitude difference and vice versa, VC1 and VC2 will normally rotate together Forward and reflected waves detected by the filter unit are Converted to SWR control signals in the SWR arithmetic cir cuit in the control unit and are sent to the ISW pin of the AT unit. Since the SWR control signals ae current wave- forms, the signals are converted from | to V waveforms by CB [b/4) in the AT unit andto obtain the corresponding vol- tage mode SWR signals are generated. The SWA signals are then fed into the SWR comparator ICB (C/), The reference voltage pin 9 of the ICB [C/4) is supplied with a voltage cor responding to an SWR of 1.25 to 1 via a potentiometer. Therefore, when the actual SWR value exceeds 1.25, pin 8 of SWR comparator ICB (C/A) is H, s0 the motor drive vol ‘age control transistor Q5 turns on and the collector of 04 is supplied with voltage from pin 14S. The voltage is also Used to turn the tuning LED on. The inverted input pin of CB (d/4) is supplied with triangular waves generated by IC7, and its non-inverted input pinis supplied withthe above SWR vo ‘tage signals. As a result, as SWR lowers, IC8 (4/4) outputsTS-4405 12 CIRCUIT DESCRIPTION ‘waves changing from continuous waves to relatively low duty pulses. Q1 is driven by this voltage waveform to control Q2, Which is connected to the collector of 4 in series and mo. tor drive voltage is generated If the motor turns too fast, the SWR value will be smaller than the motor stop value because of the inertia of the mo: tor. As a result, the motor will continue to operate even if ‘the motor stop signal is sent and the SWR value will con- tinue to be greater than the motor stop value, causing the ‘motor stop signal to turn off. That is, the motor will not stop and it wil be difficult to obtain a match. If the motor speed is too stow, it will tke along time to satisty a matching con: dition, The TS-840 therefore controls the motor speed ac cording to changes in SWR, THES] ice 05 on on one Bat me wc ca v/a i isw 0 vsw wv Motor drive voiteg - (eae, ar 04 on Pann, +8 7 -, at NN Fig. 7. Antenna tun The antenna coupler is a T type. Six relays RL100 to RL105 ‘are used to change taps within the range 3.5 MHz to 30 MHz. 2) Cooling fan circuit ‘The final unit contains the temperature-sensitive thermistor THI thermally coupled with final transistor Q4. When tem: perature onthe surface of O4 reaches approx. 50°C, the fan start comparator QB operates (H level, causing Q8 to turn Con to operate the fan. During operation ofthe fan, tempera ture protection comparator QA i at a L level, 80 the tem: perature protection circuit does not operate. When temperature on the surface of @4 goes down to 45°C, the cooling fan turns off Fig. 8 temperature protection operation circuit ‘+ Final temperature protection circuit When the temperature of the final transistor Q4 rises up to approx. 80°C, the temperature protection comparator 9A turns on (H level), 1 in the filter unit aso turns on, ‘and a minus DC voltage is supplied to the ALC line, reduc: ing the transmitter output to zero. (The TS-440 does not return to a receive state.) When the temperature of the final transistor (4 falls to approx. 70°C, the protection Circuits turns off allowing the trensmitter to operate again + SWR protection circuit When antenna VSWR is bad, or the reflected wave is too large, because the auto antenna is tuning for example, L42 ‘and L43 detect the state and its output is rectified. The rectified signal is then amplified by Q2 to control the ALC voltage so that drive power is reduced. As a result, load fn the final unit is reduced. + SWR automatic arithmetic circuit ‘The TS-440 uses the automatic arithmetic circuit in the AT-250, The forward wave voltage Ysr and reflected wave voltage Van from the fier unit are fed into the ana log arithmetic circuit of the switch unit, and used to set the voltage lovel of ICB pin 2 (5 V + Vsn/Vse). Output vol tage from the pin 2 is shifted by ICS to move the needle in the SWR meter. ICS contains aleve shft/meter amplifier and an auto tuner V-leonvertor. IC7 contains a square wave generator and a voltage comparator. IC8 contains an integration circuit. 03 and 04 are used to switch forward and reflected wave input signals alternately.15-4405 CIRCUIT DESCRIPTION Ver is compared with voltage from ICB pin 6 (5.6 VI When SWR increases, Vse lowers and the voltage level of IC8 pin 8 rises. AtIC7 pin 3, a triangular wave is moni tored, The triangular wave is compared with the wave from ICB pin 8 and output. The triangular wave is con verted to a square wave by IC10 and sent to switch 3 and Q4. This voltage is used as the SWR control voltage. 3) FULL/SEMI BREAK-IN and VOX circuits stano-ay sw contro. rey. ‘incur wc oe D+ clkcur When the standby switch, the key, or the VOX switching transistor are activated, a ground is applied to the input pin ff the control circuit, which causes a standby signal to be {fed to the microprocessor to determine if a valid transmit con- dition has been met. When that condition has been met, the Fig. 9-1. FULL/SEMI a _[ovesor] 8 Output voltage from ICB pin 2 consists of the voltage com pared with Vea/Vse and +5 DC voltage. It is distributed 10 IC4 the level shiftimeter amplifier to move the needle in the SWR meter and ICS the V- convertor to control the Arado, R14 is used to adjust the SWR meter ZERO point R13 is for SWR meter adjustment RLS exe KEYING, Rcuir ‘Tayp-8y CONTROL, ImucroPRocessor Saco owen SUPPLY BREAK.IN block diagram standby circuit in the IF unit will be turned on ‘A keying signal is generated by the control circuit, whenever ‘the key is depressed, to control the keying circuits in the IF Unit. This keying signal is also used as the transmitireceive signal during break-in operations. KEYING (FULL) ——4_fone, sh ¢ D KEYING MBRATOR ‘STAND-ey vox sho 4 og CONTROLISEMI Fig, 9-2 FULL/SEMI Sime a KEYING(SEMD) BREAKIN timing chartCIRCUIT DESCRIPTION FULL BREAK.IN at KEYING IN By c o” KEYING OUT CONTROL OUT ‘SEMI BREAK-IN, VOX xeyno Ay vox td L conrrot. our as , xevne ye vox OUT Fig, 9-3 FULL/SEMI BREAK-IN timing chart ‘The above timing charts show the timing for standby and keying signals When an input from the CW key is supplied to point A as shown in the above figure during full break-in operation, the one-shot mult-vibrator and gate circuits generate con: trol (full and delayed keying (ull) signals. After the fun damental timing signal, RL (12V) for reception and ‘transmission rises, the keying wave also rises, and when the key is off, AL falls according to the preset time constant. ‘Semi-break-in operation is synchronized to VOX. When a signal is supplied to point A, the VOX dolay time mutt vibrator determines the VOX time constant. The input sig nal is converted to a keying (semi) signal by the gate These Keying semi/full and control semilful signals are converted to sppropriate break-in VOX mode signals us: ing the slide switch, The control signal is checked by the ‘microcomputer to see whether transmission is to be per- formed. The control signal is then used to switch CRL in the IF assembly unit and generate RL (12 V). TXB (trans- mit 8 +] (8.8 V) is generated, synchronized to RL. The receive control signal RXB receive B+) (8.8 V) turns ‘onjoff, synchronized to the inverted TXB signal, thats, FL, Fig. 10 STANDBY keying timing chart15-4405 CIRCUIT DESCRIPTION 4) Speech processor Ca in the IF unit functions as the first stage microphone am: plifer or audio speech processor. When the processor switch is off, [C4 functions as a 20 dB microphone amplifier. When the processor switch is on, IC4 functions as an up to 40 48 ‘ain amplifier with ALC. When the processor switch is on, 8 VOC is supplied tothe base of the gain adjustment switch- ing transistor, Q41, driving the feedback amplifier. te UNIT PCIIS8H2 4. PLL Circuits Theory of PLL circuit operations The TS-440 PLL circuit uses a reference frequency of 36 MHz and consists of five PLL loops covering the range of frequen cies from 30 kHz to 30 MHz in 10 Hz steps. The PLL circuit has an IF shift function which is implemented by inserting carrier frequencies between PLL loops. The PLL loops include {a cartier circuit PLL loop and an HET circuit PLL loop which generates a constant frequency of 36.22 MHz. Frequency ivision for these PLL loops is controlled by the microproces ‘sor. Inall PLL loops phase comparison is made using the refer lence frequency fsro (frequency control using a single crystal oscillator, Figure 12 is the PLL circuit block diagram. The reference frequency (fsro) is generated by a 36 MHz crystal oscillator and Q21 (282787). Reference frequency signals are fed into the main loop’s 1C11 (SN16913P) via a buffer consisting 022 and 023 (2SC2668). The signalis also fed into IC13 (SN74S112} via a buffer consisting of 024 (28C2668). In 1C13, the signals are frequency divided to generate a 9 MHz signal. The 9 MHz signal is used as the reference frequency signals for the PLL loops. Fig. 11 PLS PLLS consists of 1C18 /MN6 147) and its associated loop components. VC05,036 (25K 192A), is locked at a fre ‘quency of 36.22 MHz. The 8 MHz reference frequency signal is supplied to pin 3.of C18, where the signals divi: ed by 1800 (450 in FM model to generate a 5 kHz (20 kHz in FM mode) signal used for comparison. VCOS's out put signal is supplied to IC18 pin 16 via 037 (25C2668), where the signals are frequency divided by 7244 (1811 in FM mode). The phase of the signal is then compared ‘with that of the 5 kHz (20 kHz in FM mode! signal by the phase comparator and the VCOS oscillation frequency is locked. Frequency division data is supplied by digital unit (DAO to DAS and Ca). ‘As described above, the dividing ratio used varies depend- ing on which mode the TS-440 i in, FM mode or SSB. This is because the apparent time constant is increased ‘without changing the active LPF constant so thatthe PLL signals can be modulated easily and reducing distortion during FM transmission. In modes other than FM, the amount of frequency shift due to mechanical vibrations Is reduced because the apparent time constant is reduced. ‘The output from PLLS goes through buffer 038 (2SC 2668) ‘and LPFe, and is used as the HET signal in the RF unit16 CIRCUIT DESCRIPTION Spe) ao | a Hoe ire =f BORE) Ee Fig. 12 PLL circuit block diagram = Pua PLL4 consists of IC1 (MN6147) and its associated loop circuit. VCO4, 3 (2SC2668), is locked at a frequency of aproximately 91 MHz, which differs depending on the ‘operational mode. The 9 MHe reference frequency & ap. plied to pin 3 of IC1, where the signal s divided by 1800 to generated the 6 kHz signal for frequency comparison, The output of VCO4 i supplied to IC1 pin 16 via buffer amplifier Q4 (2SC2668). In IC1, the output is divided by ‘an appropriate division ratio (18200 or so) which differs depending on the mode. The phase of the signal is com- pared with that ofthe § kH2 reference signal by the phase ‘comparator and the VCO4 oscillation frequency is locked. Frequency division data & sent from the digital unit (AO 10 DA3 and CK3}, ‘The output from PLL4 goes through buffer amplifier 05 (282668) and is divided by 20 in IC2 (M5459). The signal is further divided by ton in the cartier circuit of IC3 (SN74LS9ON) and then fed into the IF unit as the carrier signal via the LPF, and buffer Q7 (2SC2458) and O8 (28C1959). In AM or FM receive mode, switching circuit 06 (2SC2458) operates when an SFT signal is sent, and as a result, IC3, Q7, and QB are stopped to cut carrier signals. The PLL4 output signal also goes through the LPF and buffer amplifier 09 (28C2458) and is fed into the mixer in the main loop, where the signal is used to form the dig- ital VEO signal. As a result, the operating frequency does rot change even if the carrier frequency is changed, which enables USB and LSB mode switching F shift and fine cae rier point adjustment. In SSB, CW, or FSK reception mode, the may be shifted +/— 1'kH2 or more and the carrier point can be adjusted in the range from -400H2 to +360 He Pus PLL3 consists of IC4 (MNG147) and its associated loop components. VCO3, Q12 (2SC2668}, is locked in the range of 99 MH2 to 103.995 MHz. The 9 MHz reference frequency signal is supplied to pin 3of IC4, where the sig nal is divided by 1800 to generate the 5 kHz signal for ‘frequency comparison. Te output of VCO3 goes through buffer amplifier 013 (2SC2668) and is applied to ICA pin 16. In IC4, the output is divided by L and the phase of the signal is compared with that of the 5 kHz reference signal by the frequency comparator, and VCO3 oscillation frequency is locked (in § kHz steps). The division ratio, LL, supplied by the microprocessor, in the digital unit, (DAO to DAS and CK2). L is in 1000 steps (19800 to 20799) corresponding to 0.00 kHz to 9.99 kHz. In CW Feceive, in order to obtain 800 Hz beat signals inthe oper: ation frequency display, the L is shifted ~ 80 19720 to 20719) and when RIT/XIT operates, the Lis changed so thot fvco is shifted +/—1.2 kHz or more. In AM or FM ‘mode, the Lis shifted by 10 steps to change fico by 100 He steps. ‘Output from PLL 3 goes through buffer amplifier Q14 (2SC2668) and itis divided by ten in C5 (MB4460L) and ‘then by five in IC6 (SN74LS9ON). The signal is then fed18-4408 CIRCUIT DESCRIPTION into pin 2 0f MIXS IC7 (SN16913P) via the LPF. In MIXS, the signal is mixed with the signal generated by PLLA and {goes through the BPF to generate a signal in the range of 6.53 MHz to 6.6301 MHz (in 100 Hz steps}. The gener. ated signal is supplied to pin 5. Pua PLL2 consists of IC9 (MNG147) and its loop circuitry C02, 018 (28C2668), is locked in the range of 58.25 MHz to 3.2501 MHz. The 9 MHz reference frequency signals supplied to pin 3 of IC8, whore the signals divided by 450 to generate a 20 kHz signal for frequency com parison. VCO2's output goes through buffer amplifier 19 (28C2668), and is fed into MIX4 pin 2 and mixed with the 6.35 MHz to 6.63 MH? signals applied to pin 8. The mixed signal then goes through the BPF to obtain 64.78 MHz to 59.88 MHz. signal (in 100 kHz steps). The (64.78 MHz to 69.88 MHz signal is fed into IC8.pin 16 va buffer amplifier 015 (25C2668). in IC9, the signal is divided by M, and the phase of signal is compared with that of the 20 kHz reference signal by the phase comparator, and this [MIX@ output is locked (in 100 kHz step). The divison ratio M is supplied from the digital unit (DAO to DA3 and CK1), and i in 50. steps from 3239 to 2884 corresponding to (0.00 MiH2 to 0.49 MHz. ‘The output from PLL2 goos through buffer amplifier Q20 (28C2668) and is divided by ten in C10 (M54460L). Via the LPF, the signal is fed into pin 2 of MIX3 IC11 (SN16919P). The frequency of the signals depends on the values of L and M, and is f the range of 5.825 MH2 to 5.32501 MHz [10 He step) \VR1 in MIX4 circuit is used to suppress spurious outputs from the mixer. It is necessary to prevent PLL? from be- coming unlocked. ‘Signals generated by PLL2 and the 9 MHz reference fre: quency are mixed in MIX3. The mixed signal goes through the BPF, and is further mixed with fo in MIX2 IC12 (SN16913P) on the IF unit. The output from MIX2 goes ‘through the BPF to obtain 38,55 MHz to 39.04999 MH2. “The signals are then mixed with the output from the final VCO oscillator in MIX1 Put The last PLL loop, PLL1, consists of C17 {MBB7006) and its loop components. IniC'17, frequency division for refer- tence and comarison frequencies is set by serial data (SO, SCK, and LE}. When an external prescaler is used, IC17 has @ modulus control function for configuring the pulse swallow counter The VCO oscillator output from the RF unit goes through 026 (2SC2668) in the PLL unit and is fed into MIX. The ‘mixed signals go through the BPF, and they are then am- plified by buffer amplifiers 027 theu Q30 (25C2668), shaped by IC18 (SN74S10N1/3}, and fod into IC16 (WN74S112NI 1/3, oF 1/2 prescaler. Basically, C16 is 3 two-level FF circuit and functions a¢ a 1/4 divider. But, ‘when IC17 of the PLL unit sends control signals, toIC16, IC16 functions as a 1/3 or 1/2 frequency divider in con: junction with IC15 (2/3). Thats, the C15, 1C16, and C17 form a pulse swallow frequency divider. The 9 MH2 reference frequency signal is supplied to pin 1 of IC17, where the signals are divided by 18 to gener ate 2 500 kHz signal for frequency comparison. Signals fed into IC17 pin 8 via MIX1 and the buffer amplifier are divided by N, and the phase is compared with that of the 1500 kHz reference signals by the phase comparator. The signal then goes through the active LPFs Q31 to 033 (28C2459) andis fed into the RF unit as VCO voltage sig als to control the variable capacitor of the final VCO. The frequency divider N covers the full range of operating fre- ‘quencies from 30 kHz to 30 MHe (500 kHz step), and it has 61 steps of frequency division data supplied by the ‘microprocessor in the digital unit. ‘The last VCO signal in PLL! therefore depends on the values of L, M, and N, and itis in the range from 45,08 MHz to 75.05 MHz (10 Hz step). N is expressed as follows: N=PNo-A, (No> Al P:Prescaler module value No: Programmable counter value A: Swallow counter vakie PLL IC contains No and A. ‘The last VCO unitis contained inthe RF unit and consists of four VCOs, each handling one portion of frequencies {rom 30 kHz to 30 MHz, The appropriate VCO is selected bythe microprocessor according to band information from the digital unit = Unlock I a PLL loop enters a unlock state, the output on the UL pin becomes L. This L signal is sent to the digital unit to ‘stop the microprocessor, ‘+ 500 kHz marker signal The 500 kHz reference signal for frequency comparison is supplied from IC 17 pin 13, anditis used as the marker nce signal 5. Digital control circuit ‘The TS-440 digital control circuit uses an 8-bit CPU (7800) which does not contain ROM, and has @ 16K ROM (27128) ‘and a 2K RAM (8418) outside the CPU. A common bus used {or data exchange between the CPU and RAM, and between the CPU and ROM and is also connected in parallel to the two 8255's for extended 1/0 and an 8251 for interface to ‘a personal computer (option). To transfer. ata to.a from an ‘appropriate IC, the CPU uses the WR or RD signal, {and the chip select signal from the 74LS138, ‘The display is dynamically controlled by software, and con- sists of 13 digits and nine segments. The 13 digit and seven segment signal is driven by the high voltage resistive buffer (6300), and the other two segment signals are driven by a transistor. The 7800 transfers data serially. The clock signal is frequency divided by twoin the 4013 and sent tothe 6300. Using the 4011 and 4030, the encoder generates count 718 CIRCUIT DESCRIPTION pulses and U/D signals from two clock signals which are 90° ‘out of phase with each other, and sends the pulses and sig nals to the 7800. A clock pulse interrupts the 7800 and @ UP signal causes the 7800 to perform a count up or down ‘operation for each step. If fast rotation occurs, the 7800 processes several steps of PLL data at one time. Voltages from the RIT and IF shift VRs are converted from analog to digital by the A/D convertor IC (4052) and fed into the 7800. The voltages are used to drive the display and are reflected in the PLL data, The digital control circuit contains two 8258's for extended VO. The 8255 in control unt A is an outputonly element and the 8255 in control unit B is an inoutonly element for key ‘scan and static data, The output 8255 emits VS-1 signals, PLL data for the 6147, clock signals, and 1 MHz LED data The input 8255 receives key scan data such as panel switch data ond DIP switch data for CAR compensation. It also receives static data which cannot be entered as a portion key scan data. ‘The 7800 outputs four bits of band and mode information (11 bands in the frequency range from 30 kHiz to 30 MHz). Each time the 8251, used as the interface to @ personal com: puter, receives ane byte of data, the 7800 is interrupted and reads the data from the 8251. The 7800 analyzes any com mand in the data. in response to the command, the 7800 Controls setting or writes data to the 8281 as required. The £8251 serially sends one byte of data including a star bit, syn chronizing to 2 4800 Hz clock signal. : eee) tek Heel} Es] if Fig. 13 Control circult block diagram18-4405 CIRCUIT DESCRIPTION 1. Encoder ‘The TS-4408 uses an optical encorder. Two different clock signals from the encoder are 90°, out of phase with each cother. This phase difference is not adjustable but depends Con the precision of the module. The two clock signals are converted into clock pulses (250 pulsesirotation x4) end UID signals indicating the direction of rotation by the 4011 and 4030 and fed into the 7800. Figure 18 is a timing chart for clock pulse and the U/D signal transmitted to the 7800. Fig. 14. Encoder circuit re oorae Se aces erences] ee TUTTE Sra en Os [— wosKnat Fig, 18 Encoder waveform timing chart 1913-4405 CIRCUIT DESCRIPTION 2. Digital display FP igi ane sngmen ila ae ivan by the 6300 but Geien enna ad aaa esa er ae Stan cumraieveri agasra aces {or The 700 sons pay dt sary 1 Me bt te Sock gnats oe dd by te 500 tthe 4060 ae fealmotne £300. Faure 1 shows how he feaveney dv ee ime rae aerae eae (imac (pin 28) and a clock signal from its SCK pin (pin 26) at ap- rox. 1 ms intervals, After the 7800 has sent 8 bits of data fivetimes, the 7800 sends a negative enable pulse from port BS (pin 46). When a decimal digit goes on, the 7800 sets port C4 to L and when a red character goes on the 7800 sets port C3 to H, 78008 Ie MP06300C 3. Key scan input The key scan input block sends key scan signals (negative pulses) from its 8255 {IC53I port C in the order of CO to C7 (C6 and C7 are output only once when the POWER switch is turned on}. When a matrix crossing point switch is on, its Fig. 16 Digital circuit corresponding bit in the 8255 port A is Lto enable the switch 10 be identified. Figure 13 shows the matrix. Key scan $6 ‘and S7 are provided for the extended function using diodes. Key scan motri 3. 7 2 3 2 5 é Lo tse [2] use | 3] ow | | aw | 5 | fw 2 | 6 a a 9 oO |_FsK 3 vine Mv SCAN MN ‘CLEAR ENT 4 ait zit TSET TMH DOWN « [os AB SPRIT A=8 2a 1 uP 6 Voice set on coc; [Tou 3 | 50 2 | wou 8 7_|_Tser oFF zoo. 4 | 250 6 | 20008 @ TIMER ser clock? | 4005 | 01 7 | 400u 10 Table 10. Key scan matrix18-4405 CIRCUIT DESCRIPTION 4. Static input 7800 (ICI) H when UP when unlock AD convertor data CO | Encoder UD signal C2_|Unlock signal 07 _| 4052 \IC: Display) 8255 (IC53) BO Lock switch 82 | AT switch 83 | Mic UP switch 84 | MIC OWN switch Bs |PTT switch ‘L"" when switch on when switch on “Lt when switch on “L" when ewiteh on “LU when switch on. 87_|VS-1 busy signal 4" when VS-1 busy Table 11. 5. A/D convertor input ‘Voltages controlled by the RIT and IF shift VRs are applied to the 4052 {IC2: Display). The 4052 has four analog inputs: AO {IC2 pin 4) is connected to the IF shift VR, and A1 (pin 5) is connected to the RIT VR, the other two inputs are not used. When reading IF shift data, the 7800 sets port C5 to O and selects 4052 AO. As a result, the 3255 sends a posi tive pulse from port BO to reset the 4052, and the 7800 sends nine postive pulses from port C6, and port C7 receives data. When reading RIT data, the 7800 sets CO from the ‘4052 to H and thereafter performs the same operations as when reading IF shift data, par 2) 1F SHIFT 40s2 yore eS LZ A/0 converter Input .17. AID convertor circuit 6. AT control When the AT switch is tured on with the AUTO/THRU switch in the AUTO position, 8255 (IC53) ports B2 and BS {90 on. When the 7800 knows that the AT switch is on via port B2, it will enter the CW-mode, and sets port A2 to H and AO, A1, and A3 to AG, and BA to L, and transfer a pow €er down signal. The 7800 then knows that the PTT switch is on via 8255 port BS, and sets port AG (transmission con- ‘rolsignal) toH, enabling transmission. However, ifthe select ed frequency does not allow the 7800 to prepare for transmission, 7800 port A6 remains L and the 7800 will not ‘enable transmission, When the selected frequency is 1.9 MHz @ ass, the 7800 will not enter CW mode nor send a power down signal 7. LED output Depending on the mode, the 7800 makes the 8255 (IC2) send M, SCR, 1 MHz, and lock LED signals from ports 84, 85, and BG. When the LED goes on, these ports are L. When the mode LED is on, 7800 ports AO to AS are H. AO 10 AB correspond to LSB, USB, CW AM, FM, and FSK respec- tively. Mode LED output is used as made control signals in tho IF unit 8. VS-1 (option) When the voice switchis turned on, an address correspond: ing to the instruction (numerical data) entered is sent from 8255 (IC2) ports AO to A4 and a positive start pulse signal is sent from port AS. The VS-1 sends busy signals (H) to £8255 {IC53) port 87 while the voice switch is on. After the voice switch goes off, an address corresponding to the next Instruction and a start signal are sent. 9. uPD 7800 reset circuit ‘The 7800 reset circuit is used to initialize the 7800 when the POWER switch is turned on. This circuit supplies a reset pulse to the 7800 after the clock is supplied to the 7800 sys tem clock input, X1 (pn 31). Since IC3 remains on until PST520D {IC;3) pin 1 reaches 4.3V,C10 is not charged, ena: bling a reset signal to be supplied. When pin 1 exceeds 4.3 V, IC3 goes off, causing C 10 to charge via R2 and R3 and the reset signal is removed. 2115-4405 2 CIRCUIT DESCRIPTION ype bt hes rT ‘yr07200 Fig. 18 Reset circuit 8285 (1C) 10. PLL output block “The PLL output block controls five PLL loops. The 600 kHz ‘step PLL loop uses an MBB7006 and the other PLL loops use MN6147. ‘The M387006 has two dividers: one for the PLL reference {roquency and tho other fora swallow type counter. Froquen: cy division data forthe reference frequency is sent only one when the TS-440 power is switched on ‘The MN6147 uses the PLL data format shown figure 19. Port Ban.87 Bones Fig. 19 MN6147 PLL data ‘Since the MN6147 has latches as shown in Figure 20, only data following a change is output. GO data can be any data since iti used to wansfer G2 and G7 data to the GB latch, 1. Other outputs AL output (7800 port A6) This output signal controls transmission. When transmitting, this signal is “H”. BZ (Buzzer) output (7800 port A7) This output signal makes the BZ circuit active, When this sig- nal is "H', the oscillator circuit operates. RESET output (7800 port 87) ‘This output signal resets the two 8255s and 8251 (option) ‘SBK output (8255 (IC2) port A6) ‘This output signal switches the RF unit to prevent noise due 10 PLL siwtching, MT output (8255 (IC2) port A7) This output signal controls the AF output to prevent noise due to PLL siwtching SCH output (8255 (IC2) port CO) This signal controls the sub audible tone encoder. The sub. tone is activated whenever a transmit frequency in M-CH 120-99 has been selected, in the FM made. A logic H acti vvates the encoder. 12. CAR compensation DIP switch This switch is used to compensate the absolute frequency characteristic of the 455 kHe fiter. The characteristic can 'be compensated within the range of ~ 400 Hz to +375 Hz LSB and USB can be compensated separately. When LSB is compensated, FSK is also compensated. Fig. 20 Data input terminal and programmable counter ‘SW No. He 7 25 2 50 3 700 use [4 200 5 ~400 6 25 [7 50 8 100 use, 3 200 70 400. Table 12 When all bits are off, 400 Hz is supplied for compensa: tion. When no compensation is required, bits § and 10 must be on.CIRCUIT DESCRIPTION 13. Band information generation circuit {in the RF Band information 7800 PBo ~ 2, B:828;80 13-4405 unt Doi = 0s 308 Bandini fan he conto itis sto connector sir ~ our 001 "othe Rr ue. Sand omaton sgn BO to 99 form ‘ne = ashe 3010 2°5C0 ‘cose m wth 80 responds 10 LSB. Qed anne So in7a.s aoe to conver da om 80D DEC na ee ; it generates control signals for ten of the 11 bands. Control = ei a oreo ‘signals for the remaining band (25.5 MHz to 30 MHz) are il inen o101 generated in the AND circuit consisting of D57, 058, and zmabe — VO.shiite, O19 {6 These conor sg 9 rauan te cure aercon TDi = 14 ae ont Sting of a to Ges MSASeTP nd 2SA56), and re inane iced Of by nde, segue, and sano AT nt ite, aE a 9, ano ANT BF, a8 shown'n Fgure 2 ee oor Tale 13 ~ ‘at {al teat oles ama ig) wont esr wsaseie ott Yar YuYeu¥ Fig. 21 Band information generation circuit 2318-4405 14. Mode control Transmitireceive mode signals are generated by IC10 in the IF unit. IC10 is a hybrid IC containing five pairs of PNP tran sistors and diodes, Figure 22 shows its equivalent circuit. When the mode sig- SSB, CWB, RYB, AMB, and FMB are applied to pins 6 exer2 CIRCUIT DESCRIPTION 10 10, the voltages of control pins 16 and 17 change. Dur ing reception, these signals change to SSR, CWR, RYR, AMR, ‘and FMR. During transmission, these signals change to SST, CWT, RYT, AMT, and FMT. TT 18, Expand function Control unit (X53-1450- 11) ais orewaes ig. 22 Mode control circuit Ne. ‘Shipped! Diode eat 65 ‘Made boop tone: Morse Single tone 66 10H cisplay OFF ON, 7 Memory protect oFF on B Cw shitt 00H 00H 78 W246 1K No Yes 79 wis 1 No Yor 4 Table 14 Expand function18-440 CIRCUIT DESCRIPTION 16. Semi-self test function Semi-self test is started by turning the POWER switch on with the [4] (AM) and T-F SET switches pressed This test provides a method of testing the TS-440 digital ‘system in a shorter time during production or servicing. The ‘est enables the following: 1. Circuits which are difficult to test during program execu tion to be tested easily. For example, dynamic data can be ouput as static data 2. Items on which information ie hald only by the CPU and is not available to the user to be tested. b ‘Approximately threshold level input Incorrect input due to input pin fauit Operation procedure 1 2 3 4 POWER SW OFF ‘The power switch on while pushing switch [4] (AM) and switeh T-F SET ‘The test number has starts from “0” to ““56"” and END ‘when turn the VFO knob clockwise. Operation chart shows as follow. To reset SEMI-SELF TEST function, Power switch OFF. TEST NO, LIST = er Condition 0 | Start Ab Fip’s lgnt’s a | Res = 1 | AILFip’s ght’s Segment) oe | es 2 | AI Fip's tight n | co="H 3 |All Fip’s OFF (digit wu |e 4 | Each digit ghts G1 a | ax 5 oz ae [emery ‘ “gs 37 | 8255 Por & al =H" C2) D ce Pall | atekeneaaes bo ' Gs 38 | 8255 Pon 8 all oa | a wf bet on o “6 41 | 8285 Pon ¢ co~cs: ca~c7="L" " ees @ co~C3="U" ton c4~c7="H" ” ” 69 | 8255 Port ¢ al="H" 11083) n | “Gio “ mal ba “ “oon ss | Lock.prT,mic,U/0,AT,VS-11BUSVichock 5 G12 «6 ISIMPLEXI VS-11BUS¥icheck 6 "gia 29 | Key sean inport check | a oN | 1 sei, (B).via.voice tcheck) 1s | az OFF 8 13 | Mode LED all ON 2 OFF a (invmediany fa 2 a se 6 (AM), [JL.MIN.T-FSET,A=B,100L 200% 400 |) 6] (FM, [TFSKY.CLEAR.IWH, 26. SOL 25U 5 O.2.0.0 =n ENTDOWN.UP, 100U 209U 400U END 518-4405 CIRCUIT DESCRIPTION SW Monitor Display changes by TEST number a 1 1 i 1 ’ Fi ; Tes ! ri O i i] ga 3 Lock | ar J mc ane | err vs “ s ur pour | oat Busy | | “ 1 @ | wm vorce “ @ | @ | wv | en re 2 o S| seas | xr sprit | cw | | ; | A mo | o | mw | reser poet eed eet ee an_| | | o | @ © 2 ele tree | cree (freee ae | su | au | sot FM ® ® © ® 2 ext | vows vo | me | a | ow Iv the display changes from") "* to)" by operate the key in chart then function working properly. 2618-4405 SEMICONDUCTOR ‘SN74L$138H (Control unit IC51) + weuzriee Pinz0 ce (P0828 (162) Ps meeais rons! Pi) TRUTH TABLE output 2TS-4405 SEMICONDUCTOR C4013 (Display unit IC3) ‘TC40408P (Control unit IC55) PH aaa Ba Bos be Se Be TC4069BP {Control unit 1C4) 2 GUsLisL LS 113-4405 SEMICONDUCTOR mB4052 7800 rad = Los ‘8255 (12) MB4082 Pin Description NO Signal Pin Functions Pin No- | Pin Name | Symbor Function 2 |Range expander | Ex. 2 [Analog input pin for expanding the range. input Ex. 1 [Analog output pin for expanding the range. Connect to any pin from AO to AS. 3 |Range expander By using Ex. 1, Ex. 2, the ange Is expanded to the % 4 range. output 47 [Analog entrance | Ao~ As |4-ch analog input pin. Channel 1 is selected by channel select input COtoC1. ‘3 [Channel select input | Co | The input pin to designate the analog input channel for A/D converter. Ths signal is latched 10 C1_| atthe trang edge of CS. 11 [Chip cotectinput | CS _| Thi i the chip select input pin, When CS is inverted from "1" to "0%, AID converting starts and data output is enabled. After A/D converting is over or when an interupt is re quired, set the CS back to "7 12 [AID convertion ‘ADC | This isthe clock input pin for A/D convertion input to the comparator register sequentially lock Lk |Convertion speed fs determined by the clock speed. In the case of 8-bt, approx. 10 clocks willbe needed. However, itis not necessary that the clock period be fixed 13 [Data output DATA | This & the open collector fo output the rest of A/D convertion. The date © output the (OUT | order ofthe start bit, most significant bt, 2nd significant bit, .. least significant bit, and the stop bit, synchronized with ADCCLK. 14 [Range select input | RS [This & the input pin for selecting the voltage range of analog input, The VFS =Veu\/a range is selected at “0, and the range of FVS: hold this pin to."0" or "1" /eey2 ls selocted st “1”, During convertion, 1 [Analog ground AG | Ground terminal 8 _|oigitat grauna DG 15 [Power supply pin 2 | Vecs |When diving with 3.5 o 6.0 V of power, connect Voc and Vee: to each other, and apply 16 [Power supply pin 1 | Vee | the power voltage to thom. When driving 8 t0 18 V of power, apply the power voltage to Vecs. At this time, the 5 V stabized voltage is output to Vee, and approx. 10 mA current ean be supplied externally : =—| [of os aa 1 ves : = vas Owe 29MB8418-LP20-GRA (Control unit IC50) : SEMICONDUCTOR Te + Te~Ave | Aas input ecr—oo | a Wyeth | Oats inoue | zs np saect 1 C82 Chip select 2 | WE | write enol ves | Power 11.5 Vi xo ovo S Ne No eonnacion eo ae ica sn7a.si36 T MBM27128 (Control unit IC52) sr07800 Pm name Rowan | Aasier np O:=0, | Date utr oe Chip enable ut od Out enable pik FER Power input | o Vee Foner =u6 : ce Veo Progtem power supiy exo | ano snvaisise 30 SSS 115-4405 SEMICONDUCTOR MC3347 (IF unit 1C2) : | rs Ue 5 i t 7a [~ 7a -" Eel 3 ¥ ® oe fete ee eel tee 3 bes je 318-4408 uPC1158H2 [a> fac ce uae ers Pin connection Pin Funston 7 Input 2 NE a Output 4 GND. uPC2002V (IF unit 17) SEMICONDUCTOR Funston TALC output ‘ALC tnput 32 4: OutputTS-4405 SEMICONDUCTOR »PD8251AC (Control unit 154) 4sP07800 (ano Gos a rt: a0) 0 1 prone rs ® 0 #PD8255AC-5 (Control unit IC2, 53) 7451368 suen @ Basic function A [Ac |S [RO [WA Function Of [0] 0] 1 [Data bus = Port A O [1 [0] 0] 1 [Data bus = Port a 1 [0 [0] 0 | 1 [Data bus ~ Por C ofo]o| 1] © [Pot ~ Date bus oft [0] | 0 [Pore ~ data bus 1] 0] 0] 1 | 0 [Porc = Date bur 1 [1 [0 [1 | © [Controt register ~ Data bus vf [1 | | = [Pa bs non mosaics 111 [0 [011 [combination & inhibited “0 shows low level () 1 shows high level (H) 3318-4408 34 nPD63OOC (Display unit IC1) Pin description SEMICO INDUCTOR Pin No. | Symbot Pin name 10 1 Ons oe lee Or High dielctc-strength (40V) output in the Feh open Segment Ore | Seer ° on ue Corroeponds to the output of Q13-Qs9 a oer 7 O10 ‘utp serial data the traling edge of SCK. When the n-rumber 8 80 _| Serial data output pin © | ef wPD6300Cs ore connected n series, th can be comected to the Si of the following stan. === This input ean ten off all incator @ eplays, and ean dim them ° BY _| Stenting pi ' | bv applying @ random duty pulse from outside. Active low. — Transmit the connects of Oe sera shift egter tothe buffer 10 TH |taten in 1 | register a tow fevel,t atch the connect a the sng tine. ‘etve rising Wleadinal ede, ee This & the data input pin. Inputs data 10 the shift register atthe " aie | Sieaceans "| ising edge of SCK = Reads out the SI data to the shift register atthe rising edge of 2 SEK | Serial clock input pin 1 | scx _ Outputs data fom $0 atthe wang edge of SCR , El Soa [When GS i high, this inhibits SCK and LH. and when CS & low. 2 Siam | bees sctvates SCK ond UF 14 Ves [GND = [eonnect te the GND terminal ofthe systom 18 os 18 o eh opendain system, high lect strength output 7 o. | 18 |r Corresponds to the o output of Os t0 Ors va 25 | segment : iver Pen orp lta On 05 | (Oo-Ou) Oro . a Ore cS 05-0» 27 Ons 28 oo | Power supaiy pn = [svrio%18-4405 PARTS LIST capaciTors ce ect cee ce) 10 3-00me 1 = Type... ceramic, electrolyic, ete, 4 = Voltage ratin oe f] oe ARQ mr 2=stape round, snuwreete. B= Valve cholo tstounberf Mbnoner 3+ Temp, coefficient 6 = Tolerance, 10 1 100pF 2nd number 4 Tomperatre Coetficiont 10 Tawes Te] cP? Tas [To] fame [ula pe tT Cotrt | ek | Aes [Orage Voto | Green| Bue [Vint] [ gone [v0] s6s [2130 [e 20 [sa some [0 [ -20 [100 [200 [200 [aro 750 Example CE48TH = 17060 por"e Tolan feel [o[e]s [ex [u[x][= nove alae es we) [rozs]zos]=2 [25 [=i )=m [>a | veo towr-10+80 ] [ort [+03 [raas [eos | er [Es [Po AI 10~ 078 = Rating voltage wy a fe le foletle le fu lute dv See | 50] 315 | 400 5 soo —[a1e0 [2000 s Refer to the above table, e 7 ‘ashen 20 3202 ass than 1.25 Gi zo=0a | 126202 [Lest than 1.25 Dimenalon (om BF) 1 = Type .... ceramic, electrolytic, ete, | Dimension code L Ww T_[Watiae + chip rviter (Carbon 22 Shape round sua et © [aaz02 [v6=02 fos] 28 rene A soe F 20203 [125202045 | 2a egg emp, cotficent —— a a 3 Vatage rating Rating wattage o eee i Cora [ Wavaoe [Cord | Watione [Cord [Watione] >#nension oe 2a [1 10w | = | 1 aw [aa | w Qe zap jiwio|w | & ac [1_ ow 35TS-4408 SEMICONDUCTOR PARTS LIST N: New Parts "> Please note that parts ara sometimes notin stock, and it takes much time to deliver Re Re ee = trem |) Name trom —|ynmns) Name | t a Diode 151585 Digital Tr N [prertaes, N |uw29ai2-6.0 18133 rciasts an 152588 orcizaes M5449 181507 Drciaaws Msas61P 151007 DTA114ES nv [azausoor Hevess n |avausi23e ny | isvisa 1" 28862 (Y) M7aisiasP 158101 n | 250562 TM ase 1ss99 28A350 (Y) ees rm Nv | Mae7o08 anaes 28c1959 (¥) | Mona7129-25,a1 28ci818 vi /MaMe418-20LP. sarc 28¢2053, GRA BA282 282075 Mcior25t n [masse 2562858 (¥) Mc101310 nv |usi030 28¢2459 (BL) ee NN [DANao1 2862509, McIols ca 25028708 nena i204 282668 (¥) pene coz 2862603 (6) Nesssr nv |28¢2873 Naw28030 Vart-cap irrsi0Te 28¢3113 (8) Ngw25035 2862787 iL) Nuwagoane varistor vig Naw2094s Mv-sT Fer 28K30 (GA) e nv203 28K30 (0), ou 28K 192 (GR) /SN74LS90N Nv |svosys 29K 192A (GR) /SN7ALS10N 25K 192A (GR) +d [sn7ais112N zener diode rz 3.018 28K 125.5, Nv |sn7aoan rz a.33¢ Ny |sn7ausi2an MTZ 6.20, 38K 73 (GA) /SN74LSOON MTZ 7.518, 38K 74 1) [si7aisi3eN rz 9.198 38K 122 (L) [Sw7aus145N rz 9.13¢ jsv16913° Pp puelz N | rcao018F N Juz 3.08 AN6S51 eoteey n fuze2a. ‘AN7808, ree nN fuz.9.18L ‘AN7808 noes lane ee nv | Teso69uee HTMPB25SAP-5 Thermistor /sDT1000 sasioou2 w [stax 8x6128 PCr 18842 112-5022 8x7 191 /-PC2002V 32027 PCASBEC H010116 Nv |,P06300¢ Surge absober | N |OSP-201N 010131 PDB255AC-5 010125 PD 7800S Destination table K for U.S.A. (M1 : GENERAL MARKET M2 : GENERAL MARKET T 3 for England W. = for Europe X + for Australia 3613-4405 es PARTS LIST Parts without Parts No. ae rot suopled. Les articles non mentiornes dans le Parts No. re sort pas Fours ‘Tetle one Parts No. wercen nont gatlefert Ref, No. [Address|tin) Parts No Description om tit ei) wae Bassas TS-440 1 ] AnT-0998-n2 re (a) UPPER 2 +) An-0999-Ue EASE (i) LOWER 3 +| nzo-25s6-05 | PANEL assy 4 «| pat-o6r?-03 | BATTEN PLATE 9 nos-oa1t-o4 | GP MGUNTING. HARNUARE 10 oS-0708-04 SP GRILL CLOTH ir | na0-oare-15 LST LAMP (14V.a0n1A) ie x} for-a6s?-n5 | METER la +) Ba0-3625-04 NQDEL NAME PLATE kmnine 14 +] pao~z625-04 NQDEL NAME PLATE ™ la | man-3626-n4 MODEL NAME PLATE x % x] Ba-2ara-o4 UX Heme PLATE 22 *) a3-1063-04 NAME PLATE (TRIB TS-a405) t eB +) bas-r0e4-04 NAME PLATE (KENUBAD TS-aaxr | x ze 2c | «| na3-1065-08 NAME PLATE (KENUBED TS-sa05> | Krim2 a ac | x] Bas-1065-04 NAME PLATE (KENANAD TS-aans) |W 23 ir || ma-osto-1g | wakReNTY CARD r 2a is | | ps0-anan-n0. INSTRUCT MANUAL krnane 2a 48 | +] p30-ecan-op INSTRUCTION MANUAL ux 24 1s | +] mo-ana9-00 INSTRUCTION MANUAL T bap-1729-04 LABEL (WITH ANTENNA TUNER) 2 1s E0?-0751-05 WP DIN PLUG (ACCESBRY) 2 18 £07-0852-05 a METAL PLUG keane 28 18 ES0-re3-0e De PAWER CARD. Assy - E1-0431-15 WIRE WITH CONNECTOR (SP) 30 1s Fos-20se-05 | ruse (20a Er 15 ros-2030-05 | FUSE (20a vaccessory 33 0 oe-o5n5-05 | KNB FIXED SPLING (xa) Gs5-0509-08 PACKING (2) CASE SIDE 4 Ho1-aens-o4 CARTAN ROX ——CINSTDE) kame 4 Hoi-aea3-04 CARTON BOX = CINSTDE) a 3s +] WOI-aena-o4 CARTEN BOX INSIDE) a a | HoL-ages-na CARTAN BAX CINSTDED x s | Hos 270-04 CARTAN BOX (RUT SIDE) xi | wo3-2270-04 CARTAN BOX —— (BUT SIDE) = +] Hos-2285-04 CARTAN BAX (OLIT SIDE) % | Hia-2615-02 PACK ING FIXTURE (ED 3 4) H10-2616-0e PACKING FIXTURE(R) 3 Hiz-igis-aa | CUSHION 2 Heo-1425-03 | PROTECTIVE caver a0 Ho5-007-04 | PROTECTIVE fing cnEe krume “0 Wes-o079-04 | PRATECTIVE HAG CHIC) x a HOs-oll2-04 | PROTECTIVE BAG (Dr CARD) as 3B so2-os23-05 | Fae cer ek 4a 38 | «| Jo3-naa0-0a | assistant Farr s ta.3a| || “Jo2-oaa1-o5 | FRST (ay 46 3A 3o2-osa2-0a | FRGT 2) F a PA Yei-11aa-34 | PRUNTING HARDWARE CSP) 49 ae || sen-2779-14 | MOUNTING HARDWARECPILAT LAMP) ° a 0-0526-04 | SPACER 50 ie ‘ar-orat-oa | SPACER RING cmc) 3718-4405 % Now Parts Parts without Parts Ne. arenot supped PARTS LIST Les ertiies non mantiornes dans io Pats No. ne sont p28 fours Tolle ome Parts No, werden nine gelefert, Ret. No, [Adsress|iy] Parts No, Description Desti- Re- ation. mori emes |e mie) sae s Beara eae 55 te a32-0765-04 HEX BOSS 2) 6. sie 56 a 3, -07H2-Da HEX BOSS cca) 1a st irae] | J3e-o7%-02 | Hex nuss OB) 10nmt Ey as | «| Ys2-0793-04 HEX BOSS Ga) nin | 59 tras] +] Jae-0796-04 | Hex Bass oa) Sit “3 38 KO1-0407-05 CARRING HONDLE 6s St | | at-orze-a2 | natn Knap & 3c kes-ovio-oa | te aNsIDE) xa | 66 is K23-0712-04 | Knap come) XL oe 3 Kes-on2-04 | NAB CELEETIVIT 0 68 3c ke9-orat-24 | novos carsipe) x4 o 2 ¥29-0758-04 FUSH Kova «PAWER) 11 i be koe-aree-os | van an a 2 Ke 3001-04 | PUSH KNOR ay ve br ‘2o-go02-04 | PUSH KNa Oe) | 3 a || nig-o6oo1-1a | FLar wasieR % Es Nig-e37-04 | FLAT WASHER CHAIN. KNAB) - Nav—snda—ae | RRAZTER HEAD TAPTITE SCREWCX1) NB?-3012—46 | BRAZTER HEAD TAPTITE SCREWCX2) fA acvae| | Nov-dase-o8 | nn’ stREW (xa) ry 2H NO9-0644-04 BIND SCREW (x6) cc 2H No9-0658-04 | RLND SCREW CxS) DD St.ac| +] No9-o899-05 | SeREW 6) E at N3C-2608-41 PAN HEAD MACHINE SCREW (x6) F Tes] | nae-2606-46 | FLAT HEAD MACHINE SCREW OG) 6 aceen| | ns2-sona-a6e | FLAT HEAD MACHINE SCREW (xa) H i€.20] | N32-s006-ae FLAT HEAD MACHINE SCREW (XG) a 1a Ni3-3006-41 UAL HEAD AACHINE SCREW. (x4)5P r 36-11) | NGS-26N8—86 | BINDING HEAD MACHINE SCREWLXED t tare) | N3S~3N06-41 BINDING HEAD RACHINE SCREWCK2O " acer] | naz2eo-a6 BRAZIER HEAD TAPTITE SCREWOC N icvak) | Naz-Snoe-ae | BRAZIER HEAD TAPTITE SCREWCXIs P 3A Nav staat BRAZIER HEAD TAPTITE SCREWUX2) & a Na?-s010- 4 coroig-05 | CERAMIC =O, 047uF Case s| ceoaucinoion =| ELerTRa =| HOU th (253, cor-1ooa-o5 | CERAMIC =O. 022uF ret c05~0320-05, TRIMMING CAP (SOPF) - £04-0157-05 | RE COAXIAL CABLE RECEPTACLE (XS - E23-0512-05, TERMINAL - E31-1488-05 | CANNECTING MIRE “415-4408 PARTS LIST Les articles nonmentionnes dans e Parts No. ne sont pas fours. Tele ome Parts No. werden nit getofert. Ref, No, [Adéress]New] Parts No. Description Pes om #i|t ein) wa es BAAD a Ea0-1173-05 | PIN cANNEcTaR re E40-0473-05 | PIN CONNECTOR (MINI-4P) Sh sa ©40-0273-05 | PIN CONNECTOR (MINL.2P) | 36 10-0573-05 | PIN CONNECTOR my -3 E40-0273-05 | PIN CONNECTRY (HINT.2P) mu PIN CONNECTOR (HINT .2P) | ue €40-0473-05 | PIN CONNECTAR (MINT. 4P) na E40-0373-05 | PIN CANNECTOR CMINISP) ha €40-0673-05 | PIN CANNECTOR 15 16 E40-0073-05 | PIN CONNECTOR CHINI AP) - y32-0795-04 | HEX - L92-0110-05 BEAD CORE (FOR_LT?L7B) | Ft | C7i-0259-05 | CRYSTAL FILTER (45. o5nHZ) Fe x| Cri-ageo-o5 | ERYSTAL FILTER (& a3RHZ) u tao-1st1-13 | SMALL FLxeD INDUCTARCTSOUM) ts Uao-s32-14 | SMALL FIXED INDUETAR(O. 33UH) La Lag-2262-14 | seu FIXED INDUCTARCO. 22H) is -8 Lag-2292-14 | SMALL FIXED TNDUCTAR (1. 2UH) re) Lag-tart-13 | SmeLL FIXED INDUCTAR (100UH) cio 40-1021-0! FIED INDUCTOR IZ) tn Lag-1n1=13 FIXED INDUCTARCIMHZ) Liz +13 Lan-2701-14 FIXED INDUCTERC7UHY ua Lao-201-14 FIXED INDUCTOR 22UH) LS 6 Lao-a70r-1a | FIXED TNDUCTARCATUH) uz | | tao-to01-14 FIXED TNDUCTOR( 10UH) ua | | Gao-azgr-ta FIXED INDUCTOR(A. 2UH) Leo | | Lap-ea9r-14 | sau FixeD INDUCTARCa. 2UH) at Lag-er92-14 | SHALL FIXED INDUCTAR(2. 7UH) lee Cao-1592-14 | SMALL FIXED INDUCTOR. SUH) Le Lao-a29i-14 | SheLL FIXED INDUCTOR(G. 2H) (za Vao-ro2t-13 | SHALE FIXED INDUCTARCtimZ) Ls. Lao-2792-14 | SMALL. FIXED INDUCTAR(2. 7H) (26 27 Lao-Se9t-14 | SmALL FIXED INDUCTAR(S: GUND re Lag-1892-14 | SMALL. FIXED INDUCTOR 1. BUH) 29 Lag-1062-14 | ShetL FIXED INDUCTARC1UHZ) Uso Lag-1992-14 | SMALL FINED INDUCTOR. GUM) Lag-1o2t-13 | SmeLL FINED INDUCTARCaMZ) Lag-3991-14 SMALL FIXED INDUCTER(S. 9UK) Uao-6an2-14 | SRACL FIXED INDUCTAR(O: 60H) Can-s9e2-14 | SMALL FIXED INDUCTOR(D, SUM) Uan-een2-14 SMALL FIXED INDUCTER(O, B8UH) Lag-1o2t~13 | SmALL FIXED INDUCTARCIMHZ) La0-S691-14 FIXED TNDUCTOR(S. 6UH) Uao-39a2-14 FIXED INDUCTOR (O, J9UMD tag-2282-14 FIXED TNDUCTAR(O, 220K) tan-39r2-14 FIXED INDUCTOR(O, 39UH) Lag-1021-13 FAMED INDUCTOR IMHZ) tan-2292-18 FIXED INDUCTORCL. 2UH) (ao-a7ee~ 14 FIXED INDUCTOR (O. 47UM) ) Canara 1a FEXED INDUCTOR (O. 27UH) Lao-a7e2-14 FINED INDUCTOR(O. 470M) Las Lan-1921-13 FIXED INDUCTARCIMHZ) Sa Vag-1s92-14 | SACL FIXED INDUCTARCL. SUH) ts tao-1092-14 | SMALL FIXED INDUCTOR IUHZ) 45