PCIe 100MHz Reference

Clock Test
Li, Yu (yu.li@tektronix.com)
26 AUGUST 2021
Revison History
Revision Date Author Description
v0.1 2021/07/15 Li, Yu Initial Release.

26 AUGUST 2021 2
Overview
HCSL Interface for PCIe Refclk
Principle of HCSL: High-Speed Current Steering Logic
Open-Source
Outputs HCSL接口是事实上的 接收端为
14 mA PCIe参考时钟的接口。 高阻输入

Rt = 50Ω
I+ I-=14mA I+=14mA
Output+ +700mV

I-
Output- +0mV
Rt = 50Ω
I+=0mA I-=0mA
电流导引开关，
当其开启时，
Rds(on) ≈ 17 Ω 差分的任何一端的电流在0mA~14mA之间变化，因
HCSL Output Structure 此单端摆幅为50 Ω × 14 mA = 700 mV；从而共模 HCSL Input Structure

电压大致在350 mV左右。

26 AUGUST 2021 4
HCSL Interface for PCIe Refclk
Termination for Signal Integrity: Source Termination

Termination for Applications Where Driver and Receiver will be on Separate PCBs
(CEM Card Application)

Rs with MOSFET Rds(on) forms

50Ω to avoid excessive ringing

Two Rt provide the appropriate voltage

swing for the Clock Receiver

26 AUGUST 2021 5
HCSL Interface for PCIe Refclk
Termination for Signal Integrity: Source Termination

Termination for Applications Where Driver and Receiver will be on Separate PCBs
(Embedded PCIe or SRIS Application)

near to the clock receiver

as close as possible

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Test Setup for PCIe Refclk
No Termination and 2pF Load to GND at the test point Except 32GT/s Jitter

using high-impedance single-ended or

differential probes to connect here

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Test Setup for PCIe Refclk
Only for 32GT/s Clock Jitter Test
“ Reference clock jitter measured with a phase noise analyzer, and 32.0 GT/s reference clock jitter
measured with an oscilloscope, are tested with the reference clock terminated by 50 Ohm
terminations without a channel. ”
- Quoted from PCIe 5.0 Base Spec “8.6.1 Refclk Test Setup”

Reference
Oscilloscope
Clock
Rs
Coaxial Cable

Coaxial Cable
Rs
ZC-DC ZC-DC 50 ohm 50 ohm

26 AUGUST 2021 9
Test Setup for PCIe Refclk
Using the CLB Board: merely used for jitter test
• The CLB (Compliance Load Board) is not optimized for clock compliance tests:
• Normal test configuration connect 50 Ohm SMA cables to Scope input with 50 Ohm
termination
• This does not fit to the specified test load configuration: No Termination and 2pF load to
GND
• Due to 50 Ohm termination this setup does Edge SMP to Scope
not allow crossing point and rise/fall time input with 50 ohm
tests termination Connect for
• Jitter tests will have only small difference to differential
open circuit test active Probe
• Using a differential active probe provides the 2pF Load to GND
open circuit, but can not measure the clock
crossing point.
• Best would be to use two single ended active 这样的结构出现在CLB 2.0、3.0中，但
probes, But there is no GND Pin at the probe 是在CLB 4.0中则不再有2pF电容到地，
connector of the CLB! 也没有排针引出供差分探棒连接

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Test Setup for PCIe Refclk
Oscilloscope Requirement
• BW >= 5 GHz; Sample Rate: >= 20 GSa/s, <= 50 GSa/s
• Record Length = 1.6 ms(Number of Intervals >= 160,000)

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Test Setup for PCIe Refclk
Measurement Categories
Categories Examples Details
AC Specifications Edge Rate, Diff Voltage, Period, Cycle-to- Measurements require single-
cycle jitter, Duty Cycle, DC Impedance… ended & differential waveforms.
Pass/fail limits are independent of
data rate
Data Rate Independent Refclk Freq, SSC Freq, SSC Deviation, Measurements with differential
Transport Delay, SSC df/dt, … waveforms. Pass/fail limits are
independent of data rate.
Transport delay only applies to CC
Unfiltered Low Low freq jitter mask requirement (above) Measured from 30KHz to 500KHz
Frequency Jitter
Filtered Phase Jitter High freq jitter Limits only provided for CC
architecture

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AC Specifications
• Singled-Ended Voltage Requirements
• Differential Volatef Requirements
• Differential Timing Requirements
REFCLK DC Specifications and AC Timing Requirements
Symbol Description Min Max Unit Note
VMAX Absolute Max input voltage +1.15 V Single-Ended Probe
VMIN Absolute Min input voltage -0.3 V Single-Ended Probe
VCROSS Absolute crossing point voltage +250 +550 mV Single-Ended Probe
VCROSS DELTA Variation of VCROSS over all rising clock edges +140 mV Single-Ended Probe
Rise-Fall Matching Rising edge rate (REFCLK+) to falling edge rate (REFCLK-) matching 20 % Single-Ended Probe
ZC-DC Clock source DC impedance 40 60 Ω Single-Ended Probe
Rising Edge Rate Rising Edge Rate The Classified 0.6 4.0 V/ns Single-Ended or Diff Probe
Falling Edge Rate Falling Edge Rate
Order 0.6 4.0 V/ns Single-Ended or Diff Probe
VIH Differential Input High Voltage +150 mV Single-Ended or Diff Probe
VIL Differential Input Low Voltage -150 mV Single-Ended or Diff Probe
VRB Ring-back Voltage Margin -100 +100 mV Single-Ended or Diff Probe
TSTABLE Time before VRB is allowed 500 ps Single-Ended or Diff Probe
TPERIOD AVG Average Clock Period Accuracy -300 +2800 ppm Single-Ended or Diff Probe
TPERIOD AVG_32G_CC Average Clock Period Accuracy for devices that support 32.0 GT/s in CC Mode at any speed -100 +2600 ppm Single-Ended or Diff Probe
TPERIOD AVG_32G_SRIS Average Clock Period Accuracy for devices that support 32.0 GT/s in SRIS Mode at any speed -100 +1600 ppm Single-Ended or Diff Probe
TPERIOD ABS Absolute Period (including Jitter and Spread Spectrum modulation) 9.847 10.203 ns Single-Ended or Diff Probe
Absolute Period (including Jitter and Spread Spectrum modulation) for devices that support
TPERIOD ABS_32G_CC 9.849 10.201 ns Single-Ended or Diff Probe
32.0 GT/s in CC Mode at any speed
Absolute Period (including Jitter and Spread Spectrum modulation) for devices that support
TPERIOD ABS_32G_SRIS 9.849 10.181 ns Single-Ended or Diff Probe
32.0 GT/s in SRIS Mode at any speed
TCCJITTER Cycle to Cycle jitter 150 ps Single-Ended or Diff Probe
Duty Cycle Duty Cycle 40 60 % Single-Ended or Diff Probe

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 Single-Ended Voltage Requirement
VMAX, VMIN, VCROSS, VCORSS DELTA
VMAX
REFCLK-

VCROSS(max)= +550 mV

VCROSS(falling) VCROSS(falling)
VCROSS(rising) VCROSS(rising)
VCROSS(falling)
VCROSS(rising)

VCROSS(max)= +250 mV

REFCLK+
VMIN

• VMAX和VMIN的要求；
• VCROSS的要求：REFCLK+与REFCLK-的所有交叉点的位置都必须在+250 mV ~ 550 mV之间；
• VCROSS DELTA的要求：仅仅之对REFCLK+上升沿（即差分信号的上升沿）所在的交叉点进行要求
V𝐶𝑟𝑜𝑠𝑠 𝑟𝑖𝑠𝑖𝑛𝑔 . 𝑚𝑎𝑥 − V𝐶𝑟𝑜𝑠𝑠 𝑟𝑖𝑠𝑖𝑛𝑔 . 𝑚𝑖𝑛 ≤ 140 𝑚𝑉

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 Single-Ended Voltage Requirement
Rise-Fall Matching: only for REFCLK+ Rising Edges
REFCLK-

VCROSS(max)= +550 mV

VCROSS(rising).median + 75 mV VCROSS(rising)
VCROSS(rising)
VCROSS(rising).median
VCROSS(rising)
VCROSS(rising).median - 75 mV

VCROSS(max)= +250 mV

REFCLK+

• 计算REFCLK+上升沿与REFCLK-下降沿相交的交叉点的中位值电压，VCROSS(rising).median
• 在同一个差分上升沿处，计算单端信号在VCROSS(rising).median – 75mV ~ VCROSS(rising).median +
75mV电压范围内的REFCLK+的上升时间和REFCLK-的下降时间，分布记作tr+(n)和tf-(n)：
150 𝑚𝑉 Τ𝑡𝑟+ 𝑛 − 150 𝑚𝑉 Τ𝑡𝑓− 𝑛
𝑀𝑎𝑡𝑐ℎ𝑖𝑛𝑔 = ≤ 20%
min 150 𝑚𝑉 Τ𝑡𝑟+ 𝑛 , 150 𝑚𝑉 Τ𝑡𝑓− 𝑛
其中，n为差分时钟的第n个上升沿。

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Diff Voltage Requirements
VIH, VIL, Ringback Voltage and Timing
高电平的ring back最低点
电压必须要大于+100mV
Rising TSTABLE Falling TSTABLE
Edge Edge
Rate Rate
VIH

VIH(min)= +150 mV

VRB(max)= +100 mV

0V

VRB(min)= -100 mV

VIL(max)= -150 mV
VIL

上升下降沿在-150mV~+150mV 低电平的ring back最高点

的范围内必须单调 电压必须要小于-100mV

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Diff Timing Requirements
TPERIOD ABS,TPERIOD AVG, TCCJITTER, Duty Cycle
⚫ 计算差分时钟信号的每一个周期值及正脉冲的持续时间，分别记作TPERIOD(n)和THIGH(n)，其中n为
第那个差分时钟周期；
⚫ TPERIOD ABS的要求： TPERIOD(n)必须在所要求的min和max之间：
TPERIOD ABS Absolute Period (including Jitter and Spread Spectrum modulation) 9.847 10.203 ns Single-Ended or Diff Probe
TPERIOD ABS_32G_CC Absolute Period (including Jitter and Spread Spectrum modulation) for devices that support 9.849 10.201 ns Single-Ended or Diff Probe
32.0 GT/s in CC Mode at any speed
TPERIOD ABS_32G_SRIS Absolute Period (including Jitter and Spread Spectrum modulation) for devices that support 9.849 10.181 ns Single-Ended or Diff Probe
32.0 GT/s in SRIS Mode at any speed

⚫ TPERIOD AVG的要求：偏离理想值100MHz(即10ns的范围)必须在min和max之间：
𝑇𝑃𝐸𝑅𝐼𝑂𝐷 1 + 𝑇𝑃𝐸𝑅𝐼𝑂𝐷 2 + ⋯ 𝑇𝑃𝐸𝑅𝐼𝑂𝐷 𝑁
𝑇𝑃𝐸𝑅𝐼𝑂𝐷 𝐴𝑉𝐺 =
𝑁
𝑇𝑃𝐸𝑅𝐼𝑂𝐷 𝐴𝑉𝐺 −10𝑛𝑠
要求：𝑚𝑖𝑛 ≤ ≤ 𝑚𝑎𝑥
10𝑛𝑠
TPERIOD AVG Average Clock Period Accuracy -300 +2800 ppm Single-Ended or Diff Probe
TPERIOD AVG_32G_CC Average Clock Period Accuracy for devices that support 32.0 GT/s in CC Mode at any speed -100 +2600 ppm Single-Ended or Diff Probe
TPERIOD AVG_32G_SRIS Average Clock Period Accuracy for devices that support 32.0 GT/s in SRIS Mode at any speed -100 +1600 ppm Single-Ended or Diff Probe

• TCCJitter(n)= TPERIOD(n+1) - TPERIOD(n)和Duty Cycle(n)= THIGH(n) / TPERIOD(n)；

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Data Rate Independent Refclk Parameters
• 主要针对SSC进行了规定。
• PCIe的SSC扩频是由100MHz参考时钟提供的。
Data Rate Independent Refclk Parameters Requirements

Symbol Description Min Max Unit Note

FREFCLK Refclk Frequency 99.97 100.03 MHz Single-Ended or Diff Probe
FREFCLK_32G Refclk Frequency for devices that support 32.0 GT/s 99.99 100.01 MHz Single-Ended or Diff Probe
FSSC SSC frequency range 30 33 kHz Single-Ended or Diff Probe
TSSC-FREQ-DEVIATION SSC deviation -0.5 0 % Single-Ended or Diff Probe
SSC deviation for devices that support 32.0 GT/s and
TSSC-FREQ-DEVIATION_32G_SRIS -0.3 0 % Single-Ended or Diff Probe
SRIS when operating in SRIS mode at all speeds
TTRANSPORT-DELAY Tx-Rx transport delay 12 ns Single-Ended or Diff Probe
TSSC-MAX-FREQ-SLEW Max SSC df/dt 1250 ppm/μs Single-Ended or Diff Probe

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 Refclk with SSC Modulation

100 MHz Refclk with -5000ppm SSC

-9 dB Attenuation by
SSC can significantly
reduce system EMI
radiation 100 MHz Refclk without SSC

Time Trend of Period(Ch1)

Time Trend of Period(Ch2)

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 Refclk with SSC Modulation
Theory of SSC
• 不带SSC的理想时钟的表达式为：A0 𝑠ℎ𝑎𝑝𝑒 2𝜋𝑓0 𝑡 + 𝜙0 ，其中A0 为时钟的幅度， 𝑓0 为时钟频率， 𝜙0
为初始相位，shape函数指的是波形的归一化形状函数，无量纲。例如，若时钟为正弦波，则shape =
cos，若时钟为方波，则shape = rect；那么带SSC的时钟的表达式则为：
𝑡
y = 𝐴0 𝑠ℎ𝑎𝑝𝑒 2𝜋𝑓0 𝑡 + 𝜙0 + 2𝜋𝑓0 𝐷𝑓 න 𝑚 𝜎 𝑑𝜎
−∞
𝐷𝑓 为SSC调制相对于时钟频率的频偏峰值，无量纲； 𝑚 𝜎 为归一化的SSC调制的形状函数，无量纲。
• 对于PCIe SSC来说，𝑚 𝑡 为一个三角波函数，即
𝑚 𝑡 = 0.5 + 0.5 ∗ 𝑠𝑎𝑤𝑡𝑜𝑜𝑡ℎ(2𝜋𝑓𝑠𝑠𝑐 𝑡)
• PCIe SSC一般采用下变频，这会导致频率稍微减小，周期稍微变大，对于非32G SRIS来说， 𝐷𝑓 =
− 5000 𝑝𝑝𝑚，对于32G SRIS来说， 𝐷𝑓 = −3000 𝑝𝑝𝑚。
• 假设第n+1个时钟边沿和第n个时钟边沿的时刻分别为𝑡n+1 和 𝑡n ，那么有：
1/𝑓0 1
𝑡𝑛+1 − 𝑡𝑛 = ≈ 1 − 𝐷𝑓 𝑚 𝑡𝑛
1 + 𝐷𝑓 𝑚 𝑡𝑛 𝑓0
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Refclk with SSC Modulation
Triangle-Profile Modulation

10.05 ns

-5000 ppm

10.00 ns
经过SSC调制之后，周期不再是固定值10ns，而是随
时间缓慢地周期性地变化。如上图，周期随时间呈
三角周期函数变化。

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Refclk with SSC Modulation
Period Trend SSC Profile v.s. TIE Trend

进行积分，为一个
二次函数

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Unfiltered Low Frequency Jitter
• 这些参数要求主要是规定SSC的多次谐波的spur特性。
• 验证TIE的频谱特性满足低频模板要求，时钟恢复方法选择Constant Ref Clock
• Silicon Labs的分析工具中直接称这一项为“SSC Phase Jitter”
 Unfiltered Low Frequency Jitter Requirements
• 采集差分时钟信号波形，得到其上
30-33 KHz
升沿在电压0处的时刻，记为：
25000 ps
Tedge(n)，其中n代表第n个上升
沿的位置。而这个差分时钟的周期
100 KHz 为P；那么TIE(n)可以表达为：
TIE 𝑛 = 𝑇𝑒𝑑𝑔𝑒 𝑛 − 𝑛𝑃 − 𝛿
Jitter (ps pp)

1000 ps
其中，P为已知量， 𝛿是一个常
数，为未知量，需要最小二乘法或
者其他方法来确定其值。
500 KHz
• TIE 𝑛 为一个时间离散序列，可以
对其进行傅里叶变换，求得其频
25 ps
谱。
• 其频谱在30 kHz ~ 500kHz的范围
内必须满足左图的频谱模板要求
Frequency (Hz)

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Spectrum of TIE

傅里叶变换
得到频谱
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Filtered Phase Jitter
• 这个抖动是指在Rx Latch进行0/1判决输入处所看到的抖动；
• 会进行两步滤波：
• Edge Filtering：补偿由于示波器有限采样率所造成的误差；
• PLL Difference Function：考虑到TXPLL、RXPLL和CDR的性能对抖动的影响；

• 使用CLB治具其他From Factor的治具，采用同轴线缆连接到示波器中，示波器输
入阻抗设置为50 Ω。这种替代方法可以用于评估Filtered Phase Jitter；
Common Refclk Architecture
Case 1: Transmitter in the Motherboard Case 2: Transmitter in the Adapter
Motherboard Adapter Motherboard Adapter
Transmitter in the RC chip Ext_Tx_data Receiver in the EP Chip Receiver in the RC Chip Ext_Tx_data Transmitter in the EP chip

Tx Latch Channel Rx Latch Rx Latch Channel Tx Latch

Int_Rx_data Int_Rx_data
CDR H3(s) H3(s) CDR
Int_Tx_clk Int_Tx_clk
H1(s) Tx PLL Tx PLL H1(s)
_data Int_Rx_clk Int_Rx_clk _data
Rx PLL H2(s) H2(s) Rx PLL

Ext_Tx_clk Ext_Rx_clk Ext_Rx_clk Ext_Tx_clk

Refclk Channel Refclk Channel

Ext_delay = Ext_Tx_data + Ext_Tx_clk – Ext_Rx_clk ≤10.0 ns

Int_Tx_delay = Int_Tx_clk_data ≤2.0 ns
Int_Rx_delay = Int_Rx_clk – Int_Rx_data ≤2.0 ns
Total delay = Ext_delay + Tx_int_delay – Rx_int_delay ≤12.0 ns

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Common Refclk Architecture
The Spec Limits

PCIe CEM 5.0

的spec放宽为
0.2ps

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PCIe Base 2.0
Jitter Difference Function Requirement for 2.5 GT/s Speed

• PCIe Base 2.0 & 3.0沿用PCIe CEM PLL #1 3.0 dB Peaking

1.1中的定义，未作改动 ωn1 = 11.83·2π Mrad/s
f1_3dB = 22 MHz
• PCIe Base 4.0改动了2.5GT/s的时 ζ1 = 0.54
钟抖动规范
PLL #2 3.0 dB Peaking

ωn2 = 0.807·2π Mrad/s

𝐻 𝑠 = 𝐻1 𝑠 − 𝐻2 𝑠 𝑒 −𝑠∗𝑇 ∙ 𝐻3 𝑠 f2_3dB = 1.5 MHz
ζ2 = 0.54
2.5 GT/s in PCIe Base 2.0 𝑇 = 12𝑛𝑠 𝑚𝑎𝑥

CDR
注意此处：延迟量是和H2相结合
的，这意味着最差情况只考虑 f3_3dB(min) = 1.5 MHz

RXPLL路径上的延迟量更大。而在
后续的规范中，则会同时考虑
TXPLL路径延迟量较大和RXPLL路 1 Combinations
径上延迟量较大这两种情况

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PCIe Base 2.0
Jitter Difference Function Requirement for 5.0 GT/s Speed

• PCIe Base 3.0沿用PCIe Base 2.0中 PLL #1 0.01 dB Peaking 1.0 dB Peaking
的定义，未作改动 ωn1 = 1.82·2π Mrad/s
f1_3dB(min) = 5.0 MHz
• PCIe Base 4.0改动了5.0GT/s的时 ζ1 = 1.16
钟抖动规范 ωn1 = 4.31·2π Mrad/s
f1_3dB(max) = 8.0 MHz
ζ1 = 1.16

𝐻 𝑠 = 𝐻1 𝑠 𝑒 −𝑠∗𝑇 − 𝐻2 𝑠 PLL #2 3.0 dB Peaking

5.0 GT/s in PCIe Base 2.0 𝑇 = 12𝑛𝑠 𝑚𝑎𝑥
ωn2 = 8.61·2π Mrad/s
f2_3dB(max) = 16 MHz
ζ2 = 0.54
注意此处：延迟量是和H1相结合的，
这意味着最差情况只考虑TXPLL路径 CDR
上的延迟量更大。而在后续的规范中，
f3_3dB(min) = 1.5 MHz
则会同时考虑TXPLL路径延迟量较大
和RXPLL路径上延迟量较大这两种情 2 Combinations
况。并且后续规范会考虑CDR的影响

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PCIe Base 3.0
Jitter Difference Function Requirement for 2.5 GT/s Speed

• PCIe Base 2.0 & 3.0沿用PCIe CEM PLL #1 3.0 dB Peaking

1.1中的定义，未作改动 ωn1 = 11.83·2π Mrad/s
f1_3dB = 22 MHz
• PCIe Base 4.0改动了2.5GT/s的时 ζ1 = 0.54
钟抖动规范
PLL #2 3.0 dB Peaking

ωn2 = 0.807·2π Mrad/s

𝐻 𝑠 = 𝐻1 𝑠 − 𝐻2 𝑠 𝑒 −𝑠∗𝑇 ∙ 𝐻3 𝑠 f2_3dB = 1.5 MHz
ζ2 = 0.54
2.5 GT/s in PCIe Base 3.0 𝑇 = 12𝑛𝑠 𝑚𝑎𝑥

CDR
注意此处：延迟量是和H2相结合
的，这意味着最差情况只考虑 f3_3dB(min) = 1.5 MHz

RXPLL路径上的延迟量更大。而在
后续的规范中，则会同时考虑
TXPLL路径延迟量较大和RXPLL路 1 Combinations
径上延迟量较大这两种情况

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PCIe Base 3.0
Jitter Difference Function Requirement for 5.0 GT/s Speed

• PCIe Base 3.0沿用PCIe Base 2.0中 PLL #1 0.01 dB Peaking 1.0 dB Peaking
的定义，未作改动 ωn1 = 1.82·2π Mrad/s
f1_3dB(min) = 5.0 MHz
• PCIe Base 4.0改动了5.0GT/s的时 ζ1 = 1.16
钟抖动规范 ωn1 = 4.31·2π Mrad/s
f1_3dB(max) = 8.0 MHz
ζ1 = 1.16

𝐻 𝑠 = 𝐻1 𝑠 𝑒 −𝑠∗𝑇 − 𝐻2 𝑠 PLL #2 3.0 dB Peaking

5.0 GT/s in PCIe Base 3.0 𝑇 = 12𝑛𝑠 𝑚𝑎𝑥
ωn2 = 8.61·2π Mrad/s
f2_3dB(max) = 16 MHz
ζ2 = 0.54
注意此处：延迟量是和H1相结合的，
这意味着最差情况只考虑TXPLL路径 CDR
上的延迟量更大。而在后续的规范中，
f3_3dB(min) = 1.5 MHz
则会同时考虑TXPLL路径延迟量较大
和RXPLL路径上延迟量较大这两种情 2 Combinations
况。并且后续规范会考虑CDR的影响

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PCIe Base 3.0
Jitter Difference Function Requirement for 8.0 GT/s Speed

PLL #1 0.01 dB Peaking 2.0 dB Peaking

PCIe Base 4.0的8GT/s和16GT/s速率的PLL要
求与PCIe Base 3.0的8GT/s相同 ωn1 = 0.448 Mrad/s ωn1 = 6.02 Mrad/s
f1_3dB(min) = 2.0 MHz
ζ1 = 14 ζ1 = 0.73
ωn1 = 0.896 Mrad/s ωn1 = 12.04 Mrad/s
f1_3dB(max) = 4.0 MHz
ζ1 = 14 ζ1 = 0.73

𝐻 𝑠 = 𝐻1 𝑠 𝑒 −𝑠∗𝑇 − 𝐻2 𝑠 ∙ 𝐻3 𝑠
PLL #2 0.01 dB Peaking 1.0 dB Peaking
𝐻 𝑠 = 𝐻2 𝑠 𝑒 −𝑠∗𝑇 − 𝐻1 𝑠 ∙ 𝐻3 𝑠
8.0 GT/s in PCIe Base 3.0
𝑇 = 12𝑛𝑠 𝑚𝑎𝑥 ωn1 = 0.448 Mrad/s ωn2 = 4.62 Mrad/s
f2_3dB(min) = 2.0 MHz
ζ1 = 14 ζ2 = 1.15
ωn2 = 1.12 Mrad/s ωn2 = 11.53 Mrad/s
总共有4*4*2=32种可能性，但是由于 f2_3dB(max) = 5.0 MHz
ζ2 = 14 ζ2 = 1.15
PLL #1和PLL 2#有一个极限值参数相同，
因此需要去掉一个重复项，其实，只有 CDR
31项可能性。PCIe Base 4.0规范种说有 32 Combinations
64种是错误的。 f3_3dB(min) = 10 MHz

26 AUGUST 2021 36
PCIe Base 4.0
Jitter Difference Function Requirement for 2.5 GT/s Speed

注意到：PLL #1和PLL PLL #1 0.01 dB Peaking 3.0 dB Peaking

2#的参数规格一样， ωn1 = 0.336 Mrad/s ωn1 = 5.09 Mrad/s

f1_3dB(min) = 1.5 MHz
因此只有16种可能性， ζ1 = 14 ζ1 = 0.54
否则则有32种可能性 ωn1 = 4.93 Mrad/s ωn1 = 74.68 Mrad/s
f1_3dB(max) = 22.0 MHz
ζ1 = 14 ζ1 = 0.54

𝐻 𝑠 = 𝐻1 𝑠 𝑒 −𝑠∗𝑇 − 𝐻2 𝑠 ∙ 𝐻3 𝑠
PLL #2 0.01 dB Peaking 3.0 dB Peaking
𝐻 𝑠 = 𝐻2 𝑠 𝑒 −𝑠∗𝑇 − 𝐻1 𝑠 ∙ 𝐻3 𝑠
2.5 GT/s in PCIe Base 4.0
𝑇 = 12𝑛𝑠 𝑚𝑎𝑥 ωn2 = 0.336 Mrad/s ωn2 = 5.09 Mrad/s
f2_3dB(min) = 1.5 MHz
ζ2 = 14 ζ2 = 0.54
ωn2 = 4.93 Mrad/s ωn2 = 74.68 Mrad/s
• PCIe Base 2.0 & 3.0沿用PCIe CEM f2_3dB(max) = 22.0 MHz
ζ2 = 14 ζ2 = 0.54
1.1中的定义，未作改动
• PCIe Base 4.0改动了2.5GT/s的时 CDR
钟抖动规范 16 Combinations
f3_3dB(min) = 1.5 MHz

26 AUGUST 2021 37
PCIe Base 4.0
Jitter Requirement for 5.0 GT/s Speed

PLL #1 0.01 dB Peaking 1.0 dB Peaking

• PCIe Base 2.0 & 3.0沿用PCIe CEM
ωn1 = 1.12 Mrad/s ωn1 = 11.01 Mrad/s
1.1中的定义，未作改动 f1_3dB(min) = 5.0 MHz
ζ1 = 14 ζ1 = 1.16
• PCIe Base 4.0改动了2.5GT/s的时
钟抖动规范 f1_3dB(max) = 16 MHz
ωn1 = 3.58 Mrad/s ωn1 = 35.26 Mrad/s
ζ1 = 14 ζ1 = 1.16

𝐻 𝑠 = 𝐻1 𝑠 𝑒 −𝑠∗𝑇 − 𝐻2 𝑠 ∙ 𝐻3 𝑠
PLL #2 0.01 dB Peaking 3.0 dB Peaking
𝐻 𝑠 = 𝐻2 𝑠 𝑒 −𝑠∗𝑇 − 𝐻1 𝑠 ∙ 𝐻3 𝑠
5.0 GT/s in PCIe Base 4.0
𝑇 = 12𝑛𝑠 𝑚𝑎𝑥 ωn2 = 1.79 Mrad/s ωn2 = 26.86 Mrad/s
f2_3dB(min) = 8.0 MHz
ζ2 = 14 ζ2 = 0.54
ωn2 = 3.58 Mrad/s ωn2 = 53.73 Mrad/s
总共有4*4*2=32种可能性，但是由于 f2_3dB(max) = 16 MHz
ζ2 = 14 ζ2 = 0.54
PLL #1和PLL 2#有一个极限值参数相同，
因此需要去掉一个重复项，其实，只有 CDR
31项可能性。PCIe Base 4.0规范种说有 32 Combinations
64种是错误的。 f3_3dB(min) = 5 MHz

26 AUGUST 2021 38
PCIe Base 4.0
Jitter Difference Function Requirement for 8.0 GT/s Speed and 16GT/s Speed

PLL #1 0.01 dB Peaking 2.0 dB Peaking

In PCIe Base 4.0 the 16GT/s speed and the
8GT/s speed use the same PLL limits ωn1 = 0.448 Mrad/s ωn1 = 6.02 Mrad/s
f1_3dB(min) = 2.0 MHz
ζ1 = 14 ζ1 = 0.73
ωn1 = 0.896 Mrad/s ωn1 = 12.04 Mrad/s
f1_3dB(max) = 4.0 MHz
ζ1 = 14 ζ1 = 0.73

𝐻 𝑠 = 𝐻1 𝑠 𝑒 −𝑠∗𝑇 − 𝐻2 𝑠 ∙ 𝐻3 𝑠
PLL #2 0.01 dB Peaking 1.0 dB Peaking
8.0 GT/s and 16.0 GT/s in 𝐻 𝑠 = 𝐻2 𝑠 𝑒 −𝑠∗𝑇 − 𝐻1 𝑠 ∙ 𝐻3 𝑠
PCIe Base 4.0 𝑇 = 12𝑛𝑠 𝑚𝑎𝑥 ωn1 = 0.448 Mrad/s ωn2 = 4.62 Mrad/s
f2_3dB(min) = 2.0 MHz
ζ1 = 14 ζ2 = 1.15
ωn2 = 1.12 Mrad/s ωn2 = 11.53 Mrad/s
总共有4*4*2=32种可能性，但是由于 f2_3dB(max) = 5.0 MHz
ζ2 = 14 ζ2 = 1.15
PLL #1和PLL 2#有一个极限值参数相同，
因此需要去掉一个重复项，其实，只有 CDR
31项可能性。PCIe Base 4.0规范种说有 32 Combinations
64种是错误的。 f3_3dB(min) = 10 MHz

26 AUGUST 2021 39
PCIe Base 5.0
Jitter Difference Function Requirement for 2.5 GT/s – 16GT/s Speed

Good News: all the same as PCIe Base 4.0

26 AUGUST 2021 40
PCIe Base 5.0
Jitter Difference Function Requirement for 32.0 GT/s Speed

注意到：PLL #1和PLL PLL #1 0.01 dB Peaking 2.0 dB Peaking

2#的参数规格一样， ωn1 = 0.112 Mrad/s ωn1 = 1.51 Mrad/s

f1_3dB(min) = 0.5 MHz
因此只有16种可能性， ζ1 = 14 ζ1 = 0.73
否则则有32种可能性 ωn1 = 0.403 Mrad/s ωn1 = 5.42 Mrad/s
f1_3dB(max) = 1.8 MHz
ζ1 = 14 ζ1 = 0.73

𝐻 𝑠 = 𝐻1 𝑠 𝑒 −𝑠∗𝑇 − 𝐻2 𝑠 ∙ 𝐻3 𝑠
PLL #2 0.01 dB Peaking 1.0 dB Peaking
𝐻 𝑠 = 𝐻2 𝑠 𝑒 −𝑠∗𝑇 − 𝐻1 𝑠 ∙ 𝐻3 𝑠
32.0 GT/s in PCIe Base 5.0
𝑇 = 12𝑛𝑠 𝑚𝑎𝑥 ωn1 = 0.112 Mrad/s ωn1 = 1.51 Mrad/s
f1_3dB(min) = 0.5 MHz
ζ1 = 14 ζ1 = 0.73
ωn1 = 0.403 Mrad/s ωn1 = 5.42 Mrad/s
The CDR of 32GT/s Speed is different f1_3dB(max) = 1.8 MHz
ζ1 = 14 ζ1 = 0.73
from the CDR of other speeds
CDR
16 Combinations
32.0GT/s CC

26 AUGUST 2021 41
Analysis Tool
• PCI-SIG Official: Clock Jitter Tool
• Silicon Labs: PCIe Clock Jitter Tool
PCI-SIG Clock Jitter Tool
How to download this tool？
https://www.intel.com/content/www/us/en/design/technology/high-speed-io/tools.html

26 AUGUST 2021 43
PCI-SIG Clock Jitter Tool
Only for Jitter Evaluation

将保存的波形导
入到工具中

不同的模板代表前述所讨论
的不同的滤波器的组合。

26 AUGUST 2021 44
PCI-SIG Clock Jitter Tool
Test Results

UnFiltered TIE Spectrum

Filtered TIE Spectrum

26 AUGUST 2021 45
Silicon Labs: PCIe Clock Jitter Tool
How to download this tool？

Skyworks | Timing - PCIe Clock Jitter Tool (skyworksinc.com)

26 AUGUST 2021 46
Silicon Labs: PCIe Clock Jitter Tool
使用Silicon Labs的工具可以完成所有规范要求的测试，包括AC Spec、SSC、Unfiltered Low Frequency jitter（即
SSC Phase Jitter）、Filtered Jitter

一次可以完成所有滤
波器组合的测试
26 AUGUST 2021 47
Silicon Labs: PCIe Clock Jitter Tool

所有的结果都在
同一份报告中，
报告整齐规范

26 AUGUST 2021 48
Ref-clk BASE-TX Software (option PCE5)
• Ref-clock jitter and signal quality
tests built into same software
used for data signal validation.
• Integrated Silicon Labs
algorithms for ref-clock analysis.
• User may enable scope noise de-
embed to improve jitter
measurement accuracy.
• Manual or automated modes
supported.

26 AUGUST 2021 49