Surface Laptop 3 MB HOOK-P - DV

5 4 3 2 1
Table of Contents
Page Title Page Title Page Title
01 TABLE OF CONTENTS 31 Power/Volume Button Debug 61 VDDPSB and VDDP
D 02 Build Options 32 EMPTY 62 +1.8VSB & Load SW D
03 BLOCK DIAGRAM 33 Debug Conn 63 CHARGER

04 CLOCK DISTRIBUTION 34 SAM_1_PWR_ADC_Debug 64 +5V Load SW
05 SIGNAL & RESET MAP 35 SAM_2 65 +3P3V Load SW
06 POWER FLOW 1 of 3 36 EMPTY 66 APU Core Controller
07 POWER FLOW 2 of 3 37 Level Shifters 67 APU VDDCORE Phases
08 POWER FLOW 3 of 3 38 TPM 68 VDDSOC Phase
09 I2C MAP 39 Temp Sensor / System Fan 69 EMPTY
10 APU(1)_Display 40 REALTEK ALC3269C-GRT CODEC 70 SL1 PWR/ BATT CONN.
11 APU(2)_DDR4 41 Headphone/Speaker Connector 71 SL1 SIGNALS
C C
12 APU(3)_DLS_POWER1 42 Audio Smart Amp 72 +3P3V_HPD/LCD backlight

13 APU(4)_DLS_POWER2 43 EMPTY 73 EMPTY
14 APU(5)_GND 44 M.2 SSD Connector 74 KBTP Connector
15 APU(6)_RESERVED 45 USB A 3.0 Port 75 EMPTY
16 DDR4(1)_MEMORY DOWN 46 EMPTY 76 MTE Test Points
17 DDR4(2)_MEMORY DOWN 47 EMPTY 77 USB Type-C Port
18
19
DEBUG
Mechanical Parts
48
49
EMPTY
EMPTY
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79
EMPTY
USB Type-C PD
20 APU(7)_SPI,UART,RTC, CLK 50 Wi-Fi_BT 80 Mechanical Parts
B 21 UEFI AND TOUCH SPI 51 EMPTY 81 EMPTY B
22 APU(8)_SYS PWR CONTR, I2C, HDA 52 EMPTY 82 EMPTY

23 APU(9)_CSI 53 EMPTY
24 APU(10)_PCIE,USB 54 Camera Front/IR Connector
25 EMPTY 55 VA and VCCRTC
26 EMPTY 56 EMPTY
27 EMPTY 57 eDP connector
28 Power Monitor 58 Silego Controller
29 Type-C Debug 59 +5VSB & +3P3VSB
30 Touch Controller 60 +1P2V_DUAL&++0P6V_DDR_VDDQ
A A
DBG_S - Replace with board short for MP
CAD Note: DBG_R - Replace with lower cost component for MP
Property: BUILD-OPT DBG_N - Install for Non-Debug Builds
DNP = Do Not Place DBG_D - Remove from BOM (Depopulate) for MP
DBG_T - Used for Telemetry in MP as needed
DBG_TS - Used for Telemetry in MP as needed. This part needs to be
replaced with a short if telemetry is not needed.
5 4 3 2
5 4 3 2 1
D D
BUILD-OPT BOM Assy Remarks

ALL Common DEFAULT - Populated as shown in Core schematic for all variants
DNP Common NO-STUFF for all variants
TBL1001 Common CPU selection (Moved to Common, only one SOC cfg used)
TBL3602 Common Res Jumpers (Moved to Common, only one SOC cfg used)
U23E Common Only populated to support U23e variants (Moved to Common, only one SOC cfg used)
C
TBL6601 Common U23e/U22 Part Changes (Moved to Common, only one SOC cfg used) C
TBL2301 Bd ID Res Jumpers
TBL3601 BdID Res Jumpers
TBL1601 Mem LPDDR3 Memory Assembly Options
TBL3801 TPM Security Device Options
TBL4301 SSD SSD Memory part options
SSD1 SSD Only populated for single SSD configurations.
SSD2 SSD Only populated for dual SSD configurations.
S Debug Legacy - Originally intended same as DBG_S. please replace with DBG_S, DBG_R, or DBG_D as appropriate.
DBG Debug Legacy - Same as DBG_D shown below. Part depopulated for MP.
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DBG_D Debug Debug Part - Remove from BOM(Depopulate) for MP
DBG_N Debug Non-Debug Part - Installed only in non-debug builds
DBG_R Debug Debug Part - Replace with lower cost component for MP (Ex; replace precision shunt with 0-ohm jumper)
DBG_S Debug Debug Part - Replace with board short for MP (not commonly used anymore)
DBG_T Debug Debug Part - Used for Power Telemetry in MP as needed.
DBG_D_TBL4301Debug Debug Remove for MP, Install for Debug per TBL4301
B B
XDP XDP Legacy - Same as XDP_D
XDP_D XDP Only used as needed for CPU Debug. Depopulated for MP and most EV/DV/PV assemblies.
FAN FAN Parts used to support Fan option.
A A
CAD Note:
Defaults: Footprint SMD 0201, Cap tmp Coeff X5R, 1% resistors
5 4 3 2
5 4 3 2 1
Architectural Diagram Hook-D Connector to Chimera:

Drive
CONN
Sense
CONN
IR & RGB Cameras TPM
128Mb
Dragonfly Debug connector +ALS + Accel/Gyro Nuvoton
SPI ROM
+Left & Right DMICs NationZ SPI Isolator Ntrig G5 SPI Buffer EDP Conn
D
+Left & Right Hall Effect D
Power Monitor Components
USB2 SPI ALC 3300 R ALC1304M

Right
USB-C Multiple MBD Codec L AMP
Firefly conn Type C Debug interfaces
I2C
ALC 2251 Left
HD Audio DSP
Analog audio combo jack
SSD M.2
I 2C3 U ART1 USB2[1_1] SFI1 I2C1
128GB, 256GB eSPI/SPI
512GB, 1TB 4x PCIe P _GPP[0:3]
HDA
U SB3[0_1] U SB3.1 USB A Port
USB2[0_1] USB2
DDR4 x16
DDR4 x32
LPDDR3
LPDDR3 x16
32,16,8 GB x32
LPDDR3
LPDDR3 x32
(8x) 128-bit (16b x 8) – 2 Chl -64 bit each
GB x32
DDR
C
LPDDR3
LPDDR3
16,8,4 x32
x32
(8x) C
U SB3[1_0] U SB3.1
USB2[1_0] U SB2
OR S L40
D P1 DP
PWM
PWR_SL
Backlight Controller
I 2C2 Picasso P _GPP[4] 1x PCIe Wifi abgn+ax
I 2S I2S
eDP_DP0
LCD I2C P_GFX[0:7] QCA6390
13.5" eDP
eDP 1.3 P_GPP[5:7] USB-UART
UART BT
USB C Port
CONN USB2
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USBC[1] FTDI
15" USB3[0_2] USB2[0_2]
USB3[0_3]
USB2[0_3]
Greenpak CSI0[0:3]
IOx CSI1[0:1] USBC
PWM SFI0 I2C0
USBC[0] USBC Redriver
UART UART0
KBTP USB2[0_0] USB2

B B
GPIO SAM U SBC I2C

CONN FAN
UART PWM I2C
SPI
I2C
PD Controller TCP_VBUS
16Mb I2C
SPI Flash BQ25713
I2C
Battery SPI
Battery Charger LEGEND
Connector EXT_DC_IN
8Mb
Thermal +5VSB Hook-D specific
+BATT +VSYS SPI Flash
Sensors I2C
Charging Common to Edan-A
VDDSOC_ VDDCORE
A A
ROP
VBAT Fuel Gauge FET’s RUN _ RUN
Power
PWR_SL
5 4 3 2
5 4 3 2 1
D D
DDR4-1 CH A
DDR4 - CH B
M _CHA_CLK[0..1]/#
M_CHB_CLK[0..1]/#
P CIE_WIFI_RCLK_N
GPP_CLK1N
PCIE_WIFI_RCLK_P WIFI
GPP_CLK1P
DLS 100 MHz
APU
C C
PCIECLK_SSD_DN
GPP_CLK0N
PCIECLK_SSD_DP SSD
GPP_CLK0P
100 MHz
AZ_BITCLK
HDA_BCLK AUDIO CODEC
24 MHz
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SPI_CLK
48 MHz SPI ROM
B B
TPM_CLK
17 MHz TPM
Touch_CLK
17 MHz Touch
A A
XTAL48_IN RTCX
48MHz 32.768KHz
5 4 3 2
5 4 3 2 1
SIGNAL & RESET MAP
+BAT_LDO
D
Battery VDD_BATA_PACK D
SL1_PWR_GOOD
PWR_SL1_F SW Switch 1-1 +V_ALWAYS_ON
SL1 (Diode)
TCP0_VBUS_PWR_GOOD
+VBUS_P0_CONN SW 2
USB-C +3P3VAS
+VCC_RTC
Step Down
TCP1_VBUS_PWR_GOOD
+VBUS_P1_CONN SW LDO
USB-C
Silego 3P3VA_EN 10 SLP_S4#
1 of 2 LDO
SAM_SL1_PWR_EN LS 3 4
12 SLP_S3#
1V8_SAM
TCP0_LS_EN_N Charging +1P8VAS
LS
circuit 9
SAM_PCH_PWRBTN#
EXT_DC_IN PWRBTN# SLP_S3#
TCP1_LS_EN_N & Switch
LS
5 SAM 8 RSMRST#
SLP_S5#
LPC RSMRST#
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C Power PWRBTN#_1V8 C
Button
DLS
CHG_BATDRV_A
FET 6 VSUS_ON APU
+3P3VSB SAM
+5VSB SUS_PWRGD 7
TPM
+5VSB2 ALLVSB_PG
SSD/M.2
+1P8VSB
1-2
PLTRST_BUF#
+VSYS
+VDDPSB
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PLTRST#
AND Gate
PCIe_RST0_L Buffer
+1P2V_DUAL
+2P5VPP 11 SLP_S4_DRV#
B 16 B
13
SLP_S3_DRV# SYS_PWROK 17
+1P2V_DDR_PG
PWR_GOOD
APU_SOC_EN
Silego
2 of 2 3P3V/5V
3P3V_SSD_M2
ML_3P3V_PWR_FUSE (MDP)
+VDDP
PWROK
14
+3P3V_SSD
ALL_SYS_PWRGD Power On Sequence
1 19
EN
VDDCORE
A VDDSOC 15 A
VRDY VRM_PWRGD
PWROK 18
5 4 3 2
5 4 3 2 1
U5501
Surflink Q5505 +V_ALWAYS_ON MP2269GD
+3P3VAS
Imax = 0.01A
PWR_SL1_F IRLML6402
P-MOS FET
Efficiency : 88%
BUCK ; Iout = 0.1772A
+V_ALWAYS_ON U5506
SL1_PWR_GOOD NX3P1108 +3P3VA
Imax = 0.01A
LSW ; Iout = 0.012A
R6547
3P3VA_EN +3P3V_PMI
Type C P0 Imax =0.002A
+VBUS_P0_CONN
D D
U5505
NCP170AMX180TCG +1P8VA
Imax = 0.08A
LDO ; Iout = 0.08A
3P3VA_EN
Type C P1 U7201
FPF2495
+3P3V_HPD
Imax = 0.001A
+VBUS_P1_CONN LSW ; Iout = 0.001A +VAT_LDO
Battery R5502
SL1_HPD2_EN#
+VCC_RTC
Imax =0.0002A
U5502 +1P8VAS
NCP170AMX180TCG Imax = 0.01A
LDO ; Iout = 0.01A
+3P3VAS
U6302 U6601+FET +APU_VDDCORE

U6301 BQ25713 +VSYS MP2945 Imax = 70A
NX20P5090 EXT_DC_IN Efficiency : 88%
Efficiency : 90%
USB PD BUCK ; Iout = 70A
C SAM_SL1_PWR_EN APU_SOC_EN C
U6601+FET
MP2945 +APU_VDDSOC
U7906 Efficiency : 88% Imax = 13A
NX20P5090 BUCK ; Iout = 13A
USB PD
APU_SOC_EN
TCP0_LS_SINK_EN
U7904
NX20P5090
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USB PD
TCP1_LS_SINK_EN
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NB685A
Efficiency : 88%
BUCK ; Iout =12A
SLP_S4_DRV#
+1P2V_DUAL
Imax = 12A
U6001
NB685A +V_VDDQ_VTT
Imax = 1A
LDO ; Iout =1A
B
SLP_S3_DRV# B
U7202 +VCC_EDP_BKLT_OUT
MP3376A Imax = 0.115A
Efficiency : 88%
PCH_LCD_BKLT_EN /
SAM_LCD_BKLT_EN
U4901
MP2370 IR_OUT
Efficiency : 88% Imax = 1A
BUCK ; Iout = 1A
CAM_IR_STB
A A
5 4 3 2
5 4 3 2 1
U5902 U5204 +1P2V_CAM_R

NB502/NB693 +3P3VSB LP3991
+VSYS Imax = 0A Imax = 0.2A
Efficiency : 88% LDO ; Iout = 0.2A
U6504 CAM_R_PWR_EN_R
VSUS_ON +3P3V_PANEL
NCP451
LSW ; Iout = 0.46A Imax = 0.45A U5202 +2P8V_CAM_R
D 2.8V-LD39115J28R Imax = 0.045A D
PCH_VDD_PANEL_EN / U5705 +1P8V_PANEL LDO ; Iout = 0.45A

SAM_VDD_PANEL_EN LD39115J18R Imax = 0.01A
LDO ; Iout = 0.01A CAM_R_PWR_EN
+3P3V_PANEL U5203 +2P8V_CAM_F

U6508 2.8V-LD39115J28R Imax = 0.07A
NX3P1108 +3P3V_ACC LDO ; Iout = 0.07A
LSW ; Iout = 0.5A Imax = 0.5A
CAM_F_PWR_EN
ACC_PWR_EN
R6514 U5206 +2P8V_CAM_IR
+3P3V_WWAN 2.8V-LD39115J28R Imax = 0.02A
Imax =1.5A LDO ; Iout = 0.02A
U6502 CAM_IR_PWR_EN
NCP451 +3P3V_SSD_M2
LSW ; Iout =2A Imax = 2A U5101 CAM_W_AVDD_2P8V
2.8V-LD39115J28R Imax = 0.02A
SIL_SSD_VR_EN LDO ; Iout = 0.02A
C CAM_W_PWR_EN C
U6002
NCP170AMX250TCG +2P5VPP U5205
LSW ; Iout =0.12A Imax = 0.12A NX3P1108UK +3P3V_VCM
Imax = 0.09A
SLP_S4_DRV# LSW ; Iout = 0.09A
U6511 RTD3_CAM_PWREN
NX3P1108 +3P3V
Imax = 0.75A U5208
LSW ; Iout = 0.75A
LP3991TLX-1.2/NOPB +1P2V_CAM_F
Imax = 0.2A
SLP_S4_DRV# LDO; Iout = 0.2A
U6512 CAM_F_PWR_EN_R
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NX3P1108UK +3P3V_SDXC
Imax =0.9A U6204 +1P8VSB
LSW ; Iout = 0.9A NB691 Imax = 0A
+VSYS Efficiency : 88%
PWRENJ_W# BUCK ; Iout = 5.6A
R1208 VSUS_ON / SUS_PWRGD R6206
+3VSUS_ORG +1P8V_AUDIO
Imax =0.25A Imax =0.5A
B B
U4703 R1204
RT9728 ML_3P3V_PWR_FUSE +1P8VSUS_ORG
LSW ; Iout = 0.75A Imax = 0.75A Imax =0.5A
SLP_S3_DRV#
R5213 U6205
U5201 +1P8V_CAM_F
RT9013 NX3P1108UK +1P8V_TS
Imax = 0.03A Imax = 0.452A
LDO ; Iout = 0.148A LSW ; Iout = 0.27A
R5214
SLP_S3_DRV# +1P8V_CAM_IR RTD3_TPANEL_PWR
Imax = 0.055A
U6202
R65216 SLG5NT1477VTR +1P8V
CAM_W_DOVDD_1P8V LSW ; Iout = 2A Imax = 2A
Imax =0.055A
R5215 SLP_S3_DRV#
+1P8V_CAM_R
Imax = 0.008A
A A
5 4 3 2
5 4 3 2 1
U5904 +5VSB
NB503 Imax = 0A
+VSYS Efficiency : 88%
BUCK ; Iout =6.83A
U6405 +5V
VSUS_ON NCP451 Imax = 0A
LSW ; Iout = 0A
D
SLP_S3_DRV# D
U6407 +5V_TS
NCP451 Imax = 0.22A
LSW ; Iout = 0.22A
RTD3_TPANEL_PWR
R6413
+5V_AUDIO
Imax = 0.66A
U7404 +5V_BLADE
RT9728A Imax = 0.75A
LSW ; Iout = 0.75A
BLADE_PWR_EN
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C C
U7902 +VBUS_P0_CONN
TPS65988BCRSLR Imax = 1.5A
Iout = 1.5A
Iout = 1.5A +VBUS_P1_CONN
Imax = 1.5A
USB PD
U6403 +5V_KIP
NCP451AFCT2G Imax = ???A
LSW ; Iout = 0.75A
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SAM_KBTP_PWR_EN
U6408 +5V_FAN
NCP451AFCT2G Imax = 0.5A
LSW ; Iout = 0.5A
B +5V_FAN_EN B
U5901 +5VSB2
TPS51395 Imax = 0A
Efficiency : 88%
BUCK ; Iout =3.5A
U4503 CON2_VBUS
VSUS_ON NCP380 Imax = 1.5A
LSW ; Iout = 1.5A
USB3_PA_PWREN
U4507 CON1_VBUS
NCP380 Imax = 1.5A
LSW ; Iout = 1.5A
USB3_P4_PWREN
A A
5 4 3 2
5 4 3 2 1
I2C & SMBUS Map

SAM_PD_SDA
SAM_PD_SCL
PANEL_I2C_SDA
PANEL_I2C_SCL
SAM_SEN_SDA
SAM_SEN_SCL Debug Conn
I2C5
PMI_I2C_SDA
D
PMI_I2C_SCL J3302 D
APU POWER_SMB_SDA
U1001 ISP I2C2
I2C_SDA_RCAM
I2C_SCL_RCAM IRCam Connector
POWER_SMB_SCL
Master J4901 0x60 SOCVR_SDA
U5402 SOCVR_SCL
I2C_SDA_FCAM
I2C1
I2C_SCL_FCAM FCam Connector
J5401 0x36 PwrMonitor0
I2C2 U2813 0x10
I2C3 PwrMonitor1
U2802 0x12
C C
PwrMonitor2
PD_I2C PANEL_I2C_SDA EDP_I2C_SDA U2813 0x14
SFI SFI PANEL_I2C_SCL EDP_I2C_SCL EDP Connector
I2C1 I2C0 0x5C R5709 J5701
PMI_I2C_SDA R5710 0x3E&0x44&0x66 PwrMonitor1
PCH_ISH_I2C1_SDA
PCH_ISH_I2C1_SCL
PMI_I2C_SCL
PCH_ISH_I2C0_SDA
PCH_ISH_I2C0_SCL
U2803 0x16
PD_I2C2_SDA Redriver 0x0F PwrMonitor4

PD_I2C2_SCL U7700&U78000x0E U2805 0x18
R7705/R7815
R7704/R7845
PD Controller I2C1 PwrMonitor5
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I2C2 SAM_PD_SDA
PCH_SAM_SNSR_SDA U7800 0x20 SAM_PD_SCL U2806 0x1A
B
PCH_SAM_SNSR_SCL B
R2510
R2519 PCH_SENSOR_ISH_SDA 64K EEPROM
PCH_SENSOR_ISH_SCL FC7 FC8 U2201 0x51
SOCVR_SDA R3515 R2223
Q2501 SVI VR R3516 R2230 DBG_D
SOCVR_SCL
Q2502
U6601 0x?? R3517
FC2
R3511
Accel & Gyro SAM_SEN_SDA POWER_SMB_SDA
SAM_SEN_SCL
R3518 R3512
POWER_SMB_SCL Charger
U3207 0x68 FC9 FC3
R3502 U6302 0x6B
BAT_SMCLK
Skin Temp Q7204 Backlight
R3503
BAT_SMDATA
Magnetometer U3904 0x4B U7202 0x28 Battery 0x0B
L7003
U3208 0x30 J7001, J7002
Blade Accel SAM L7004
Ambient Light Skin Temp U3400

U3903 0x4A
R7401 U7408 0x68
R7403
J3202 0x44
A A
Skin Temp Host Auth

PE Sensor U3101 DNP0x60
J3200 0x2C U3902 0x49
PE Sensor Host Auth

Skin Temp U3102 DNP0x60
J3201 0x2D U3901 0x48
R3109
R3110
5 4 3 2
5 4 3 2 1
PCB1001
D TOP D
Bottom
M1095499-007
C C
1001C
U
DP_HPD [57]
C8 DISPLAY/SVI2/JTAG/TEST G15 1.8 E
[57] DP_TX0_DP A8 P0_TXP[0] P_BLON F15 CH_LCD_BKLT_EN [34,72] L_DP_HPD [71]
E D D 1.8 P S
[57] DP_TX0_DN P0_TXN[0] P_DIGON L14 CH_VDD_PANEL_EN [30,65]
E D D 1.8 P
D8 P_VARY_BL CH_BKLT_CTRL_PWM [72]
[57] DP_TX1_DP D P
E B8 P0_TXP[1] D9
[57] DP_TX1_DN D DP_AUX_DP [57]
P0_TXN[1] P0_AUXP eDP_AUX
1M
100K
E D D B9 E
eDP B6 P0_AUXN
D C10 DP_AUX_DN [57]
E
[57] DP_TX2_DP C7 P0_TXP[2] P0_HPD
E D D
[57] DP_TX2_DN P0_TXN[2]
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E D G11
P1_AUXP L_AUX_DP [71]
1032
1017
C6 D F11 S
[57] DP_TX3_DP
E D6 P0_TXP[3]
D
P1_AUXN
D G13
L_AUX_DN [71]
S DP_AUX SL40
R
[57] DP_TX3_DN P0_TXN[3] P1_HPD
E D D
E6 J12
[71] SL_DATA0_DP D5 P1_TXP[0] P2_AUXP H12
D D
[71] SL_DATA0_DN P1_TXN[0] P2_AUXN K13
D D
E1 DP2_HPD
[71] SL_DATA1_DP C1 P1_TXP[1] J10
D CP0_AUX_DP [77]
[71] SL_DATA1_DN P1_TXN[1] P3_AUXP H10 T
D D CP0_AUX_DN [77]
DP SL40 F3 P3_AUXN
D K8 T
[71] SL_DATA2_DP E4 P1_TXP[2]
D DP3_HPD DP_AUX USB-C
[71] SL_DATA2_DN P1_TXN[2] P_STEREOSYNC YPEC0_HPD
T [77,79]
D K15 D
F4 P_STEREOSYNC
D
[71] SL_DATA3_DP F2 P1_TXP[3] F14
D
[71] SL_DATA3_DN P1_TXN[3] SVD12
1022100K
D R F12
SVD13
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R
B F10 B
SVD14
R
R
1P8V
+
1P8V
+
1013
R
1K
APU_TCK AP14 1021
R 1029
R 1031
R 1030
R
APU_TDI APU_TCK [18,76] EST4
T AN14
P1022
T 1K 1K 1K 1K
APU_TDO APU_TDI [18,76] +1P8V +1P8V
EST5
T P1017
T DNP DNP DNP DNP P_STEREOSYNC
D
APU_TMS APU_TDO [18,76] F13
APU_TRST# APU_TMS [18,76] EST6
T
APU_DBREQ# APU_TRST# [18,76] G18
APU_DBREQ# [18,76] EST14
T H19
P1015
T
R1011 R1014 EST15 P1020
4.99K 330 T F18 T 1008
EST16 P1016 R
T F19 T 1K
EST17
T P1021
T
utput
o to SOC VR DNP
W24
[18,20,33,66] PW ROK EST31
T P1023
T
[18,33] APU_RESET# P1004
T
+3P3V AR11
P1019
EST41
T T P_STEREOSYNC 1: HDMI enable, 0: DP only
D
TP1001 APU_TDI AU2 AJ21 VDDP
+
DI EST47[0] P1014
T
R1020 APU_TDO AU4 T T AK21
DO EST47[1] P1018
T
1K APU_TCK AU1 T T 3P3VSB
+
0201S_P28-W35 APU_TMS AU3 CK
T
APU_TRST# AV3 MS
T 1019
RST_L R
R1018 0 PM_THRMTRIP# APU_DBREQ# AW 3 T 196 DNP
[58] H_THERMTRIP# BREQ_L
D
0201S_P28-W35 1012
R
10K
RB520CS3002L D1002 TP1007 +3P3V AW 4 V4
AW 2 RESET_L MU_ZVDD
S
[66] K A
VR_PROCHOT# PW ROK
D1001 APU_SIC DUAL H14 AW 11
P1009
T SIC ORETYPE
+1P8V K A R1006 APU_SID DUAL J14 C
[79] BC_PROCHOT# P1010
T J15 SID P1011
T
1K 3.3
P1008
T AP16 ALERT_L AN11 P1012
T
3.3
RB520CS3002L L19 HERMTRIP_L
T DDP_SENSE
V J19 DDP_VIN_SENSE [61]
V
3.3
PROCHOT_L DDCR_SOC_SENSE
V DDSOC_VIN_SENSE [66]
V
K18
A [63,76] H_PROCHOT# DDCR_SENSE
V DDCORE_VIN_SENSE [66]
V A
P
T 1013
R1001 R1027 R1015 H_CPU_SVIDCLK F16 1004
R 0
1K 1K 1K TP1006 1037 H_CPU_SVIDDAT H16 SVC0 J18 1005 0
DDSOC_VSS_SENSE [66]
V
R R DDCORE_VSS_SENSE [66]
DNP DNP DNP 100 H_CPU_SVIDALERT#J16 SVD0 SS_SENSE_A
V AM11 V
SVT0 SS_SENSE_B
V DDP_VSS_SENSE [61]
V
0402S_P4
0201S_P28-W35 0 R1007 H_CPU_SVIDALERT# +3P3V +1P8VSB YW 3500C4T4MFG
[66] SVID_ALERT# H_CPU_SVIDCLK
0201S_P28-W35 0 R1010
[66] VIDSCLK H_CPU_SVIDDAT
0201S_P28-W35 0 R1024
D
[66] VIDSOUT U1002

R1039
5 10K G
1%
1%
VCC [35] SAM_PROCHOT

SP_TP_SMDP58 TP1005
240
240
SP_TP_SMDP58 TP1002 H_PROCHOT# 2 4 Q1001

SP_TP_SMDP58 I O H_PROCHOT_1P8V# [33,34]
TP1003 SOT-VMT3_1P2XP8XP55_P4MM-1
S
1 C1009
R1028
R1026
NC1 3 0.1u 10V

GND
DNP DNP 74AUP1G07GX
5 4 3 2
5 4 3 2 1
U 1001A
EMORY A
[16] M _A_A[16:0] M
M _A_A0 AF25
M _A_A1 M A_ADD[0] M M _A_D[7:0] [16]
AE23 J21 _A_D0
M _A_A2 M A_ADD[1] M A_DATA[0] M
AD27 H21 _A_D1
M _A_A3 M A_ADD[2] M A_DATA[1] M
AE21 F23 _A_D2
M _A_A4 M A_ADD[3] M A_DATA[2] M U 1001I
AC24 H23 _A_D3
D M _A_A5 M A_ADD[4] M A_DATA[3] M _A_D4 [17] M _B_A[16:0] EMORY D
AC26 M A_ADD[5] M A_DATA[4] G20 MB
M _A_A6 AD21 F20 M _A_D5
M _A_A7 M A_ADD[6] M A_DATA[5] M M
AC27 J22 _A_D6 _B_A0 AG30 M _B_D[7:0]
M _A_A8 M A_ADD[7] M A_DATA[6] M M M B_ADD[0] M [17]
AD22 J23 _A_D7 _B_A1 AC32 B21 _B_D0
M _A_A9 M A_ADD[8] M A_DATA[7] M M B_ADD[1] M B_DATA[0] M
AC21 M _A_D[15:8] _B_A2 AC30 D21 _B_D1
M _A_A10 M A_ADD[9] M [16] M M B_ADD[2] M B_DATA[1] M
AF22 G25 _A_D8 _B_A3 AB29 B23 _B_D2
M _A_A11 M A_ADD[10] M A_DATA[8] M M M B_ADD[3] M B_DATA[2] M
AA24 F26 _A_D9 _B_A4 AB31 D23 _B_D3
AC23 L24 _A_D10 _B_A5 AA30 A20 _B_D4
AJ25 L26 _A_D11 _B_A6 AA29 C20 _B_D5
M _A_A14 M A_ADD13_BANK2 M A_DATA[11] M M M B_ADD[6] M B_DATA[5] M
AG27 L23 _A_D12 _B_A7 Y30 A22 _B_D6
M _A_A15 M A_WE_L_ADD[14] M A_DATA[12] M M M B_ADD[7] M B_DATA[6] M
AG23 F25 _A_D13 _B_A8 AA31 C22 _B_D7
M _A_A16 M A_CAS_L_ADD[15] M A_DATA[13] M M M B_ADD[8] M B_DATA[7]
AG26 K25 _A_D14 _B_A9 W29 M _B_D[15:8]
M A_RAS_L_ADD[16] M A_DATA[14] M M M B_ADD[9] M [17]
K27 _A_D15 _B_A10 AH29 D24 _B_D8
M A_DATA[15] M M B_ADD[10] M B_DATA[8] M
M _A_D[23:16] _B_A11 Y32 A25 _B_D9
M [16] M M B_ADD[11] M B_DATA[9] M
AF21 M25 _A_D16 _B_A12 W31 D27 _B_D10
[16] M _A_BA0 AF27
M A_BANK[0] M A_DATA[16]
M27 M _A_D17 M _B_A13 AL30
M B_ADD[12] M B_DATA[10]
C27 M _B_D11
[16] M _A_BA1 M A_BANK[1] M A_DATA[17]
P27 M _A_D18 M _B_A14 AK30
M B_ADD13_BANK2 M B_DATA[11]
C23 M _B_D12
M A_DATA[18] M M M B_WE_L_ADD[14] M B_DATA[12] M
AA21 R24 _A_D19 _B_A15 AK32 B24 _B_D13
[16] M _A_BG0 AA27
M A_BG[0] M A_DATA[19]
L27 M _A_D20 M _B_A16 AJ30
M B_CAS_L_ADD[15] M B_DATA[13]
C26 M _B_D14
[16] M _A_BG1 M A_BG[1] M A_DATA[20]
M24 M _A_D21 M B_RAS_L_ADD[16] M B_DATA[14]
B27 M _B_D15
M A_DATA[21] M M B_DATA[15]
AA22 P24 _A_D22
[16] M _A_ACT# M A_ACT_L M A_DATA[22] M M M _B_D[23:16] [17]
P25 _A_D23 AH31 C30 _B_D16
M A_DATA[23] [17] M _B_BA0 M B_BANK[0] M B_DATA[16] M
M _A_DM0 F21 M _A_D[31:24] AG32 E29 _B_D17
[16] M A_DM[0] M _A_D24 [16] [17] M _B_BA1 M B_BANK[1] M B_DATA[17] M _B_D18
M _A_DM1 G27 M A_DM[1] M A_DATA[24] M22 M B_DATA[18] H29
[16] N24 N21 M _A_D25 V31 H31 M _B_D19
[16] M _A_DM2 M A_DM[2] M A_DATA[25] M [17] M _B_BG0 M B_BG[0] M B_DATA[19] M
N23 T22 _A_D26 V29 A28 _B_D20
[16] M _A_DM3 M A_DM[3] M A_DATA[26] M [17] M _B_BG1 M B_BG[1] M B_DATA[20] M
AL24 V21 _A_D27 D28 _B_D21
[16] M _A_DM4 M A_DM[4] M A_DATA[27] M M B_DATA[21] M
M _A_DM5 AN27 L21 _A_D28 V30 F31 _B_D22
[16] M A_DM[5] M A_DATA[28] M _A_D29 [17] M _B_ACT# M B_ACT_L M B_DATA[22] M _B_D23
M _A_DM6 AW25 M A_DM[6] M A_DATA[29] M20 M B_DATA[23] G30
[16] AT21 R23 M _A_D30 C21
[16] M _A_DM7 M A_DM[7] M A_DATA[30] M [17] M _B_DM0 M B_DM[0] M M _B_D[31:24] [17]
T27 T21 _A_D31 C25 J29 _B_D24
R SVD9 M A_DATA[31] [17] M _B_DM1 E32
M B_DM[1] M B_DATA[24]
J31 M _B_D25
M M _A_D[39:32] [16] [17] M _B_DM2 M B_DM[2] M B_DATA[25] M
C F22 AL27 _A_D32 K30 L29 _B_D26 C
[16] M _A_DQS0 M A_DQS_H[0] M A_DATA[32] M _A_D33 [17] M _B_DM3 M B_DM[3] M B_DATA[26] M _B_D27
G22 AL25 AP30 L31
[16] M _A_DQS#0 H27
M A_DQS_L[0] M A_DATA[33]
AP26 M _A_D34 [17] M _B_DM4 AW31
H30 M _B_D28
H26 AR27 BB26 H32
[16] M _A_DQS#1 N27
AK26 M _A_D36 [17] M _B_DM6 BD22
L30 M _B_D30
N26 AK24 N32 L32
[16] M _A_DQS#2 M A_DQS_L[2] M A_DATA[37] M _A_D38 R SVD17 M B_DATA[31]
R21 AM24
[16] M _A_DQS3 P21
M A_DQS_H[3] M A_DATA[38]
AP27 M _A_D39 D22 AP29 M _B_D32
M _B_D[39:32] [17]
[16] M _A_DQS#3 M A_DQS_L[3] M A_DATA[39] [17] M _B_DQS0 M B_DQS_H[0] M B_DATA[32] M _B_D33
AM26 B22 AP32
[16] M _A_DQS4 AM27
M A_DQS_H[4]
AM23 M _A_D40
M _A_D[47:40] [16] [17] M _B_DQS#0 D25
M B_DQS_L[0] M B_DATA[33]
AT29 M _B_D34
[16] M _A_DQS#4 M A_DQS_L[4] M A_DATA[40] M _A_D41 [17] M _B_DQS1 M B_DQS_H[1] M B_DATA[34] M _B_D35
AN24 AM21 B25 AU32
[16] M _A_DQS5 M A_DQS_H[5] M A_DATA[41] M _A_D42 [17] M _B_DQS#1 M B_DQS_L[1] M B_DATA[35] M _B_D36
AN25 AR25 F29 AN30
[16] M _A_DQS#5 AU23
AU27 M _A_D43 [17] M _B_DQS2 F30
M B_DQS_H[2] M B_DATA[36]
AP31 M _B_D37
[16] M _A_DQS6 M A_DQS_H[6] M A_DATA[43] M _A_D44 [17] M _B_DQS#2 M B_DQS_L[2] M B_DATA[37] M _B_D38
AT23 AL22 K31 AR30
[16] M _A_DQS#6 AV20
AL21 M _A_D45 [17] M _B_DQS3 K29
AT31 M _B_D39
[16] M _A_DQS7 M A_DQS_H[7] M A_DATA[45] M _A_D46 [17] M _B_DQS#3 M B_DQS_L[3] M B_DATA[39]
AW20 AP24 AR29
[16] M _A_DQS#7 M A_DQS_L[7] M A_DATA[46] M _A_D47 [17] M _B_DQS4 M B_DQS_H[4] M _B_D40
M _B_D[47:40] [17]
V23 AP23 AR31 AU29
V10
R SVD10 M A_DATA[47] [17] M _B_DQS#4 AW30
AV30 M _B_D41
R SVD11 M M _A_D[55:48] [16] [17] M _B_DQS5 M B_DQS_H[5] M B_DATA[41] M
AW26 _A_D48 AW29 BB30 _B_D42
AD25
M A_DATA[48]
AV25 M _A_D49 [17] M _B_DQS#5 BC25
BA28 M _B_D43
[16] M _A_DIM0_CLK0 M A_CLK_H[0] M A_DATA[49] M _A_D50 [17] M _B_DQS6 M B_DQS_H[6] M B_DATA[43] M _B_D44
AD24 AV22 BA25 AU30
[16] M _A_DIM0_CLK#0 M A_CLK_L[0] M A_DATA[50] M _A_D51 [17] M _B_DQS#6 M B_DQS_L[6] M B_DATA[44] M _B_D45
AE26 AW22 BC22 AU31
AE27
M A_CLK_H[1] M A_DATA[51]
AU26 M _A_D52 [17] M _B_DQS7 BA22
AY32 M _B_D46
M A_CLK_L[1] M A_DATA[52] M _A_D53 [17] M _B_DQS#7 M B_DQS_L[7] M B_DATA[46] M _B_D47
AV27 N31 AY29
M A_DATA[53] M _A_D54 R SVD18 M B_DATA[47]
AW23 N29 M _B_D[55:48]
M A_DATA[54] M _A_D55 R SVD19 M _B_D48 [17]
AT22 BA27
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M A_DATA[55] M B_DATA[48] M _B_D49
M _A_D[63:56] AC31 BC27
AW21 M _A_D56 [16] [17] M _B_DIM0_CLK0 AD30
M B_CLK_H[0] M B_DATA[49]
BA24 M _B_D50
M A_DATA[56] M _A_D57 [17] M _B_DIM0_CLK#0 M B_CLK_L[0] M B_DATA[50] M _B_D51
AG21 AU21 AD29 BC24
[16] M _A_DIM0_CS#0 AJ27
M A_CS_L[0] M A_DATA[57]
AP21 M _A_D58 AD31
M B_CLK_H[1] M B_DATA[51]
BD28 M _B_D52
M A_CS_L[1] M A_DATA[58] M _A_D59 M B_CLK_L[1] M B_DATA[52] M _B_D53
AN20 BB27
M A_DATA[59] M _A_D60 M B_DATA[53] M _B_D54
AR22 BB25
M A_DATA[60] M _A_D61 M B_DATA[54] M _B_D55
B AN22 BD25 B
M A_DATA[61] M _A_D62 M B_DATA[55]
AT20 M _B_D[63:56]
M A_DATA[62] M _A_D63 M _B_D56 [17]
AR20 BC23
M A_DATA[63] M B_DATA[56] M _B_D57
Y23 AJ31 BB22
+ 1P2V_DUAL [16] M _A_DIM0_CKE0 Y26
M A_CKE[0]
T24 [17] M _B_DIM0_CS#0 AM31
M B0_CS_L[0] M B_DATA[57]
BC21 M _B_D58
M A_CKE[1] R SVD1 M B0_CS_L[1] M B_DATA[58] M _B_D59
T25 AK27 BD20
R SVD2 R SVD20 M B_DATA[59] M _B_D60
W21 AL3 BB23
R SVD3 R SVD21 M B_DATA[60] M _B_D61
W22 BA23
RSVD4 M B_DATA[61] M _B_D62
AG24 R26 BB21
[16] M _A_DIM0_ODT0 AJ22
MA_ODT[0] RSVD5
R27
M B_DATA[62]
BA21 M _B_D63
MA_ODT[1] RSVD6 M B_DATA[63]
V26 U29
R 1102 RSVD7 + 1P2V_DUAL [17] M _B_DIM0_CKE0 M B0_CKE[0]
V24 T30 M31
RSVD8 M B0_CKE[1] R SVD24
1K N30
R SVD25
AA25 P31
[16] M _A_ALERT# MA_ALERT_L R SVD26
AF24 R32
MA_PAROUT M _A_PAR [16] R SVD27
AE24 AL31 M30
MA_EVENT_L [17] M _B_DIM0_ODT0 M B0_ODT[0] R SVD28
Y24 AM32 M29
[16] M _A_RST# MA_RESET_L
AL29
M B0_ODT[1] R SVD29
P30
R 1101 R SVD22 R SVD30
AM30 P29
R SVD23 R SVD31
YW3500C4T4MFG 1K
W30
[17] M _B_ALERT# M B_ALERT_L
AG31
AG29 M B_PAROUT M _B_PAR [17]
M B_EVENT_L
T31
[17] M _B_RST# M B_RESET_L
YW3500C4T4MFG
5 4 3 2
5 4 3 2 1
APU_VDDSOC
+
1001F APU_VDDCORE
U +
Vinafix.com M15
M18
M19
V
V
DDCR_SOC
DDCR_SOC
POWER
DDCR
V
DDCR
V
G7
G10
G12
N16 DDCR_SOC DDCR G14
V V
N18 DDCR_SOC DDCR H8
V V
1P8VSB 1P8VSUS_ORG 3P3VSB 3VSUS_ORG N20 DDCR_SOC DDCR H11
+ + + + V V
DBG_TS DBG_TS P17 DDCR_SOC DDCR H15
D V V D
1204 0.01 1208 0.01 P19 DDCR_SOC DDCR K7
R R V V
0402S_P5-W65 0402S_P5-W65 R18 DDCR_SOC DDCR K12
V V
R20 VDDCR_SOC DDCR
V K14
T19 VDDCR_SOC DDCR
V L8
U18 VDDCR_SOC DDCR
V M7
PMTP1202
U20 VDDCR_SOC DDCR
V M10
PMTP1204 PMTP1201 SP-TP-C0P381 PMTP1203
V19 VDDCR_SOC DDCR
V N14
SP-TP-C0P381 SP-TP-C0P381 SP-TP-C0P381
W18 VDDCR_SOC DDCR
V P7
+1P2V_DUAL W20 VDDCR_SOC DDCR
V P10
Y19 VDDCR_SOC DDCR
V P13
VDDCR_SOC DDCR
V P15
T32 DDCR
V R8
V28 VDDIO_MEM_S3 DDCR
V R14
W28 VDDIO_MEM_S3 DDCR
V R16
W32 VDDIO_MEM_S3 DDCR
V T7
Y22 VDDIO_MEM_S3 DDCR
V T10
V T13
V T15
AA20 VDDIO_MEM_S3 DDCR
V T17
V U14
V U16
+1P8V +1P8V_APU +1P8V_ORG +3P3V +3P3V_APU +3P3V_ORG AA28 VDDIO_MEM_S3 DDCR
V V13
DBG_TS DBG_TS AA32 VDDIO_MEM_S3 DDCR
V V15
R1211 0 R1212 0.01 R1207 0 R1209 0.01 AC20 VDDIO_MEM_S3 DDCR
V V17
0402 DNP 0402S_P5-W65 0402 DNP 0402S_P5-W65 AC22 VDDIO_MEM_S3 DDCR
V W7
AC25 VDDIO_MEM_S3 DDCR
V W10
C AC28 VDDIO_MEM_S3 DDCR
V W14 C
AD23 VDDIO_MEM_S3 DDCR
V W16
PMTP1205 AD26 VDDIO_MEM_S3 DDCR
V Y8
PMTP1207 PMTP1208 PMTP1206 AD28 VDDIO_MEM_S3 DDCR
V Y13
SP-TP-C0P381
SP-TP-C0P381 SP-TP-C0P381 +3P3V_ORG AD32 VDDIO_MEM_S3 DDCR
V Y15
SP-TP-C0P381
AE20 VDDIO_MEM_S3 DDCR
V Y17
V AA7
V AA10
C1241 C1230 C1216 AE28 VDDIO_MEM_S3 DDCR
V AA14
22u 1u 1u AF23 VDDIO_MEM_S3 DDCR
V AA16
AF26 VDDIO_MEM_S3 DDCR
V AA18
0603 6.3V 6.3V AF28 VDDIO_MEM_S3 DDCR
V AB13
+1P8V_ORG 20% 20% 20% AF32 VDDIO_MEM_S3 DDCR
V AB15
AG20 VDDIO_MEM_S3 DDCR
V AB17
10V 0201 0201 VDDIO_MEM_S3 DDCR
+1P2V_DUAL put those caps under SOC +1P8VSUS_ORG AG22 V AB19
AG25 VDDIO_MEM_S3 DDCR
V AC14
C1250 C1245 C1237 AG28 VDDIO_MEM_S3 DDCR
V AC16
C1201 C1247 C1242 C1214 C1234 C1217 C1236 C1212 C1231 C1227 C1244 C1229 22u 1u 1u AJ20 VDDIO_MEM_S3 DDCR
V AC18
10u 10u 10u 10u 10u 10u 10u 10u 10u 1u 1u AJ23 VDDIO_MEM_S3 DDCR
V AD7
0603 6.3V 6.3V AJ26 VDDIO_MEM_S3 DDCR
V AD10
180p
0402 0402 0402 0402 0402 0402 0402 0402 0402 6.3V 6.3V AJ28 VDDIO_MEM_S3 DDCR
V AD13
20% 20% 20% C1211 C1204
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 22u 1u 6.3V AJ32 VDDIO_MEM_S3 DDCR
V AD15
10V 0201 0201 VDDIO_MEM_S3 DDCR
+1P8VSUS_ORG AK28 V AD17
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0201S_P35-W35
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 0201 0201GND 0603 AL28 VDDIO_MEM_S3 DDCR
V AD19
20% AL32 VDDIO_MEM_S3 DDCR
V AE8
VDDIO_MEM_S3 DDCR
V AE14
10V AP12 DDCR
V AE16
C1254 C1252 C1259 C1257 C1255 C1253 C1260 C1258 C1256 C1228 C1233 C1221 VDDIO_AUDIO DDCR
V AE18
B DDCR B
10u 10u 10u 10u 10u 10u 10u 10u 10u 22u 1u 1u AL18 V AF7
+3VSUS_ORG AM17 VDD_33 DDCR
V AF10
0402 0402 0402 0402 0402 0402 0402 0402 0402 0603 6.3V 6.3V VDD_33 DDCR
V AF13
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% AL20 DDCR
V AF15
AM19 VDD_18 DDCR
V AF17
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 10V 0201 0201 VDD_18 DDCR
V AF19
AL19 DDCR
V AG14
C1220 C1218 C1238 AM18 VDD_18_S5 DDCR
V AG16
22u 1u 1u VDD_18_S5 DDCR
V AG18
DDCR
V
+VDDPSB AL17 AH13
0603 6.3V 6.3V AM16 VDD_33_S5 DDCR
V AH15
20% 20% 20% VDD_33_S5 DDCR
V AH17
AL14 DDCR
V AH19
10V 0201 0201 AL15 VDDP_S5 DDCR
V AJ7
C1213 C1222 C1206 C1203 AM14 VDDP_S5 DDCR
V AJ10
22u 1u 1u 1u VDDP_S5 DDCR
V AJ14
AL13 DDCR
V AJ16
0603 6.3V 6.3V 6.3V AM12 VDDP DDCR
V AJ18
20% 20% 20% 20% AM13 VDDP DDCR
V AK13
AN12 VDDP DDCR
V AK15
10V 0201 0201 0201 AN13 VDDP DDCR
V AK17
+VDDP VDDP DDCR
V AK19
+1P2V_DUAL AT11 DDCR
V
VDDBT_RTC_G
+VCC_RTC
C1224 C1225 C1240 C1215 C1210 C1205 C1202 C1249 C1243 C1235 C1232
A
C1226 C1219 22u 22u 1u 1u 1u 1u 1u 1u 1u 1u YW3500C4T4MFG
A
C1207 C1246 C1251 C1239 0603 0603 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
180p
0.22u 0.22u 0.22u 0.22u 180p 180p C1223
6.3V 6.3V 6.3V 6.3V 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 1u C1209
10V 10V 0201 0201 0201 0201 0201 0201 0201 0201GND 6.3V 0.22u
GND GND 6.3V
20%
0201
5 4 3 2
5 4 3 2 1
+ APU_VDDSOC
C 1315 C 1310 C 1305 C 1306 C 1308 C 1302 C 1312 C 1304 C 1317 C 1322 C 1316
10u 10u 10u 10u 10u 10u 10u 10u 10u 1u
180p
0402 0402 0402 0402 0402 0402 0402 0402 0402 6.3V
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
D D
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 0201
C 1347 C 1343 C 1336 C 1329 C 1340

10u 10u 10u 10u 10u All Cap in here put on bottom side of SOC
0402 0402 0402 0402 0402
20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
+ APU_VDDCORE
+ APU_VDDCORE
C 1320 C 1311 C 1321 C 1318 C 1313 C 1323 C 1326 C 1303 C 1314 C 1307 C 1324
C 1390 C 1391 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u C 1309
10u 10u
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
180p
0402 0402
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
C 20% 20% C
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
6.3V 6.3V G ND
C 1364 C 1360 C 1349 C 1358 C 1337

+APU_VDDCORE 10u 10u 10u 10u 10u
0402 0402 0402 0402 0402
All Cap in here put on bottom side of SOC 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
Additional caps to support a max load step up to 56A
C 1335 C 1331 C 1352 C 1350 C 1346 C 1342 C 1334 C 1327 C 1338 C 1330 C 1319
10u 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u
C1370 C 1371 C 1372 C 1373 C 1374 C 1375 C 1376 C 1377 C 1378 C 1379 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
10u 10u 10u 10u 10u 10u 10u 10u 10u 10u
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
B
+APU_VDDCORE
https://vinafix.com C 1345
10u
0402
C 1344
10u
0402
C 1341
10u
0402
C 1339
10u
0402
C 1332
10u
0402
All Cap in here put on bottom side of SOC B
20% 20% 20% 20% 20%

C1380 C 1381 C 1382 C 1383 C 1384 C 1385 C 1386 C 1387 C 1388 C 1389 6.3V 6.3V 6.3V 6.3V 6.3V
10u 10u 10u 10u 10u 10u 10u 10u 10u 10u
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
A A
5 4 3 2
5 4 3 2 1
U 1001H U 1001K
U1001G GND GND/RSVD
GND V5 V SS V SS AG5 AR1 V SS V SS BD14
BD30 V SS V SS K32 V8 V SS V SS AG8 AR5 V SS V SS BD16
A3 V SS V SS L5 V11 V SS V SS AG11 AR7 V SS V SS BD19
D
A12 V SS V SS L20 V18 V SS V SS AG17 AR19 V SS D
A14 V SS V SS L25 V20 V SS V SS AG19 AR21 V SS
A16 V SS V SS L28 V22 V SS V SS AH14 AR26 V SS
A19 V SS V SS M1 V25 V SS V SS AH16 AR28 V SS
A21 V SS V SS M5 W1 V SS V SS AH18 AR32 V SS
A23 V SS V SS M12 W5 V SS V SS AH20 AU5 V SS
A26 V SS V SS M21 W13 V SS V SS AJ1 AU8 V SS
A30 V SS V SS M23 W15 V SS V SS AJ5 AU11 V SS
C3 V SS V SS M26 W17 V SS V SS AJ13 AU13 V SS
C32 V SS V SS M28 W19 V SS V SS AJ15 AU15 V SS
D16 V SS V SS M32 W23 V SS V SS AJ17 AU18 V SS
D18 V SS V SS N4 W26 V SS V SS AJ19 AU20 V SS
D20 V SS V SS N5 Y5 V SS V SS AK5 AU22 V SS R SVD32 B20
E7 V SS V SS N8 Y11 V SS V SS AK8 AU25 V SS R SVD33 G3
E8 V SS V SS N11 Y12 V SS V SS AK11 AU28 V SS R SVD34 J20
E10 V SS V SS N12 Y14 V SS V SS AK12 AV1 V SS R SVD35 K3
E13 V SS V SS N17 Y20 V SS V SS AK18 AV10 V SS R SVD38 M3
E14 V SS V SS N19 AA1 V SS V SS AK20 AV12 V SS R SVD39 M6
E15 V SS V SS N22 AA5 V SS V SS AK22 AV14 V SS R SVD40 M13
E16 V SS V SS N25 AA13 V SS V SS AK25 AV16 V SS R SVD41 P6
C E18 V SS V SS N28 AA15 V SS V SS AL1 AV19 V SS R SVD42 P22 C
E19 V SS V SS P1 AA17 V SS V SS AL5 AV21 V SS R SVD43 T3
E20 V SS V SS P5 AA19 V SS V SS AL7 AV23 V SS R SVD44 T6
E21 V SS V SS P14 AB14 V SS V SS AL10 AV26 V SS R SVD45 T29
E22 V SS V SS P16 AB16 V SS V SS AL12 AV28 V SS R SVD46 V27
E23 V SS V SS P18 AB18 V SS V SS AL16 AV32 V SS R SVD47 W11
E25 P20 AB20 AL23 AW5 W12
V SS V SS V SS V SS V SS R SVD48
E26 P23 AC5 AL26 AW28 Y9
E27 P26 AC8 AM5 AY6 Y10
F5 P28 AC11 AM8 AY7 Y21
F28 P32 AC12 AM15 AY8 Y27
G1 R5 AC13 AM20 AY10 AC9
G5 R11 AC15 AM22 AY11 AC10
G16 R12 AC17 AM25 AY12 AC29
G19 R13 AC19 AM28 AY13 AD11
G21 R15 AD1 AN1 AY14 AD12
G23 R17 AD5 AN5 AY15 AF3
G26 R19 AD14 AN7 AY16 AF6
https://vinafix.com
G28 R22 AD16 AN10 AY18 AF8
G32 R25 AD18 AN15 AY19 AF9
H5 R28 AD20 AN18 AY20 AF29
H13 R30 AE5 AN21 AY21 AF30
B V SS V SS V SS V SS V SS R SVD63 B
H18 T1 AE11 AN23 AY22 AJ29
H20 T5 AE12 AN26 AY23 AK23
H22 T14 AE13 AN28 AY25 M14
H25 T16 AE15 AN32 AY26 AF31
H28 T18 AE17 AP5 AY27 AJ6
K1 T20 AE19 AP8 BB1 AJ24
K5 T23 AF1 AP13 BB20 AL6
K16 T26 AF5 AP15 BB32 AL11
K19 T28 AF14 AP18 BD3 AM29
K21 U13 AF16 AP20 BD7 AN16
K22 U15 AF18 AP25 BD10 AN29
K26 U17 AF20 AP28 BD12 AN31
K28 U19
V SS V SS
YW3500C4T4MFG YW3500C4T4MFG
YW3500C4T4MFG
Vinafix.com
5 4 3 2
5 4 3 2 1
U1001L
RSVD
T11 AA6
RSVD76 RSVD86
AA3
RSVD87
AA12 AA11
RSVD77 RSVD88
Y6
RSVD78
Y7 AD3
RSVD79 RSVD89
D W8 AC6 D
RSVD80 RSVD90
W9 AA8
RSVD81 RSVD91
U31 T12
RSVD82 RSVD92
V9 AD6
RSVD83 RSVD93
W25
RSVD94 W27
RSVD95
AA9 V32
AC7 RSVD84 RSVD96 W6
RSVD85 RSVD97
YW3500C4T4MFG
C C
B
https://vinafix.com B
A A
5 4 3 2
5 4 3 2 1
[11,16] M_A_A[16:0] U1601A

P3 G2 M_A_D[7:0] [11]
M_A_A0 P7 0 QL0 F7 M_A_D3 [11,16] U1602A 1603A
U
M_A_A1 A1 DQL1 M_A_D7 M_A_A[16:0] [11,16] _A_A[16:0]
M
R3 H3 P3 G2 _A_D[16:23]
M [11] P3 G2 _A_D[32:39]
M [11]
M_A_A2 N7
A2 DQL2
H7 M_A_D6 M_A_A0 P7 0 QL0 F7 M_A_D18 _A_A0
M P7 0 QL0 F7
_A_D33
M
M_A_A3 A3 DQL3 M_A_D5 M_A_A1 A1 DQL1 M_A_D17 _A_A1
M A
1 D
QL1 _A_D37
M
N3 H2 R3 H3 R3 H3
M_A_A4 P8
A4 DQL4
H8 M_A_D2 M_A_A2 N7
A2 DQL2
H7 M_A_D22 _A_A2
M N7
A
2 D
QL2 H7
_A_D39
M
M A
3 D
QL3 _A_D32
M
P2 J3 N3 H2 N3 H2
M A
4 D
QL4 _A_D34
M
R8 J7 P8 H8 P8 H8
M_A_A7 R2
A7 DQL7
A3 M_A_D0 M_A_A5 P2
A5 DQL5
J3 M_A_D16 _A_A5
M P2
A
5 D
QL5 J3
_A_D36
M
M_A_A8 A8 DQU0 M_A_D12 M_A_D[15:8] [11]
M_A_A6 A6 DQL6 M_A_D19 _A_A6
M A
6 D
QL6 _A_D35
M
R7 B8 R8 J7 R8 J7
M_A_A9 M3
A9 DQU1
C3 M_A_D9 M_A_A7 R2
A7 DQL7
A3 M_A_D21 _A_A7
M R2
A
7 D
QL7 A3
_A_D38
M
A10/AP DQU2 A8 D _A_D[24:31]
M [11] A D _A_D[40:47]
M [11]
D M_A_A10 T2 C7 M_A_D10 M_A_A8 R7 QU0 B8 M_A_D31 _A_A8
M R7 8 QU0 B8
_A_D42
M D
M_A_A11 A11 DQU3 M_A_D14 M_A_A9 A9 DQU1 M_A_D25 _A_A9
M A
9 D
QU1 _A_D40
M
7 C2 M3 C3 M3 C3
M_A_A12 M
T8
A12/BC DQU4
C8 M_A_D11 M_A_A10 T2
A10/AP DQU2
C7 M_A_D29 _A_A10
M T2
A
10/AP D
QU2 C7
_A_D46
M
M_A_A13 A13 DQU5 M_A_D8 M_A_A11 A11 DQU3 M_A_D30 _A_A11
M A
11 D
QU3 _A_D45
M
L2 D3 7 C2 7 C2
M_A_A14 M8
A E_N/A14 DQU6
D7 M_A_D15 M_A_A12 M
T8
A12/BC DQU4
C8 M_A_D27 _A_A12
M M
T8
A
12/BC D
QU4 C8
_A_D43
M
M_A_A15 WAS_N/A15 DQU7 M_A_D13 M_A_A13 A13 DQU5 M_A_D28 _A_A13
M A
13 D
QU5 _A_D44
M
L8 CAS_N/A16 D L2 A E_N/A14 DQU6 D3 L2 AE_N/A14 D D3
M_A_A16 M_A_A14 M8 D7 M_A_D26 _A_A14
M M8 QU6 D7
_A_D47
M
3
R
G3 M_A_A15 L8
WAS_N/A15 DQU7 M_A_D24 _A_A15
M L8
W
AS_N/A15 D
QU7 _A_D41
M
L CT QSL_T M_A_A16 CAS_N/A16 D _A_A16
M C
AS_N/A16 D
[11,16] M_A_ACT# F3 M_A_DQS0 [11]
A DQSL_C R R
N2 D M_A_DQS#0 [11] 3 G3 3 G3
[11,16] M_A_BA0 N8 A0 B7 [11,16] L CT QSL_T F3 L CT QSL_T F3
BA1 M_A_ACT# A D M_A_DQS2 [11] [11,16] _A_ACT#
M A D _A_DQS4 [11]
M
[11,16] M_A_BA1 QSU_T A7 N2 QSL_C N2 QSL_C
B DQSU_C M_A_DQS1 [11] A0 D M_A_DQS#2 [11] A0 D _A_DQS#4 [11]
M
M2 D M_A_DQS#1 [11] [11,16] M_A_BA0 N8 BA1 B7 [11,16] _A_BA0
M N8 B B7
TBL1601 G0 QSU_T A1 QSU_T
[11,16] M_A_BG0 _A_BG1_R M9 BG1 [11,16] M_A_BA1 B D A7 M_A_DQS3 [11] [11,16] _A_BA1
M B D A7 _A_DQS5 [11]
M
[11] M_A_BG1 R1639 0 M 9 M2 QSU_C M2 QSU_C
B D M_A_DQS#3 [11] D _A_DQS#5 [11]
M
R1641 0
K7 LERT P G0 G0
TBL1601 A M_A_ALERT# [11,16] [11,16] M_A_BG0 M_A_BG1_R M9 BG1 [11,16] _A_BG0
M _A_BG1_R M9
M B
[11,16] M_A_DIM0_CLK0 K8 K_T0 9 G1 9
CK_C0 B LERT P B LERT P
[11,16] M_A_DIM0_CLK#0 C K7 A M_A_ALERT# [11,16] K7 A _A_ALERT# [11,16]
M
K2 [11,16] M_A_DIM0_CLK0 K8 K_T0 [11,16] M_A_DIM0_CLK0 K8 K_T0
KE CK_C0 C
K_C0
[11,16] M_A_DIM0_CKE0 C [11,16] M_A_DIM0_CLK#0 C [11,16] M _A_DIM0_CLK#0 C
7 K2 K2
[11,16] M_A_DIM0_CS#0 L S [11,16] KE KE
C M_A_DIM0_CKE0 C [11,16] _A_DIM0_CKE0
M C
7 7 7
[11] M_A_DM0 E2 ML_N/DBIL [11,16] L S L S
DMU_N/DBIU M_A_DIM0_CS#0 C [11,16] _A_DIM0_CS#0
M C
[11] M_A_DM1 E 7 7
D E2 ML_N/DBIL E ML_N/DBIL
K3 [11] M_A_DM2 DMU_N/DBIU [11] M_A_DM4 2 D
[11,16] M_A_DIM0_ODT0 T3 DT [11] M_A_DM3 E [11] M_A_DM5 E MU_N/DBIU
OAR D D
[11,16] M_A_PAR P K3 K3
1 [11,16] T3 DT T3 DT
M_A_DIM0_ODT0 OAR [11,16] _A_DIM0_ODT0
M O
[11,16] M_A_RST# P
N9 ESET [11,16] M_A_PAR [11,16] M
_A_PAR AR
REN P P
T 1 1
[11,16] P
N9 ESET P
N9 ESET
H5ANAG6NCMR-VKC M_A_RST# REN [11,16] _A_RST#
M R
EN
T T
H5ANAG6NCMR-VKC H5ANAG6NCMR-VKC
1604A
U
[11,16] _A_A[16:0]
M
C _A_A0 P3 G2 _A_D51 _A_D[48:55]
M [11] C
M 0 QL0 M
_A_A1 P7 A D F7 _A_D48
M 1 QL1 M
REFER TO MEMORY BOM CONFIGURATION _A_A2
M
R3 A
2 D
QL2
H3 _A_D49
M
N7 H7
TBL1601 ON SCHEMATICS PAGE 17 _A_A3
M
_A_A4
M
N3
A
3
A
D
QL3
D H2
_A_D50
M
_A_D54
M
P8 4 QL4 H8
+V_VDDQ_VTT _A_A5
M A
5 D
QL5 _A_D55
M
_A_A6
M
P2 A D J3 _A_D53
M
R8 6 QL6 J7
_A_A7
M A
7 D
QL7 _A_D52
M
_A_A8 R2 A D A3 _A_D57 _A_D[56:63]
M [11]
M 8 QU0 M
_A_A9
M R7 A D B8 _A_D56
M
M3 9 QU1 C3
C1612 C1635 C1621 C1636 C1614 _A_A10
M A
10/AP D
QU2 _A_D62
M
_A_A11
M T2 A D C7 _A_D58
M
0.22u 0.22u 0.22u 0.22u 0.22u 7 11 QU3 C2
6.3V 6.3V 6.3V 6.3V 6.3V _A_A12
M M A D _A_D63
M
T8 12/BC QU4 C8
+1P2V_DUAL _A_A13
M A D _A_D61
M
L2 13 QU5 D3
+1P2V_DUAL _A_A14
M AE_N/A14 D
QU6 _A_D59
M
_A_A15
M M8 W D D7 _A_D60
M
+V_VREF_CA_DIMM AS_N/A15 QU7
_A_A16
M L8 C D
AS_N/A16
R
3 G3
C1626 C1615 C1630 C1610 C1613 C1627 C1607 C1633 C1603 2P5VPP
+ [11,16] _A_ACT# L CT QSL_T _A_DQS6 [11]
M A D F3 M
R1638 0.22u 0.22u 0.22u 0.22u 0.22u 0.22u 0.22u 0.22u 0.22u QSL_C _A_DQS#6 [11]
1K 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V N2 D M
C1620 C1623 C1604 C1628 [11,16] _A_BA0
M N8 A0 B7
1% +V_VREF_CA_DIMM 10V 0.1u 10V 0.1u 10V 0.1u 10V 0.1u B
[11,16] _A_BA1
M A1 QSU_T A7 _A_DQS7 [11]
M
0201S_P33-W390201S_P33-W390201S_P33-W390201S_P33-W39 B D
TP1601 M2 QSU_C _A_DQS#7 [11]
M
1602
C 1632
C 1606
C 1634
C D
[11,16] _A_BG0 G0
C1618 C1637 C1624 C1609 C1622 C1605 C1629 C1617 C1616 1u 1u 1u 1u M _A_BG1_R M9
M B
TP1602 G1 9
B P
one for each chip M1 pin 0.22u
6.3V
0.22u
6.3V
0.22u
6.3V
0.22u
6.3V
0.22u
6.3V
0.22u
6.3V
0.22u
6.3V
0.22u
6.3V
0.22u
6.3V
6.3V 6.3V 6.3V 6.3V K7 LERT
A _A_ALERT# [11,16]
M
[11,16] M_A_DIM0_CLK0 K8 K_T0
20% 20% 20% 20% C
[11,16] M _A_DIM0_CLK#0 K_C0
R1637 C1638 C1639 C
+V_VDDQ_VTT 0201 0201 0201 0201 K2
1K 0.1u 10V 0.1u 10V KE
https://vinafix.com
[11,16] _A_DIM0_CKE0
M C
1%
7
[11,16] _A_DIM0_CS#0 L S
1643 1642 1641 1640 M C
C C C C
TP1603 1u 1u 1u 1u 7
[11] M_A_DM6 E ML_N/DBIL
2 D
C1611 C1625 C1608 C1631 C1619 6.3V 6.3V 6.3V 6.3V [11] M _A_DM7 E MU_N/DBIU
TP1604 +1P2V_DUAL D
0.22u 0.22u 0.22u 0.22u 0.22u K3
6.3V 6.3V 6.3V 6.3V 6.3V 20% 20% 20% 20% DT
[11,16] _A_DIM0_ODT0
M T3 O
B 0201 0201 0201 0201 [11,16] M
_A_PAR AR
P B
1
P
[11,16] _A_RST#
M N9 ESET
R
ne
o for each VPP pin EN
T
+V_VREF_CA_DIMM U1601B H5ANAG6NCMR-VKC
+2P5VPP
M1
VREFCA +V_VREF_CA_DIMM U1602B
+V_VDDQ_VTT B1 +2P5VPP +V_VREF_CA_DIMM U1603B
+1P2V_DUAL R9 VPP1 M1 +2P5VPP
[11] M_A_A[14:0]
M_A_A16 R1636 39 VPP2 VREFCA M1 V_VREF_CA_DIMM
+ 1604B
U
M_A_A15 R1615 39 J1 B1 VREFCA 2P5VPP
+
M_A_A14 R1616 39 VDDL +1P2V_DUAL R9 VPP1 B1 M1
M_A_A13 R1610 39 B3 VPP2 +1P2V_DUAL R9 VPP1 REFCA
V
M_A_A12 R1622 39 B9 VDD1 B2 J1 VPP2 B1
M_A_A11 R1625 39 D1 VDD2 VSS1 E1 VDDL J1 1P2V_DUAL
+ R9 PP1
V
M_A_A10 R1618 39 G7 VDD3 VSS2 G8 B3 VDDL PP2
V
M_A_A9 R1621 39 J9 VDD4 VSS3 K1 B9 VDD1 B2 B3 J1
M_A_A8 R1631 39 L1 VDD5 VSS4 K9 D1 VDD2 VSS1 E1 B9 VDD1 B2 DDL
V
M_A_A7 R1608 39 L9 VDD6 VSS5 N1 G7 VDD3 VSS2 G8 D1 VDD2 VSS1 E1 B3
M_A_A6 R1627 39 R1 VDD7 VSS6 T1 J9 VDD4 VSS3 K1 G7 VDD3 VSS2 G8 B9 DD1
V B2
M_A_A5 R1632 39 T9 VDD8 VSS7 T7 L1 VDD5 VSS4 K9 J9 VDD4 VSS3 K1 D1 DD2
V SS1
V E1
M_A_A4 R1605 39 VDD9 VSS8 L9 VDD6 VSS5 N1 L1 VDD5 VSS4 K9 G7 DD3
V SS2
V G8
M_A_A3 R1602 39 A1 A2 R1 VDD7 VSS6 T1 L9 VDD6 VSS5 N1 J9 DD4
V SS3
V K1
M_A_A2 R1613 39 A9 VDDQ1 VSSQ1 A8 T9 VDD8 VSS7 T7 R1 VDD7 VSS6 T1 L1 DD5
V SS4
V K9
M_A_A1 R1620 39 C1 VDDQ2 VSSQ2 C9 VDD9 VSS8 T9 VDD8 VSS7 T7 L9 DD6
V SS5
V N1
M_A_A0 R1624 39 D9 VDDQ3 VSSQ3 D2 A1 A2 VDD9 VSS8 R1 DD7
V SS6
V T1
R1634 39 F2 VDDQ4 VSSQ4 D8 A9 VDDQ1 VSSQ1 A8 A1 A2 T9 DD8
V SS7
V T7
[11,16] M_A_BG0 M_A_BG1_R R1630 TBL1601
39 F8 VDDQ5 VSSQ5 E3 C1 VDDQ2 VSSQ2 C9 A9 VDDQ1 VSSQ1 A8 DD9
V SS8
V
R1635 39 G1 VDDQ6 VSSQ6 E8 D9 VDDQ3 VSSQ3 D2 C1 VDDQ2 VSSQ2 C9 A1 A2
[11,16] M_A_BA0
R1611 39 G9 VDDQ7 VSSQ7 F1 F2 VDDQ4 VSSQ4 D8 D9 VDDQ3 VSSQ3 D2 A9 DDQ1
V SSQ1
V A8
[11,16] M_A_BA1
R1607 39 J2 VDDQ8 VSSQ8 H1 F8 VDDQ5 VSSQ5 E3 F2 VDDQ4 VSSQ4 D8 C1 DDQ2
V SSQ2
V C9
[11,16] M_A_ACT#
R1626 39 J8 VDDQ9 VSSQ9 H9 G1 VDDQ6 VSSQ6 E8 F8 VDDQ5 VSSQ5 E3 D9 DDQ3
V SSQ3
V D2
[11,16] M_A_PAR
R1629 39 VDDQ10 VSSQ10 G9 VDDQ7 VSSQ7 F1 G1 VDDQ6 VSSQ6 E8 F2 DDQ4
V SSQ4
V D8
[11,16] M_A_DIM0_CS#0 E9 J2 VDDQ8 VSSQ8 H1 G9 VDDQ7 VSSQ7 F1 F8 DDQ5
V SSQ5
V E3
R1606 39
[11,16] M_A_DIM0_ODT0
R1619 39 F9 ZQU J8 VDDQ9 VSSQ9 H9 J2 VDDQ8 VSSQ8 H1 G1 DDQ6
V SSQ6
V E8
[11,16] M_A_DIM0_CKE0 ZQL VDDQ10 VSSQ10 J8 VDDQ9 VSSQ9 H9 G9 DDQ7
V SSQ7
V F1
H5ANAG6NCMR-VKC E9 VDDQ10 VSSQ10 J2 DDQ8
V SSQ8
V H1
A
R1612 39 F9 ZQU E9 J8 DDQ9
V SSQ9
V H9 A
1%
[11,16] M_A_DIM0_CLK0
1%
ZQL F9 ZQU DDQ10

V SSQ10
V
240
240
H5ANAG6NCMR-VKC ZQL E9
F9 QU
Z
TBL1601 H5ANAG6NCMR-VKC
1%
1%
QL
Z
240
240
R1601
R1614
1%
1%
C1601 H5ANAG6NCMR-VKC
240
240
0.1u 10V TBL1601
1%
1%
R1623 39 TBL1601
240
240
R1628
R1633
[11,16] M_A_DIM0_CLK#0
R1609
R1617
BL1601
T
Wx H 602 x 390 mm
R1603
R1604
5 4 3 2
5 4 3 2 1
[11,17] _B_A[16:0] [11,17] _B_A[16:0]

M 1702A M 1703A
U U
[11,17] _B_A[16:0] _B_A0 _B_D31 _B_D[31:24] [11] _B_A0 _B_D41 _B_D[47:40] [11]
M 1701A M M
U M_B_A1 M_B_D29 M
_B_A1 M
_B_D44
_B_D[15:8] [11] P3 A 0 D G2 P3 A D G2
_B_A0 _B_D14 M_B_A2 QL0 M_B_D27 M
_B_A2 0 QL0 M
_B_D46
M P7 A 1 D F7 P7 A D F7
M_B_A1 M_B_D12 M_B_A3 QL1 M_B_D25 M
_B_A3 1 QL1 M
_B_D40
P3 A0 D QL0 G2 R3 A 2 D H3 R3 A D H3
_B_A4 2 QL2 M
_B_D47
P7 A1 D QL1 F7 N7 A 3 D H7 N7 A D H7
_B_A5 3 QL3 M
_B_D45
R3 A2 D QL2 H3 N3 A 4 D H2 N3 A D H2
_B_A6 4 QL4 M
_B_D43
N7 A3 D QL3 H7 P8 A 5 D H8 P8 A D H8
_B_A7 5 QL5 M
_B_D42
N3 A4 D QL4 H2 P2 A 6 D J3 _B_D[23:16] [11] P2 A D J3 _B_D[39:32] [11]
M_B_A6 M_B_D10 M_B_A8 QL6 M _B_D22 M
_B_A8 6 QL6 M
_B_D34
P8 A5 D QL5 H8 R8 A 7 D J7 M R8 A D J7 M
_B_A9 7 QL7 M
_B_D33
P2 A6 D QL6 J3 _B_D[7:0] [11] R2 A 8 D A3 R2 A D A3
M_B_A8 M _B_D2 M_B_A10 QU0 M_B_D23 M
_B_A10 8 QU0 M
_B_D39
R8 A7 D QL7 J7 M R7 A 9 D B8 R7 A D B8
M_B_A9 M_B_D4 M_B_A11 QU1 M_B_D17 M
_B_A11 9 QU1 M
_B_D32
R2 A8 D QU0 A3 M3 A 10/AP D C3 M3 A D C3
M_B_A10 M_B_D7 M_B_A12 QU2 M_B_D18 M
_B_A12 10/AP QU2 M
_B_D35
R7 A9 D QU1 B8 T2 A 11 D C7 T2 A D C7
M_B_A11 M_B_D0 M_B_A13 M 7 QU3 M_B_D20 M
_B_A13 M 7 11 QU3 M
_B_D37
M3 A 10/AP D QU2 C3 A 12/BC D C2 A D C2
D M_B_A12 M_B_D3 M_B_A14 QU4 M_B_D19 M
_B_A14 12/BC QU4 M
_B_D38 D
T2 A 11 D QU3 C7 T8 A 13 D C8 T8 A D C8
M_B_A13 M7 M_B_D1 M_B_A15 QU5 M_B_D21 M
_B_A15 13 QU5 M
_B_D36
A 12/BC D QU4 C2 L2 W E_N/A14 D D3 L2 W D D3
M_B_A14 M_B_D6 M_B_A16 QU6 M M
_B_A16 E_N/A14 QU6 M
T8 A 13 D QU5 C8 M8 C AS_N/A15 D D7 M8 C D D7
M_B_A15 M_B_D5 M QU7 M AS_N/A15 QU7
L2 W E_N/A14 D QU6 D3 L8 R AS_N/A16 L8 R
M_B_A16 M AS_N/A16
M8 C AS_N/A15 D QU7 D7
M [11,17] _B_ACT# L 3 _B_DQS3 [11] [11,17] _B_ACT# L 3 _B_DQS5 [11]
L8 R AS_N/A16 M A CT D QSL_T G3 M_B_DQS#3 [11] M A CT D QSL_T G3 M
_B_DQS#5 [11]
D QSL_C F3 M D QSL_C F3 M
[11,17] _B_ACT# L3 _B_DQS1 [11] [11,17] _B_BA0 [11,17] _B_BA0
M A CT D QSL_T G3 M_B_DQS#1 [11] M_B_BA1 N2 B M_B_BA1 N2 B
[11,17] _B_DQS2 [11] [11,17] _B_DQS4 [11]
D QSL_C F3 M M N8 B A0 D QSU_T B7 M_B_DQS#2 [11] M N8 B A0 D QSU_T B7 M
[11,17] _B_BA0 A1 A1 _B_DQS#4 [11]
N2 A7 A7
[11,17] M_B_BA1 B A0 _B_DQS0 [11] [11,17] _B_BG0 _B_BG1_R D QSU_C M [11,17] _B_BG0 _B_BG1_R D QSU_C M
M N8 B A1 D QSU_T B7 M_B_DQS#0 [11] M M2 B M M2 B
M M
TBL1601 D QSU_C A7 M M9 B G0 M9 B G0
[11,17] _B_BG0 _B_BG1_R G1 P 9 _B_ALERT# [11,17] G1 P 9 _B_ALERT# [11,17]
1739 0 M M2 B G0 A LERT M A LERT M
[11] _B_BG1 R1737 M [11,17] _B_DIM0_CLK0 [11,17] _B_DIM0_CLK0
M 0 M9 B G1 M K7 C M K7 C
P9 _B_ALERT# [11,17] [11,17] _B_DIM0_CLK#0 [11,17] _B_DIM0_CLK#0
R TBL1601 A LERT M M K8 C K_T0 M K8 C K_T0
[11,17] _B_DIM0_CLK0 K_C0 K_C0
M K7 C K_T0
[11,17] _B_DIM0_CLK#0 [11,17] _B_DIM0_CKE0 [11,17] _B_DIM0_CKE0
M K8 C K_C0 M K2 C M K2 C
KE KE
[11,17] _B_DIM0_CKE0 [11,17] _B_DIM0_CS#0 L 7 [11,17] _B_DIM0_CS#0 L 7
M K2 M M
teknisi indonesia
C KE C S C S
[11,17] _B_DIM0_CS#0 L7 [11] _B_DM3 E 7 [11] _B_DM5 E 7
M CS [11] M_B_DM2 D [11] M_B_DM4 D
E 2 ML_N/DBIL E 2 ML_N/DBIL
[11] _B_DM1 M D MU_N/DBIU M D MU_N/DBIU
E7
[11] M _B_DM0 E2 D ML_N/DBIL [11,17] _B_DIM0_ODT0 K3 O [11,17] _B_DIM0_ODT0 K3 O
M D MU_N/DBIU M
[11,17] _B_PAR M
[11,17] _B_PAR
M T3 P DT M T3 P DT
[11,17] _B_DIM0_ODT0 K3 AR AR
M
[11,17] _B_PAR O DT [11,17] _B_RST# [11,17] _B_RST#
T3 P 1 P 1
M P AR M R M R
N9 T ESET N9 T ESET
[11,17] _B_RST# P1 EN EN
M R ESET H5ANAG6NCMR-VKC H5ANAG6NCMR-VKC
N9 T EN [11,17] _B_A[16:0]
H5ANAG6NCMR-VKC M 1704A
U
_B_A0 _B_D57 _B_D[63:56] [11]
M M M
_B_A1 P3 G2 _B_D60
M A 0 D QL0 M
_B_A2 P7 A D F7 _B_D62
M
_B_A3 R3 1 QL1 H3 M
_B_D56
C M A 2 D QL2 M C
_B_A4 N7 A D H7 _B_D58
M
_B_A5 N3 3 QL3 H2 M
_B_D61
M A 4 D QL4 M
_B_A6 P8 A D H8 _B_D59
M
_B_A7 P2 5 QL5 J3 M
_B_D63
M A 6 D QL6 M _B_D51 _B_D[55:48] [11]
V_VDDQ_VTT _B_A8 R8 A D J7 M
+ M R2 7 QL7 A3 M
_B_A9 A D _B_D49
M R7 8 QU0 B8 M
_B_A10 A D _B_D55
M
_B_A11 M3 9 QU1 C3 M
_B_D52
M A 10/AP D QU2 M
1P2V_DUAL _B_A12 T2 A D C7 _B_D50
+ M M 7 11 QU3 C2 M
1730 1710 1733 1719 1736 _B_A13 A D _B_D53
C C C C C M T8 12/BC QU4 C8 M
0.22u 0.22u 0.22u 0.22u 0.22u V_VREF_CA_DIMM _B_A14 A D _B_D54
+ M L2 13 QU5 D3 M
6.3V 6.3V 6.3V 6.3V 6.3V _B_A15 W D _B_D48
M E_N/A14 QU6 M
TBL1601 _B_A16
M
M8
L8
C AS_N/A15 D QU7
D7
2P5VPP 1737 1724 1704 1720 1705 1729 1715 1727 1707 R AS_N/A16
+ C C C C C C C C C
0.22u 0.22u 0.22u 0.22u 0.22u 0.22u 0.22u 0.22u 0.22u [11,17] _B_ACT# L 3 _B_DQS7 [11]
1723 1713 1734 1716 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V M G3 M
A CT D QSL_T _B_DQS#7 [11]
C C C C F3 M
10V 0.1u 10V 0.1u 10V 0.1u 10V 0.1u [11,17] _B_BA0 D QSL_C
0201S_P33-W390201S_P33-W390201S_P33-W390201S_P33-W39 M N2
[11,17] _B_BA1 B A0 _B_DQS6 [11]
1711 1702 1728 1714 M N8 B7 M
C C C C B A1 D QSU_T _B_DQS#6 [11]
1u 1u 1u 1u 1709 1725 1708 1731 1717 1732 1712 1735 1721 A7 M
C C C C C C C C C [11,17] _B_BG0 D QSU_C
M _B_BG1_R M2
6.3V 6.3V 6.3V 6.3V 0.22u 0.22u 0.22u 0.22u 0.22u 0.22u 0.22u 0.22u 0.22u M B G0
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V M9
B G1
20% 20% 20% 20% one for each chip M1 pin A LERT
P 9 _B_ALERT# [11,17]
M
[11,17] _B_DIM0_CLK0 K7
M C K_T0
0201 0201 0201 0201 V_VDDQ_VTT [11,17] _B_DIM0_CLK#0 K8
+ M C K_C0
[11,17] _B_DIM0_CKE0 K2
M C KE
1741 1740 1739 1738 L 7
C C C C [11,17] _B_DIM0_CS#0
1u 1u 1u 1u M
https://vinafix.com
C S
1718 1703 1726 1706 1722 E 7
6.3V 6.3V 6.3V 6.3V 1P2V_DUAL C C C C C [11] _B_DM7
M
+ 0.22u 0.22u 0.22u 0.22u 0.22u [11] _B_DM6 E 2 D ML_N/DBIL
20% 20% 20% 20% 6.3V 6.3V 6.3V 6.3V 6.3V M D MU_N/DBIU
0201 0201 0201 0201 [11,17] _B_DIM0_ODT0
M K3
_B_PAR
[11,17] M
O DT
T3
P AR
B one for each VPP pin [11,17] _B_RST# P 1 B
M R ESET
N9
T EN
+V_VREF_CA_DIMM U1701B H5ANAG6NCMR-VKC
+2P5VPP
M1
V REFCA +V_VREF_CA_DIMM U1702B
B1 +2P5VPP +V_VREF_CA_DIMM U1703B
+1P2V_DUAL R9
V PP1
M1 +2P5VPP
V PP2 V REFCA +V_VREF_CA_DIMM 1704B
U
M1
V REFCA +2P5VPP
J1 B1
V DDL +1P2V_DUAL R9
V PP1
B1 M1
B3 V PP2 +1P2V_DUAL R9 V PP1 V REFCA
+V_VDDQ_VTT B9
V DD1
B2 J1
V PP2
B1
[11,17] M_B_A[16:0] D1
V DD2 V SS1
E1
V DDL
J1 +1P2V_DUAL R9
V PP1
M_B_A16R1736 39
G7
V DD3 V SS2
G8 B3
V DDL V PP2
M_B_A15R1728 39
J9
V DD4 V SS3
K1 B9
V DD1
B2 B3 J1
M_B_A14R1732 39 L1 V DD5 V SS4 K9 D1 V DD2 V SS1 E1 B9 V DD1 B2 V DDL
M_B_A13R1702 39
L9
V DD6 V SS5
N1 G7
V DD3 V SS2 G8 D1
V DD2 V SS1 E1 B3
M_B_A12R1708 39 R1
V DD7 V SS6
T1 J9
V DD4 V SS3 K1 G7
V DD3 V SS2 G8 B9
V DD1
B2
M_B_A11R1715 39 T9
V DD8 V SS7
T7 L1
V DD5 V SS4 K9 J9
V DD4 V SS3 K1 D1
V DD2 V SS1 E1
M_B_A10R1717 39 V DD9 V SS8
L9
V DD6 V SS5 N1 L1
V DD5 V SS4 K9 G7
V DD3 V SS2 G8
_B_A9
M
_B_A8
R1725 39 A1 A2 R1 V DD7 V SS6 T1 L9 V DD6 V SS5 N1 J9 V DD4 V SS3 K1
M R1730 39 A9 V DDQ1 V SSQ1 A8 T9 V DD8 V SS7 T7 R1 V DD7 V SS6 T1 L1 V DD5 V SS4 K9
M_B_A7 R1735 39 C1 V DDQ2 V SSQ2 C9 V DD9 V SS8 T9 V DD8 V SS7 T7 L9 V DD6 V SS5 N1
M_B_A6 R1701 39 D9 V DDQ3 V SSQ3 D2 A1 A2 V DD9 V SS8 R1 V DD7 V SS6 T1
M_B_A5 R1711 39 F2 V DDQ4 V SSQ4 D8 A9 V DDQ1 V SSQ1 A8 A1 A2 T9 V DD8 V SS7 T7
M_B_A4 R1714 39 F8 V DDQ5 V SSQ5 E3 C1 V DDQ2 V SSQ2 C9 A9 V DDQ1 V SSQ1 A8 V DD9 V SS8
M_B_A3 R1703 39 G1 V DDQ6 V SSQ6 E8 D9 V DDQ3 V SSQ3 D2 C1 V DDQ2 V SSQ2 C9 A1 A2
_B_A2 V DDQ7 V SSQ7
M R1712 39 G9 F1 F2 V DDQ4 V SSQ4 D8 D9 V DDQ3 V SSQ3 D2 A9 V DDQ1 V SSQ1 A8
_B_A1 V DDQ8 V SSQ8
M R1718 39 J2 H1 F8 V DDQ5 V SSQ5 E3 F2 V DDQ4 V SSQ4 D8 C1 V DDQ2 V SSQ2 C9
M_B_A0 R1716 39 J8 V DDQ9 V SSQ9 H9 G1 V DDQ6 V SSQ6 E8 F8 V DDQ5 V SSQ5 E3 D9 V DDQ3 V SSQ3 D2
R1726 39 V DDQ10 V SSQ10 G9 V DDQ7 V SSQ7 F1 G1 V DDQ6 V SSQ6 E8 F2 V DDQ4 V SSQ4 D8
[11,17] M_B_BG0
M_B_BG1_R R1731 TBL1601
39 E9 J2 V DDQ8 V SSQ8 H1 G9 V DDQ7 V SSQ7 F1 F8 V DDQ5 V SSQ5 E3
R1709 39 F9 Z QU J8 V DDQ9 V SSQ9 H9 J2 V DDQ8 V SSQ8 H1 G1 V DDQ6 V SSQ6 E8
[11,17] M_B_BA0 Z QL V DDQ10 V SSQ10
[11,17] M_B_BA1 R1721 39 J8 V DDQ9 V SSQ9 H9 G9 V DDQ7 V SSQ7 F1
A
R1729 39 H5ANAG6NCMR-VKC E9 V DDQ10 V SSQ10 J2 V DDQ8 V SSQ8 H1
A
[11,17] M_B_ACT#
[11,17] M_B_PAR R1704 39 F9 Z QU E9 J8 V DDQ9 V SSQ9 H9
1%
1%
R1713 39 Z QL F9 Z QU V DDQ10 V SSQ10

[11,17] M_B_DIM0_CS#0
240
240
R1710 39 H5ANAG6NCMR-VKC Z QL E9
[11,17] M_B_DIM0_ODT0
[11,17] M_B_DIM0_CKE0 R1720 39 TBL1601 H5ANAG6NCMR-VKC F9 Z QU
1%
1%
Z QL
240
240
1%
R1724
R1733
1%
H5ANAG6NCMR-VKC
240
240
[11,17] M_B_DIM0_CLK0 R1705 39 TBL1601
1%
1%
TBL1601
240
240
R1706
R1719
1734
1707
BL1601
T
R
1727
1722
C1701
0.1u 10V
R
[11,17] M_B_DIM0_CLK#0 R1723 39
5 4 3 2
5 4 3 2 1
+1P8V +1P8V_HDT
R1808 0 DNP
+1P8VSB
D D
R1809 0 DBG_D
R1803 R1802 R1810 R1805

1K 1K 1K 1K
DBG_D DBG_D DBG_D DBG_D
+1P8V_HDT
HDT+ conn.
R1801
not implemented
1K in form factor mbd.
DBG_D It is in Palomino. APU_TCK
APU_TCK [10,76]
APU_TMS
HDT_APU_TDI APU_TMS [10,76]
R1807 DBG_D0 APU_TDI [10,76]
APU_TDO
HDT_TRST# APU_TDO [10,76]
R1812 DBG_D33
[10,76] APU_TRST#
C1805 C1802 DNP
0.01u APU_DBREQ# 0.01u
C
DBG_D C
GND GND APU_DBREQ# [10,76]
C1804 DNP
0.01u
GND
+1P8V +1P8V
U1801 APU_TCK
R1814 R1817 DBG_D0
APU_TMS APU_TCK_MUX [29]
5 1K R1815 DBG_D0
VCC APU_TDI APU_TMS_MUX [29]
DBG_D R1818 DBG_D0 APU_TDI_MUX [29]
2 4 APU_TRST#_BUF APU_TDO R1816 DBG_D0
[10,18,33] APU_RESET# I O +3P3VSB APU_TRST# APU_TDO_MUX [29]
Nano-HDT+ conn. R1819 DBG_D0 APU_TRST#_MUX [29]
https://vinafix.com
1 C1803 APU_DBREQ# R1820 DBG_D0
NC1 APU_DBREQ#_MUX [29]
3 0.1u 10V
GND J1802
DBG_D
2 1
74AUP1G07GX 4 2 1 3 SAM_PCH_PWRBTN#_R R1822 DBG_D0 SAM_PCH_PWRBTN# [22,37]
DBG_D 6 4 3 5
B PCH_SYS_RST#_R R1821 DBG_D0 PCH_SYS_RST# [22,33]
B
+1P8V +1P8V 8 6 5 7 APU_RESET#_R R1823 DBG_D0 APU_RESET# [10,18,33]
APU_TCK 10 8 7 9 APU_TMS
HDT_TRST# 12 10 9 11 HDT_APU_TDI
U1802 12 11 APU_TDO
R1806 14 13
5 +1P8V APU_DBREQ# 16 14 13 15 APU_PWROK_BUF
1K
VCC 18 16 15 17 APU_TRST#_BUF
DBG_D
2 4 APU_PWROK_BUF 20 18 17 19
[10,20,33,66] PWROK I O 20 19
1 C1801 22 21
NC1 3 24 MH2 MH1 23
0.1u 10V
GND MH4 MH3
DBG_D
CPB0320-0150F
74AUP1G07GX
DBG_D
DBG_D
M1095858-001
Note:
J1802 layout symbol is wrong (mirrored)
Thus schematic symbol connections have been mirrored
in order to achieve correct implementation.
Decided to stay with layout symbol as is to not disrupt program.
A A
NEW DESIGNS:
Recommend fixing layout symbol for new designs and change schematics accordingly.
W x H 392 x 254 mm
5 4 3 2
5 4 3 2 1
D D
C C
B
Vinafix.com
A A
5 4 3 2
5 4 3 2 1
+ 1P8VSB
+ 3P3VSB
R 2041
100K 10K + 3P3V
R 2042 R 2022 49.9K
S AM_PCH_BASE [35]
R 2037 49.9K 0201S_P28-W35
0201S_P28-W35 T CON_VENDOR_ID [20,57,76]
D
Q 2002
Use 2-FET circuit to G
replace R2033 pull-up ALL R 2015 49.9K
D + 3P3V 0201S_P28-W35 S AM_PCH_LID_STATE [35] D
D
DNP
S
Q 2003
[10,18,20,33,66] PWROK G
ALL R 2049
10K ALL + 1P8VSB
S PI_CLK [20,21,38]
U 1001E
S
CLK/LPC/EMMC/SD/SPI/eSPI/UART
DNP
R 2046
3.3 PU AV18 10K
[44] M 2_PCIECLK_REQ# C LK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
[50] W IFI_PCIECLK_REQ# 3.3 PU AN19
3.3 PU AP19 C LK_REQ1_L/AGPIO115
[20,57,76] T CON_VENDOR_ID AT19 C LK_REQ2_L/AGPIO116
3.3 PU
3.3 PU AU19 C LK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 S PI_CS#0 [20,21,76]
APU_EGPIO120 3.3 NO AW18 C LK_REQ4_L/OSCIN/EGPIO132
3.3 PD AW19 C LK_REQ5_L/EGPIO120
0 R 2006 C LK_REQ6_L/EGPIO121
[54] I SP_FW_LOCK#
DNP BD13DUAL PD
E GPIO70/SD_CLK BB14DUAL S5 OUTPUT
AK1 L PC_PD_L/SD_CMD/AGPIO21 BB12DUAL PU B T_DISABLE# [33,50]
+3P3V +1P8V_PANEL + 1P8V [44] M 2_PCIECLK_P G PP_CLK0P L AD0/SD_DATA0/EGPIO104
M.2 SSD AK3 BC11DUAL PU
[44] M 2_PCIECLK_N G PP_CLK0N L AD1/SD_DATA1/EGPIO105 BB15DUAL PU
AM2 L AD2/SD_DATA2/EGPIO106 BC15DUAL PU
[50] P CIECLK_WIFI_DP G PP_CLK1P L AD3/SD_DATA3/EGPIO107
10K
10K
10K
WIFI AM4 BA153.3 OUTPUT

[50] P CIECLK_WIFI_DN G PP_CLK1N L PCCLK0/EGPIO74 BC133.3 OUTPUT
R 2008
R 2009
R 2047
R2035 0
AM1 L PC_CLKRUN_L/AGPIO88 BB133.3 OUTPUT D EPROM_PROG [57]
C DNP DNP D NP D NP C
AM3 G PP_CLK2P L PCCLK1/EGPIO75 BC123.3 PU
G PP_CLK2N S ERIRQ/AGPIO87 BA123.3 OUTPUT M EM_ID0 [22]
AL2 L FRAME_L/EGPIO109 U SBA_EN [45]
AL4 G PP_CLK3P BD113.3 S5 OUTPUT R 2040 49.9K
G
DNP
G PP_CLK3N L PC_RST_L/SD_WP_L/AGPIO32 BA113.3 PD
AN2 A GPIO68/SD_CD BA133.3 S5 PU T P2002
D S TPANEL_RST# [20,30,33,35]
AN4 G PP_CLK4P L PC_PME_L/SD_PWR_CTRL/AGPIO22
G PP_CLK4N S AM_PCH_LID_STATE R2010 2K
D
Q2005 AN3 ALL
SOTFL-3_1P3XP9XP55_P4 AP2 G PP_CLK5P BC8 1.8 S5 PD S AM_PCH_BASE G
G PP_CLK5N S PI_ROM_REQ/EGPIO67 BB8 1.8 S5 PD ALL P WROK [10,18,20,33,66]
AJ2 S PI_ROM_GNT/AGPIO76 Q 2001
EGPIO142 [20] AJ4 G PP_CLK6P BB11DUAL PU
S
G PP_CLK6N E SPI_RESET_L/KBRST_L/AGPIO129 BC6 DUAL PD
X 48M_OSC AJ3 E SPI_ALERT_L/LDRQ0_L/EGPIO108
T P2004 X 48M_OSC BB7 1.8 S5 A PU_SPI_CLK 5.1 R 2029
S PI_CLK/ESPI_CLK BA9 1.8 S5 A PU_SPI_MISO 5.1 S PI_CLK [20,21,38]
R 2024
X TAL_48M_X1 BB3 S PI_DI/ESPI_DAT1 BB101.8 S5 A PU_SPI_MOSI 5.1 S PI_MISO [21,38]
R 2003
1M X TAL_48M_X2 X 48M_X1 S PI_DO/ESPI_DAT0 BA101.8 S5 S PI_MOSI [21,38]
R2026
S PI_WP_L/ESPI_DAT2 BC101.8 S5 S PI_WP_IO2 [21]
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S PI_HOLD_L/ESPI_DAT3 BC9 1.8 S5 PU S PI_HOLD#_IO3 [21]
BA5 S PI_CS1_L/EGPIO118 BA8 1.8 S5 PU S PI_CS#0 [20,21,76]
48 MHz Y2001 X 48M_X2 S PI_CS2_L/ESPI_CS_L/AGPIO30 BA6 1.8 S5 PU S PI_TP_CS# [21]
1 3 90.9 R2083 S PI_CS3_L/AGPIO31 BD8 1.8 S5 NO T PM_IRQ# [38]
2 40201S_P28-W35 S PI_TPM_CS_L/AGPIO29 S PI_TPM_CS# [21,38]
B
GND AE30 B
R SVD15 T PANEL_RST# [20,30,33,35]
C2006 C2007 AE32 BA16 1.8 PD
25V 15p 25V 15p R SVD16 U ART0_RXD/EGPIO136 BB18 1.8 PU
0201S_P33 0201S_P33 U ART0_TXD/EGPIO138 BC17 1.8 PU + 1P8V
U ART0_RTS_L/UART2_RXD/EGPIO137 BA18 1.8 PD
T P2001 AW14 U ART0_CTS_L/UART2_TXD/EGPIO135 BD18 0
[50] S USCLK 1.8 PD AGPIO139 R 2038
R TCCLK U ART0_INTR/AGPIO139 ALL
AY1 BC18 3.3 PD

20M R 2001 R TC_X1 X 32K_X1 E GPIO141/UART1_RXD BA17
R 2036
R 2032
R 2031
R 2030
3.3 PU
100K
100K
100K
100K
0402S_P4 R TC_X2 E GPIO143/UART1_TXD BC16 3.3 PU
E GPIO142/UART1_RTS_L/UART3_RXD E GPIO142 [20]
BB19 3.3 PD
AY4 E GPIO140/UART1_CTS_L/UART3_TXD BB16
2 1 CTAL_1 0 R 2005
0201S_P28-W35 X 32K_X2 A GPIO144/UART1_INTR
3.3 PD
1.8V logic level
S AMTX_PCHRX [29,33,34]
C2002 X2001
25V 15p 32.768KHZ P CHTX_SAMRX [29,33,34]
C 2001
0201S_P33 XTAL2_3P3X1P6XP9_2P5 25V 15p P CHRTS_SAMCTS [29,33,34,76]
5% 0201S_P33 YW3500C4T4MFG S AMRTS_PCHCTS [29,33,34,76]
5%
+ 1P8VSB Debug UART

R 2019 0 + 3P3V
P CH_DBG_RX [29,33,76]
R 2034 0
P CH_DBG_TX [29,33,76]
DNP
R 2033
10K R 2027
A 100K 100K
R 2021 A
3.3V logic level

S PI_CLK [20,21,38]
1:USE 48MHZ CRYSTAL CLOCK AND

GENERATE BOTH INTERNAL AND EXTERNAL CLOCKS(DEFAULT)
5 4 3 2
5 4 3 2 1
D D
Vinafix.com
1P8VSB
+
1P8V_TS
+
2102
C
0.1u 1P8VSB
+
2101
C
0.1u ND
G
place close to TPM and UEFI chip

U2101
ND 3
G 2 CCA
VCCB
V 5 1P8VSB
C S_SPI_MOSI_BUFF 1 PI_MOSI [20,21,38] + C
2136 0 T 16 A 4 S
[30] S_SPI_MOSI R 1 IR1
T B D
6
S_SPI_MISO_BUFF 15 2 1 PI_MISO [20,21,38]
2135 0 T A S 2103
[30] S_SPI_MISO R 2 IR2 R
T B D 10K
7
S_SPI_CLK_BUFF 14 3 12 PI_CLK [20,21,38]
2139 0 T A S
[30] S_SPI_CLK R 3 IR3
T B D
8
S_SPI_CS#_BUFF 13 4 9 PI_TP_CS# [20]
2131 0 T A S
[30] S_SPI_CS# R 4 IR4
T B D
10 1
ND E 1
G O
4AVC4TD245GU
7 DIRn: HIGH A->B, LOW A<-B
ND
1P8VSB G
+
1P8VSB ND
+ G
2104
U
https://vinafix.com
5 P2102
CC T
2103 V
C S_SPI_AND_B S_SPI_OE#
0.1u 2 A Y 4 T 2151 0 ALL T
R
2105 0201
U
74AUP1G08GX 10V 1 OE 3
C2104
5 GND 0.1u 10V
2 VCC 4 TS_SPI_AND 74AUP1G240GX R2150
[20,21,76] SPI_CS#0
1 A Y 0
B 3
0 GND DNP +1P8VSB 1P8VSB
[20,38] SPI_TPM_CS# R2101 +
GND GND GND
+1P8V_TS
R2121
10K
R2120
10K
DNP
UEFI SPI ROM C2111
0.1u
10V
0201 2122
R
TP2101 ALL
10K
2102
R
10K
B U2102 DNP 10K B

R2106
8 5
6 VCC DI/IO0 2
1 CLK O/IO1
D 3
4 CS_N O2
I 7
D2101 +1P8VSB +3P3V 9 GND O3
I
K A MPAD
TS_SPI_EN [30] W25Q128JWPIQ
10K
RB520CS3002L
C2106
2105
0.1u 10V
1P8VSB
+ 1P8VSB
+ 1P8VSB
+
R
U2106
5
VCC
2 4
SPI_CLK = 20/33/50Mhz 2103
U 2125
R
I O TS_SPI_EN_SOC [22] UEFI_SPI1_CLK 1 5 100K
OM1 + 2148 2124
1 UEFI_SPI_IO0 3 C V R
1K
R
1K
0201 IN1/IN2 = L => COM to NC
NC1 3 ALL UEFI_SPI_IO1 4 OM2
C 17 DNP IN1/IN2 = H => NC to COMTP2107
GND R2107 UEFI_SPI_IO2 6 OM3
C N#
E 2110
C DBG_D DBG_D M
OM4
499K UEFI_SPI_IO3 7 C 21 0.1u R2126
AM_FLASH_UEFI [35,76]
74AUP1G07GX OM5 N1 S
UEFI_SPI_CS# 9 C I 11 10V 2K
OM6
C N2
I DBG_D DBG_D
25 2
24 PAD ND
G
23 N.C. 8
[76] SPI_CLK_R1 22 NC1 O1
N 10 AM_UEFIROM_SPI_CLK [34]
S
[76] SPI_MOSI_R1 20 NC2 O2
N 12 AM_UEFIROM_SPI_MOSI [34]
S
[76] SPI_MISO_R1 18 NC3 O3
N 14 AM_UEFIROM_SPI_MISO [34]
S
SPI1_WP#_DBG
[76] SPI_WP_IO2_R1 16 NC4 O4
N 15 SPI1_HOLD#_DBG
[76] SPI_HOLD#_IO3_R1 NC5 O5
N
19 13
[20,21,76] SPI_CS#0 NC6 O6
N AM_UEFIROM_SPI_CS# [35]
S
0 DBG_N SPI_CLK_R1 TS3A27518ERTW

2138 15 R PI_CLK
S
R2127 R PI_CLK [20,21,38]
S
R2128 0 DBG_N SPI_MOSI_R1 2137
R 15 PI_MOSI
S
PI_MOSI [20,21,38]
S
R2146 0 DBG_N SPI_MISO_R1 2145
R 15 PI_MISO
S
PI_MISO [20,21,38]
S
R2130 0 DBG_N SPI_WP_IO2_R1 R
2144 33 PI_WP_IO2
S
PI_WP_IO2 [20]
S
R2147 0 DBG_N SPI_HOLD#_IO3_R1R2108 33 PI_HOLD#_IO3
S
PI_CS#0 PI_HOLD#_IO3 [20]
S
R2149 0 DBG_N S
A Populate for production only A
5 4 3 2
5 4 3 2 1
TBL2201
+1P8VSB
+3P3V +3P3VSB +3P3V
C2202 R2242 R2240 R2044

10V 0.1u 10K 10K 10K
0201S_P33-W 39 U2202 TBL2201 TBL2201 TBL2201
74AUP1G08GX
5 SOT1226_P85XP85XP35_P48
V CC MEM_ID0 [20]
4 2
[33,34,38,44] PLT_RST_BUF# Y A 1 MEM_ID1 [22]
3 B MEM_ID2 [22]
TP2203 G ND
D R2224 C2204 D
49.9K 100p 25V R2243 R2241 R2045
0201S_P28-W35
Note: 0201S_P33
10K 10K 10K
Place C2204 TBL2201 TBL2201 TBL2201
next to U2202.2
PLTRST#
[58] PLTRST#
R2208
75K
DNP
+3P3VSB
+1P8V_PANEL
0201
C2205 +3P3VSB +
3P3VSB
U2204 0.1u 10V
74AUP1G08GX 2.2K 2.2K
5 DNP DNP
V CC
R2260 0 2 4 APU_PW R_GOOD [61] R2252 R2253 R2206 R
2233
[58] ALL_SYS_PW RGD A Y
R2261 0 1
0201S_P28-W35
10K 10K
[37] SYS_PW ROK 0201S_P28-W35 B 3 U1001D
GND
ACPI/AUDIO/I2C/GPIO/MISC
C AW12 3.3 S5 ?? A
GYRO_INT1#_R C
+3P3VSB S FI_S5_EGPIO41 AU12 3.3 S5 ?? ALS_INT#_R T 2205
P
R2255 3.3 S5 OUTPUT BD5 S FI_S5_AGPIO39 T 2210
P
TP2219 P CIE_RST0_L/EGPIO26
100K TP2209 RST1 3.3 S5 PD BB6 AR13 DUAL S5
PM_RSMRST_R 1.8 S5 AT16 P CIE_RST1_L/EGPIO27 I 2C0_SCL/SFI0_I2C_SCL AT13 DUAL S5 T 2211
P
R2225 R2239 0
[35,37] RSMRST_1v8# R SMRST_L I 2C0_SDA/SFI0_I2C_SDA T 2212
P
10K
0201S_P28-W 35 0 R2232 3.3 S5 PU AR15 AN8 DUAL S5
TP2218 [18,22,37] SAM_PCH_PW RBTN# AV6 P WR_BTN_L/AGPIO0 I 2C1_SCL/SFI1_I2C_SCL AN9 DUAL S5
P
MI_I2C_SCL [28,33,76]
APU_PW R_GOOD
3.3 S5 PU AP10 P WR_GOOD I 2C1_SDA/SFI1_I2C_SDA P
MI_I2C_SDA [28,33,76]
[18,33] PCH_SYS_RST# 3.3 S5 PU AV11 S YS_RESET_L/AGPIO1 BC20 DUAL
[50] WIFI_W AKE# W AKE_L/AGPIO2 I 2C2_SCL/EGPIO113/SCL0 BA20 DUAL P
ANEL_I2C_SCL [33,57]
R2212 APU_SLP_S3# AV13 I 2C2_SDA/EGPIO114/SDA0 P
ANEL_I2C_SDA [33,57]
0
R2267 SLP_S4#_R AT14 S LP_S3_L AM9 DUAL S5 R
[33,34] SLP_S4# 33 0 ALL 2247
S LP_S5_L I 2C3_SCL/AGPIO19/SCL1 AM10 DUAL S5 R S
OC_SENSOR_ACS_SCL [54,76]
0 2248 S
APU_S0A3 TP2220 3.3 S5 PU AR8 I 2C3_SDA/AGPIO20/SDA1 OC_SENSOR_ACS_SDA [54,76]
ALL
R2203 S 0A3_GPIO/AGPIO10 L16
[33,34,58] SLP_S3# P SA_I2C_SCL
75K 3.3 S5 PU AT10 M16
[37] SAM_PCH_ACPRESENT A C_PRES/AGPIO23 P SA_I2C_SDA
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3.3 S5 OUTPUT AN6
TP2221 R2209 TP2202 L LB_L/AGPIO12
75K +3P3VSB AT15 3.3 S5 PU
R2268
3.3 S5 PUAW8 A GPIO3 AW10 3.3 S5 PD M

EM_ID1 [22]
10K
TP2208 R2213 E GPIO42 A GPIO4/SATAE_IFDET P

CIE_W IFI_PERST# [50]
2.2K S
AP9 3.3 S5 PD AM_PCH_RTCW AKE_D [22] R
2216 49.9K
A GPIO5/DEVSLP0 AU10 3.3 S5 PD R2228
APU_S0A3 [33,37] 1K R
A GPIO6/DEVSLP1 AV15 3.3 PU TD3_CAM_PW REN [54,76]
S ATA_ACT_L/AGPIO130 M
EM_ID2 [22]
R2226 10K LLB# AU7 3.3 S5 PD
+3P3VSB A GPIO9 I
SH_SAM_INT [34]
AU6 3.3 S5 NO
A GPIO40 P
CIE_SSD_PERST# [44]
0 DNP R2205 FLASH_PROTECT#_R AW13 3.3 PD
B [30] FLASH_PROTECT# A GPIO69 AW15 3.3 Pu R R B
2246 0 DNP P 2215 49.9K
AR2 A GPIO86 CH_SAM_INST_ON [34,72]
AP7 A Z_BITCLK/TDM_BCLK_MIC P
CH_SAM_INT [22,34]
R2020, R2053, R2054 can be R2249 0
changed to 33ohm to tune if HDA AP1 A Z_SDIN0/CODEC_GPI AU14
A Z_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK I NTRUDER_ALERT T
P2217 T
P2206
doesnt work. AP4 AU163.3 PD
HDA_BCLK_R AP3 A Z_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK S PKR/AGPIO91 AV8 3.3 S5 PU PCH_PW RBTN# RTD3_TPANEL_PW R [62,64]
R2201 0 R
2202 0
[40] MHDA_BCLK HDA_SYNC_R AR4 A Z_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC B LINK/AGPIO11 S
AM_PCH_PW RBTN# [18,22,37]
R2229 0
[40] MHDA_SYNC HDA_SDO_R AR3 A Z_SYNC/TDM_FRM_MIC AW163.3 PU
R2210 0 T 2201
P
[40] MHDA_SDOUT A Z_SDOUT/TDM_FRM_PLAYBACK G ENINT1_L/AGPIO89 BD153.3 PU +P8V_PANEL
1
[40] MHDA_SDIN HDA_RST# AT2 G ENINT2_L/AGPIO90
AT4 S W_MCLK/TDM_BCLK_BT +
3P3V
0 R2007 AGPIO7 AUD PD AR6 S W_DATA0/TDM_DOUT_BT AR183.3 PU
10K
AUD PD AP6 A GPIO7/FCH_ACP_I2S_SDIN_BT F ANIN0/AGPIO84 AT183.3 PU
R2204
A GPIO8/FCH_ACP_I2S_LRCLK_BT F ANOUT0/AGPIO85
2p
2p
2p
10K
R2214
R2217
75K YW 3500C4T4MFG
C2206
C2201
C2207
DNP
[54] ACS_INT# R2207 TS_IRQ#_R
0
[30] TS_IRQ_3V3#
G
D S
R2023 E
DP_I2C_INT [57,76]
49.9K
PCH_SAM_INT [22,34]
49.9K R2016
[35] SAM_PCH_INT Q
2206
DNP
SOTFL-3_1P3XP9XP55_P4
T
S_SPI_EN_SOC [21]
+3P3VSB
A A
R2234 49.9K ISH_SAM_INT 100K

0201S_P28-W 35 R2002
R2222 49.9K RTD3_TPANEL_PW R
0201S_P28-W 35
RTD3_CAM_PW REN D2001
R2227 49.9K
0201S_P28-W 35 K A
PCH Signal Glitch Free Implementation Requirements [35] SAM_PCH_RTCW AKE SAM_PCH_RTCW AKE_D [22]
ALL
RB520CS3002L
200mA
5 4 3 2
5 4 3 2 1
D D
U1001M
CAMERAS
A18 B15
C18 C AM0_CSI2_CLOCKP C AM0_CLK
C AM0_CSI2_CLOCKN D15
A15 C AM0_I2C_SCL C14
C15 C AM0_CSI2_DATAP[0] C AM0_I2C_SDA
C AM0_CSI2_DATAN[0] B13
B16 C AM0_SHUTDOWN
C16 C AM0_CSI2_DATAP[1]
C AM0_CSI2_DATAN[1]
C19
B18 C AM0_CSI2_DATAP[2]
C AM0_CSI2_DATAN[2]
B17
D17 C AM0_CSI2_DATAP[3]
C AM0_CSI2_DATAN[3]
D12 B10
B12 C AM1_CSI2_CLOCKP C AM1_CLK
C AM1_CSI2_CLOCKN A11
C13 C AM1_I2C_SCL C11
A13 C AM1_CSI2_DATAP[0] C AM1_I2C_SDA
C AM1_CSI2_DATAN[0] D11
B11 C AM1_SHUTDOWN
C C AM1_CSI2_DATAP[1] C
C12 D13
C AM1_CSI2_DATAN[1] C AM_PRIV_LED D10
J13 C AM_IR_ILLU
R SVD98
YW 3500C4T4MFG
B
XTAL FREQUENCY SELECTION

GPP_F0
0 Default 38.4MHZ
1 24MHZ
CNVI ENABLE
GPP_F2
0 Default Integrated CNVi Enabled

A A
1 Integrated CNVi Disabled
W x H 422 x 273 mm
5 4 3 2
5 4 3 2 1
U 1001B
PCIE
P8 N1
P9 P _GFX_RXP[0] P _GFX_TXP[0] N3
U 1001J P _GFX_RXN[0] P _GFX_TXN[0]
N6 M2
USB
N7 P _GFX_RXP[1] P _GFX_TXP[1] M4
AE7 AD2 P _GFX_RXN[1] P _GFX_TXN[1]
[77] USB2_TCP0_DP U SB_0_DP0 U SBC0_A2/USB_0_TXP0/DP3_TXP[2] T CP0_TX_P0 [77]
AE6 AD4 M8 L2
USB2 USB-C [77] USB2_TCP0_DN U SB_0_DM0 U SBC0_A3/USB_0_TXN0/DP3_TXN[2] T CP0_TX_N0 [77] M9 P _GFX_RXP[2] P _GFX_TXP[2] L4
D AG10 AC2 P _GFX_RXN[2] P _GFX_TXN[2] D
[45] USB2_USBA_DP
AG9 U SB_0_DP1 U SBC0_B11/USB_0_RXP0/DP3_TXP[3] AC4 T CP0_TXRX_P0 [77] L6 L1
USB2 USB-A [45] USB2_USBA_DN U SB_0_DM1 U SBC0_B10/USB_0_RXN0/DP3_TXN[3] T CP0_TXRX_N0 [77] L7 P _GFX_RXP[3] P _GFX_TXP[3] L3
AF12 AF4
TPC USB-C P _GFX_RXN[3] P _GFX_TXN[3]
[50] USB2_BT_DP U SB_0_DP2 U SBC0_B2/DP3_TXP[1] T CP0_TX_P1 [77]
AF11 AF2 K11 K2
USB2 WIFI [50] USB2_BT_DN U SB_0_DM2 U SBC0_B3/DP3_TXN[1] T CP0_TX_N1 [77] J11 P _GFX_RXP[4] P _GFX_TXP[4] K4
AE10 AE3 P _GFX_RXN[4] P _GFX_TXN[4]
AE9 U SB_0_DP3 U SBC0_A11/DP3_TXP[0] AE1 T CP0_TXRX_P1 [77] H6 J2
U SB_0_DM3 U SBC0_A10/DP3_TXN[0] T CP0_TXRX_N1 [77] H7 P _GFX_RXP[5] P _GFX_TXP[5] J4
USB2 SL40 AJ12 AG3 P _GFX_RXN[5] P _GFX_TXN[5]
[71] USB2_SL1_DP U SB_1_DP0 U SB_0_TXP1 U SB3_USBA_TX_DP [45]
AJ11 AG1 G6 H1
[71] USB2_SL1_DN U SB_1_DM0 U SB_0_TXN1 U SB3_USBA_TX_DN [45] P _GFX_RXP[6] P _GFX_TXP[6]
F7 H3
AD9 AJ9
USB3 USB-A P _GFX_RXN[6] P _GFX_TXN[6]
USB2 Camera [54] CAM_USB_DP_SOC U SB_1_DP1 U SB_0_RXP1 U SB3_USBA_RX_DP [45]
AD8 AJ8 G8 H2
+3P3VSB [54] CAM_USB_DM_SOC U SB_1_DM1 U SB_0_RXN1 U SB3_USBA_RX_DN [45] F8 P _GFX_RXP[7] P _GFX_TXP[7] H4
AG4 P _GFX_RXN[7] P _GFX_TXN[7]
U SB_0_TXP2 AG2
U SB_0_TXN2 PCIE M.2 SSD PCIE M.2 SSD
R2404 1K
R2418 1K AG7 N10 N2
U SB_0_RXP2 [44] P CIE_SSD2_RX0_DP P _GPP_RXP[0] P _GPP_TXP[0] P CIE_SSD2_TX0_DP [44]
[77,79] APU_PD_SCL AM6 AG6 N9 P3
U SBC_I2C_SCL U SB_0_RXN2 [44] P CIE_SSD2_RX0_DN P _GPP_RXN[0] P _GPP_TXN[0] P CIE_SSD2_TX0_DN [44]
AM7 AA2 L10 P4
[77,79] APU_PD_SDA U SBC_I2C_SDA U SBC1_A2/USB_0_TXP3/DP2_TXP[2] [44] P CIE_SSD2_RX1_DP P _GPP_RXP[1] P _GPP_TXP[1] P CIE_SSD2_TX1_DP [44]
AA4 L9 P2
U SBC1_A3/USB_0_TXN3/DP2_TXN[2] [44] P CIE_SSD2_RX1_DN P _GPP_RXN[1] P _GPP_TXN[1] P CIE_SSD2_TX1_DN [44]
Y1 L12 R3
U SBC1_B11/USB_0_RXP3/DP2_TXP[3] [44] P CIE_SSD2_RX2_DP P _GPP_RXP[2] P _GPP_TXP[2] P CIE_SSD2_TX2_DP [44]
Y3 M11 R1
C U SBC1_B10/USB_0_RXN3/DP2_TXN[3] [44] P CIE_SSD2_RX2_DN P _GPP_RXN[2] P _GPP_TXN[2] P CIE_SSD2_TX2_DN [44] C
[33,50] W LAN_DISABLE#
AC1 P12 T4
USBC1_B2/DP2_TXP[1] AC3 [44] P CIE_SSD2_RX3_DP P11 P _GPP_RXP[3] P _GPP_TXP[3] T2 P CIE_SSD2_TX3_DP [44]
USBC1_B3/DP2_TXN[1] [44] P CIE_SSD2_RX3_DN P _GPP_RXN[3] P _GPP_TXN[3] P CIE_SSD2_TX3_DN [44]
3.3 S5 PU AK10
TP2402 3.3 S5 PU AK9 USB_OC0_L/AGPIO16 AB2
[79] TCP0_OC# 3.3 S5 PU AL9 USB_OC1_L/AGPIO17 USBC1_A11/DP2_TXP[0] AB4
TP2401 3.3 S5 PU AL8 USB_OC2_L/AGPIO18 USBC1_A10/DP2_TXN[0] PCIE WIFI V6 W2
PCIE WIFI
[45] USBA_OVCUR# USB_OC3_L/AGPIO24 [50] P CIE_WIFI_RX0_DP P _GPP_RXP[4] P _GPP_TXP[4] P CIE_WIFI_TX0_DP [50]
3.3 S5 PU AW7 AH4 V7 W4
[31,33] VOL_UP# AGPIO14/USB_OC4_L U SB_1_TXP0 U SB3_SL1_TXP4 [71] [50] P CIE_WIFI_RX0_DN P _GPP_RXN[4] P _GPP_TXN[4] P CIE_WIFI_TX0_DN [50]
3.3 S5 PU AT12 AH2
[31,33] VOL_DOWN# AGPIO13/USB_OC5_L U SB_1_TXN0 U SB3_SL1_TXN4 [71] T8 W3
P _GPP_RXP[5] P _GPP_TXP[5]
PU_AGPIO17
AK7 USB3 SL40 T9 V2

U SB_1_RXP0 AK6 U SB3_SL1_RXP4 [71] P _GPP_RXN[5] P _GPP_TXN[5]
0 U SB_1_RXN0 U SB3_SL1_RXN4 [71] R6 V1
R2410
A
[65] +3P3V_PANEL_EN_R R7 P _GPP_RXP[6]/SATA_RXP0 P _GPP_TXP[6]/SATA_TXP0 V3

YW3500C4T4MFG P _GPP_RXN[6]/SATA_RXN0 P _GPP_TXN[6]/SATA_TXN0
R9 U2
R10 P _GPP_RXP[7]/SATA_RXP1 P _GPP_TXP[7]/SATA_TXP1 U4
P _GPP_RXN[7]/SATA_RXN1 P _GPP_TXN[7]/SATA_TXN1
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YW3500C4T4MFG
B B
Vinafix.com
A A
5 4 3 2
5 4 3 2 1
D D
C C
B
A A
5 4 3 2
5 4 3 2 1
D D
C C
B
A A
5 4 3 2
5 4 3 2 1
D D
C C
B
5 4 3 2
5 4 3 2 1
D D
3P3VSB 3P3V_PMI
+ +
2801 DBG_TS 0.1

R
+3P3V_PMI
Imax=0.0042A
3P3V_PMI
+
201S_P28-W35
201S_P28-W35
2K
2K
C r*2 = 730uA C
I
0
MI1_I2C_SCL_R [76]
2862
2863
PMI1_I2C_SDA_R [76]
R
BG_TBG_T P
D D
DBG_T DBG_T
2854 0 2874 0
[22,33,76] MI_I2C_SCL R R M_DBG_I2C_SCL [29]
P 0201S_P28-W35 0201S_P28-W35 P
DBG_T DBG_T o debug connector
t
2855 0 2875 0
[22,33,76] MI_I2C_SDA R 3P3V_PMI R M_DBG_I2C_SDA [29]
P 0201S_P28-W35 + 0201S_P28-W35 P
3P3V_PMI 3P3V_PMI
+ +
Avila +5VSB while Carmel monitors PM_BLADE_IN+ U2802 DBG_T
U2813 DBG_T
[59] M_5VSB_IN+ A3 A4 C
2801 U2803 DBG_T MAX34417 VDD Average Supply Current
2825 0.1u 10V 2802
[68] M_VDDSOC_IN+
P A3
I N1+ V DD
A4 C
0.1u 10V
P
[59] M_5VSB_IN-
P A2
I N1+
I N1-
V DD
0201S_P33-W39
[67] M_VDDCORE_IN+
P A3
I N1+ V DD
A4 C
0.1u 10V
700uA PDNB=VIO and SLOW=GND
[68] M_VDDSOC_IN- [67] M_VDDCORE_IN-
P A2
I N1-
B2
0201S_P33-W39
[59] M_3P3VSB_IN+ A1
V IO
B2
G
ND P A2
I N1-
B2
0201S_P33-W39 10uA PDNB=VIO and SLOW=VIO
Avila V IO P I N2+ V IO
+VSYS [62] M_1P8VSB_IN+
P
[62] M_1P8VSB_IN-
A1
I N2+ G
ND [59] M_3P3VSB_IN-
P B1
I N2-
[60]
[60]
M_1P2V_DDR_VDDQ_IN+
P
M_1P2V_DDR_VDDQ_IN-
A1
I N2+
ND
G 2uA PDNB=GND
while P B1 C4 P B1
Carmel I N2- [65] M_3P3V_SSD+ S CL I N2-
C4 P D1 D4 DBG_T C4
S CL I N3+ S DA S CL
monitors
+3P3VAS
[63] M_VSYS+
P
[63] M_VSYS-
D1
C1
I N3+ S DA
D4 DBG_T
[65] M_3P3V_SSD-
P C1
I N3- B 3 P
MI1_PDN_N 2865
R
10K 3P3V_PMI
[65]
[65]
M_3P3V_PANEL_IN+
P
M_3P3V_PANEL_IN-
D1
C1
I N3+ S DA
D4 DBG_T 6x700uA=4.2mA
MI0_PDN_N 2856 + MI2_PDN_N 2867
P I N3-
P DN
B3 P R
10K
0201S_P28-W35 +
3P3V_PMI [65] M_3P3V_WWAN+
P D3
I N4+
P DN 0201S_P28-W35 P I N3-
P DN
B 3 P R
10K
0201S_P28-W35
3P3V_PMI
+ 3.3Vx4.2mA=13.86mW
[61] M_VDDP_IN+ D3 [65] M_3P3V_WWAN- D2 C3 [72] M_BKLT_IN+ D3
P I N4+ P I N4- S LOW P I N4+
[61] M_VDDP_IN- D2 C3 MI1_ADDR [72] M_BKLT_IN- D2 C3
P I N4- S LOW P I N4- S LOW
MI0_ADDR C2 P MI2_ADDR
P A DDR
C2 P
C2
B DBG_T
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A DDR A DDR
A G ND
B4
DBG_T
2866
G ND
AX34417
B4
R
2864
499
C G ND
B4
DBG_T
2850
R M R
AX34417 0 DBG_T 0201S_P28-W35 AX34417 931
M M
DBG_T 0201S_P28-W35 DBG_T 0201S_P28-W35
Address(7b) = 0x10 Address(7b) = 0x12 GND

GND GND GND GND Address(7b) = 0x14 ND
G
B GND ND G
G ND
B
Ir=12uA
Part A
VDDCR SOC Delos Core Power Supply Part B
1P8 VSB Part C
5VSB VDDCR Delos Core Power Supply
VSYS 3P3 VSB
VDDP Delos Power Supply Memory VDDQ Power Supply
3P3 SSD 3P3V Display Panel Supply
3P3V WWAN Backlight Power Supply
A A
5 4 3 2
5 4 3 2 1
+3P3V_DEBUG
+3P3VA +3P3V_DEBUG +3P3V_DEBUG +3P3V_DEBUG
C2902 R2913 0 DBG_D C2901

U2906
U2901 0.1u 0603S_P6-W95 0.1u C2906
10V DBG_D 0.1u
VDD 20 VCC 54
keep USB2 traces as short as possible between muxes GND [37,79] PD_SAM_DBG_ACC_MODE R2904 DBG_D0 2 10V
DBG_D A Y
[33,74] SAM_KIP_UART_TX_DBG 7 8 GND U2902 [29,58] SAM_DBG_MODE R2911 DBG_D0 1 DBG_D
IA0 YA B
[30,33] TS_TCK_1V8 6 IA1 VDD 20 GND 3 GND
[74,76] KIP_SWD_CLK 5 IA2 +3P3V_DEBUG 74LVC1G32GX
[20,33,34] SAMTX_PCHRX 4 IA3 [33,34,76] SAM_SWD_CLK 7 IA0 YA 8
[18] APU_TCK_MUX R2926 DBG_D 0 APU_TCK_MUX_R R2907 DBG_D
D 6 IA1 D
13 12 R2918 DBG_D 0 PCH_DBG_TX_R 5 100K
[33,74] SAM_KIP_UART_RX_DBG IB0 YB [20,33,76] PCH_DBG_TX IA2 0201 C2909 GND
[30,33] TS_TDI_1V8 14 IB1 4 IA3
[74] KIP_SWD_DIO 15 1 DBG_D 0.1u
IB2 NC_1 DBG_D U2908
[20,33,34] PCHTX_SAMRX 16 IB3 NC_2 9 [33,34,76] SAM_SWD_DIO 13 IB0 YB 12
11 [18] APU_TDI_MUX R2919 DBG_D0 APU_TDI_MUX_R 14 5
MUX0_EN# 2 NC_3 R2927 DBG_D0 PCH_DBG_RX_R 15 IB1 4 VCC 1 DBG_USB_EN
EN NC_4 18 [20,33,76] PCH_DBG_RX IB2 NC_1 1 [77] MUX0_EN# Y A
19 16 9 2
USBC_MUX0 17 NC_5 IB3 NC_2 B SAM_MUX0_EN [35]
S0 NC_3 11 3
GND
MUX0_EN# 2 R2924 100K
USBC_MUX1 GND 10 EN NC_4 18
SN74LV1T02DCKR
3 S MPAD 21 NC_5 19
1 USBC_MUX2_SEL 17 GND DBG_D DBG_D GND
PI3USB14-AZHE S0 TCP0_DBG0_A_DP [77]
GND GND 10 TCP0_DBG1_A_DN [77]
DBG_D USBC_MUX3_SEL 3 21
+3P3V_DEBUG S1 MPAD TCP0_DBG2_B_DP [77]
PI3USB14-AZHE TCP0_DBG3_B_DN [77]
U2903 C2904 DBG_D GND +3P3V_DEBUG
20 0.1u
teknisi indonesia
VDD 10V +3P3V_DEBUG
7 8 DBG_DGND C2905 U2909 C2910
[33,35,79] SAM_PD_SCL IA0 YA
[30,33] TS_TDO_1V8 6 U2905 R2901 74AUP1G08GX 0.1u
IA1 0.1u 100K DFN5_P85XP85XP4_P48 DBG_D
[74] KIP_TRACE_SWO 5 IA2 VDD 20
4 10V DBG_D
[20,33,34,76] PCHRTS_SAMCTS IA3 USBC_MUX3_SEL_INV 2 VCC 54 USBC_MUX4_SEL
[33,34,76] SAM_SWD_SWO 7 IA0 YA 8 A Y GND
C [33,35,79] SAM_PD_SDA 13 12 [18] APU_TDO_MUX R2920 DBG_D0 APU_TDO_MUX_R 6 DBG_D USBC_MUX2_SEL 1 C
IB0 YB R2928 DBG_D0 PM_DBG_I2C_SCL_R IA1 B
D
[30,33] TS_TMS_1V8 14 IB1 [28] PM_DBG_I2C_SCL 5 IA2 GND 3
[35,74] SAM_KIP_RST# 15 IB2 NC_1 1 4 IA3 USBC_MUX3_SEL G GND +3P3V_DEBUG
[20,33,34,76] SAMRTS_PCHCTS 16 IB3 NC_2 9
NC_3 11 [33,34,58,76] SAM_RESET# 13 IB0 YB 12
2 18 [18] APU_TMS_MUX R2921 DBG_D0 APU_TMS_MUX_R 14 Q2902
EN NC_4 R2929 DBG_D0 PM_DBG_I2C_SDA_R IB1 DBG_D C2903
19 [28] PM_DBG_I2C_SDA 15 1
S
NC_5 IB2 NC_1 0.1u
[35] USBC_MUX0 17 S0 16 IB3 NC_2 9
10 11 GND U2912 10V
GND 2 NC_3
[35] USBC_MUX1 3 S1 MPAD 21 EN NC_4 18 VDD 20 DBG_D
NC_5 19 GND
PI3USB14-AZHE USBC_MUX2_SEL 17 [29,77] TCP0_BB_SBU1 7 8
S0 I YA TCP0_SBU1 [29,77]
DBG_D GND 10 6 A0
USBC_MUX3_SEL GND I
A1
3 S1 MPAD 21 [33,34,71,76] SAM_DBG_RX 5 I
4 A2
+3P3V_DEBUG [18] APU_TRST#_MUX I
A3
PI3USB14-AZHE GND
DBG_D [29,77] TCP0_BB_SBU2 13 I YB 12 TCP0_SBU2 [29,77]
14 B0
I
B1
15 1
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[33,34,71,76] SAM_DBG_TX I NC_1
R2923 C2908 R2902 0 16 B2 9
[18] APU_DBREQ#_MUX I NC_2
100K 0.1u B3 11
1% U2910 10V 2 NC_3
EN NC_4 18
0201 5
0201S_P28-W35
19
VCC DBG_D NC_5
DBG_D 1 GND 17
B
2 A 4 USBC_MUX3_SEL S0 B
[35] USBC_MUX3 10
B O DBG_USB_EN GND
3 21
S1 MPAD
D
3
GND PI3USB14-AZHE
G SN74LV1T08DCKR +3P3V_DEBUG
[29,58] SAM_DBG_MODE DBG_D
DBG_D R2905
Q2905 1K
R2909 GND C2907 DBG_D GND
S
100K 0.1u
DBG_D
1% 10V
0201 U2911
DBG_D
DBG_D 5 GND
R2903 0 1 VCC R2908 DBG_N 0
GND A [29,77] TCP0_BB_SBU1 TCP0_SBU1 [29,77]
R2910 0 2 4 USBC_MUX2_SEL R2906 DBG_N 0
[35] USBC_MUX2 B O [29,77] TCP0_BB_SBU2 TCP0_SBU2 [29,77]
0201S_P28-W35
3
DBG_D
0201S_P28-W35 GND
DBG_D SN74LV1T08DCKR
DBG_D GND
USBC_MUX3
USBC_MUX2
A USBC_MUX1 A
USBC_MUX0
R2917 R2916 R2915 R2914

100K 100K 100K 100K
1% 1% 1% 1%
0201 0201 0201 0201
DBG_D
GND DBG_DGNDDBG_D
GND DBG_D
GND
5 4 3 2
5 4 3 2 1
T D T
M T T
+ S_BOOST_HV_IN A 3001 K S_HV_IN
T TP3039 S_BOOST_HV_IN S_HV_IN
5V_TS
T PANEL_RST_N
[20,33,35] PANEL_RST#
M T PMEG4015EPK315
TP3024 T S_HV_IN E3 U3002 C1 H
S_HV_IN V_IN
H NT_HV0
A C2
C NT_HV1 H0
3022 C C A D1 H1
NT_HV2
A D2
T + 25V 10u 3012 3069 NT_HV3 H2
S_V1P0_TCH_DIG 1P8V_TS 0603 2.2u 25V 0.1uF A C3 H3
NT_HV4
A D3
+ 0402 DNP H4
T A2 NT_HV5
A E2
3P3V C C T H5
S_HV_IN OOST_HV_OUT
B NT_HV6
A E1
3075 2.2u 3052 2.2u SGND_BOOST H6
NT_HV7
A F2
6.3V 6.3V T NT_HV8 H7
C C 2.2uH T
S_BOOST_HV_IN A1 A F1 H8
S_BOOST_HV_IN OOST_HV_IN
B NT_HV9
A G2
R 3051 DNP 0.1uF 3037 DNP 0.1uF L 1.4A H9
NT_HV10
A G1
3020 C C 3003 H10 NOTE: Place shorts close to Master ATrig.
B1 NT_HV11
A H2
M 100K C 3044 3019 2.0X1.6X1.0MM H11
OOST_VSS
B NT_HV12
A H1
TP3043 T 3073 10u 0.1uF 6.3V 10u H12
NT_HV13
A J2
+ S_V1P0_TCH_SSI DNP 0603 + H13
NT_HV14
A J1
D 1P8V_TS C 1P8V_TS H14 W W D
T B8 NT_HV15
A K2
J
F 15
3
MP
MP
C C 3004 10u 3002 3001
[22] S_IRQ_3V3# A7 UCK_1V8_IN
B NT_HV16
A K1 FC_AY0_HV16
D 3007 2.2u 3074
2.2u T 0603
UCK_VSS
B NT_HV17
A L2 C_AY0_HV17
Q R 6.3V C 6.3V T SGND_BOOST C
NT_HV18
A L1
3004 G 1 3004 3035 DNP 0.1uF S_V1P0_TCH_DIG
NT_HV19 C 3081 JUMPER_0201_SHORTED_PADS
49.9K
0201S_P28-W35
C T A8 A M2 3030 220p
B7 UCK_OUT_FB
B NT_HV20
A M1
s 3046 DNP 0.1uF L SGND_BUCK
TS_AY ALON1_LVDCDC_LX
220p G T T
UCK_LX
B NT_HV21
A M3
3002 4.7uH ND SGND_BUCK SGND_BOOST
D4 NT_HV22
A L3
2
NX3008NBKMB + C 0805 T G
T S_V1P0_TCH_SSI DD_SSI
V NT_HV23
A
1P8V_PANEL TS_SPI_CLK 3057 ND
F11
G
G3
B8
F5
T S_SPI_CLK U3006 D6 T 10u 6.3V C B5 ND
[21,30] S_SPI_CLK T ESERVED_GND[0]
R B4 1 DO_1V0_OUT
L M8
TS_SPI_MOSI S_V1P0_TCH_SSI 0603 C3068 4.7u 0402 V
T S_SPI_MOSI ESERVED_GND[1]
R D5 J3
P8V_TS NT_LV0
A M7
DD_CORE
DD_SSI
DE_H
DE_F
3054 2.2u 0402 V23
[21] S_SPI_MOSI ESERVED_GND[2]
R C5 DD_1V8_IN
V NT_LV1
A L8
V
V
R ESERVED_GND[3] T C NT_LV2 V22
R B5 A L7
V
3011 G SGND_BUCK
T 3011 DNP 0.1uF V21
100K
ESERVED_GND[4]
R C6 S_V1P8A T C8 NT_LV3
A L6
PIO signals may toggle during boot V20
V
M ESERVED_GND[5] VDD_IN NT_LV4
TP3029 (see errata document). Please make F2 R B6 R C C S_V1P8A A A K8 V19
sure to implement the workaround F4 SPI_CLK/I2C_SCL ESERVED_GND[6]
R C3 3001 3033 3032 2.2u 0402 F3 NT_LV5
A K7 V18
described in the errata
R TS_TOUCH_SPI_DO_RF3 SPI_DI / I2C_SDA ESERVED_GND[7]
R C4 4.99K 0.1uF C H3 VDD_1V8_3
A NT_LV6
A K6 V17
T T G1 GPIO7 / SPI_DO ESERVED_GND[8]
R B3 G3 VDD_1V8_2
A NT_LV7
A J8
3
3017 22.1 DNP 3059 DNP 0.1uF V16

[30] S_IRQ_1V8#
D
[21,30]T S_SPI_MISO GPIO6 / SPI_CS ESERVED_GND[9]
R 0402 VDD_1V8_1
A NT_LV8
A J7 V15
[21,30] S_SPI_CS# D4 D8 NT_LV9
A J6
Q G TS_GPIO0 V14
3003 G 1 T TP3001 D3 GPIO0 ESERVED_NC[0]
R J10 T NT_LV10
A H6 V13
S_IRQ_1V8 D2 GPIO1 / INT ESERVED_NC[1]
R H10 PANEL_RST_N C 1 L5 NT_LV11
A H7 V12
s R TS_FLASH_PROTECTn_GPIO_RC1 GPIO2 / IF_SEL ESERVED_NC[2]
R J9 3062 0.033u P8V_TS DE_H
V NT_LV12
A H8 V11
F 3015 1K T C2 GPIO3 ESERVED_NC[3]
R H9 C C 0201 B2 NT_LV13
A G6 V10
[22,30] LASH_PROTECT# GPIO4 ESERVED_NC[4]
R DE_F
V NT_LV14
A
2
NX3008NBKMB R TP3002 B1 J8 3053 3031 0.033u G7 V9

3016 R P3004 GPIO5 ESERVED_NC[5]
R H8 0.1u 0201 NT_LV15
A G8 V8
10K 3021 H2 ESERVED_NC[6]
R 0201 T M6 NT_LV16
A F6
R V7
0 P
T3003 1K H1 GPIO9 PANEL_RST_N
T K5 STN_H
R NT_LV17
A F7 V6
[57] ANEL_VSYNCH G2 GPIO10 J1 S_AY_RSTN_D A3 STN_D
R NT_LV18
A F8
0201 P3003 T T V5
R GPIO11 STN_D
R J5 TS_AY_RSTN_D TS_VDD_OK_F M5 DD_OK_F
V NT_LV19
A E7 V4
T 0 3022 T H5 DD_OK_F
V B2 TS_VDD_OK_F S_VDD_OK_H DD_OK_H
V NT_LV20
A E8
[21] S_SPI_EN M V3
TS_TCK_1V8 H6 TCK STN
R S_VDD_OK_H TP3038 NT_LV21
A D7 V2
DNP TS_TDI_1V8 R T G6 TDI G10 T R T T A6 NT_LV22
A D8 V1
TS_TDO_1V8 3013 22.1 S_JTAG_TS_TDO_R F6 TDO CKL
S S_SCKL0 3012 22.1 S_SCKL S_SCKL CLK
S NT_LV23
A 0
T S_TMS_1V8 0201 TMS B10 T A5 D5
[29,33] TS_TCK_1V8 D0 5_SSI_D0 ESERVED_GND1
[29,33] S_TDI_1V8 T (If Availible) J3 S B11 TS_SD0 TS_SD0 B4 A R D6
T S_HOST_CLK CLK_IN SD1 C9 TS_SD1 TS_SD1 B3 5_SSI_D1
A ESERVED_GND2
R C6
[29,33] TS_TDO_1V8 D2 5_SSI_D2 ESERVED_GND3
R T H11 S C10 TS_SD2 TS_SD2 A4 A R
[29,33] S_TMS_1V8
3019 T S_DLITE_XI J11 XI SD3 C11 TS_SD3 TS_SD3 5_SSI_D3
A K3
200K S_DLITE_XO_R XO SD4 C8 TS_SD4 ESERVED_NC1
R C5
F10 SD5 D9 TS_SD5 T ESERVED_NC2
R C4
M
CLK_SLCT SD6 D10 TS_SD6 MTP3036 TS_SCKL ESERVED_NC3
R
G5 SD7 F8 TS_SD7 TS_SD0 B6 C7 T
R MTP3012 T
3018 H3 FSCK SD8 G8 TS_SD8 MTP3020 TS_SD4 ND
G TB
A S_AYALON0_ATB P3006
0 G4 FSDI SD9 F9 TS_SD9 TP3002 S_SD8
ALL H4 FSDIO D10
S G9 TS_SD10
ND1
ND2
D Add underfill
0201 FSCS G D11
S S_SD11 S-A5048_82BGA
G
4
TS_FLASH_CSn
Y T
1 33001
T D T S_HV_IN T E3 U3003 C1 H
S_DLITE_XO
J2 S_HV_IN S_HV_IN V_IN
H NT_HV0
A
B9
S-D5000-B064 C2 H32
Special keepout made to isolate NT_HV1
A D1
48MHz buck and boost ground from system ground C C H33
NT_HV2
A D2
2
XTAL,SM,48 MHZ,10 PPM,7 PF,2X1.6X0.45MM 3066 3040 H34

2.2u 25V 0.1uF NT_HV3
A C3 H35
TS_FLASH_MOSI
TS_FLASH_MISO
0402 DNP NT_HV4

A D3 H36
TS_FLASH_SCK
+
1P8V_TS A2 NT_HV5
A E2
C C H37
3079 3063 OOST_HV_OUT
B NT_HV6
A E1 H38
2% 25V 12p 2% 25V 12p NT_HV7
A F2
C H39 C
A1 NT_HV8
A F1
U C H40
3005 3067 OOST_HV_IN
B NT_HV9
A G2 H41
NT_HV10
A
1 SON9_4P1X4P1XP6_P8
8 2.2u 6.3V G1 H42
6 CS CC
V B1 NT_HV11
A H2 H43
T 5 CK OOST_VSS
B NT_HV12
A H1 H44
+ he crystal and capacitors should be placed 2 SI/0 +
NT_HV13
A J2 H45
as close as possible to the D5, with short and /1 NT_HV14
1P8V_TS 3 Q 9 1P8V_TS A J1 H46
symmetrical traces to the XI and XO pins P/2 MTG 4 NT_HV15
7 W B8 A K2 H47
M HLRS/3 VSS A7 UCK_1V8_IN
B NT_HV16
A K1 H48
TP3027 UCK_VSS
B NT_HV17
A L2
R H49
3014 NT_HV18
A
M MX25U1635FZUI T L1 H50
200K TP3023 S_V1P0_TCH_SSI A8 NT_HV19
A M2 F51
M B7 UCK_OUT_FB
B NT_HV20
A M1 FC_AY1_HV20
DNP UCK_LX NT_HV21 C_AY1_HV21
MTP3022 C B A M3
NT_HV22
MTP3011 3050 2.2u 0402 D4 A L3 C C
DD_SSI
V NT_HV23
A
MTP3034 C 3017 3080
MTP3037 3064 DNP 0.1uF B5 220p 220p
F TP3042 DO_1V0_OUT
L M8
LASH_PROTECT# V
F R NT_LV0
A
LASH_PROTECT# [22,30] + 3002 T M C J3 M7 V47
1P8V_TS S_V1P8A 3061 2.2u 0402 DD_1V8_IN
V NT_LV1
A
TP3035 L8 V46 G G
NT_LV2
A
T C L7 V45 ND ND
ALL S_V1P8A 3043 DNP 0.1uF NT_LV3
A
R V1P8 C8 L6 V44
G VDD_IN NT_LV4
C3041
C3047
3025
3023 0 A A
+ PIO5_24_LCK# [35,54,57] 0 Analog C K8 V43
1P8V_TS 3010 2.2u 0402 NT_LV5
A
Option for SAM GPIO F3 K7 V42
C
VDD_1V8_3
A NT_LV6
A
M lock flashing function C H3 K6 V41
TP3001 3045 DNP 0.1uF VDD_1V8_2
A NT_LV7
A
0 0 0 G3 J8 V40 +
10u
10u
10u
603 603 603 VDD_1V8_1 NT_LV8 5V_TS

A A J7 V39 +
NT_LV9 1P8V_TS
M T
PANEL_RST# DNP DNP DNP
A J6 V38
NT_LV10
MTP3041 F
LASH_PROTECT#
A H6 V37
TP3003 NT_LV11
C L5 A H7 V36 C C
T 3056 0.033u 0201 DE_H
V NT_LV12
A H8 35 3002 3029
M
M
TP3021 T
S_TCK_1V8 Not to be used for DEBUG build C B2 NT_LV13
A G6
V
V
34
C
3027
C
3001 2.2u 6.3V 0.1u 10V
TP3032 S_TMS_1V8 3078 0.033u 0201 DE_F
V NT_LV14
A 33 0.1u 10V 10u 6.3V 0201S_P39-W39 0201S_P33-W39
T G7
M
TP3026 S_TDO_1V8 Use MTP points on pg 31 instead NT_LV15
V
32 0201S_P33-W39 0402S_P7-W70
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M T A G8 V
TP3040 S_TDI_1V8 NT_LV16
T
S_VDD_OK_H
M6 A F6 V31 G G
T K5 STN_H
R NT_LV17
A F7 30 ND ND
S_AY_RSTN_D V G G
T A3 STN_D
R NT_LV18
A F8 29 ND ND
M S_SPI_CLK V
TP3031 T M5 DD_OK_F
V NT_LV19
A E7 28
M S_SPI_MISO V
TP3033 T DD_OK_H
V NT_LV20
A E8 27
M S_SPI_MOSI V
TP3030 NT_LV21
A D7 V26
T A6 NT_LV22
A D8 25
S_SCKL V
T CLK
S NT_LV23
A 24
M S_SPI_CS#
TP3025 T A5 D5
S_SD4 5_SSI_D0
A ESERVED_GND1
R
T B4 D6
S_SD5 5_SSI_D1
A ESERVED_GND2
R
M T B3 C6
TP3028 S_SD6 5_SSI_D2
A ESERVED_GND3
R
T A4
S_SD7 5_SSI_D3
A K3
ESERVED_NC1
R C5
ESERVED_NC2
R C4
ESERVED_NC3
R
B6 C7 T T
80 pin Sense Connector ND

G TB
A S_AYALON1_ATB P3007
60 pin Drive Connector J

3003
T
D
S-A5048_82BGA Add underfill
S_HV_IN T E3 U3004 C1
V 2 1 TS_HV_IN S_HV_IN H
B 77 2 1 V_IN
H NT_HV0
A C2 16 B
J V 4 3 V H
3002 75 4 3 76 NT_HV1
A D1 17
V 6 5 V C C H
73 6 5 74 3071 3021 NT_HV2
A D2 18
2 1 V 8 7 V H
2 1 71 10 8 7 72 2.2u 25V 0.1uF NT_HV3
A C3 19
H 4 3 V 9 V H
0 4 3 69 12 0
1 9 11 70 0402 DNP NT_HV4
A D3 20
H 6 5 H V V H
2 6 5 1 67 14 2
1 1 13 68 A2 NT_HV5
A E2 21
H 8 7 H V V H
4 10 8 7 3 65 16 4
1 3
1 15 66 OOST_HV_OUT
B NT_HV6
A E1 22
H 9 H V V H
6 12 10 9 11 5 63 18 6
1 5
1 17 64 NT_HV7
A F2 23
H H V V H
8 14 12 11 13 7 61 20 8
1 7
1 19 62 A1 NT_HV8
A F1 24
H H V V H
10 16 14 13 15 9 59 22 0
2 9
1 21 60 OOST_HV_IN
B NT_HV9
A G2 25
H12 H11 V57 V58 H26
H14 18 16 15 17 H13 V55 24 2 1
2 23 V56
NT_HV10
A G1 H27
H16 20 18 17 19 H15 V53 26 4
2 3
2 25 V54 B1 NT_HV11
A H2 H28
H18 22 20 19 21 H17 V51 28 6
2 5
2 27 V52
OOST_VSS
B NT_HV12
A H1 H29
H20 24 22 21 23 H19 V49 30 8
2 7
2 29 V50 +1P8V_TS NT_HV13
A J2 H30
H22 26 24 23 25 H21 V47 32 0
3 9
2 31 V48 TS_V1P0_TCH_SSI NT_HV14
A J1 H31
H24 28 26 25 27 H23 V45 34 2
3 1
3 33 V46 B8 NT_HV15
A K2 FC_AY2_HV16
H26 30 28 27 29 H25 V43 36 4
3 3 35 V44 A7 UCK_1V8_IN
B NT_HV16
A K1 FC_AY2_HV17
H28 32 30 29 31 H27 V41 38 6
3 5
3 37 V42 UCK_VSS
B NT_HV17
A L2 V77
H30 34 32 31 33 H29 V39 40 8
3 7
3 39 V40
NT_HV18
A L1 V76 C3024 C3016
H32 36 34 33 35 H31 V37 42 0
4 9
3 41 V38 A8 NT_HV19
A M2 V75
H34 38 36 35 37 H33 V35 44 2
4 1
4 43 V36 B7 UCK_OUT_FB
B NT_HV20
A M1 V74
220p 220p
H36 40 38 37 39 H35 V33 46 4 3
4 45 V34 C3042 UCK_LX
B NT_HV21
A M3 V73
40 39 6
4 5
4 2.2u 0402 NT_HV22
A
H38 42 41 H37 V31 48 47 V32 D4 L3 V72
H40 44 42 41 43 H39 V29 50 8
4 7
4 49 V30 C3018 DNP DD_SSI
V NT_HV23
A GND GND
44 43 0
5 9
4 0.1uF
H42 46 45 H41 V27 52 51 V28 B5
H44 48 46 45 47 H43 V25 54 2
5 1
5 53 V26
DO_1V0_OUT
L M8 V71
H46 50 48 47 49 H45 V23 56 4
5 3
5 55 V24 C3006 J3 NT_LV0
A M7 V70
50 49 6
5 5 2.2u 0402 DD_1V8_IN
V NT_LV1
A
H48 52 51 H47 V21 58 57 V22 L8 V69
H50 54 52 51 53 H49 V19 60 8
5 7
5 59 V20 TS_V1P8A C3014 DNP NT_LV2
A L7 V68
54 53 0
6 9
5 0.1uF NT_LV3
A
56 55 H51 V17 62 61 V18 C8 L6 V67
58 56 55 57 V15 64 2
6 1
6 63 V16 C3008 VDD_IN
A NT_LV4
A K8 V66
58 57 4
6 3
6 2.2u 0402 NT_LV5
A
60 59 V13 66 65 V14 F3 K7 V65
60 59 V11 68 6 5
6 67 V12 C3013 DNP H3 VDD_1V8_3
A NT_LV6
A K6 V64
8
6 7
6 0.1uF VDD_1V8_2
A NT_LV7
A
62 61 V9 70 69 V10 G3 J8 V63
64 MT2 MT1 63 V7 72 0
7 9
6 71 V8
VDD_1V8_1
A NT_LV8
A J7 V62
MT4 MT3 V5 74 2
7 1
7 73 V6 C3038 NT_LV9
A J6 V61
4
7 3
7 10u 0603 NT_LV10
A
V3 76 75 V4 H6 V60
V1 78 6
7 5
7 77 V2 C3058 L5 NT_LV11
A H7 V59
8
7 7 0.033u 0201 DE_H
V NT_LV12
A
H 0 to H47 are the horizontal sensor traces 80 79 V0 H8 V58
0
8 9
7 C3055 B2 NT_LV13
A G6 V57
V0 to V71 are the vertical sensor lines 0.033u 0201
82 81 DE_F
V NT_LV14
A G7
84 P2
M
P4
M
P1
M
P3
M
83
TS_VDD_OK_H M6
NT_LV15
A
NT_LV16
A
G8
F6
V56
V55 +1P8V_PANEL SPI Buffer
V54
TS_AY_RSTN_D K5 STN_H
R NT_LV17
A F7 V53 +1P8V_PANEL
A3 STN_D
R NT_LV18
A F8 V52
51338-0874 DD_OK_F
V NT_LV19
A
201S_P28-W35
M5 E7 V51 R3005
DD_OK_H
V NT_LV20
A E8 V50
NT_LV21 100K
A D7 V49 C3003
TS_SCKL A6 NT_LV22
A D8 V48
CLK NT_LV23 0.1u 10V
S A
0201S_P33-W39
TS_SD8 A5 D5 U3001
D0
TS_SD9 B4 5_SSI_D0
A ESERVED_GND1
R D6
TS_SD10 B3 5_SSI_D1
A ESERVED_GND2
R C6 14
5_SSI_D2 ESERVED_GND3 CCV GND
TS_SD11 A4 A R G Q3002
5_SSI_D3
A [10,65] PCH_VDD_PANEL_EN EDP_SPI_CS_R#
K3 2 3 R3009
50 pin Flex Breakout ESERVED_NC1 [21,30] TS_SPI_CS# A 1 Y 1 33 EDP_SPI_CS# [57]

R C5
ESERVED_NC2
R C4 1
S
ESERVED_NC3
R OE1
A
80 pin Flex Breakout B6
ND
G TB
A
C7 TS_AYALON2_ATB TP3005
GND [21,30] TS_SPI_MISO
5
4
A 2 Y 2
6 EDP_SPI_MISO_R R3008 33 EDP_SPI_MISO [57]
A
OE2
DS-A5048_82BGA Add underfill
9 8 EDP_SPI_INT_R# R3010
[30] TS_IRQ_1V8# A 3 Y 3 33 EDP_SPI_INT# [57]
0 1
OE3
12 11 EDP_SPI_CLK_R R3007 33
[21,30] TS_SPI_CLK A 4 Y 4 EDP_SPI_CLK [57]
3 1
OE4
7
15 NDG
PAD
E
74LVC125ABQ
GND
5 4 3 2
5 4 3 2 1
+1P8VA
+3P3VAS_SIL to silego
P
W RBTN#_3V3 [58]
R3104
100K +1P8VA
R3109
100K
0201S_P28-W 35
DNP Power Button Filter DNP
0201S_P28-W 35 0 R3105 R3108
100K ALL
Q3101 0201S_P28-W35
R3107
D D S D
P
W RBTN#_1V8 [33,34,74]
100 SOTFL-3_1P3XP9XP55_P4
X865865-001 Prevent SAM IO leakage when sysoff
G
Uses Lynx Debug ATM
A1
SW 3103 D3102 C3108 C3104
DBG_D +1P8VA
0.1u 1000p
V5.5MLA0402NR
2 1
A2
CDS2C05GTA
4 N-O 3
GND
5
6
GND
GND GND
GND PW RBTN#_1V8_FILT [76]
TP3101
TP3107
C +1P8VSB C
R3103
4.7K Vinafix.com
Volume Up Button Filter VOL_UP# [24,33]
R3101
Uses Lynx Debug ATM 100

A1
SW 3101 D3104
DBG_D
V5.5MLA0402NR C3107 C3103
https://vinafix.com
2 1
A2
CDS2C05GTA 0.1u 1000p

4 N-O 3
GND
5
6
GND GND GND

B B
VOL_UP#_FILT [76]
GND
+1P8VSB
R3102
4.7K
Volume Down Button Filter

VOL_DOW N# [24,33]
R3106
100
A1
Uses Lynx Debug ATM

A SW 3104 D3103 C3105
DBG_D 0.1u
V5.5MLA0402NR C3109
2 1 CDS2C05GTA
A2
1000p
4 N-O 3
GND
5
6
GND GND GND
VOL_DOW N#_FILT [76]

GND
5 4 3 2
5 4 3 2 1
D D
C C
https://vinafix.com
B B
A A
5 4 3 2
5 4 3 2 1
J 3302
2 1
[29,34,76] SAM_SWD_CLK 4 2 1 3
TP3307 [29,34,58,76] SAM_RESET# LTE_JTAG_TCK 6 4 3 5
S AM_SWD_DIO [29,34,76]
LTE_JTAG_TDO 8 6 5 L TE_JTAG_TDI S AM_SWD_SWO [29,34,76]
TP3306 7 T P3302
10 8 7 9 L TE_JTAG_TMS T P3305
[29,34,71,76] SAM_DBG_TX 10 9
12 11
[20,29,76] PCH_DBG_RX 12 11 S AM_DBG_RX [29,34,71,76]
D 14 13 D
[20,29,34] PCHTX_SAMRX 16 14 13 15
P CH_DBG_TX [20,29,76]
[29,30] TS_TCK_1V8 16 15 S AMTX_PCHRX [20,29,34]
18 17
[29,30] TS_TDO_1V8 18 17 TS_TDI_1V8 [29,30]
20 19
[35,66] SOCVR_SCL_P 20 19 T S_TMS_1V8 [29,30]
22 21
[22,28,76] PMI_I2C_SCL 22 21 S OCVR_SDA_P [35,66]
24 23
24 23 P MI_I2C_SDA [22,28,76]
26 25
DEBUG CONN
[35,70] POWER_SMB_SDA 26 25 P OWER_SMB_SCL [35,70]
28 27
[29,74] SAM_KIP_UART_RX_DBG 28 27 S AM_KIP_UART_TX_DBG [29,74]
30 29
[24,31] VOL_UP# 30 29 B AT_SHUTDOWN# [58,70,76]
+3P3VSB 32 31
32 31 V OL_DOWN# [24,31]
34 33
TP3300 [22,34] SLP_S4# PCH_CATERR#_1V8 36 34 33 35 S LP_A# S LP_S3# [22,34,58]
T P3311
36 35
38 37
TP3301 [18,22] PCH_SYS_RST# CPU_C10_GATE# 38 37 P WRBTN#_1V8 [31,34,74]
40 39
40 39 A PU_S0A3 [22,37]
[29,35,79] SAM_PD_SDA 42 41
TP3312 CNV_RF_RESET# 44 42 41 43 S AM_PD_SCL [29,35,79]
46 44 43 45
[22,57] PANEL_I2C_SCL 48 46 45 47 A PU_RESET# [10,18]
[20,50] BT_DISABLE# 50 48 47 49 P ANEL_I2C_SDA [22,57]
TP3308 [10,18,20,66] PWROK 52 50 49 51 W LAN_DISABLE# [24,50] T P3309
54 52 51 53 1.27mm
[35,76] PCH_SAM_SNSR_SDA 54 53 P CH_SAM_SNSR_SCL [35,76]
C 56 55 C
[35,39] SAM_SEN_SDA 56 55 S AM_SEN_SCL [35,39]
58 57
[20,29,34,76] SAMRTS_PCHCTS 58 57 P CHRTS_SAMCTS [20,29,34,76]
60 59
[22,34,38,44] PLT_RST_BUF# 62 60 59 61 H _PROCHOT_1P8V# [10,34] + 3P3VSB + 3P3VA + 5VSB + 1P8VA
[33,35] SAM_LED1# 64 62 61 63 S OC_DEBUG_AGPIO87 S AM_LED0# [33,35] T P3310
+5VSB 64 63
+1P8VA 66 65 + 3P3VA
LTE_JTAG_TRST# 68 66 65 67
68 67 L TE_JTAG_SRST# T PANEL_RST# [20,30,35]
70 69 T P3303 C 3302 C 3301 C 3304 C 3305
70 69
10V 0.1u 10V 0.1u 10V 0.1u 10V 0.1u
72 71 0201 0201 0201 0201
MTG2 MTG1
DBG_D DBG_D DBG_D DBG_D
[58,76] FPC_DET_LOGIC_OVERRIDE#
M1008509-001
GND DBG_D
G ND
B
+3P3VA
https://vinafix.com + 3P3VA B
R 3301 R 3302
1K 1K
0201S_P28-W35 0201S_P28-W35
DBG_D DBG_D
LED_R_A L ED_O_A
A
A
D 3302
Green FW Debug LED Orange
Heartbeat LED DBG_D
D 3301
LED_1P1XP6XP6
K
K
DBG_D
[33,35] S AM_LED1#
A [33,35] SAM_LED0#
LOW = LED ON LOW = LED ON
5 4 3
5 4 3 2 1
System
Aggregator
1 v8_SAM
Module
Local RailSource
D D
+ 1P8VA C 3405 C 3413 C 3406 C 3414 C 3407 C 3415 C 3408 C 3416 C 3417 C 3418 C 3420 C 3421 C 3427 C 3428
0.01u 0.1u 0.01u 0.1u 0.01u 0.1u 0.01u 0.1u 0.01u 0.1u 0.01u 0.1u 0.01u 0.1u
DBG_TS 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
0201S_P330201S_P33-W39
0201S_P33 0201S_P33-W39
0201S_P33 0201S_P33-W39
0201S_P33 0201S_P33-W39
0201S_P33 0201S_P33-W39
0201S_P33 0201S_P33-W39
0201S_P33 0201S_P33-W39
P MTP3400 R 3411 0.2
SP-TP-C0P381 0603S_P6-W100
P MTP3401
SP-TP-C0P381
D 3402 K A
U3400D C 3402
V PP
N4
E6
T P3401 R 3410
10
10u
6.3V
0402S_P7-W70
Configuration ID TBD
0201S_P28-W35
C 3409 32KHZ_XIN L12 V DD_1 E8 20170827sjs0747:
D 3401
1 v8_SAM 18p R TCXIN V DD_2 F5 We need to get TBL3400 resistors into
V DD_3
K11 G5 R 3401 ds-2
1
[29,33,58,76] SAM_RESET# K A 32KHZ_XOUT
X 3400 R TCXOUT V DD_4 J12 10 1 v8_SAM 1 v8_SAM 1 v8_SAM 1 v8_SAM
V DD_5 L6 C 3426 C 3425 0201S_P28-W35
RB520CS3002L 32.768KHZ
V DD_6 L11 2.2u 0.01u
20170831sjs1912
2
R 3400 V DD_7 6.3V 10V
R 3402 R 3403 R 3404 R 3405
10K 1% N13 N6 1V8_SAMA
0201S_P39-W39 0201S_P33
+ 1P8VAS Caution: Max input voltage is 2K 2K 2K 2K
R ESETN V DDA
0201 R 3429
N11
1v8 !!!
0
V BAT CFG_ID_THOS
P6 [35] C FG_ID_THOS CFG_ID_HUNS
C 3419 V REFP
VREFP
[35] C FG_ID_HUNS
0.1u 18p CFG_ID_TENS
10V C 3410 C 3403 CFG_ID_ONES
0201S_P33-W39 C 3412
B3 0.1u 2.2u
V SS_1 D7 10V 6.3V ADC_RD_EN
V SS_2 D8 0201S_P33-W39 0201S_P39-W39
SAM_RESET#r R 3406 R 3407 R 3408 R 3409
V SS_3 E11 C 3401 4.99K 634 301 0
C V SS_4 H5 1u TBL3403 TBL3402 TBL3401 TBL3400 C
V SS_5
FG_ID_HUNS_EN
FG_ID_ONES_EN
FG_ID_THOS_EN
FG_ID_TENS_EN
J5 6.3V
K4 V SS_6 K7
0201S_P35-W35
X TALIN V SS_7 T P3434

T P3435
C
J4 L5
X TALOUT V SSA T P3436
FG_ID_EN
T P3437 Refer to below tables
+1P8VA L PC54S001JEV180 Rev 1B T P3438 to identify resistor strappings
corresponding to your board config
D C
Q 3401
[35,70] A DC_RD_EN G SOTFL-3_1P3XP9XP55_P4
+ 1P8VA
R3424 R3425 R3436 R3433 R3434 R3435 + 1P8VA + 1P8VA
47K 47K 47K 47K 47K 47K
S
C 3422
R 3421
teknisi indonesia
1u 6.3V R 3414 G ND
10K
0201S_P35-W35 U 3402 0
SAM_PIO0_3 DNP NX3P1108UK
U 3401 T P3431
BGA4_2X2_P98XP98XP59_P5 ALL
SAM_SWD_CLK GND A2 A1 8 1 SPIFI_CS#
+ 1P8VA VIN V OUT V CC CS 6
SAM_SWD_DIO C 3430
S CLK 5
SPIFI_Clk
SPIFI_io0 TBL3400
B2 B1 0.1u S I/SIO0 2 SPIFI_io1
SAM_PIO0_2 R 3412 EN G ND 10V 4 S O/SIO1 3 SPIFI_io2
G ND W P/SIO2
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SAM_PIO0_4 100K DNP 9 7 SPIFI_io3
SAM_PIO0_5 DNP M PADN C/SIO3
SAM_PIO0_6 T P3430
G ND MX25U1635EZUI-10G T P3427
[35] SAM_FLASH_EN T P3428
+1P8VA
R3415
47K
T P3429 TBL3401
B T P3432 B
ALL S AM_UEFIROM_SPI_MOSI [21]
S AM_UEFIROM_SPI_MISO [21]
R3441
499K S AM_UEFIROM_SPI_CLK [21]
[59] SUS_PWRGD_5VSB
ALL U3400A
0 R3440 SAM_PIO0_0
D6 N3 P IO1_0
TP3422 PIO0_0 PIO1_0/ADC0_6 T P3423
A1 K12FC10
[39] FAN_TACH1 SAM_PIO0_2 PIO0_1 PIO1_1 T P3408
E9 L14
SAM_PIO0_3 PIO0_2/TRST PIO1_2 T P3407
A10 J13
PIO0_4/5/6 used [76] SAM_PIO0_3 SAM_PIO0_4
C8 PIO0_3/TCK PIO1_3 D4 T P3404
for ISP Strap [76] SAM_PIO0_4 SAM_PIO0_5
E7 PIO0_4/TMS PIO1_4 E4 FC0 PCH_UART_RXr P
D_SAM_INT# [79]
10 R 3416
[76] SAM_PIO0_5 SAM_PIO0_6
A5 PIO0_5/TDI PIO1_5 G4 P CHTX_SAMRX [20,29,33]
PCH_UART_TXr 10 R 3417
[66] SOCVR_ALT_P# [76] SAM_PIO0_6 H12 PIO0_6/TDO PIO1_6 N1 S AMTX_PCHRX [20,29,33]
PCH_UART_RTSr 10 R 3418
PIO0_7 PIO1_7 S AMRTS_PCHCTS [20,29,33,76]
TP3425
0 R3426 SAM_PIO0_8 H10 P8 PCH_UART_CTSr 10 R 3419
G12 PIO0_8 PIO1_8 K6 EXP_UART_CTSr 0 P CHRTS_SAMCTS [20,29,33,76]
R 3427
[58,66] VRM_PWRGD P2 PIO0_9 PIO1_9 N9 FC1 DEBUG_RXr R 3428 10
T P3405 TBL3402
[29,33,76] SAM_SWD_SWO PIO0_10/ADC0_0 PIO1_10 S AM_DBG_RX [29,33,71,76]
L3 B4 DEBUG_TXr R 3422 10
[29,33,76] SAM_SWD_CLK M3 PIO0_11/ADC0_1 PIO1_11 K9 S AM_DBG_TX [29,33,71,76]
[29,33,76] SAM_SWD_DIO PIO0_12/ADC0_2 PIO1_12 S EN_HALL_INT#_S [54,76] T P3402
O D PINF11 G10
OD PINE13 PIO0_13 PIO1_13 C12 S L1_PSU_DET [70,76] T P3403 B LADE_UART_DBG_EN [74]
CFG_ID_ONES L4 PIO0_14 PIO1_14 A11 PIO1_15_A11 S EN_HALL_INT#_N [54,76]10 R 3423 T P3406
0 CFG_ID_TENS M4 PIO0_15/ADC0_3 PIO1_15 B7 P D_SAM_DBG_ACC_MODE_1V8 [37]
[10,72] PCH_LCD_BKLT_EN R3432 T P3409
E14 PIO0_16/ADC0_4 PIO1_16 N12 P IO1_17
PIO0_17 PIO1_17 T P3410
C14 D1 P IO1_18
[22,72] PCH_SAM_INST_ON BATEN_PULSE_SAM C6 PIO0_18 PIO1_18 L1 T P3411
0
[58,70] BATEN_PULSE R3420
D13 PIO0_19 PIO1_19 M1 R 3430 0
T P3412 TBL3403
[39] THERMAL_MODULE_DET PIO0_20 PIO1_20 S AM_KIP_UART_TX [74,76] I SH_SAM_INT [22]
C13 N8 R 3431 0
[10,33] H_PROCHOT_1P8V# B12 PIO0_21 PIO1_21 P11 S AM_KIP_UART_RX [74]
PIO0_22 PIO1_22 T P3413
SPIFI_CS# N7 M10
A PIO0_23/ADC0_11 PIO1_23 T P3414 A
SPIFI_io0 M7 N14
SPIFI_io1 K8 PIO0_24 PIO1_24 M12 P WRBTN#_1V8 [31,33,74]
SPIFI_Clk M13 PIO0_25 PIO1_25 J10 ALLVSB_PG [58,61,62]
SPIFI_io3 L9 PIO0_26 PIO1_26 F10 P CH_SAM_INT [22]
PIO0_27 PIO1_27 T P3415
SPIFI_io2 M9 E12
B13 PIO0_28 PIO1_28 C11
[70] BAT_DET# PIO0_29 PIO1_29 T P3418 P LT_RST_BUF# [22,33,38,44]
A2 A8
[63] CHRG_OK PIO0_30 PIO1_30 T P3419
M5 C5
[63] BAT_VOLT PIO0_31/ADC0_5 PIO1_31 T P3420
A PU_S0A3_1V8 [37]
C3423 LPC54S001JEV180 Rev 1B
S LP_S3# [22,33,58]
0.01u
10V S LP_S4# [22,33]
0201S_P33
5 4 3 2
5 4 3 2 1
T P3531 Memory top swap

T P3530 not implemented
U3400B on Delos design.
P3 D12 P IO3_0
[34] C FG_ID_HUNS P4
PIO2_0/ADC0_7 PIO3_0
D11 S AM_KIP_RST#_SAM_SIDE R 3507 ALL 0 T P3526
[34] C FG_ID_THOS C3
PIO2_1/ADC0_8 PIO3_1
C10
S
[72] AM_BKLT_CTRL_PW M PIO2_2 PIO3_2 S AM_PCH_RTCW AKE [22] S AM_KIP_RST# [29,74]
B1 A13
[66] A PU_SOC_EN D3
PIO2_3 PIO3_3
B11
[22,37] R SMRST_1v8# was PM_PCH_PWROK C1
PIO2_4 PIO3_4
B10
PIO2_5 PIO3_5
D F3 C9 eSPI not implemented D
[37] S AM_PW RBTN_1v8# J2
PIO2_6 PIO3_6
B8 on Delos design.
[58,60,61,62,65] S LP_S3_DRV# F4
PIO2_7 PIO3_7
A7
[58,60] S LP_S4_DRV# K2
PIO2_8 PIO3_8
C7
S
[37] YS_PW ROK_1v8 PIO2_9 PIO3_9
+ 1P8VA P1 A3
R 3523 [55] V CCRTC_RST K3
PIO2_10 PIO3_10
B2
[59,62] V SUS_ON R 3533 SL_UART_RXr M2 PIO2_11 PIO3_11
L2
S AM_PCH_LID_STATE [20]
100K S 499 PIO2_12 PIO3_12 E XT_VOLT_ADC_EN [63]
[37] L_UART_RX_1V8
PIO2_13FC5
0201S_P28-W35
R 3532 499
SL_UART_TXr P7 H4 A DC_RD_EN [34,70]
S
[37] L_UART_TX_1V8 PIO3_13 this is for SAM_SOC_JTAG_TRST#
R 3501 R 3500 L7 E3
[57] P ANEL_LOGO M8
PIO2_14 PIO3_14
D2
F AN1_PW M_1v8 [37]
needs to be Open TDrain
2K 2K
[72] S AM_LCD_BKLT_EN L8
PIO2_15 PIO3_15
E1 PD_SDAr R 3511 P3527
S PIO2_16 PIO3_16 0 S AM_PD_SDA [29,33,79]
[65] AM_VDD_PANEL_EN P10 K1 FC8 PD_SCLr R 3512 0201S_P28-W35
PIO2_17 PIO3_17 0 S AM_PD_SCL [29,33,79]
[33,70] P OW ER_SMB_SDA
00201S_P28-W35 R 3502
BAT_SDAr
FC3 N10 PIO2_18 PIO3_18
M6 0201S_P28-W35
T P3511
[33,70] POWER_SMB_SCL
R
00201S_P28-W35 3503
BAT_SCLr P12 J3 S AM_3P3V_PD_EN_R R 3505 0 S AM_3P3V_PD_EN [79] S AM_LS_DIR1 [37]
PIO2_19 PIO3_19
P13 N2 S AM_PD_HRESET_R R 3506 0 S AM_PD_HRESET [79]
[10] S AM_PROCHOT R 3504 0 ALL SAM_PIO2_21
L10
PIO2_20 PIO3_20
P5 ALL
[20,30,33] T PANEL_RST# K10
PIO2_21 PIO3_21/ADC0_9
N5 + 1P8VA
P SU_VOLT [63]
[29] S AM_MUX0_EN M14
PIO2_22 PIO3_22/ADC0_10
C2 OD PIN P IO3_23 S L1_ADC [70]
[21] S AM_UEFIROM_SPI_CS# PIO2_23 PIO3_23 T P3528
S AM_PIO2_24 K14 E2 OD PIN P IO3_24 C 3501 C 3502
T P3505 PIO2_24 PIO3_24 T P3529
S AM_PIO2_25 J11 P9 A CPRESENT_SAM
T P3509 PIO2_25 PIO3_25 0.01u
10V 0.01u
10V
S AM_PIO3_26
[21,76] S AM_FLASH_UEFI
H11
PIO2_26 PIO3_26
K5 T P3522 R 3513 R 3514 0201S_P33 0201S_P33
H14 P14 S AM_PIO3_27 2K 2K
T P3508 PIO2_27 PIO3_27 T P3525
G13 M11 S AM_PIO3_28
[64] S AM_KBTP_PWR_EN [29] U SBC_MUX0 PIO2_28 PIO3_28 T P3514
G11 L13 S AM_FLASH_EN [34]
[29] U SBC_MUX1 F12
PIO2_29 PIO3_29
K13 SAM_SEN_SDA_R R 3515 0
C [29] U SBC_MUX2 D14
PIO2_30 PIO3_30
J14 FC9 SAM_SEN_SCL_R R 3516
S AM_SEN_SDA [33,39]
C
0
[29] U SBC_MUX3 PIO2_31 PIO3_31 S AM_SEN_SCL [33,39]
L PC54S001JEV180 Rev 1B
S AM_UEFIROM_SPI_CS# R 3540 0
T P3532 S AM_PANEL_SDA [72]
R 3541 0 S AM_PANEL_SCL [72]
A CPRESENT_SAM [37]
T P3521
T P3515
+ 1P8VA
https://vinafix.com
R 3508 U3400C
P IO5_16 S AM_DSP_RESET# [43]
10K H13 F2 T P3510
[33] S AM_LED0# G14 PIO4_0 PIO5_16 F1 P IO5_17
[33] S AM_LED1# PIO4_1 PIO5_17 T P3523
R 3534 0 F14
EXP_UART_RXr G1
[63] C HARGER_SDA R 3535 PIO4_2 PIO5_18 S AM_PCH_INT [22]
B [63] C HARGER_SCL
0 FC6
EXP_UART_TXr F13
PIO4_3 PIO5_19
G2 S AM_PCH_BASE [20] B
D9 G3 EXP_SDAr R 3519 0
PIO4_4 PIO5_20 P CH_SAM_SNSR_SDA [33,76]
DV change: E10 H1 FC7 EXP_SCLr R 3520 0201S_P28-W35 0
P CH_SAM_SNSR_SCL [33,76]
S AM_PIO4_6 D10 PIO4_5 PIO5_21 H2 0201S_P28-W35
RAFLA DETECT T P3516 PIO4_6 PIO5_22 S L1_UART_LS_EN# [37]
S AM_PIO4_7 A14 H3
T P3517 PIO4_7 PIO5_23 T P3506
M TP3518 S AM_PIO4_8 B14 J1 S AM_PIO5_24
PIO4_8 PIO5_24 T P3507
T P3519 A12 E5 T P3502
PIO4_9 PIO5_25 + 1P8VA K IP_LS_EN [74]
T P3520 B9 FC2 D5 S AM_PIO5_26 T P3504
A9 PIO4_10 PIO5_26
R 3518 [59] + 5VSB_EN A6 PIO4_11
0
[33,66] S OCVR_SDA_P R 3517 0201S_P28-W35 [37] S AM_LS_DIR2 B6 PIO4_12 R 3542 R 3510
0 ALL 0
[33,66] S OCVR_SCL_P 0201S_P28-W35 [70] S L1_RX_SEL# B5 PIO4_13 G PIO5_24_LCK# [30,54,57]
499K
[63,79] S AM_SL1_PW R_EN A4 PIO4_14 R 3543 0
[72,76] S L1_HPD2_EN#
R 3521 + 5V_FAN_EN_SAM C4 PIO4_15 G PIO5_26_LCK# [54]
0 ALL
[64] + 5V_FAN_EN PIO4_16
T DM_DET [54]
L PC54S001JEV180 Rev 1B
TBL3501
R 3509 Ref Des 13" 15"
R3509 DNP 0-ohm
0
TBL3501
A A
5 4 3 2
PCH
Battery
5 4 3 2 1
D D
C C
B
5 4 3 2
5 4 3 2 1
1P8VA
+
3701
C
200K 0.1u SN74AVC2T245RSWR
3706 10V 3700
R R
DNP 499K 3700 3P3VA
U +
D
7 VCCA VCCB 6 D
3719 0
[35] L_UART_TX_1V8 8 5 R AM_SL1_TX [70]
S A1 B1 3720 0 S
[35] L_UART_RX_1V8 9 4 R AM_SL1_RX [70]
S A2 B2 S
3740 0
[35] AM_LS_DIR1 R 10 2
S 3741 0 DIR1 OE
[35] AM_LS_DIR2 R 1
S DIR2
3
GND
3700
C
200K 200K 1u
6.3V
3701 3707 200K 200K
R R
3704 3705
R R
DNP DNP
OE "HIGH" for hi-impedance both sides
[35] SL1_UART_LS_EN# R3721 0
R3703
C 499K C
DNP
Vinafix.com
+1P8VA
10K
+3P3VSB
R3718
10K
R3717
G
[35] FAN1_PWM_1v8 S D R3716 0

FAN1_PWM [39]
Q3703
https://vinafix.com
B B
[29,79] PD_SAM_DBG_ACC_MODE R3709 0

PD_SAM_DBG_ACC_MODE_1V8 [34]
+3P3VSB
C3713
0.1u
Series Rs to protec inputs in event SAM 6.3V
drives signals HIGH and Silego IC is not powered U3713 DNP
1 [22,33] R3702 0
VDD APU_S0A3 APU_S0A3_1V8 [34]
GND
3 11
R3724 ALL 1K SAM_PWRBTN_1v8#_R 4 A0 Y0 10 S0A3 not implemented but leaving 0-ohm R option.
[35] SAM_PWRBTN_1v8# A1 Y1 SAM_PCH_PWRBTN# [18,22]
[35] SYS_PWROK_1v8 R3728 ALL 1K SYS_PWROK_1v8# 5 9
ACPRESENT_SAM_R A2 Y2 SYS_PWROK [22]
[35] ACPRESENT_SAM R3726 ALL 1K 6 8
R3729 ALL 1K RSMRST_1V8#_R A3 Y3 SAM_PCH_ACPRESENT [22]
[22,35] RSMRST_1v8# 2 12
B0 A0B0
7 RSMRST# TP3701
GND
SLG4R42324 Do not need to translate to 3.3V level.
Both APU & SAM are 1.8V level
GND
A A
5 4 3 2
5 4 3 2 1
Trusted Platform Module +1P8VSB +1P8V_TPM
DBG_S
D TBL3801 R3817 0.1
0603S_P65-W95
D
PMTP3801 PMTP3802
SP-TP-C0P381 SP-TP-C0P381
+1P8V_TPM
+1P8V_TPM
TBL3801
C3807
0.1u 10V ALL
0201S_P33-W39 C3801
0.1u 10V
C 0201S_P33-W39 Neet INT Conn, May need add'l cfg for NatZ C
GND
R3808 GND
0
TBL3801
ALL DNP +1P8V_TPM
C3806 C3805
U3801 0.1u 10V 0.1u 10V
0201S_P33-W39 0201S_P33-W39
R3802 15 TPM_SPI_CLK 19 1
[20,21] SPI_CLK SCLK V SB R3811 +1P8V_TPM
17 8 GND GND 10K +1P8V_TPM
[22,33,34,44] PLT_RST_BUF# RESET V HIO_8 22 ALL
2 V HIO_22
3 NC1
5 NC2 29
TPM_PP Z_PP_NUVO_NC 7 NC3 S DA/GIO0 30 TP3803 SP_TP_SMDP58
R3809 TBL3801 0 R3813 R3810
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9 NC4 S CL/GIO1 TP3804 SP_TP_SMDP58
DNP 18 4.99K 10K
10 NC5 S PI_IRQ/GPIO2 6 TPM_IRQ# [20] ALL ALL
C3804
11 NC6 G PIO3 TP3801 SP_TP_SMDP58
22p 13
NC7 G PIO4/SINT TP3802 SPI_TPM_CS# [20,21]
0201S_P33 12 20 SP_TP_SMDP58
25V 14 NC8 S CS/GPIO5 4 NUVO_PP_Z_NC R3805 TBL3801 0 TPM_PP
B NC9 P P/GPIO6 B
15 21 TPM_SPI_MOSI R3803 15
25 NC10 MOSI/GPIO7 24 TPM_SPI_MISO SPI_MOSI [20,21]
GND R3801 15
26 NC11 M ISO SPI_MISO [20,21] DNP
27 NC12 16 R3814
28 NC13 G ND1 23 4.99K
31 NC14 G ND2 0201S_P28-W35
32 NC15 33
NC16 M PAD
NPCT750SAAYX
M1041056-001 GND
TBL3801
R3804 R3806 R3807 GND
0 0 0
TBL3801 TBL3801 TBL3801
GND GND GND
5 4 3 2
5 4 3 2 1
+5V_FAN
Imax=0.7A
Trace Width>30mil
+5V_FAN
J3901
M TG1
7 THERMAL_MODULE_DET
1
2 1 FAN Connector LOW: AAC
2
D 3
4 3 HIGH: DELTA D
+1P8VSB 5 4 +5V_FAN
C3903 6 5
6 8
22u 6.3V
M TG2
K
0603
R3906 D3901
499K 1N4148W S-R2
MTP3902 75V
A
X862668-001 +1P8VAS
[34] THERMAL_MODULE_DET Fan Supplier Detect
CFAN_PW M_R_1 R3903 100 FAN1_PW M [37]

0603
FAN_TACH1 [34]
D3903
MTP3904
RB520CS3002L
+3P3V C3906
close to J39001
K A R3902 4.99K 0.1u +5V_FAN MTP3901 C3901
+
1P8VAS +P3VAS_SIL
3
0201 DNP 0.1u
MTP3903
C3907
0.1u GND R
3916 R
3905
100K 100K
C GND
250uA for 32conv/sec C
U3901
SAM_SEN_SCL 1 5 Q
3901
S CL V+
SAM_SEN_SDA 6 3 R3904 0 T
EM_DEVICE_RST# S D
S DA A LERT D
EVICE_RST# [58]
+1P8VAS 0201S_P28-W35
4 2
250uA for 32conv/sec A DD0 G ND SOTFL-3_1P3XP9XP55_P4
G
U3903
1 5 SN1608035
[33,35] SAM_SEN_SCL SCL V+ +
1P8VAS
6 3 R3918 0201S_P28-W350 TEM_DEVICE_RST#
[33,35] SAM_SEN_SDA SDA ALERT DNP
4 2
ADD0 G ND Skin1
SN1608035 GND
GND
https://vinafix.com 7-bit I2C Address = 0x48

C3904
Skin4
0.1u
7-bit I2C Address = 0x4A

GND +1P8VAS
250uA for 32conv/sec
U
3902
SAM_SEN_SCL 1 5
B S CL V+ B
SAM_SEN_SDA 6 3 R
3919 0 T M_DEVICE_RST#
E
S DA A LERT 0201S_P28-W35
DNP
4 2
A DD0 G ND
+1P8VAS
SN1608035
250uA for 32conv/sec G
ND
U3904 C3902
SAM_SEN_SCL 1 5
SCL V+
Skin2
0.1u
SAM_SEN_SDA 6 3 R3917 0201S_P28-W350 TEM_DEVICE_RST#
SDA ALERT
4
ADD0 GND
2
DNP
7-bit I2C Address = 0x49
GND
VDD_U3904 SN1608035
GND
C3905
Skin3
0.1u
7-bit I2C Address = 0x 4B

GND
temp sensor for the right location testing
5 4 3 2
E D C B A
1P8V_AUDIO_DVDD 1P8V_AUDIO 5V_AUDIO

+ 1P8V_AUDIO_DVDD 0 4014 + +
+ R 5V_AUIDO_AVDD 0 4034
+ R
4003 4010 10V

C0.1u C10u 0402
4029 4020
C 4015 C 4013
0.1u C 10u 0.1u C 10u GND GND
A A
ND ND ND ND
G G G G
1P8V_AUDIO
+
4021
4 4018 4025 C 4
4002 4033 R
100K C
10u 4022 4008 0.1u
4016 C C 4023 C C 10u
C
10u 0.1u 0.1u C 10u 0.1u
4009 DNP
U H11
VDD ND ND
D F1 GND GND GND GND GND GND GND G G
C8 VDD_IO A A A A A A A
CBEEP D
P C12
VDD1
A
E4 D3 5VSB 5V_AUDIO
[22] HDA_SDOUT DATA_OUT VDD2 + +
M S A
D5 A12 ODEC_LDO1
[22] HDA_SYNC YNC DO1_CAP D1 CODEC_LDO2
M S LDO2_CAP CODEC_LDO3
[22] HDA_BCLK E6 LDO3_CAP E2 4036 4035
CLK C R R
M B L 10K 10K
POUT_JD_R D7 D11 DNP
H D1 REF
4006 J V
C F11 A8 LC3260_VD5STB
22p [43] oV_IRQ D2 VSTB A
1P8V_AUDIO DNP W
+ J 5
G10 B5 PVEE
100K 4019 [43] MIC_CLK_CODEC PIO1/DMIC_CLK PVEE C UDIO_VREF
R D G C A
1% ND F9
G [43] MIC_DATA1_CODEC PIO0/DMIC_DATA12 B3
D G 4001
PVDD 4030 C 4019
H C C
200K 4006 2.2u 0.1u 2.2u
[41,76] POUT_JD R
H 1% A6
E12 POUT_L A4 POUT_L [41]
[42] ODEC_AMP_OUTL H HPOUT_R [41]
E10 INE2_L POUT_R GND GND
[42] CODEC_AMP_OUTR LINE2_R H H GND
A A A 1P8V_AUDIO_DVDD
C L +
4026
C G2 DATA_IN_R 4004 33
DATA_IN S R HDA_SDIN [22]
0.1u S M
B9
[41] P_MIC_L A10 IC2_L/RING2
ALL 4001
[41] HP_MIC_R MIC2_R/SLEEVE
C6 R
H M P_MIC_VREFO_L [41] 10K
GND H9 IC2_VREFO_L B7
[41] OMBO_JACK MIC2_VREFO_R H
A PIO2/I2S_EN/SPDIF_OUT/DMIC_DATA34
C G M
G6 F3
[43] OST I2S_BCLK_R D9 2S_BCLK APD G12 ODEC_PD_N [42]
P OST I2S_DIN_R I EEST 4002 10K C
[43] F5 2S_IN G4 R
[43] OSTP I2S_LRCK_R I T
3 2S_LRCK CAN 3
P I S
H7 G8
[43] ODEC_I2C_SCL H5 2C_CLK 2S_OUT1 F7
C
[43] ODEC_I2C_SDA I I ND
2C_DATA 2S_MCLK/I2S_OUT2 G
C I I OST I2S_DOUT_R [43]
C10 B11 P
IC2_CAP VSS1 C2
M A
B1 VSS2
A
A2 BP C4
C
4009 2.2u ODEC_CBN1_R BN PGND
C C C C
H3
ODEC_CBP1_R E8 GND_1 H1
C D
ESETB GND_2 GND
R D A
ALC3300-GRT
P4001
J 4017
C
1 2 10u
DNP ND
G
0201 SHUNT
P4002 GND
J A
1 2
0201 SHUNT
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P4003
J
1 2
0201 SHUNT
GND AGND
2 2
1 1
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E D C B
E D C B A
HP/MIC1 Combo Jack R4107 0

[40] HP_MIC_VREFO_L
DNP
AGND GND
R4104 L4101 place close to CON4101
2.2K Place close to connector
L4101 GBK160808T-121Y for ESD protection
120 OHM,100MHZ
C4104 MIC1_CR R4101 MIC1_CR_F [76] HP_MIC_LR_CON
4.7u 1K This is the
[40] HP_MIC_R Lynx combo
4 4
C4108 [76] HPOUT_R_CON jack.
Schematic
100p [76] HPOUT_L_CON symbol is only
C4105 4.7u R4105 0201
[40] HP_MIC_L C4103 used for the
22K footprint
100p (Screw on
C4107 GND connector). DNP
Therefore, it J
is DNP. 4103
4700p
1
M IC
AGND AGND
AGND 3
R IGHT
R4106 22K 4
[40] COMBO_JACK D ET
5
L EFT
C4106 R4102 10 1% HPOUT_L_F L4102 GBK160808T-121Y 2
[40] HPOUT_L 120 OHM,100MHZ
G ND
10u 0402
R4103 10 1% HPOUT_R_F GBK160808T-121Y
[40] HPOUT_R L4103 120 OHM,100MHZ
0402
A
GND
AGND R4110 R4111
A2
A2
A2
10K 10K D4104 D4102 D4103
V5.5MLA0402NR
V5.5MLA0402NR
V5.5MLA0402NR
3 C4101 C4102 CDS2C05GTA CDS2C05GTA CDS2C05GTA 3
A1
A1
A1
AGND AGND 100p 100p
AGND AGND GND GND GND

[40,76] HPOUT_JD
A2
D4101
C DS2C05GTA
V5.5MLA0402NR
A1
GND
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[76] SPK_L+_CON
LYNX Speaker Connector
4J101
ONN_B2B_2-X872411-001
R4114 0 S
PK_L+_CON 1
X872411-001
2 [42] SPK_L+ 1 2
2
2
C4121 S
PK_L-_CON
C
1000p 3
D4105 M TG1
A1
4
D4106 M TG2
A1
GND
V18MLA0402NR
C4122 V18MLA0402NR
R4115 0 G
ND
A2
[42] SPK_L- 1000p
A2
LYNX Speaker Connector
[76] S
PK_L-_CON
GND
[76] S
PK_R+_CON
GND 4J102
ONN_B2B_2-X872411-001
R4116 0 S
PK_R+_CON 1
X872411-001
[42] SPK_R+ 1
2
2
C4123 S
PK_R-_CON
C
1000p 3
M TG1
A1
A1
D4108 D
4107 4
M TG2
GND
V18MLA0402NR V18MLA0402NR
1 C4124 G
ND 1
R4117 0
A2
A2
[42] SPK_R- 1000p [76] S
PK_R-_CON
GND GND
E D C B
5 4 3 2 1
+VSYS R4224
E1 E2
PTP4203 SENS PTP4204
I1 I2
Inductor may be changed based on placement constraints
L4201
L OAD +V_AUDIOBOOST R4210 R4212
U4202 0.01
R4215 0.02 11 6
C4223 SW V OUT DBG_S
1.5uH 0.1u 10 3 VBOOST_FB R4221 DNP 681K
DNP B OOT FB
C4221 DBG_D 0201 VBOOST_BOOT
R4219 150K VBOOST_FSW 1 4 VBOOST_COMP C4225 C4226 C4222
22u DBG_D F SW C OMP
25V R4222 22u 22u 22u
D DBG_D 9 8VBOOST_ILIM 100K 25V 25V 25V D
DBG_D V IN I LIM R4218
CODEC_PD_N VBOOST_EN 7 DBG_D DBG_D DBG_D
R4223 DNP 0 4.99K
EN R4220 C4220
R4225 VBOOST_VCC 2 5 DBG_D
127K
PTP4202 V CC G ND C4224
100K 10p
C4227 DBG_D
TPS61089RN
PTP4201 DNP
DBG_D 0.01u
DBG_D
DBG_D
2.2u Peak current at 3A
Switching frequency set to roughly 1 MHz
DBG_D boost output voltage = 9.375V
Need to confirm with TI for compensation
DBG_D 15dB
SPK_L- [41]
SPK_L+ [41]
SPK_R+ [41]
SPK_R- [41]
OUTPR O UTNR O UTNL O UTPL
R4211 C4212 C4201 R4202 R4203 C4218 C4214 R4204
0201 0201 330p

10 330p 330p 10 10 330p 10
0201 0201 0201 Close IC Close IC 0201 0201 0201 15dB
25V 25V 25V 25V
C4219 C4210 C4206 C4208
teknisi indonesia 0.33u 0.33u 0.33u 0.33u

C Close IC 0201 0201 0201 0201 Close IC C
25V 25V 25V 25V
+V_AUDIOBOOST A
24
23
22
21
20
19
18
17
MP_VCC
AMP_VCC
G ND
B SNR
G ND
G ND
B SNL
G ND
O UTNR
O UTNL
AMP_VCC AMP_VCC
25
O UTPR 16
C4217 O UTPL C4202
10u C4207 C4213 26 C4204 C4205 10u
B SPR 15
0603 0.1u 1000p 1000p 0.1u 0603
B SPL
16V 0201 0201 0201 0201 16V
16V 25V 27 25V 16V
P VCC 14
+1P8V_AUDIO
Close IC Shut-down Control P VCC Close IC
U4201
Hi : Normal
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28
Low: shut-down P VCC 13
+5V_AUDIO ALC1304
P VCC AM Avoidance Setting
R4205 100K AMP_PD_N 29
R4201 S DZ 12 GVDD
0201
A VCC
10K
0201 30 R4213
F AULTZ 11
S ync 10K
0201
31 DNP
I NPR 10
G
A M0
B S D 32 B
[40] CODEC_PD_N I NNR 9 R4209
C4216 A M1 R4214
P BTL/BTL
10K
Gain/SLV
0.1u 33 10K 0201
E PAD
GVDD
M UTE
0201 C4209 BTL/PBTL Setting 0201
P limit
Q4201
I NNL
I NPL
16V
GND DNP
[40] CODEC_AMP_OUTR 0.1u
0201 R4217
16V 10K
1
8
0201
DNP R4208
10K
R4216 10K 1% GVDD AGND Gain/SLV Setting 0201
ALL 0201
C4203 R4207
R4206 C4215 0.1u 10K
AGND 0 1u 0201 C4211 R4210 0201
0201 0201 16V 0.1u 54.9K
DNP 10V 0201 0201
Close IC 16V
GAIN / SLV
AGND CODEC_AMP_OUTL [40]

AGND
R4212
34.8K
0201
A
AGND
AGND
5 4 3 2
5 4 3 2 1
[43] BVDD
D
4345
BVDD [43] 4342 0.1uC
D 10K
R
ALL 4302 ALL
K K
U
2 2
V 8
[43] PI_MOSI0_IO0_FLASH CC PI_MISO0_IO1_FLASH [43]
R4333 R4334
S 5D D 2 S
0 [43] PI_SCL_FLASH I/IO0 O/IO1
[40] ODEC_I2C_SDA 2C_SDA_S [43] S
4320 6C
C I [43] PI_MISO2_IO3_FLASH LK
R [43] PI_MISO1_IO2_FLASH 7
0 To connect Codec's I2C bus S 3 H OLD/IO3 G 4
[40] ODEC_I2C_SCL 2C_SCL_S [43] [43] PI_CS_FLASH S ND
4321 1 W P/IO2
C I S C
W 25Q16FWUXIE M 9
R S PAD
M1103684-001
D D
0
[40] oV_IRQ RQ1 [43]
4322 To connect Codec GPIOs 16Mbit part recommended by Realtek
W I
R
0 MIC2_SCL [43] 4301A

[54,76] MIC1_SCL_DSP
4323 U
D D [43] PI_SCL_S PIO26_TP [43]
R [43] SPI_CS_S PIO27_TP [43]
0 N7 G G G13 G
[54,76] MIC1_SDA_DSP MIC2_SDA [43] [43] PI_MISO_S
S N5 G PIO0/DMIC1_SCL/SPI_SCL_S G PIO26/DSDA/DACDAT1 L9 OST
G I2S_BCLK2_R [43]
4324
D D [43] PI_MOSI_S
S M6 G PIO1/DMIC1_SDA/SPI_CS_S PIO27/DSDB/ADCDAT1
G E15 OST
P I2S_LRCK2_R [43]
4340 R
S L7 G PIO2/DMIC2_SCL/SPI_MISO_S G PIO28/BCLK2 G15 OST
P I2S_DOUT2_R [43]
22p
C To connect 2 x DMICs Unit PIO3/DMIC2_SDA/SPI_MOSI_S PIO29/LRCK2
4340 4341 K12 G G J15 OST
P I2S_DIN2_R [43]
[43] LC5521_I2CSCL_M2 E13 G PIO4/SPDIF_OUT/PDM_SCL/DMIC4_SCL/I2C_SCL_M1 G PIO30/DACDAT2 L15 P [43] TAL_OUT
R0 R 0 0201S_P33
[43] LC5521_I2CSDA_M2
A A15 G PIO5/PDM_SDA/DMIC4_SDA/I2C_SDA_M1 G PIO31/ADCDAT2 D16 X
DNP DNP 25V
PIO6/SPDIF_OUT/PDM_SCL/DMIC3_SCL/DMIC1_SDA_BYPASS/I2C_SCL_M2 G PIO32/UART1_TX/DMIC1_SDA/BCLK3
A [43] 2C_SCL_S B16 G F16 [43] TAL_IN
ND [43] 2C_SDA_S PIO7/PDM_SDA/DMIC3_SDA/DMIC2_SDA_BYPASS/I2C_SDA_M2 PIO33/UART1_RX/DMIC1_SCL/LRCK3
I B12 G G H16 X 8Y2457670011
BYPASS PATH G [43]I RQ1 C13 G PIO8/DMIC4_SCL/I2C_SCL_S G PIO34/UART1_RTS#/DMIC2_SDA/DACDAT3 K16 PI_SCL_FLASH [43]
PIO9/DMIC4_SDA/I2C_SDA_S PIO35/UART1_CTS#/DMIC2_SCL/ADCDAT3 4303
I M14 G G P4 S Y 160 4331
PIO10/DMIC3_SCL/DMIC4_SCL/DMIC3_SDA_BYPASS/IRQ1 PIO36/SPI_SCL_M/JTCK/SPI_SCL_S/SPI_SCL_FLASH
1 0201S_P28-W 35R
3
[43] TCK PI_CS_FLASH [43] ND
2 4
0 [43] TMS
J C11 G G R3 PI_MOSI0_IO0_FLASH
S [43] G 4342
[40] MIC_DATA1_CODEC MIC2_SDA_Bypass [43] [43] TDIJ D12 G PIO11/JTCK PIO37/JTMS/SPI_CS_S/SPI_CS_FLASH N3 PI_MISO0_IO1_FLASH
S [43]
4325 G 4341 25V 15p
C
D
R
D [43] TDO
J M8 G PIO12/JTMS G PIO38/SPI_MOSI_M/JTDI/SPI_MOSI_S/SPI_MOSI0_IO0_FLASH P2 PI_MISO1_IO2_FLASH
S [43] 25V 15p
C 0201S_P33
[43] TRST#J F12 G PIO13/JTDI G PIO39/SPI_MISO_M/JTDO/SPI_MISO_S/SPI_MISO0_IO1_FLASH R1 PI_MISO2_IO3_FLASH
S [43] 0201S_P33
To connect Codec DMIC Input J H12 G PIO14/JTDO PIO40/DMIC2_SCL/SPI_CS0_M/JTRST#/SPI_MISO1_IO2_FLASH
G M2 S
0 PIO15/JTRST# PIO41/DMIC2_SDA/SPI_CS1_M/SPI_MISO2_IO3_FLASH
[40] MIC_CLK_CODEC MIC_CLK_IN [43]
4326
D D
R
D14 G G L3
F14 G PIO16/DMIC4_SCL/UART1_TX G PIO42/DMIC3_SCL/SPI_SCL_M J7
K14 G PIO17/DMIC4_SDA/UART1_RX G PIO43/BCLK1/DMIC4_SCL/UART1_TX/SPI_MOSI_M K6 MIC2_SCL [43]
N11 G PIO18/LED_PWM2/DMIC1_SCL/UART1_RTS G PIO44/LRCK1/DMIC4_SDA/UART1_RX/SPI_MISO_M M4 MIC2_SDA
D [43]
C15 PIO19/DMIC2_SCL/LED_PWM3/DMIC1_SDA/UART1_CTS PIO45/DACDAT1/DMIC2_SCL/UART2_TX/SPI_CS0_M L5 D
G G
B14 G PIO20/DMIC3_SCL/UART2_TX PIO46/ADCDAT1/DMIC2_SDA/UART2_RX/SPI_CS1_M
P10 G PIO21/DMIC3_SDA/UART2_RX
L11 G PIO22/LED_PWM2/IRQ1/PDM_SCL/DMIC2_SCL/UART2_RTS RQ2_TP [43] [43] RQ2_TP P4307
4327 33 1% ALL PIO23/LED_PWM3/IRQ2/PDM_SDA/DMIC2_SDA/UART2_CTS T
[40] OST I2S_BCLK_R OST I2S_BCLK2_R [43] G N9 I I
R PIO47/DMIC4_SDA_BYPASS/IRQ2 P4321 P4308
P P G M16 MIC2_SDA_Bypass [43] [43] PIO26_TP [43] PI_MOSI_S
4328 33 1% ALL PIO48/SPDIF_OUT/DMIC3_SCL/PDM_SCL/LED_PWM1/DMIC1_SDA_BYPASS T T
[40] OST I2S_LRCK_R OST I2S_LRCK2_R [43] [43] PIO24_TP G P16 D G S
R
P
4329 33 1% ALL
P [43] G
PIO25_TP J13 G G PIO49/SPDIF_IN/DMIC3_SDA/PDM_SDA/DMIC2_SDA_BYPASS/MIC_SECU N15 MIC_CLK_IN [43] [43] PIO27_TP P4302 [43] PI_MISO_S P4309
[40] OST I2S_DOUT_R OST I2S_DOUT2_R [43] G P8 G PIO24/DSDCLK/BCLK1 G PIO50/PDM_SDA/DMIC4_SDA/SPDIF_IN/DMIC3_SDA_BYPASS/DMIC3_SCL P14 D G T S T
P
R
P To connect Codec I2S I/F PIO25/LRCK1 PIO51/PDM_SCL/DMIC4_SCL/SPDIF_OUT/LED_PWM1/DMIC4_SDA_BYPASS/DMIC_CLK_IN [43] PIO24_TP P4303 [43] PI_SCL_S P4310
33 1% ALL ALC3311-GRT T T
[40] OST I2S_DIN_R OST I2S_DIN2_R [43] G S
P P [43] PIO25_TP P4304 [43] PI_CS_S P4311
4330
C
R M1113651-001 G T S T C
4350
4351
4352
4353
C
2p
C
2p
C
2p
C
2p
2 ALL 2 ALL 2 ALL 2 ALL
Place filter close to DSP
0
[35] AM_DSP_RESET# SP_RST# [43]
S 4332
R D
t's recommeded to allocate a GPIO from system EC and refer to the latest datasheet
I "Power Supply On/Off Sequence" section to control the Reset pin.
of
CVDD3 4312 ALL 0 DO_DSP_O
D R L 3P3VSB
VDD18 4311 ALL 0 AD18 +
LC5521_I2CSCL_M2 [43] A R V
A 3P3VSB
+
0 ALL
4337 2C_SCL_S [43] 4310 DNP 0
I [43] DO_HV_O
R To I2C loopback for reset L
R
0 ALL of DSP after FW updates 4309 DNP 0
2C_SDA_S [43] AD18 [43] [43] ICVDD R
4338 I V M
R 4301B
U VDD18 [43] 4308 ALL 0 1P8V_AUDIO
LC5521_I2CSDA_M2 [43] [43] MA_ELF A [43] VDD18 R +
A D L13 D V AD18 E3 A
MA_ELF BVDD [43] 4307 ALL 0
[43]FT D [43] DO18_IN R
M10 D A1
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D A VDD18 CVDD1 [43] L
FT 4306 ALL 0
[43] LASH_BOOT D [43] BVDD R
F P12 F D BVDD R5 D
[43] BVDD [43] BVDD [43] BVDD [43] BVDD LASH_BOOT 0
D D D D [43] 2C_ADDR CVDD3 [43]
I M12 I D CVDD1_K4 K4 4301 D
2C_ADDR P6 R 4313 0
D CVDD1_P6 ICVDD [43] R
D CVDD3_A13 A13 M
D CVDD3_J11 J11 ALL
4350 4351 4352 4353 DO18_IN [43]
D CVDD3_R9 R9 L
B R R R R R13 B
22K 22K 22K 22K D CVDD3_R13 DO_CORE18_O [43]
L
DNP DNP DNP DNP B8 I M ICVDD A3
C9 I N1P 0 DO_DSP_O [43]
N1N L
L DO18_IN J1 4302
E7 I R
0 DO_HV_O [43]
L
[43]
D
FT [43] 2C_ADDR
I
[43]
S
PIS_RAW [43] MA_ELF
D F6 I N2P L DO_CORE18_O K2 4303
N2N R
0
D10 I L DO_DSP_O L1 4304
E9 I N3P R
0
4354 4355 4356 4357 N3N B2 4305
R R R R L DO_HV_O R
22K 22K 22K 22K D4 I
E5 I N4P
ALL ALL N4N
C5 I
D6 I N5P/DMIC3_SDA M ICBIAS1 B10
N5N/DMIC4_SDA A9
M ICBIAS2
C7 I M ICBIAS3 A5 All Capacitors here should close to U4301
D8 I N6P/DMIC1_SDA M ICBIAS4 A7
N6N/DMIC2_SDA B6
[43] DCREF
M ICBIAS5 CVDD1 [43] CVDD1 [43] CVDD3 [43] CVDD3 [43] CVDD3 [43] CVDD3 [43]
A E1 L M ICBIAS6 B4 D D D D D D
DO_ADCREF
[43] BVDD [43] BVDD [43] BVDD [43] TAL_IN H4 X J5 TAL_OUT [43]
D D D X TALI X TALO X
4306 4316 4305 4318 4304 4319 4303 4320 4302 4321 4301 4322
EEPROM flash operation: M ICGND C3 C
4.7u
C
0.1u
C
4.7u
C
0.1u
C
4.7u
C
0.1u
C
4.7u 0.1u
C C
4.7u 0.1u
C C
4.7u 0.1u
C
FLASH_BOOT = pu installed [43] PIS_RAW N13 S D2
DMA_ELF = pd installed S PIS_RAW A GND1
F2
4358 4359 A GND2
R R
4360
DFT = pd installed
22K 22K R [43] REF1 [43] DO_EN
V L J3 L D GND_A11 A11
22K [43] REF2 DO_EN
ALL EEPROM flashless operation: V D GND_H10 H10
G1 V N1
FLASH_BOOT = pd installed H2 V REF1
D GND_N1
R7 REF1 [43] REF2 [43] DCREF [43] VDD18 [43] ICVDD [43] DO18_IN [43]
D GND_R7 V V A A M L
[43]
D
SP_RST# DMA_ELF = pd installed REF2
D GND_R11 R11
[43]
F
LASH_BOOT [43]
L
DO_EN DFT = pd installed [43] SP_RST#
D H14 R
ESET D GND_R15 R15
4334 4312 4323 4311 4324 4310 4325 4309 4326 4308 4327 4307 4328
C C C C C C C C C C C C C
1u ALC3311-GRT 4.7u 0.1u 4.7u 0.1u 4.7u 0.1u 4.7u 0.1u 4.7u 0.1u 4.7u 0.1u
0402
R
4361
R
4362 10% M1113651-001
22K 22K 25V
DNP DNP
DO_HV_O
L [43] AD18
V [43] DO_DSP_O
L [43] DO_CORE18_O
L [43] BVDD
D [43]
A 4317 4329 4300 4330 4315 4331 4314 4332 4313 4333 A
C C C C C C C C C C
4.7u 0.1u 4.7u 0.1u 4.7u 0.1u 4.7u 0.1u 4.7u 0.1u
P4301_8
P4301_7
[43] JTDI TP4351 TP4352
P4301_9
[43] JTDO TP4353 TP4354
[43] JTCK TP4355 TP4356
TP4357 TP4358
0 TP4359 TP4360 JTMS [43]
[43] DBVDD
TP4361 TP4362
R4335 TP4363 TP4364
P4301_13 JTRST# [43]
5 4 3 2
5 4 3 2 1
CIECLK_SSD_N_F
[20] 2_PCIECLK_N 2 1 P
M
DLP11TB800UL2L CIECLK_SSD_P_F
[20] 2_PCIECLK_P 3 4 P
M 4402
L
2 3
N44051 DNP 40
R
D D
CIE_SSD_TN1_F
4414 0.22u CIE_SSD_TN1_C 2 1 P 4410 0.22u CIE_SSD_TN2_C CIE_SSD_TN2_F
[24] CIE_SSD2_TX1_DN C P DLP11TB800UL2L CIE_SSD_TP1_F [24] CIE_SSD2_TX2_DN C P 2 1 P
P 3 4 P P
4404 0.22u CIE_SSD_TP1_C 4403 4415 0.22u CIE_SSD_TP2_C DLP11TB800UL2L CIE_SSD_TP2_F
[24] CIE_SSD2_TX1_DP C P L [24] CIE_SSD2_TX2_DP C P 3 4401 4 P
P P
L
2 3
N44031 DNP 40 2 3
R N4404 1 DNP 04
R
4406 0.22u CIE_SSD_TN0_C CIE_SSD_TN0_F

[24] CIE_SSD2_TX0_DN C P 2 1 P CIE_SSD_TN3_C CIE_SSD_TN3_F
P 4405 0.22u
CIE_SSD_TP0_C DLP11TB800UL2L CIE_SSD_TP0_F [24] CIE_SSD2_TX3_DN C P 2 1 P
4408 0.22u P
[24] CIE_SSD2_TX0_DP C P 3 4 P CIE_SSD_TP3_C DLP11TB800UL2L CIE_SSD_TP3_F
P 4404 4409 0.22u
L [24] CIE_SSD2_TX3_DP C P 3 4 P
P 4405
L
2 3
N44021 DNP 40 2 3
R N4401 1 DNP 04
R
3P3VAS_SIL
+
4419
R
1M
0201
+3P3VSB 1%
CON4401
74 75 4417 0
+3P3V_SSD_CON 72 .3V_1 ND1 73 R ET_A# [58]
3.3V_2 GND2 D
70 3.3V_3 GND3 71
4402 68 3USCLK(32KHZ) G 69
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C C 4407 EDET(NC-PCIE/GND-SATA) 67 C
C S P
0.1u 4413 4416 4417 C22
C C C N
K
4412 47u 0.1u 100p 10p 4401
R D
100K
DNP
G
ND Connector Key
ND ND ND ND
3P3V_SSD_CONG G G G NO PINS
A
+
4401 58 57
U 5 56 C1 ND4 55 CIECLK_SSD_P_C CIECLK_SSD_P_F
4416 10K ND N G P 4408 0 P
CC R G 54 C2 EFCLKP 53 CIECLK_SSD_N_C R CIECLK_SSD_N_F
V PESD3V3U1UL315 N R P 4415 0 P
[22,33,34,38] LT_RST_BUF# 1 EW AKE#/NC3 EFCLKN R
P A 52 P R 51
[22] CIE_SSD_PERST# 2 4 [20] 2_PCIECLK_REQ# SD_RESET_N LKREQ#/NC4 ND5 CIE_SSD_TP0_F
P B O M S 50 C G 49 P
3 48 ERST#/NC5 ETP0/SATA-A+ 47 CIE_SSD_TN0_F
P P P
ND 46 C6 ETN0/SATA-A- 45
G N P
SN74LV1T08DCKR 44 C7 ND6 43 CIE_SSD_RP0_C 4402 0
N G P R CIE_SSD2_RX0_DP [24]
4407 42 C8 ERP0/SATA-B- 41 CIE_SSD_RN0_C 4409 0 P
ALL R N P P R CIE_SSD2_RX0_DN [24]
40 C9 ERN0/SATA-B+ 39 P
100K N P
ND 38 C10 ND7 37 CIE_SSD_TP1_F
G N G P
DNP 36 EVSLP ETP1 35 CIE_SSD_TN1_F
D P P
4406 DNP 0 34 C11 ETN1 33
R N P
32 C12 ND8 31 CIE_SSD_RP1_C 4403 0
N G P R
30 C13 ERP1 29 CIE_SSD_RN1_C CIE_SSD2_RX1_DP [24]
N P P 4401 0 P
C14 ERN1 R CIE_SSD2_RX1_DN [24]
ND 28 N P 27 P
G C15 ND9 CIE_SSD_TP2_F
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26 N G 25 P
24 C16 ETP2 23 CIE_SSD_TN2_F
+3P3V_SSD_CON N P P
22 C17 ETN2 21 3P3VAS_SIL
N P +
20 C18 ND10 19 CIE_SSD_RP2_C 4410 0
N G P R CIE_SSD2_RX2_DP [24]
18 NC19 PERP2 17 PCIE_SSD_RN2_C 4411
R 0 P
.3V_4 CIE_SSD2_RX2_DN [24]
16 3 PERN2 15 P
4420
14 3.3V_5 GND11 13 CIE_SSD_TP3_F R
.3V_6 P
12 3 PETP3 11 CIE_SSD_TN3_F
P
1M
10 3.3V_7 PETN3 9 0201
8 DAS/DSS#/LED1# GND12 7 PCIE_SSD_RP3_C 4404
R 0 1%
CIE_SSD2_RX3_DP [24]
6 NC20 PERP3 5 PCIE_SSD_RN3_C 4405
R 0 P
CIE_SSD2_RX3_DN [24]
4 NC21 PERN3 3 P
2 3.3V_8 GND13 1 4418
R 0
ET_B# [58]
3.3V_9 GND14 D
76 77
C4411
78 MTG1 MTG2 79
C4403 C4401 C4412
80 MTG3 MTG4 81
B 47u 0.1u 100p 10p 82 MTG5 MTG6 83 B
K2
K2
D4421 D4422 84 MTG7 MTG8 85

86 MTG9 MTG10 87
GND GND GND 88 MTG11 MTG12 89
GND PESD5V0H1BSF
PESD5V0H1BSF
90 MTG13 MTG14 91
2
MTG15 MTG16
K
92 D4420 D4402 D4403 D4404 D4405 D4406 D4407 D4408 D4409 D4410 D4411 4412
D 4413
D 4414
D 4415
D 4416
D 4417
D 4418
D 4419
D 4423
D
MTG17
K1
K1
M1108459-002 PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
M1108459-002
GND
1
1
K
K
GND
GND
GND
A A
5 4 3 2
5 4 3 2 1
E E
+
3P3VSB
R
4510 +
C 10V 10K 5VSB
4504 0.1u C C
U
[24] USB3_USBA_TX_DN 4514 4507
[24] SB3_USBA_TX_DP C 10u 0.1u R
4526 0.1u U 1E 4536 2E
4503 10V 10V P P J
3 6 GND C
U 10V U LAG#
F NI GND MTP4504 SENS MTP4503 4501
4 ON2_VBUS 1I 2 I 21
[24] USB3_USBA_RX_DN [24]
[20] USBA_EN SBA_OVCUR# NE TG12
M
5 1 0.01 1 20
D [24] SB3_USBA_RX_DP ND1 UT L BUS TG11 D
7 G O 2 2 V M 19
K
U ND2 LIM C OAD mD TG10
R G I + C 3 M 18
[24] USB2_USBA_DN 4505 pD TG9
9 4501 4517 D DBG_S 4 M 17
[24] SB2_USBA_DP 0.1u GND NDG TG8
M
0 Ohm, Differential Pair 499K NCP380HMUAJAATBGR 150u 4504 5 16
ALL 10V 6 tdA_SSRXm
S TG7
M 15
4520 GND tdA_SSRXp TG6
A
GND 7 S M 14
11.5K GND ND_DRAIN TG5
GND GND 8 G M 13
0201 9 tdA_SSTXm
S TG4
M 12
GND GND
1% tdA_SSTXp
S TG3
M 11
TG2
M 10
U
4503 Min VIH = 1.2V TG1
M
R = 11.5 K M1015489-005
I(Max) = 2.05 A U
CONN-USB-A,BLACK
I(Typ) = 1.78 A [76]

[76]
USB2_USBA_DN_CONN
SB2_USBA_DP_CONN
I(Min) = 1.5 A GND
D
D 4503 D
A1 P_O DP_I A2
B1 D M_I B2
M_O I C2 9
D 0 Ohm, Differential Pair
G C1
ND GND
U 4 3 U
SB3_USBA_TX_DN_C SB3_USBA_TX_DN_CONN
U 0nH 1 2 U
SB3_USBA_TX_DP_C SB3_USBA_TX_DP_CONN
L
4506
90 Ohm, Differential Pair
C C
1
K
K
D D D D
4509 4510 4511 4512
PESD5V0H1BSF PESD5V0H1BSF PESD5V0H1BSF PESD5V0H1BSF
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2
K
K
G
ND
B B
A A
5 4 3 2
5 4 3 2 1
D D
C C
B
5 4 3 2
5 4 3 2 1
D D
C C
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B B
A A
5 4 3 2
5 4 3 2 1
E E
D D
C C
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B B
5 4 3 2
5 4 3 2 1
D D
C C
Vinafix.com
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B B
A A
5 4 3 2
5 4 3 2 1
+
3P3V_WLAN_VCC V V
CC_FEM CC_FEM
R
5030
U
ALL 0 0603 C C C
[24] USB2_BT_DP
U 5004 5005 5027
[24] SB2_BT_DN 11
5003 G_VCC1
5 12 1000p 1u 10u
F 9 G_VCC2
5
G_LNA_EN ALL ALL ALL
R R EM_CTRL_SE50_1 5 21
X 10 G_VCC1
2 22
5025 5026 G_PA_EN G_VCC2 C C
PABIAS5_SE50_0 5 2 5009 5010
0 0
ALL ALL
2 1000p 1u J
DET
P ALL ALL 5003
5 W
PLR
C IFI_RF_PDET_IN_CHA_SE50 C
CONN_COAX_4_2P1X2X1P0MM
PROBE C
7 W 5006 W 1 2 W SIG
NT N I UTO R5002
W C W A IFI_PROBE_CHA_SE50_1 IFI_PROBE_CHA_SE50_2 IFI_CHA_ANT_SE50
IFI_CHA_2G_ICOUT_SE50 5014 10pF IFI_CHA_2G_RX_SE50 W 16 14 W C 4 3
IFI_CHA_5G_TX_SE50 G_TX
5 G_RX
5 IFI_CHA_5G_RX_SE50 ND4
G ND3
G
5012 C
W W 18 19 W 10p 5048
C ALL G_TX G_RX
IFI_CHA_2G_XPAOUT_SE50 5015 10pF IFI_CHA_2G_TX_SE50 2 2 IFI_CHA_2G_RX_SE50 0.2p D GND 2,3,4
1
A
D DNP 0.2p 5005 X867338-001 D
W C ALL W 1 DNP
U IFI_CHA_5G_ICOUT_SE50 ND1
G 3 ALL
5016 10pF IFI_CHA_5G_RX_SE50 ALL ALL
U SB2_BT_DP_QC [50] ND2
G 4
ND3
2
SB2_BT_DN_QC [50]
A
W C ALL G 6
ND4 G
IFI_CHA_5G_XPAOUT_SE50 5017 10pF G 8 ND
ND5
G 13
ND6
G 15
ALL Right antenna connector
ND7
G 17
C C C C DIO_0402_P33MM-AA
ND8
G 20
5050 5051 5052 5053 X935756-001
F 24 ND9
G LXES15AAA1-153
EM_CTRL_SE50_0 G_LNA_EN
2 25
0.5p 0.5p 0.5p 0.5p
X 23 PAD1
M 26
ALL DNP DNP DNP
PABIAS2_SE50_0 G_PA_EN
2 PAD2
M
U QM48184
5001B 162 ALL
F 160 L_BT_RFIO_2G_0
W 131
FEM_CTRL_SE50_0 150 EM_CTRL0
F WL_XPA_2G_0 101
F L_RFIO_5G_0
W 111 V
F WL_XPA_5G_0 140 W CC_FEM
EM_CTRL_SE50_3 EM_CTRL3
F L_RF_PDET_IN_0
W IFI_RF_PDET_IN_CHA_SE50
X 118 81 W C WIFI_CHB_2G_RX_SE50
XPABIAS2_SE50_0 78 PABIAS2_0
X L_RFIO_2G_1
W 51 WIFI_CHB_2G_ICOUT_SE50 5018 10pF WIFI_CHB_2G_TX_SE50
PABIAS2_1 L_XPA_2G_1 C
XPABIAS2_SE50_1 97 X W 21 WIFI_CHB_2G_XPAOUT_SE50 5019 10pF
C WIFI_CHB_5G_RX_SE50
XPABIAS5_SE50_0 58 PABIAS5_0
X L_RFIO_5G_1
W 31 WIFI_CHB_5G_ICOUT_SE50 5020 ALL10pF WIFI_CHB_5G_TX_SE50
C C C C
PABIAS5_SE50_1 PABIAS5_1
X WL_XPA_5G_1 60 WIFI_CHB_5G_XPAOUT_SE50 5023 ALL
10pF 5021 5022 5024
U
L_RF_PDET_IN_1
W IFI_RF_PDET_IN_CHB_SE50 5005 11 1000p 1u 10u
ALL
G_VCC1
5 12 ALL ALL ALL
ALL
QCA-6174A-5-172BWLNSP-TR-0C-0 F 9 G_VCC2
5
C C C C
5054 5055 5056 5057 EM_CTRL_SE50_3 G_LNA_EN
5 21
ALL G_VCC1
X 10 2 22 C C
0.5p 0.5p 0.5p 0.5p PABIAS5_SE50_1 G_PA_EN
5 G_VCC2
2 5025 5026
ALL DNP DNP DNP 1000p 1u
2 ALL ALL J
DET
P 5004
5 W
PLR
C IFI_RF_PDET_IN_CHB_SE50 C CONN_COAX_4_2P1X2X1P0MM
5044
PROBE M
R W 7 W W 1 2 W R W R W R 1 P5004
P WIFI_RST# NT
A IFI_PROBE_CHB_SE50_1 IFI_PROBE_CHB_SE50_2 N I UT
O IFI_CHB_ANT_SE50_1 IFI_CHB_ANT_SE50_2 IFI_CHB_ANT_SE50_3
[22] CIE_WIFI_PERST# R5014 ALL 0 5017 0 5016 0 5010 0
W IFI_WAKE#_R 16 14 4 3
R5015 ALL 0 W W
W [22] IFI_WAKE#
5007 ALL 0 IFI_PCIECLK_REQ#_R G_TX
5 G_RX
5 IFI_CHB_5G_RX_SE50 ND4
G ND3
G 0402 L 0402 L 0402
[20] IFI_PCIECLK_REQ# 18 19 10p 5011 ALL 5010
P W C C ALL ALL M1075199-001
P PCIECLK_WIFI_DP G_TX
2 G_RX
2 IFI_CHB_2G_RX_SE50 5013 50131 FCAOS14B02G1PC
D 0.6pF 0.6pF
1
[20] PCIECLK_WIFI_DP
A
CIECLK_WIFI_DN 0.2p 0.2p 5006 X867338-001 DNP DNP
[20] CIECLK_WIFI_DN ALL
R P 1 DNP DNP ALL M
P PCIE_WIFI_RX0_DP_C ND1
G 3
[24] P CIE_WIFI_RX0_DP R5020 ALL 0 ALL 1 P5005
5021 ALL 0 CIE_WIFI_RX0_DN_C ND2
G 4
[24] CIE_WIFI_RX0_DN
2
ND3
A
C P G 6 G G
ND4 G
P
C 5029 0.1u 10V PCIE_WIFI_TX0_DP_C G 8 ND ND ND
[24] P CIE_WIFI_TX0_DP CIE_WIFI_TX0_DN_C ND5
G
5030 0.1u 10V 13 M1075199-001
[24] CIE_WIFI_TX0_DN ND6 G
ALL G 15 DIO_0402_P33MM-AA ND FCAOS14B02G1PC
ALL ND7
G 17 X935756-001 ALL
R ALL B ND8
G 20 LXES15AAA1-153 M
B
R
5066 0 WT_EN F 24 ND9
G P5006
[20,33] W T_DISABLE# 1
[24,33] LAN_DISABLE# R5065 ALL 0 3 L_EN EM_CTRL_SE50_2 G_LNA_EN
2 25
S 5061 0 2KHz_CLK_IN PAD1
[20] USCLK ALL X 23 M 26
PABIAS2_SE50_1 G_PA_EN
2 PAD2
M
C
G M1075199-001 C
QM48184 ND FCAOS14B02G1PC
+ ALL ALL
3P3V_WWAN +
3P3V_WLAN_VCC
L Left antenna spring clip
5003
+
3P3V_WLAN_VCC
FB_50OHM ALL
C +
5031 ALL ALL 3P3V_WLAN_VCC
ALL C C
10u 5032 5033 0 R SWREG_IN
6.3V 0.1u 0.1u 0603 5035
0402 ALL Spring finger to improve grounding to bucket
G
ND
G
ND
G
ND Place all caps close to pins C
50127
R
5036
+ 1u 0
1P1V_WLAN_DVDD 0201 0201 M1110500-001 M1110500-001 M1110500-001
ALL DNP J J J
5005 5006 5007
1
P1V_WLAN_AVDD
C C SPRING_CONTACT_1P SPRING_CONTACT_1P SPRING_CONTACT_1P
50128 50129 U
5001C
1
163 153
22u 22u WREG_IN
S BATT
V
L
ALL ALL 5015 152
SWREG_OUT 144 +
WREG_OUT
S EG33_GATE
R 3P3V_WLAN_VCC
1.5uH50MHz
C C A 132 164 G
50102 50130 LL WREG_FB
S EG33_FB
R ND
Optional 1.1V External LDO 143 133
2.2u 1u ND_SWREG
G ND_REG33
G C
50100
+ ALL 123 134 4.7u
3P3V_WLAN_VCC ALL DD11A_PM_OUT DD11_AO_PM_OUT
+ V V ALL
3P3V_WWAN
124 C
DDIO_AO_IN 50101
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V
44 1u
C
+ 50103 54 DDIO_GPIO
V 64 ALL
3P3V_WWAN R NCP134_BIAS
5032 0 27 DDIO_GPIO0
V ND_GPIO0
G 48
C
0201 DNP DNP 1u 50104 166 DDIO_GPIO1
V ND_IO_GPIO1
G 156
C C
50134 50105 DDIO_GPIO2
V ND_IO_GPIO2
G
ALL C
1u 0.1u 50106 7 17
C R P
10V 0.1u 50107 5072 DDIO_XTAL
V ND_XTAL
G lace all caps close to pins
ALL
DNP DNP 0201 + 0.1u 0 120
C C U 1P1V_WLAN_DVDD ALL C
50135 50136 5007 DNP 2 0.1u ALL 50108 40 DD11_LO_0
V 168
ALL
1u 0.1u BIAS 1u DD11_LO_1
V ND_BT_LO
G
ALL
10V 16V 4 1 1 151 141
0201 0201 IN OUT P1V_WLAN_AVDD DD11_WL_2GPA_0
V ND_WL_2GPA2_0
G
ALL 71 61
3
NCP134_EN 5 DD11_WL_2GPA_1
V ND_WL_2GPA2_1
G
EN MPAD 121 142
DNP 41 DD11_WL_LNA_0
V ND_WL_BT_2GLNA_0
G 62
C C
NCP134AMX110TCG 50133 50109 DD11_WL_LNA_1
V ND_WL_BT_2GLNA_1
G
DNP 10u 70 69
R C
5034 6.3V 0.1u 50110 DD11_WL_SYNTH
V ND_WL_SYNTH
G
0 0402 119 129
ALL C
0201 0.1u 50111 39 DD11_WL_ADDAC_0
V ND_WL_ADDAC_0
G 49
ALL C
DD11_WL_ADDAC_1
V ND_WL_ADDAC_1
G
2.2u 50112 98 109
C
50113 59 DD11_WL_BB_0
V ND_WL_BB_0
G 29
ALL
B 1u DD11_WL_BB_1
V ND_WL_BB_1
G B
0.1u 88
ALL
ALL DD11_WL_VCO
V 148
C 138 ND_BT_RFPLL
G 130
50114 158 DD11_BT_PLL
V ND_ISO_0
G 50
169 DD11_BT_SYNTH
V ND_ISO_1
G 159
1u DD11_BT_ADDAC
V ND_BT_BB
G
170 24
ALL C + DD11_BT_BB
V ND_PCIE
G
50115 1P1V_WLAN_DVDD
25 1
DD11_PCIE
V NDD_1
G 2
1u NDD_2
G
C50116 11
ALL C50117
NDD_3
G 12
23 NDD_4
G 22
1u 33 DD11D_1
V NDD_5
G 32
1u DD11D_2
V NDD_6
G
ALL 35 34
ALL 46 DD11D_3
V NDD_7
G 43
C50118 86 DD11D_4
V NDD_8
G 45
94 DD11D_5
V NDD_9
G 68
0.1u DD11D_6
V NDD_10
G
96 74
104 DD11D_7
V NDD_11
G 77
ALL 105 DD11D_8
V NDD_12
G 84
106 DD11D_9
V NDD_13
G 87
115 DD11D_10
V NDD_14
G 107
117 DD11D_11
V NDD_15
G 116
C50132 125 DD11D_12
V NDD_16
G 128 WIFI_DBG_UART_RXD
126 DD11D_13
V NDD_17
G 136 TP5002
0.1u DD11D_14
V NDD_18
G
+3P3V_WLAN_VCC
ALL WIFI_DBG_UART_TXD
161 100
ALL 80 DD33_WL_2GPA_0
V ND_WL_5GPA2_0
G 20 TP5003
DD33_WL_2GPA_1
V ND_WL_5GPA2_1
G +3P3V_WLAN_VCC +3P3V_WLAN_VCC
ALL
C50120 90 110
10 DD33_WL_5GPA_0
V ND_WL_5GPA1_0
G 30
DD33_WL_5GPA_1
V ND_WL_5GPA1_1
G
0.1u
C50119 89 122 R5057 R5056
ALL 9 DD33_WL_5GPADRV_0
V ND_WL_5GLNA_0
G 42
DD33_WL_5GPADRV_1
V ND_WL_5GLNA_1
G 10k 10k
1u ALL DNP
108 99
ALL C50121 28 DD33_BB_0
V ND_TPC_0
G 19 U5001A
C50123 DD33_BB_1
V ND_TPC_1
G WIFI_RST# 145 112
79 38 WIFI_WAKE#_R 146 CIE_RST_L
P PIO_0
G 63
1u DD33_WL_SYNTH
V ND_PLL
G CIE_WAKE_L
P PIO_1
G
WIFI_PCIECLK_REQ#_R 114 53 BT_UART_WAKE
0.1u CIE_CLKREQ_L
P PIO_2
G
ALL C50122 171 172 52
ALL DD33_BT_PA
V ND_BT_PA
G PCIECLK_WIFI_DP R5058 PCIECLK_WIFI_DP_R 4 PIO_3
G 72
C50124 ALL 0
C50125 C50126 PCIECLK_WIFI_DN R5059 PCIECLK_WIFI_DN_R 14 CIE_REFCLKP
P PIO_4
G 82 WIFI_DBG_UART_RXD
0.1u QCA-6174A-5-172BWLNSP-TR-0C-0 0 CIE_REFCLKN
P PIO_5
G 92 WIFI_DBG_UART_TXD
2.2u ALL GND ALL PIO_6
G
ALL PCIE_WIFI_RX0_DP_C 5 102
0.1u 4.7u CIE_TXP
P PIO_7
G
ALL PCIE_WIFI_RX0_DN_C 15 113
ALL ALL CIE_TXN
P PIO_8
G 91
PCIE_WIFI_TX0_DP_C 13 PIO_9
G 73
PCIE_WIFI_TX0_DN_C 3 CIE_RXP
P PIO_10
G
CIE_RXN
P 85 BT_SIN_R
WL_XTALI 8 PIO_25
G 55 BT_DOUT_R
C5068 C5069 WL_XTALO 18 TALI
X PIO_26
G 56 BT_SYNC_R
R5060
0.01u 0.01u Y50 6 TALO
X PIO_27
G 66 BT_BCLK_R
1
100K 48MHz LK_OUT PIO_28
DNP DNP 4 2 167 C G 37 BT_UART_TX
83 2KHZ_CLK_IN
3 PIO_29
G 47 BT_UART_RX
36 LK_REQ_IN
C PIO_30
G 16 BT_UART_CTS
3
ALL LK_REQ_OUT
C PIO_31
G 26 BT_UART_RTS
A ALL 76 PIO_32
G A
J5001 67 TE_SYNC
L 75
DNP TE_ACTIVE T_WAKEUP_SLAVE
32KHz_CLK_IN 95 L B
65 TE_PRI
L 155
CONN_COAX_4_2P1X2X1P0MM
TP5013 PROBE 57 PS_COEX
G T_WAKEUP_HOST
B
BOT_COAX_NET 1 2 103 D_FRAME_SYNC
3 154
IN OUT L_EN
W T_USB_DP
B USB2_BT_DP_QC [50]
+3P3V_WLAN_VCC 93 165
+3P3V_WLAN_VCC T_EN
B T_USB_DN
B USB2_BT_DN_QC [50]
0402 Single Pad 4 3 127
GND4 GND3 137 LAN_RF_KILL_L
W
157 T_RF_KILL_L
B
147 LAN_LED
W
X867338-001 R5062 T_LED
B
R5063 135
100K 100K OW Q
J5001 added for bottom side study
ALL ALL QCA-6174A-5-172BWLNSP-TR-0C-0
WL_EN BT_EN ALL
C5070
C5071
0.01u
ALL 0.01u
ALL
5 4 3 2
5 4 3 2 1
D D
C C
B
5 4 3 2
5 4 3 2 1
D D
C C
B
5 4 3 2
5 4 3 2 1
D D
C C
B
P lace close to pin 23,25
A A
5 4 3 2
5 4 3 2 1
Sensor Connector to IR and RGB Cameras, Left and Right Microphones, and ALS Sensor +
1P8VSB
VSYS 5410 0.01u

5411 + 5407 220 OHM C 25V
ALL C0.1u 10V L 0201S_P33
5404 2A AM_IR_LED_IN
[54,76] AM_IR_STB U
74AUP1G08GX 0805S_1P1 C
C
5 5416 5409
5406 CC C 16V
10u C 16V
0.1u 5403 5401 4.7uH100KHz
R 2 V 4 R_BST 6 U R_SW L
137K 0603S_1-W 1000201S_P33 1 1.5A
1 A Y I ST W I RLED_A_P [54,76]
DNP 3 IND_2P5X2X1_1P9MM I
B ND B S R_FB
ND ND 2 4
G N B I
G G I F
AM_IR_STB_VDIV 0 AM_IR_STB_1.8V 5410 2.05K AM_IR_STB_R 3 5
C C R C N ND 7 DNP
201S_P33
1K
IO_DSN2_1P45XP65XP31
402S_P7-W70
0201S_P28-W35
E G
PAD
5409 5414 5408 5419
49.9K
0201S_P28-W35
R E
K
D DNP 5402 MP2370DG-Z 5403 C
0.01u C
4.7uF C10p D
D AM_IR_STB_R [76] D
RB520CS3002L 000mA 10V 10V 0201S_P33
150K
C
1/20W
1
0
5407 ND SR10F30NXT5G
30V 50V
0201S_P26
5401
R
165K 3P3V G N ND ND ND
5413
0
+
R
DNP G G G
A
ND
R
ND G
ND G
5425
201S_P33-W39
5402 G
220K
201S_P28-W35
NP
C
R
0.1u
D
10V 5420 100K R_FB_R 5419 1K
R I R0201S_P28-W35 RLED_C_N [54,76]
ND 5401 5415 0201S_P28-W35 I
G U
TLV3011 0R 5408
ND
G 0201S_P28-W35 5418 5423 R
0.25
201S_P33
5421
AM_IR_STB_ERR_INM 4 SC70-6_2X1P25X1P1_P65MM-2 C R
0
6 220p 7.5K 1206S_P7
0 DNP
C N- +
R
I V 25V 0201S_P3-W35
5426 4.99K 5 1 AM_IR_STB_ERR 0.5W
R CAM_IR_STB_ERR_REF EF UT C
0201S_P28-W35 R O ND
AM_IR_STB_ERR_INP 3 2 ND ND G
C N+ - G G
I V
6.3V
0201S_P35-W35
ND
G
5405 1u
10K
0201S_P28-W35
DNP
5414
C
3P3VSB
+
R
5402 ND ND
U G G
A2 A1 3P3V_CAM_OUT
IN OUT +
V V
[22,76] TD3_CAM_PWREN 5402 0 B2 B1 5406

R R N ND C ayout Note: J54001 Pin 1 and Odd Pins along North Edge
E G L
5404 0.1u 5404 Place close to pin 23
C 5436 0 NX3P1108UK L .3A
1u [35] PIO5_26_LCK# R ND 1 P3_CAM [76]
G G 120 Ohm 100MHz 402 3
0 5407 5413
DNP
ND C 6.3V
0.1u C 6.3V
10u
G ND
G 0201 0402 5401
J
AM_IR_STB
[54,76] AM_IR_STB C 2 1 EN_HALL_INT#_S [34,76]
5402 C 4 2 1 3 S
RLED_C_N [54,76]
C AM_USB_DP C
[24] AM_USB_DP_SOC L CAM_USB_DM 4 3 I
C 2 1 6 5 HIMERA_DET_CON_A#
0nH 2.5GHZ C 6 5 C 5416 0
[24] AM_USB_DM_SOC 108 80 7
7 R HIMERA_DET_A# [58]
C
C 3 4 [54,76] RLED_A_P 12 9
11
I 5403 12
lace C 6.3V
0.1u 14 19 13
P 14 13
1P8VA C54003 near 0201 16 1 1 15
3 2 + connector 6 5
18 1 1 17
4 1 8 7 MIC1_SDA_DSP [43,76]
K1
K1
0 DNP N5401 5401 5404 5401 20 1 1 19 D

R D D C 22 0 9 21 MIC1_SCL_DSP [43,76]
PESD5V0H1BSF 0.1u 2 1 D
[22,54,76] OC_SENSOR_ACS_SDA 24 2 1 23
PESD5V0H1BSF S 2 2 5430 1K
[22,54,76] OC_SENSOR_ACS_SCL 4 3 CHIMERA_23 R SP_FW_LOCK# [20,54]
S 0 CHIMERA_DET_CON_B# 26 2 2 25 5431 0 I
[58] HIMERA_DET_B# 28 6 5 27
CHIMERA_25 R CS_INT# [22,54]
C 5412 2 2 CHIMERA_27 5432 0 A
R 30 8 7 29 R DNP DM_DET [35]
2 2 T
[34,76] EN_HALL_INT#_N 0 9 GB_LED_EN [54]
K2
K2
S 3 2 R
ND 5VSB
G + 5401B
Q DF40C-30DS-0.4V
4 3 5417 3.48K
R GB_LED_A_P [76]
0402 R
5418
R
10K
0201 1P8VSB 3P3VSB
+ +
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5
ND
G
1P8VSB ND 5434 5405

+ R R
Q5401A G 100K ALL 100K
0201 0201
6
[22,54] ACS_INT# [20,54] SP_FW_LOCK#

I
[54] RGB_LED_EN 2
R5428 R5429
100K 100K
0201 0201 R5411
1
DNP DNP DNP 100K

0201
GND
[22,54,76] SOC_SENSOR_ACS_SDA
[22,54,76] SOC_SENSOR_ACS_SCL
B B
ND
G
+1P8VSB
+1P8VSB
R5439
10K ALL
R5435
100K DNP
G
[30,35,57] S D
GPIO5_24_LCK#
Option for SAM GPIO ALL
lock flashing function
Q5402
A A
5 4 3 2
5 4 3 2 1
+V_ALWAYS_ON
Iin=0.28A
+VSYS
Trace Width>30mil +V_ALWAYS_ON
D5502 DBG_S
40V
A K R5521 0.02 +V_ALWAYS_ON
0603S_P6-W100
RB520CS3002L C5506
0.1uF 25V
0201S_P35-W35
D D
Effective Capacitance
2.2uF_0.55mm => @15V=0.255uF
GND 2.2uF_0.55mm => @20V=0.194uF
22 uF_1.45mm => @20V =2.566uF
+3P3VAS
100K
C5507 Imax<=0.175A
R5501
+3P3VAS
PWR_SL1_F 10u TP5501
Q5505 25V IND,PMC,6.8uH,330mOhm,1.2A,SM,3.2X2.5X1.
TRA-P CNL,SM,DFN1010D-3,120 mOHM,30 V,2. 0805S_1P2 L5501 6.8uH DBG_S
D5507 D2 +3P3VAS_SW
40V GND R5512 0.1
A K PWR_SL1_F_S S D1 U5501 0603S_P65-W95
S
2 9 C5512 C5505 C5508
D
R5517 SOTFL4_1P1X1XP4_P75MM DNP VIN1 SW 1u 22u 10V 22u 10V PMTP5503 PMTP5504
G
RB520CS3002L100K 1
C5510 R5532 25V 0603S_1-W100 0603S_1-W100 SP-TP-C0P381 SP-TP-C0P381
MODE
G
0201S_P28-W35 0.01u 25V 1K 10+3P3VAS_BST C5513 R5514
4 BST 1M
0201S_P33 EN 5.6p GND GND
PWR_SL1_F_S_DRI 6 14+3P3VAS_FB 25V
MODE PG FB
FLOAT PFM/PWM 7
BIAS
R5516 PU PWM INT_LDO_5VCC 11
VCC
R5510
200K 324K
0201S_P3 5 15 +3P3VAS_FREQ
NC FRQ
3
Q5506A
C 10V C5520 12 13 +3P3VAS_SS C
AGND SS
6
5 8 R5515
20% 1u 3 PGND-8 C5521 165K
[70] SL1_PWR_GOOD PGND-3
4
2
DNP MP2269GD-Z 12n
fs = 86500/(R+6.5)
1
R5518 C5509 Q5506B

249K
DNP
0.1u 10V
0201S_P33-W39
GND 500KHz R5507
3P3VA_GND 3P3VA_GND GND 3P3VA_GND 3P3VA_GND 3P3VA_GND 2 1
GND
0201 SHUNT
+VBUS_P0_CONN GND
GND
A
D5504
40V
K
teknisi indonesia +3P3VAS +3P3VAS
3P3VA_GND GND
+1P8VA
RB520CS3002L
R5529
100K U5505 DBG_S
0201S_P28-W35 4 1 1P8VA_REG R5520 0.1
IN
V OUT
V
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DNP 0603S_P65-W95
3
[58] 3P3VA_EN N
E
2 5 C5518 +1P8VA
ND E
G PAD
C5501 C5502 NCP170AMX180TCG
10u 10V Imax=0.08A
0603S_1-W100
B 0.1u 10V 1u 6.3V GND B
0201S_P33-W39 0201S_P35-W35 GND
GND
+3P3VAS GND GND +3P3VA
U5506
+V3P3VAS_BATLDO A2 A1 +3P3VA_REG R5505 0.1
D5501 IN
V OUT
V
[70] BAT_LDO A K DBG_S

3P3VA_EN R5506 0 B2 B1 C5504 PTP5502 PTP5501
N
E ND
G
C5503
RB520CS3002L 0.1u
200mA
1u NX3P1108UK
GND
+3P3VA
+3P3VAS +VCC_RTC
+3P3VAS +3P3VAS
Imax=0.01A
+1P8VAS
GND GND
U5503
D5503
R5530 U5502
A K 4 1 +VCC_RTC_LSW R5502 1.5K 100K DBG_S
VIN VOUT 0201S_P28-W35 0201S_P28-W35 4 1 1P8VAS_REG R5533 0.1
3 IN
V OUT
V 0603S_P65-W95
C5515
0201S_P33-W39
RB520CS3002L C5511 EN 1u 6.3V R5522 3

0.1u 2 5 0201S_P35-W35 200K N
E
C5514
10V 1u 6.3V GND EPAD 0201S_P3 2 5 C5524 +1P8VAS
DNP 0201S_P35-W35 NCP170AMX180TCG DNP +VCC_RTC ND
G PAD
E 10u 10V Imax=???A
GND GND Imax=0.0002A C5523
0.1u 10V
C5522
1u 6.3V GND
NCP170AMX180TCG 0603S_1-W100
D
A GND A
GND GND GND 0201S_P33-W39 0201S_P35-W35 GND
R5503 499 VCCRTC_RST_R G Q5501
[35] VCCRTC_RST
DNP GND
DNP GND GND
R5504
S
DNP 100K
0201S_P28-W35 SOTFL-3_1P3XP9XP55_P4
GND GND
5 4 3 2
5 4 3 2 1
D D
C C
B
5 4 3
5 4 3 2 1
[22,33,57] R5709 0 EDP_I2C_SDA

PANEL_I2C_SDA 0201S_P28-W35
[22,33,57] R5710 0 EDP_I2C_SCL
PANEL_I2C_SCL 0201S_P28-W35
0201S_P33-W39
0201S_P33-W39
10V
10V
5725 0.1u
5724 0.1u
DNP
DNP
+3P3V_PANEL +1P8V_PANEL
B2 U5705 B1
IN OUT
C
V V
A2 A1
N ND GND GND
C5728 C5729 E G C5727 R5729
D 0.1u 1u LD39115J18R_1p8V 1u 10K [30] D
6.3V 6.3V 6.3V DNP EDP_SPI_MISO +3P3V_PANEL +3P3V_PANEL
X867741-001 GND [30] EDP_SPI_CLK
GND GND ALL 5701

J
[58] EDP_FPC_DET_B#
GND GND 4 0 1 RN5702A
3 0 2 RN5702B P5704
T FG_SDA
M 1 2 FG_SCL
M P5705
T
ALL 3 1 2 4
0201S_P33-W39 M57L3 3 4
2 3 [76] DP_I2C_SDA 5 6
EDP_TX3_DN_C E 5 6
[10] EDP_TX3_DN M57C3 0.1u 10V 7 8
10
7 08
1 4 119 9 1 12
M57C4 0.1u 10V EDP_TX3_DP_C DNP 0 DP_FPC_CONN_DET_B#
E 13 1 2 14 P5701
T
[10] EDP_TX3_DP 1 1
0201S_P33-W39 5704
R 15 3 4 16
1 1 DP_I2C_SCL [76]
E
+VCC_EDP_BKLT_OUT 17 5 6 18
ALL 1 1 EPROM_RESET_N P
D TP5701 DP_I2C_INT
E [22,76]
19 7 8 20
4 0 1 RN5703A 1
9 1
0 EPROM_TWP
D TP5702
P
21 1 2 22 EPROM_I2C_SDA
3 0 2 RN5703B 23 1 2 24 D TP5703
P
C5705 C5711 C5707 ALL 2
3 2
4 0
M57L4 25 26 CON_VENDOR_ID [20,76]
0805S_1P45
0.47u 50V 0.1u 35V 0.1u 35V 0201S_P33-W39 DP_TXN3_R
E 2 2 EPROM_I2C_SCL
D TP5704 5711 T
2 3 27 5 6 28 P R
0805S_1P45
0805S_1P45 0201S_P33 0201S_P33 M57C7 0.1u 10V EDP_TX2_DN_C DNP DP_TXP3_R
E 2
7 2
8 DNP
[10] EDP_TX2_DN 29 30
2.2u 50V
C5706
1 4 2
9 2
0
31 32 DP_HPD [10]
2.2u 50V
C5719
EDP_TX2_DP_C DP_TXN2_R 2 3 E
GND [10] EDP_TX2_DP M57C8 0.1u 10V E 33 1 2 34
0201S_P33-W39 4 0ALL 1 RN5704A DP_TXP2_R
E 3
3 3
4 ANEL_BIST
P P5712
T
GND GND 35 36
3 0 2 RN5704B 3
5 3
6
DP_TXN1_R 37 3 3 38 ANEL_LOGO [35]
P
ALL E 7 8 DP_SPI_CS# [30] P5713
T
M57L5 DP_TXP1_R 39 3 3 40 ANEL_VSYNCH E
GND GND 0201S_P33-W39 2 3 E 9 0 P
41 3 4 42 A
PNEL_VSYNCH [30]
M57C9 0.1u 10V EDP_TX1_DN_C 1 2 DP_SPI_INT# [30]
[10] EDP_TX1_DN DP_TXN0_R 43 4 4 44 DP_AUXP_R E
1 4 E 3 4 E
45 4 4 46
M57C10 0.1u 10V EDP_TX1_DP_C DNP DP_TXP0_R
E 5 6 DP_AUXN_R
E
[10] EDP_TX1_DP 47 4 4 48 DP_FPC_CONN_DET_A#
0201S_P33-W39 7 8 E 5703
R 0
49 4 4 50 D
EP_FPC_DET_A# [58]
[72,76] KLT_FB8 51 9 0 52 KLT_FB7 [72,76]
ALL B 4 5 B
[72,76] KLT_FB6 53 1 2 54 KLT_FB5 [72,76]
B 5 5 B +VCC_EDP_BKLT_OUT
4 0 1 RN5701A [72,76] KLT_FB4 55 3 4 56 KLT_FB3 [72,76]
+VCC_EDP_BKLT_OUT B 5 5 B
3 0 2 RN5701B [72,76] KLT_FB2 57 5 6 58 KLT_FB1 [72,76]
ALL B 5 5 B
59 7 8 60
EDP_TX0_DN_C M57L2 5 5
[10] EDP_TX0_DN M57C6 0.1u 10V 2 3 9 0
+3P3V_PANEL +3P3V_PANEL +3P3V_PANEL 5 6
61 62
M57C5 0.1u 10V EDP_TX0_DP_C 1 4 T1 T2
C [10] EDP_TX0_DP 63 M M 64 ANEL_LOGO C
DNP T3 T4 P P
T5702
C5704 C5702 C5712 M M
0.47u 6.3V 1u 6.3V 0.1u 10V
0201S_P33 0201S_P35-W35 0201S_P33-W39 ALL
N5705A
R 1 0 4 EDP_AUX_DP_C
N5705B
R 2 0 3 EDP_AUX_DN_C
GND GND GND ND

G ND
G ALL 0201S_P33-W39
5701
L
ALL C5708 5709
C ALL 3 4 10V 0.1u 57C1
M D
EP_AUX_DP [10]
0.1u 0.1u
2 1 10V 0.1u 57C2
M D
EP_AUX_DN [10]
10V 10V DNP 0201S_P33-W39
[22,33,57] PANEL_I2C_SCL 0uH
GND ND
G
ANEL_BIST
P
5716
R
100K
U5701
3 6 DEPROM_I2C_SCL
4 CL1 CL2 5
S S DEPROM_I2C_SDA
1.8V logic 2
S
DA1
S
DA2
7
ND
G
REF1 REF2
+1P8V_PANEL V V
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1 8 U5701_EN_1.8_R
ND N R5721 0
G E GPIO5_24_LCK# [30,35,54,57]
PCA9306DQER ALL
X867878-001 EPROM_RESET_N_R
D 5702 DNP
R 0 EPROM_RESET_N
D
C5703
C5701 0.1u
REMOVE 0ohm to avoid resetting tcon durign programming
D
GND
0.1u 6.3V 5702
Q
6.3V R5712 G
B [22,33,57] PANEL_I2C_SDA B
0 DNP
GND
S
GND
R5725 0 DEPROM_PROG_R ND
G
[20] DEPROM_PROG
DNP
EPROM_TWP
D
R5713 0
D
[30,35,54,57] GPIO5_24_LCK# 5701
3.3V logic R5706
137K
Option for SAM GPIO ALL G
Q
lock flashing function
S
U5701_EN_1.8
R5701
165K ND
G
GND
Vinafix.com
The SCL switch conducts if EN is = 1 V higher than SCL1
The SDA switch conducts if EN is = 1 V higher than SDA1
A VIO(Max) = 5V A
200K PU not needed when VREF1 = VREF2
If EN > Vref1+0.7V => device will NOT properly isolate the two sides when both sides are high
5 4 3 2
5 4 3 2 1
+ 1P8VAS + 1P8VAS
+ 1P8VAS
R 5825 R 5850
1M 1M
0201 0201 U 5806 + 1P8VAS
5 C 5806
1% 1% CC 0.1u
2 V 4 10V + 1P8VAS
[54] C HIMERA_DET_A# A Y U 5807
[54] C HIMERA_DET_B# 1 ALL C 5807
B 3 5
ND CC 0.1u
+ 1P8VAS + 1P8VAS G CHIMERA_DET_AB# 2 V 4 10V + 1P8VAS
D 74LVC1G32GX 1 A Y ALL + 1P8VAS + 1P8VAS D
B 3
ALL ND C 5813
G 0.1u
R 5817 R 5822 + 1P8VAS
CHIMERA_KIP_DET_AB#
74LVC1G32GX 10V C 5804
1M 1M ALL U5803 is BYPASS IN CASE WE WANT OD
ALL R 5832 C 5812 0.1u 10V
0201 0201 U 5811 100K 0.1u10V DNP
1% 1% U 5808 U 5812
5 C 5809 5 G ND U 5810 5
CC 0.1u + 1P8VAS CC 74AUP1G08GX CC
V V 5 V
[74] K IP_FPC_DET_A# 2 4 10V 2 R 5829 CC
1 A Y ALL A 4 FPC_DET 150K FPC_DET_R 2 V 4 3P3VA_EN_AND 2 4
[74] K IP_FPC_DET_B# B 3 U 5805 Y A Y I O
ND 5 C 5805 1 3
ALL 1 3 1
+ 1P8VAS+ 1P8VAS G KIP_FPC_DET_AB# CC 0.1u B ND B ND C1
V G G N 3
74LVC1G32GX 2 4 10V + 1P8VAS C 5850 ND
1 A Y ALL 2.2u
G
ALL 3 74AUP1G86GX
+ 1P8VAS B ND
R 5826 R 5851 G 74AUP1G07GX
1M 1M M1116379-001
74LVC1G32GX CHIM_KIP_EDP_DET R 5828 DNP
0201 0201 U 5809 G ND
5 C 5811 ALL 100K
1% 1% CC 0.1u R 5833 ALL 0 P3VA_EN [55]
V 3
[57] E DP_FPC_DET_A# 2 4 10V
1 A Y ALL
[57] E DP_FPC_DET_B# B 3 [33,76] F PC_DET_LOGIC_OVERRIDE#
ND 3 P3VA_EN_SILEGO R 5818 0201 0
G EDP_FPC_DET_AB# In RAFLA this Signal will be pulled "LOW" via 1K resistor DNP
74LVC1G32GX R 5834 R5818 IS BYPASS for 3P3VA_EN_SILEGO
ALL DNP 0
0402
For FRU or FA on the bench 0402 pads
placed at the edge of the board.
G ND
C C
R 5809 0201 0 PIN17=PIN2*PIN12*PIN3*PIN6

T P5806
SP_TP_SMDP58
+ 3P3VAS + V3P3VAS_BATLDO
[35,58,60,61,62,65] S LP_S3_DRV# Silego Controller

R 5810 R 5813
0 0
DNP
ALL
R 5831 + 3P3VAS_SIL
100K
T P5807
U 5803 + 3P3VSB SP_TP_SMDP58 C 5802
74AUP1G08GX 0.1u 10V
5 0201 SP_TP_SMDP58 P5816
T
2 V CC 4 T P5811 SP_TP_SMDP58 SP_TP_SMDP58 T P5812
[34,58,66] V RM_PWRGD
1 A Y
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[60,76] + 1P2V_DDR_PG T P5810 SP_TP_SMDP58 SP_TP_SMDP58 T P5813
B 3 SP_TP_SMDP58 T P5814
G ND C 5814
[76] D DR_PGD_SIL
T P5804 SP_TP_SMDP58 SP_TP_SMDP58 T P5815
0.1u U 5801
10V T P5803 SP_TP_SMDP58
S IL_SLP_S3_DRV# 1 2 1
S PL_3_DRV V DD
B R 5811 0201 0 S US_PGD_SIL 2 B
[34,61,62] A LLVSB_PG S US_PGD 17 S YS_PWGD_SIL R 5804 0201 0
V CORE_EN A LL_SYS_PWRGD [22]
V RM_PGD_SIL 10 B AT_SHUTDOWN# [33,70,76]
R 5808 0201 0
[34,58,66] V RM_PWRGD V RM_PGD 4 B AT_SHUTDOWN_SIL 1K 0201R 5812 SP_TP_SMDP58 T P5808
R 5821 0201 0 D DR_PGD_SIL 3 B AT_SHUTDOWN
D DR_PGD
R 5805 0201 0 S LP_3#_SIL 6 1 6 S AM_RST#_SIL R 5824 0201 0
[22,33,34] S LP_S3# S LP_3 F ORCE_OFF S AM_RESET# [29,33,34,76]
R 5806 0201 0 H _THERMTRIP#_SIL 2 0 SP_TP_SMDP58 T P5817
[10] H _THERMTRIP# T HERMTRIP 18S TART_ONESHOT_SILR 5801 0201 0
R 5803 0201 0 P LT_RST#_SIL 1 9 S TART_ONESHOT B ATEN_PULSE [34,70]
[22] P LTRST# P LT_RST 13 3 P3VA_EN_SILEGO
S LG_PWRBTN# 1 4 M CU_PWR_CTRL
S TART 15 S AM_DBG_MODE_R R 5823 0201 0
R 5844 0201 0 D ET_A#_SIL 5 S _DBG-MCU_DBG S AM_DBG_MODE [29]
[44] D ET_A# D ET_A 9 S SD_LS_EN_SIL R 5820 0201 0
R 5845 0201 0 D ET_B#_SIL 8 S SD_LS_EN S IL_SSD_VR_EN [65]
+ V3P3VAS_BATLDO + 3P3VAS
[44] D ET_B# D ET_B DNP R 5840
D EVICE_RST#_SIL 7 11 100K
T P5805 R ST G ND 0201
R 5841 R 5842 SLG4U42544 DNP
ALL DNP 100K 100K
R 5815 R 5827 SP_TP_SMDP58 0201 0201 M1092739-003
10K 10K DNP DNP G ND R 5843
0201 0201 + 3P3VSB 100K
R 5819 0201
100 DNP
0201
R 5807
S LG_PWRBTN# [76] B oth of these BOM install options 100K
ALL keep SSD ON during modern stdby 0201
C 5810 DNP
0.1u + V3P3VAS_BATLDO R 5837 R 5849 0
[35,60]S LP_S4_DRV#
A 0 DNP R 5814 0201 0 A
C 5808 10V 0201 DNP
0.1u 10V ALL
0201
D 5801
[35,58,60,61,62,65] S LP_S3_DRV# R 5852 0
K A 1M 1M
[31] PWRBTN#_3V3 ALL
R 5847 R 5846 [39] D EVICE_RST#
RB520CS3002L
200mA DNP DNP
5 4 3 2
5 4 3 2 1
M_5VSB_IN+ [28]
P
M_5VSB_IN- [28]
P
10u 5951
C
DBG_T
5947 0
R 47 5948
DBG_T RDBG_T +VSYS
Iin=7.75A
+
VSYS Trace Width>450mil
5VSB_VIN
D DBG_TS + D
0.005 5910
R
5930 5922 5921
MTP5913 MTP5914 C 16V
10u C 16V
10u C 16V
0.1u
P P
5932 ND ND ND
R G G G
0
5920 5VSB
DNP 5904 5909 C
0.22u +
5901 0 5VSB_EN_R U R
2.2 25V IND,PMC,1.5uH,20mOhm,8A TYP,SM,7.1X6.6X2
[35] 5VSB_EN R + 5904
+ 1 V B ST 10 L 7.1X6.6X2.4
ALL IN 5VSB_SW
+
16 M S W 9
ODE2 5VSB_FB 1.5uH
+
14 M F B 13
5908 0 B_PWR_ON 5907 0 ODE1 US_PWRGD_5VSB 274K
S
[35,62]
V
SUS_ON R R 15 E P G 12S 5929 1% 5946 220p
N R C 50V
DNP
3 V3 3 DNP 5926 5927 5923 5924 5925 5950 5911
or NB502 5928 5912 C
10p C
0.1u C
47u C
47u C
47u C
47u R
100K
5906 5919 F 11 C 2 R
499 R
18.7K 50V 10V 6.3V 6.3V 6.3V DNP
R 10K C LM P GND_1 6.3V
DNP
0.1u
10V
5933
R0 P GND_2
4
5
1% DNP 5.1V 0201
P GND_3
5927 P 6
5931 R0 8 N GND_4 7
R C P GND_5
232K NB502 ND
ND ND DNP ND ND ND ND ND ND ND G
G G G 5913 G G G G G G
R
10.2K
1%
ND ND ND
G G G
M_3P3VSB_IN+ [28]
P
C C
M_3P3VSB_IN- [28] ND
P CLM MODE1 MODE1 G
US_PWRGD_5VSB [34]
10u 5952 0 7 A 700 kHz < 3 V S
C 90k 10 A 1 MHz < 3 V 3P3VA 1P8VA
150K 13 A 1 MHz >= 3 V + +
DBG_T 3P3VSB
230k or floating 16.5 A 700 kHz >= 3 V +
5949 DNP
R 0 5953
47 R
DBG_T 5950 5905 10K
R R 5905
DBG_T 100K U
5
V CC
5957 0 US_PWRGD_3V3
R S 2 4 US_PWRGD [62]
I O S
DNP 5948
1 C
N C1 0.1u 10V
VSYS
+
3P3VSB_VIN +VSYS 5931
C
1u
5901
C
1u
5954
R G ND
74AUP1G07GX
3
1M
+
Iin=5 A 10V 10V DNP DNP
0.01 5917
Trace Width>250mil
R
ND ND ALL
DBG_TS 5933 5934 5932 G G 5956 0
C C C R
10u 16V 10u 16V 0.1u 16V
0201
MTP5904 MTP5903
P P
ND
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ND ND G
G G
5902
U
2.2 25V
5916 C5935 0.22u 3P3VSB
8 7R +
V CC B ST
IND,PMC,2.2uH,35mOhm,7A,SM,6.6X7X1.8
B B
C5903 L5902
C5902 1u
1 6 +3P3VSB_PHASE1_S
1u 10V V IN S W
10V 0201 2.2uH
R5938 C5937 C5936 C5909 5910

C 5911
C 5912
C 5903
R
C5947 220p 10p 50V 0.1u 10V 47u 6.3V 47u 6.3V 47u 6.3V 47u 6.3V 100K
For NB502 50V DNP 0201
422K 1% DNP
DNP
ND
G
SB_PWR_ON 11 GND GND ND
G ND
G ND
G ND
G
E N
2 R5937
P GND_1 499 R5940
3
P GND_2 1% 200K
4
P GND_3 1%
SUS_PWRGD_3V3 5
P G GND
10
F B
R5939
43.2K
1%
A A
GND
9
A GND
NB691GG-Z
GND
5 4 3 2
5 4 3 2 1
D D
[28] M_1P2V_DDR_VDDQ_IN-
P
[28] M_1P2V_DDR_VDDQ_IN+
P
10u 6001
C
DBG_T
6006
R
47 0
DBG_T
6007
VSYS RDBG_T 1P2V_VDDQ_VIN
+ +
DBG_TS
0.02 6016
R
MTP6009 MTP6010 6018 6017

P P C C 6019
10u 10u
C
0.1uF
ND ND ND
G G G
3P3VSB
+
+1P2V_DUAL
6003 5.1
R Imax = 11.52A for 16GB (eight 16Gb x16 DDR4 DRAMs)
+
3P3VSB
TDC= UPDATE
6001
U 6002 0 1P2V_DUAL_BOOT_R 1P2V_DUAL
R + +
6015 6007 1 10 1P2V_DUAL_BOOT
R C IN ST +
100K V B 6006 6001
1u 1P2V_DUAL_3V33 C L
0.47uH
+ V3 0.1u
3 9 +1P2V_DUAL_PHASE 1P2V_DUAL_REG
+
W
S
C 4 C
GND 13 +1P2V_DUAL_FB
P2DUAL_GND A
Low power mode for Connected Stanby
[58,76] 1P2V_DDR_PG
1 12 B
F 6013 6009
+ G 6 6015 R 6021 C 6027 6014 6012
P DDQ C 40.2K C C C C
6024 0 TT_EN 16 V 220p 10p 0.1u 47uF 47uF 47uF
[35,58,61,62,65] LP_S3_DRV# R V N1
S E 5 6026 DNP 1M
15 TT R
V
N2 8 6011
E R
11 TTS 499
V
TW # 7
O ND ND ND ND ND
14 TTREF G G G G G
V
ODE
GND
M
P
NB685A VDDQ_VREF
+ +V_VDDQ_VTT
6014
+1P2V_DUAL_MD
R Imax= 0.70A for 16GB (eight 16Gb x16 DDR4 DRAMs)
2
40.2K
Trace Width>40mil
ND 6016 V_VDDQ_VTT
G C +
0.22u
6025 0 1P2V_DUAL_EN ND
[35,58,60] LP_S4_DRV# R + G
S 6001 TTSNS_VDDQ_VTT_REG 6010 DBG_S0.005
R V R
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0
MTP6002
P
6010 ND MTP6004
C G P
0.01u DNP DNP DNP
C6023 C6024 6025
C 6005
C 6008
C
10u 10u 10u 10u 10u
GND
GND
GND GND ND
G ND
G ND
G
PJP6002
2 1
0201 SHUNT
B B
GND 1P2DUAL_GND
+3P3VSB +2P5VPP
Imax=0.12A
U6002 +2P5VPP
A A
4 1 2P5V_REG R6036 DBG_S 0.005
N
I OUT 0603S_P75-W100
5 PMTP6015 PMTP6016
R6038 0 VPP_EN 3 MPAD 2 C6002 SP-TP-C0P381 SP-TP-C0P381
[35,58,60] SLP_S4_DRV# 0201S_P28-W35 EN GND 1u 6.3V
C6003 C6004 0201S_P35-W35
0.1u 10V 1u 6.3V NCV8177AMX250TCG
0201S_P33-W39 0201S_P35-W35 GND
GND
GND GND
5 4 3 2
5 4 3 2 1
P M_VDDP_IN+ [28]
P M_VDDP_IN- [28]
C 6104 10u
U 6101
R 6112 +VSYS
DBG_T
D
47 R 6106 C 6101
8 VCC BST 7 C 6105 0.22u Iin=???? A D
R 6111
0 10u 16V 0201S_P33 Trace Width>100mil
+ VSYS + VDDPSB_VIN 2.2
DBG_T DBG_T 0603S_1-W 100
DBG_TS 0402S_P4
R 6104 0.01 G ND 1 6
VIN SW
C 6103 C 6113 C 6109 +VDDPSB
P MTP6101 P MTP6106 10u 16V 10u 16V 0.1u 16V Imax=6A
SP-TP-C0P381 SP-TP-C0P381 0603S_1-W 100
0603S_1-W100 0201S_P33
G ND G ND G ND
+ VDDPSB
L 6101 IIND_4P2X4P2X2-3
dc=5.8A/Isat=8.7A
+ VDDPSB_SW
11 1uH
[62] VSB_EN EN C 6110 C 6114 C 6111 C 6107
R 6102 10p 50V 47u 47u 0.1u 10V
2 C 6108 220p 0201S_P33 6.3V 6.3V 0201S_P33-W39
PGND_1 + 3P3VSB
PGND_2 3 887K 0402S_P55
PGND_3 4 DNP R 6109 G ND
499
R 6107
teknisi indonesia
C 0402S_P4 C
5 31.6K R 6115 R 6116
+ 3P3VSB PG G ND 0201 100K 100K
1% 0201S_P28-W350201S_P28-W35
DNP
R 6108 V DDP_SENSE_EN
+ VDDPSB_FB
D
100K FB 10
0201S_P28-W35
G
Q 6102
[34,58,62] A LLVSB_PG R 6103 SOTFL-3_1P3XP9XP55_P4
D
60.4K
S
1% + VDDPSB_FB_IN
0201 G
Q 6101 APU_PWR_GOOD [22]
R 6113
S
2 1 V DDPSB_SENSE_EN
G
9 AGND VDDP_VSS_SENSE [10]
NB691GG-Z 0201 SHUNT D S
VDDP_VIN_SENSE [10]
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G ND PUT R6113 CLOSE TO U6101
G
Q 6103
DNP S D
B Q 6104 B
C 6115
100p 25V DNP
PUT R6117 CLOSE TO U6102 0201S_P33
0 R 6114
R 6117
ALL
2 1
+ 5VSB + VDDPSB
0201 SHUNT
+VDDP
U 6102
+ VDDP
Imax=4A
1
VDD
MAKE TRACE AS WIDE AS POSSIBLE
2 5-6
D1 S1
3-4 7
C 6102 C 6112 D2 S2 C 6106
0.1u 10V 1u 6.3V 9 8 1u 6.3V
ON GND
0201S_P33-W39 0201S_P35-W35 0201S_P35-W35
G ND G ND G ND
SLG5NT1477VTR
R 6110 0 ON IS 1.8V LOGIC G ND

[35,58,60,62,65] S LP_S3_DRV#
PUTU6102 CLOSE TO APU
A A
Wx H 402 x 260 mm
5 4 3 2
5 4 3 2 1
PM_1P8VSB_IN+ [28]
PM_1P8VSB_IN- [28]
C6203 10u
U6204
DBG_T
R6218 +VSYS
47 R6220 C6219
8
V CC B ST
7 C6254 0.22u Iin=2 A
R6221
0 10u 16V 0201S_P33 Trace Width>100mil
+VSYS DBG_T DBG_T +1P8VSB_VIN 0603S_1-W 100 2.2
DBG_TS 0402S_P4
R6203 0.01 GND 1 6
D
V IN SW D
C6207 C6208 C6205
PMTP6201 PMTP6202 10u 16V 10u 16V 0.1u 16V
+1P8VSB
SP-TP-C0P381 SP-TP-C0P381 0603S_1-W 100 0603S_1-W 100 0201S_P33 Imax=5.6A
GND GND GND
1+P8VSB
+1P8VA L6201 IND_4P2X4P2X2-3
I dc=5.8A/Isat=8.7A
+1P8VSB_SW
11 1uH
EN C6211 C6255 C6204 C
C6202 6218
DFN5_P85XP85XP4_P48 0.1u 10V R6216 10p 50V 47u 47u 0.1u 10V
U6201 0201S_P33-W 39 2 C6253 220p 0201S_P33 6.3V 6.3V 0201S_P33-W 39
P GND_1 3
74AUP1G08GX 1M 0402S_P55
5 P GND_2 4
2 V CC 4 P GND_3 R6217
[35,59] VSUS_ON G
ND
1 A Y
499
[59] SUS_PWRGD B 3
G ND R6219
0402S_P4
5 43.2K
+3P3VSB PG GND 1%
R6202 0 0201
DNP
R6201
100K 10 +1P8VSB_FB
FB
C 0201S_P28-W 35 C
[61] VSB_EN
[34,58,61] ALLVSB_PG
R6215
20.5K
0201 +P8V_APU
1
R6210 1%
1M 1%
0201 R
6209 0 ALL
0603
9
AGND +5VSB +1P8VSB
NB691GG-Z
+1P8V
U6202
GND
GND
M1023854-001
1 +P8V
1
Imax=2A
V DD
2 5-6 +1P8V_REG R
6208 DNP 0.005
3-4 D1 S1 7 0603
D2 S2
Added individual load switch for S0 APU supply C6206 C6201 C6212
due to internal back leakage from S5 APU supply 0.1u 10V 1u 6.3V 9 8 1u 6.3V P
MTP6205 P
MTP6206
ON G ND
0201S_P33-W 39 0201S_P35-W 35 0201S_P35-W 35 SP-TP-C0P381 SP-TP-C0P381
+1P8V
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+1P8VSB GND GND GND
SLG5NT1477VTR
U6208
A2 A1 R6223 0 R6207 0 ON IS 1.8V LOGIC GND
VIN VOUT [35,58,60,61,62,65] SLP_S3_DRV#
0402 ALL
B B
R6222 0 B2 B1 C6221
[35,58,60,61,62,65] SLP_S3_DRV# EN GND
C6220 0.1u
NX3P1108UK
1u GND
+1P8VSB
GND GND
C6209
+1P8V_AUDIO 1u 6.3V
+1P8VSB 0201S_P35-W 35 U6205 1+P8V_TS
DBG_S NX3P1108UK +
1P8V_TS_REG
R6206 0.05 BGA4_2X2_P98XP98XP59_P5 DBG_TS
0603S_P6-W 105 GND A2 A1 R
6205 0.02
V IN V OUT 0603S_P6-W 100
PMTP6204 PMTP6203
SP-TP-C0P381 SP-TP-C0P381 R6204 0 +1P8V_TS_REG_EN B2 B1 C6210 P
MTP6209
[22,64] RTD3_TPANEL_PW R EN G ND
0201S_P28-W 35 0.1u 10V SP-TP-C0P381
P
+1P8V_AUDIO 0201S_P33-W 39 MTP6210
Imax=0.5A
G
ND SP-TP-C0P381
+1P8V_TS
G
ND Imax=0.455A
A A
5 4 3 2
5 4 3 2 1
3P3VAS
+
W R_SL1_F
P
XT_DC_IN
E
1P8VSB
6343 +
6345 U6301 C
D C A1 B2 10u D
6314 INT1 BUS1
R 10u B1 VINT2 VBUS2 C2
100K 6319 P6301
C1 D2 R
1% VINT3 VBUS3 100K T
D1 VINT4 VBUS4 E1
0201 E2 1%
V VBUS5
B3 V 0201
VLO
O M_VSYS+ [28]
L1_EN_N A3 A2 6327 0 L1_ACK#
S N_N CK S P
R
E A
6313 0 C3
R D3 ND1 10u 6318
GND2 6315 C M_VSYS- [28]
E3 GND3 R P
3
6301 1M
G DBG_T
D Q
NX3008NBKMB 0201
6334 0 AM_SL1_PWR_EN_R X20P5090 1% 6312
[35,79] AM_SL1_PWR_EN R S 1 G N R 0
S L1_EN_N [76] 47
S DBG_T 6311
s 6301_OVLO R
DBG_T
U
6328
2
R
4.7K TP6301
P TP6302 VSYS
P +
6335 6330
R R
71.5K 1 2
1% E E
0201 6302 1 2
Q I I
1
D 1 6304 0.005
R6328 need change back to 100K after SAM PU disable 1 2 Q 6340 6329 6334 DBG_TS
Q 9 1 C 6316 6337 6338 C C
1 D 0.01u C C C + +
2 22u 22u 22u
G1 1 47u 47u
XT_DC_IN 8 9 Q
E
ND ND ND ND
+VSYS: 6V(TBD) to 8.75V

D2S1 5 G1 G G G G
6 8
1(Sense) ND ND
S 7 5 D2S1 G G
Q2
6
1(Sense)
C 7 S C
G2 Q2
3 40
6303 0.01
R 1
S2
1508 AONP36376 G2
6301 04 3
DFN-10 L 1
6304 6301 ND 2.2uH S2
6333 6315 C C G
+ C22u + C22u 6332 6321 6322 6306 0.01u 1000p M1098470-001 AONP36376
C C C R
teknisi indonesia
22u 22u 22u 6308 10 25V 25V ND
R G DFN-10
25V 25V 25V 25V 25V 10 0201
20% 20% 0201
G
ND
G
ND C
6330 M1098470-001 PWR_SL1_F MAX Voltage: 17.2V
ND ND
330p
DNP 6310
PSU_VOLT MAX Voltage: 0.697V
G G C
330p
ND ND ND DNP W R_SL1_F
G G G P
6335 6317
C R
6341 6342 56 6325 6336 M1016334-001
C C R C
A
100p DNP VDD_BATA_PACK 6301
56 + D
0.01u 6305 0.1u 0.01u DNP 180p 6303 RB520CS3002L
C Q
25V 25V FET,P-CH,4.7mOhm,20V,36A,SM 6304 0.01
R
DNP 3
K
5
ND ND ND ND ND 2 1508
G G G G G
,6,7,8
U6302 ND 1 5
0.047u G 6313
D
C
S
HG_BTST1 HG_BTST2 6321
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6302 30 25 6331 0.047u 1u
2
C C TST1 TST2 C C R
G
25V B B 25V JP6303 JP6304 6317 6314 6339 130K
HG_SW1 HG_SW2 P P C C C 6308A
32 23 Q
4
C W1 W2 C 0201 SHUNT 0201 SHUNT 10u 10u 10u
6344 S S DNP DNP
C
1u CHG_LODRV1 29 26 CHG_LODRV2 [35] SU_VOLT 1 6
25V LODRV1 LODRV2 P
1
CHG_HIDRV1 31 24 CHG_HIDRV2 ND
HIDRV1 HIDRV2 G 6309 0.1u 1P8VA 6322
GND C + R
+1P8VA +3P3VA CHG_VBUS 1 22 CHG_VSYS
2
ND
G ND
G ND
G
VBUS VSYS 5.49K
CHG_ACN 2 21 CHG_BATDRV_A
ACN BATDRV
CHG_ACP 3 20 CHG_SRP_A_R R6332 10 HG_SRP_A
C [35] XT_VOLT_ADC_EN
ACP SRP E
CHG_REGN_D 10 R6307 CHG_VCCA 7 19 CHG_SRN_A_R R6318 10 HG_SRN_A
C
R6331 R6333 VDDA SRN 6323
R
3
100K 10K 100K
B B
CHG_ILIM_HIZ 6
LIM_HIZ
28 CHG_REGN_D 5
R6305 C6326 I REGN
HG_VCCA
+1P8VA
4
499K 1u C 6308B
Q
C6307 C6312 ND
G
C6303 1800pCHG_COMP1_R R6320 40.2K CHG_COMP1 16 17 CHG_COMP2 R6302 10K CHG_COMP2_R 680p 2.2u
33p C6306 COMP1 COMP2 C6308 15p 6310 ND
GND R G
R6342 R6343 348K
2K 2K ND
G
GND [10,76] R6329 100 CHG_PROCHOT# 11 18 CHG_CELL_BATPRES GND
H_PROCHOT# PROCHOT CELL_BATPRESZ
13
[35] CHARGER_SCL SCL
12 8 CHG_IADPT VDD_BATA_PACK
+
[35] CHARGER_SDA SDA ADPT
I 6309
R
[34] CHRG_OK
4 9 CHG_IBAT P6302
249K
CHRG_OK BAT
I T
CHG_OTG_EN 5 10 PMON_R R6336 0 PMON
A
OTG/VAP PSYS 6302
D
15 27 ND RB520CS3002L
CMPOUT PGND G
R6301 14 33 C6327 C6319 R6337

CMPIN MPAD VDD_BATA_PACK MAX Voltage: 8.7V
K
R6341 120K 100p 100p 137K C6328
10K
DNP BQ25713RSNR
100p 6340
R
11.3K
BAT_VOLT MAX Voltage: 0.69V
6324
R
6311
Q
63.4K
GND GND GND GND GND
GND [34] AT_VOLT S D
B
GND ND
G
1P8VA
+ 6326
R
G
ILIM_HIZ current limit equation - (VILIM_HIZ – 1 V ) / 40 = ACP - ACN 5.49K
7-bit I2C Address = 0x6B
D
XT_VOLT_ADC_EN
E G 6309
Q
A A
S
ND
G
5 4 3 2
5 4 3 2 1
D D
+5VSB +5V_TS
+5V_TS_REG
U6407 DBG_TS
A2 A1 R6417 0.1
B2 I N_A2 O UT_A1 B1 0603S_P65-W 95
C6415 I N_B2 O UT_B1 C6414
6.3V 1u PMTP6413 PMTP6414
0201S_P35-W 35 C2 C1 6.3V 10u SP-TP-C0P381 SP-TP-C0P381
EN G ND
GND
NCP451AFCT2G 0402S_P7-W 70
+5V_TS
Iin=0.25A
GND GND Trace Width>20mil
R6425 0 +5V_TS_EN
[22,62] RTD3_TPANEL_PW R
C6413
0.1u 10V
0201S_P33-W 39
+5VSB +5V_KIP
GND +5V_KIP_REG
U6403 DBG_TS
A2 A1 0.05 R6412
C B2 I N_A2 O UT_A1 B1 C
0603S_P6-W 105
C6412 I N_B2 O UT_B1 C6417
6.3V 1u PMTP6401 PMTP6402
0201S_P35-W 35 C2 C1 6.3V 10u SP-TP-C0P381 SP-TP-C0P381
EN G ND
GND
NCP451AFCT2G 0402S_P7-W 70
+5V_KIP
Iin=???A
GND GND Trace Width>20mil
R6415 1K KIP_EN KIP_EN [76]
[35] SAM_KBTP_PW R_EN
C6411
0.1u 10V
0201S_P33-W 39
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GND
+5V_AUDIO
+5VSB
DBG_S
R6413 0.05
0603S_P6-W 105
B B
PMTP6410 PMTP6411
SP-TP-C0P381 SP-TP-C0P381
+5V_Audio
Iin=0.66A
Trace Width>20mil
+5VSB
+5V_FAN
C6416
1u 6.3V R6420 0.02
0201S_P35-W 35 U6408 0603S_P6-W 100
A2 A1 +5V_FAN_REG
IN_A2 O UT_A1 DBG_S
B2 B1 PMTP6408 PMTP6409
IN_B2 O UT_B1 SP-TP-C0P381 SP-TP-C0P381
R6408 1K ON_+5V_FAN_REG C2 C1 +5V_Fan

[35] +5V_FAN_EN EN G ND
A 0201S_P28-W 35
NCP451AFCT2G
C6418
10u 6.3V
Iin=0.5A A
MTP6402 0402S_P7-W 70 Trace Width>20mil

GND TMAX=0.65mm
GND
5 4 3 2
5 4 3 2 1
PM_3P3V_PANEL_IN+ [28] PM_3P3V_PANEL_IN- [28]
C6521 10u
DBG_T
R6557
0
+3P3V_PANEL 47
DBG_T R6558
Imax=0.433A DBG_T
Trace Width> mil +3P3V_PANEL
D D
+3P3VSB DBG_TS
U6504 +3P3V_PANEL_REG
A2 A1 R6508 0.02
+1P8VSB B2 I N_A2 O UT_A1 B1
I N_B2 O UT_B1
PTP6501 PTP6502
C2 C1
C6501 EN G ND
C6503 NCP451AFCT2G C6502
0.1u 1u GND 1u
R6544
U6503 47
GND +3P3VSB 1/4W 0603
5 GND
GND ALL
2 V CC 4+3P3V_PANEL_EN_R R6519 +3P3V_PANEL_EN
1K
[10,30] PCH_VDD_PANEL_EN 1 A Y
[35] SAM_VDD_PANEL_EN B 3 DSG_+3P3V_PANEL
G ND R6548
+3P3V_PANEL_EN [76]
74AUP1G32GX +3P3V_PANEL_EN_R [24] 499K
6
R6501 R6529
100K 47K Q6501A
+3P3V +3P3V_PANEL_DISC_CTRL 2
GND
1
3
R6510 0.01
GND GND Q6501B
DBG_S 5
GND
C PTP6506 PTP6505 C
4
+3P3V
Imax=0.02A GND
Trace Width> mil
+3P3VSB
PM_3P3V_SSD+ [28]
U6511
PM_3P3V_SSD- [28]
A2 A1
VIN VOUT C6517 10u
R6564 0 B2 B1 C6513 DBG_T

[35,58,60,61,62,65] SLP_S3_DRV# EN GND
C6514 0.1u R6516
NX3P1108UK
1u GND 47 0
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DBG_T
R6515
GND GND DBG_T
+3P3V_SSD_CON
teknisi indonesia
+3P3V_REG
+3P3V_SSD_CON
R6511 0.02 Imax=2.25A
DBG_TS Trace Width>100mil
+3P3VSB PTP6504 PTP6503
U6502
B A2 A1 +3P3VSB B
B2 IN_A2 OUT_A1 B1
IN_B2 OUT_B1
P
M_3P3V_W W AN+ [28]
C2 C1 R6554 R6555 R6556
[58] SIL_SSD_VR_EN EN GND P
M_3P3V_W W AN- [28]
200K 140 140
C6511 NCP451AFCT2G C6512 0402 0402 C
6522 10u
1u GND 1u 1/16W 1/16W
3P3V_SSD_DCH DBG_T
Q6505B Q6505A R
6553
GND
3
GND 47
DBG_T 0
D
R
6552
5 2 DBG_T
G G
+
3P3VSB 3+P3V_W W AN
S
S
4
R
6514 0.02
DBG_TS
P
TP6510 P
TP6509
Added individual load switch for S0 APU supply +3P3V_WWAN

due to internal back leakage from S5 APU supply +3P3V_APU
GND C
6508 Imax=2A
1u
Trace Width>60mil
+3P3VSB
A A
U6510
G
ND
A2 A1
VIN VOUT
R6565 0 B2 B1 C6515
[35,58,60,61,62,65] SLP_S3_DRV# EN GND
C6516 0.1u
NX3P1108UK
1u GND
GND GND
5 4 3 2
1
1. PMbus address: 20h

2. Rdroop1 and Rdroop2 is
determined by the load line
slope value of the
application. Use MP2945
design toll to calculate the
Rdroop Values.
R 6636
V IN_SEN + 1P8V
+ VSYS
75K 0402
R 6603 C 6602 R 6607 2.2
+ 3P3V 4.99K + 3P3V
1000p
25V
C 6604 R 6606
1u 4.99K
R 6615
R 6620
R 6601
DNP R 6611
0
G ND 0402S_P4
G ND
U 6601
4.99K
4.99K
4.99K
15 35 V DD33_SOCVR
V INSEN V DD33
10V
24 17 V DD18_SOCVR C 6605
[33,35] S OCVR_SCL_P S CL_P V DD18
23 10V 1u
[33,35] S OCVR_SDA_P S DA_P
26 C 6601
R 6609 22 V CCIO
+ APU_VDDCORE 100 1u
[34] S OCVR_ALT_P# A LT_P R 6616
3 1 V DIFF1
[10] V DDCORE_VIN_SENSE V OSEN1 V DIFF1
[10] V DDCORE_VSS_SENSE 4 2 F B1 453 G ND G ND
V ORTN1 F B1 L L is 0.7mohm
C S_VDDCORE_SUM 10 12 I MON_VDDCORE
R 6613 C S_SUM1 I MON1 R 6622
100
5 7 V DIFF2
G ND R 6626 R 6627 R 6605 V ORTN2 V DIFF2
6 8 F B2 C 6608 R 6631
R 6625 V OSEN2 F B2 + 3P3V
1.5K 1.5K 1.5K 1.33K 31.6K
+ APU_VDDSOC R 6619 100 DNP 1.5KC S_VDDSOC_SUM
11
C S_SUM2 I MON2
13 LL is 2.1mohm I MON_VDDSOC 820p Max reported Current is 70A
R 6608
A
40 34 C 6603 A
[10] V DDSOC_VIN_SENSE [67] C S_VDDCORE1 C S1 P WM1 P WM_VDDCORE1 [67] R 6630
[10] V DDSOC_VSS_SENSE [67] C S_VDDCORE2 39 33 P WM_VDDCORE2 220p
C S2 P WM2 [67]
38 32 80.6K
[67] C S_VDDCORE3 C S3 P WM3 P WM_VDDCORE3 [67]
37 31
R 6628 C S4 P WM4 G ND
100 36 30 Max reported Current is 20A
[68] C S_VDDSOC C S5 P WM5 P WM_VDDSOC [68]
4.99K
G ND 9 25 R 6612 33
[67,68] T EMP_SOCVR V TEMP S VT S VID_ALERT# [10]
0 R 6602 0 29 21
R 6634 [10] V IDSOUT R 6614 S VD/PVID1 O CP_L V DDCORE_PWRGD R 6639 G ND
[10] V IDSCLK 0 28 20 0
S VC/PVID2 P G_A
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R 6635 C 6612 0 R 6604 S OCVR_PWROK 27 19 V DDSOC_PWRGD 0 R 6618
[10,18,20,33] P WROK P WROK/PVID3 P G_B V RM_PWRGD [34,58]
49.9K 0.01u
25V 16 14 S OCVR_IREF
A DDR I REF
18 41 V R_OCP# 100 R 6633
EN A GND R 6621 V R_PROCHOT# [10]
G ND + 3P3V MP2945GU-0021-C555-Z 61.9K
G ND
M1100275-002
R 6623
10K
+ 1P8VSB G ND G ND
C 6607
0.1u 10V 0.1u
0201S_P33-W39 C 6606
U 6602
16V
5
VCC G ND
2 4
[35] A PU_SOC_EN I O G ND
1
NC1
3
G ND
74AUP1G07GXG ND
1
1
[28] PM_VDDCORE_IN+
+VDDCORE_IN
[28] PM_VDDCORE_IN- C6703 10u
Place at DrMOS
DBG_T
U6701 C6730 C6731 R6703

47 +VSYS
C6714 C6704 C6705 0
15 BST 21 1u 10u 10u + + DBG_T R6702
[66] PWM_VDDCORE1 P WM R6701
0402 16V 16V DBG_T
R6713 0 16 VIN1 1 25V 0603 0603 47u 47u E2 E1
S YNC VIN14 14 GND GND GND PMTP6702 PMTP6704
17 C6701 2
I 1
I
[66,68] TEMP_SOCVR V TEMPFLT +APU_VDDCORE
0.005
HSFET
1u DBG_TS
+3P3V L6704 RES-FXD,SM,.005 OHM,1%,1W,0612,100 PPM
0201 DDCORE1_SW
DRIVE CONTROL
20 SW2 2 V
V CC 3
SW3 0.15uH Idc 30A /Isat 34A
SW4 4
C6706 30A
1K
6.3V 18 R6724 C6719
1u CS LSFET 22u
GND 0603
PGND13 13
[66] CS_VDDCORE1 PGND12 12 20%
19 PGND511 5 -11
A GND 10V
GND GND
put close to L6704
MP86902B GND
Place at DrMOS + C6715 + C6760 + C6712

GND 220u 220u 220u
ALL
U6702
C6732 C6733 C6743 C6744
[66] PWM_VDDCORE2 15 BST 21 C6713 + +
PWM 10u 10u
1u
R6711 0 16 VIN1 1 25V 16V 16V 47u 47u
SYNC VIN14 14 0402 0603 0603 GND
+3P3V TEMP_SOCVR 17 C6707
VTEMPFLT 1u 10V
HSFET
0201S_P4-W40
A A
L6703
DRIVE CONTROL
20 SW2 2 VDDCORE2_SW
VCC 3
SW3 0.15uH
SW4 4 Idc 30A /Isat 34A
C6709 30A
6.3V 18
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1u CS LSFET
GND
PGND13 13
[66] CS_VDDCORE2 PGND12 12
19 PGND511 5-11
AGND
MP86902B
U6703
C6710 C6718 C6711 C6717
[66] PWM_VDDCORE3 15 BST 21 DNP C6708 DNP DNP + +
PWM 10u 10u ALL ALL
1u
R6704 0 16 VIN1 1 25V 16V 16V 47u 47u
SYNC VIN14 14 0402 0603 0603
+3P3V TEMP_SOCVR DNP 17 C6702
VTEMPFLT DNP 1u 10V
HSFET
0201S_P4-W40
L6701
DRIVE CONTROL
20 SW2 2 VDDCORE3_SW
VCC 3
SW3
4 0.15uH
SW4
C6716 DNP 30A
6.3V 18 DNP
CS LSFET
1u
GND
PGND13 13
PGND12 12
[66] CS_VDDCORE3
19 PGND511 5-11
AGND
MP86902B
DNP
1
1
[28] P M_VDDSOC_IN+
C 6822 10u
[28] P M_VDDSOC_IN-
DBG_T
R 6882
47
0 R 6883
DBG_T
DBG_T
+ VDDSOC_IN R 6884
P MTP6802
E 2 E 1 P MTP6801 + VSYS
Place at DrMOS
I 2 I 1
U 6801
C 6824 C 6825 C 6802 C 6803 C 6804
12 B ST 1 8 C 6823 + 0.005
[66] P WM_VDDSOC P WM
1u 10u 10u 10u 10u DBG_TS
0 R 6802 13 V IN_1 1 25V 16V 16V 16V 16V 47u RES-FXD,SM,.005 OHM,1%,1W,0612,100 PPM
S YNC V IN_11 1 1 0402 0603 0603 0603 0603
14 C 6826 G ND G ND G ND G ND G ND G ND
[66,67] T EMP_SOCVR V TEMPFLT + APU_VDDSOC
1u
+ 3P3V HSFET
I dc 15.5 /Isat 17A L 6802
V DDSOC_SW
DRIVE CONTROL
17 S W 2
A
V DRV A
C 6827 0.33uH
1u 6.3V
+
1 K
0201S_P35-W35 15 C 6805 C 6801
CS L SFET
G ND 22u 220u
0603 R
20% 6
[66] C S_VDDSOC 8
16 P GND 3 -9 0
A GND 1
G ND 10V
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P GND1 10
put close to L6802
G ND
G ND MP86902A
G ND
Vinafix.com
1
1
A A
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1
5 4 3 2 1
+ VSYS P WR_SL1_F
R 7043
+ 3P3VAS
249K
A1
A2
K
D 7011
D 7010
D BAT54CW D
DNP BAT54CW
+ 3P3VA + 3P3V_HPD
A2
A1
K
U 7000 R 7000 100
9 S L1_HPD2 [71,76]
V DD R 7002 SL1_HPD1A_O R 7040
7 140 100 S L1_HPD1A [71,76]
SL1_HPD1B_U R 7004 SL1_HPD1B_O R 7039
1 H SD1p 140 100 S L1_HPD1B [71,76]
[37] SAM_SL1_TX Dp 5 SL1_HPD1A_U
[37] SAM_SL1_RX 8 H SD2p R 7042 C 7000
IO-ESD,SM,PESD24VS1UL,24 V,50 pF,1X.6X.

Sp 6 + 3P3VA 1 6 4 3
100K 100p
K PESD24VS1UL
K PESD24VS1UL
K PESD24VS1UL
2 H SD1m S D S D C 7001 C 7002 25V
Dm 4
H SD2m 100pDNP 100p
DNP
10 Q 7006A Q 7005B
25V 25V
[35] SL1_RX_SEL# Sm 3
G ND
G
6
3
R 7007 R 7005
DG2723DN-T1-E4
D
200K 200K R 7008
5
QFN10_1P85X1P45XP6_P4
R7006 C 7003
4.32K 2 5
0.1u
D
499K G G
10V
Q 7005A Q 7006B
D 7008
D 7000
D 7001
C 7022
S
0.1uF
A
25V
4
T P7009
R7035 0
[35] SL1_ADC
[34,35] ADC_RD_EN R 7010

PSU Voltage Comparator P WR_SL1
L1_ADC_RD_EN_R
+ 3P3VA
5.49K
P WR_SL1_F
D 7004 (9.4V-17.2V) D 7005
X865917-001 70 OHM
C A K PWR_SL1_F_COMP_VDD K A PWR_SL1_F L 7000 3A C
DS
PESD24VS1UL
0805S_1P1

G RB520CS3002L RB520CS3002L C 7006 R 7014 R 7015 R 7016 R 7017 X865917-001 70 OHM
Q 7000 + 1P8VA R 7021 L 7001 3A C 7008
100p 8.06 8.06 8.06 8.06
SOTFL-3_1P3XP9XP55_P4 C 7015 499K C 7009 25V 0201S_P33 0805S_1P1 C 7010 100p R 7019
0201S_P3
R 7011 25V
K
0.1uF 0.1uF 0.1uF 499K
S
X865917-001 70 OHM
100K 25V 25V0201S_P35-W35
PWR_SL1_F_C L 7007 3A C 7007 25V C 7012
SL1_20v0 0805S_1P1
R 7022 R 7023 100p 0.1uF
D NP
D 7003
499K C 7013 25V
25V
150K U 7004 1u
A
2 R 7024 25V
D
6 VDD 4 0603S_P94-W95
1 O UTA INA+ 10K

O UTB C 7016
5 3 0.022u
D 7006 G ND INB- SL1_5v5 1K BATEN_PULSE_R
120 OHM
0402S_P55 BATEN_PULSE_CONN
B ATEN_PULSE_CONN [76]
25V0201S_P33 1.2A
R7026 SL1_PSU_DETr A K [34,58] B ATEN_PULSE L 7006 + VDD_BATA_PACK
330 TPS3700DSER
[34,76] SL1_PSU_DET SON6_1P55X1P55XP8_P5
C 7005
R 7003
C 7004
INA+ <400mV OUTA=Low R 7027 100p 100p
RB520CS3002L 25V 25V
INB+ >400mV OUTB=Low 12.1K R 7050
1
R7018 100 499K
[55] SL1_PWR_GOOD POS T P7007
0201S_P3
NO-MSPN-00270 + 1P8VA
A
SHUNT-NO-MSPN-00270
R 7031
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R 7030 D 7013
33K 1K
0603S_P6-W95 Red
N EG
R
R 7034
ED
+ VDD_BATA_PACK
2
L1_DISCHARGER
R 7099 SL1_PWR_GOOD#
SL1 port discharger 150K
K
3
8.66K
B
D limits PSU anti-arc pulse voltage B
Q 7001
3
SL1_PWR_GOODg 1 G NX3008NBKMB
R 7001 1 R 7029
Q 7002
249K s 200K
SC70-3_2P2X1P35X1_P65 [33,58,70,76] B AT_SHUTDOWN#
DNP
2
2
R 7033 120 OHM @100MHz
0402S_P55
51K 1.2A
DNP [33,35] P OWER_SMB_SDA L 7003
GND C 7017
[33,35] P OWER_SMB_SCL BAT_SMDATA
100p [76] B AT_SMDATA
25V DNP BAT_SMCLK
[76] B AT_SMCLK M1106392-001
[34] B AT_DET# 8 4
120 OHM @100MHz
BATA_DET#_CON 7 8 4 3
0402S_P55
1.2A 6 7 3 2
Present State Trigger Output L 7004 5 6 2 1
C 7018 5 1
SL1_UART_TX SL1_UART_RX 1W/2W Initial 100p N3 P3
25V DNP [76] B ATA_DET#_CON N2 N 3 P3 P2
Detect A/D read SL1_UART_TX_SEL_N SL1_UART_RX_SEL_N SL Polarity N1 N 2 P2 P1
N1 P1
Low Low Detach n/a Low Low Detach J 7001
120 OHM @100MHz
+ VSYS + 3P3VAS_SIL 1K
Low High 1W n/a High Low Straight up BATA_DET#rr 0402S_P55
1.2A
L 7005
R 7037
High Low 1W n/a Low High Reversed C 7020 C 7021
100p 100p C 7019
25V 25V
High High 2W Valid Low Low Straight up 0.1uF
1.5K 1.5K 1M
High High 2W Invalid High High Reversed R 7046 R 7045
1/20W 0201 1/20W 0201 R 7044 120 OHM
0402S_P55
ALL ALL [55] B AT_LDO 1.2A B AT_LDO_PACK [76]
A ALL L 7002 A
AT_SHUTDOWN_GATE
C 7011
100p
25V
6
Q 7003A Q 7003B
D
2 5
B
G G B AT_SHUTDOWN# [33,58,70,76]
S
S
1
5 4 3 2
5 4 3 2 1
L1_LANE1N_R L1_LANE3P_R
S S
L1_LANE0P_R
S
L1_LANE0N_R L1_LANE2P_R
0nH S S
L1_LANE0P_R L1_LANE1P_R L1_LANE3N_R L1_LANE2N_R
3 4 S S S S
L1_LANE0N_R
2 1 S
7101
7103 7108 7113 7116
1
L
K
M1077716-001 D D D D 7107 7118
1
K
K
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
D D 7112 7105
1
K
K
PESD5V0H1BSF PESD5V0H1BSF
D D
PESD5V0H1BSF
PESD5V0H1BSF
2
K
K
ND ND
2
K
K
0nH G G ND ND
2
K
K
L1_LANE1P_R G G ND ND
3 4 S G G
D D
[10] L_DATA0_DP L1_LANE1N_R
[10] SL_DATA0_DN 2 1 S
S 7102
L
M1077716-001
[10] L_DATA1_DP
[10] SL_DATA1_DN
S
W R_SL1
P
0nH
L1_LANE2P_R
3 4 S
[10] L_DATA2_DP L1_LANE2N_R Same IPEX connector as LANCELOT
[10] SL_DATA2_DN 2 1 S
S 7103
L
M1077716-001 7101
J
1
2 1
[70,76] L1_HPD1A 3 2
S 4 3
SB3_SL1_RXP4_R
U 5 4
SB3_SL1_RXN4_R
U 6 5
0nH 6
L1_LANE3N_R SB3_SL1_TXP4_R 7
[10] L_DATA3_DN 3 4 S U 8 7
SB3_SL1_TXN4_R
[10] SL_DATA3_DP U 8
S L1_LANE3P_R 10 9
2 1 S L1_LANE3P_R 11 09
L
7104 S
L1_LANE3N_R 12 11
M1077716-001 S
13 21
AM_DBG2_SL1_DP_HPD_CON 14 31
S
AM_DEBUG_UART_RX_CON 15 41
S
SB2_SL1_D+_R 16 51
U
SB2_SL1_D-_R 17 61
U
18 71
[70,71,76] L1_HPD2 19 81 62
S
20 91 TG22 61
21 01 M
TG21 60
22 12 M
TG20 59
23 22 M
TG19 58
[70,71,76] L1_HPD2 32 M
TG18
Vinafix.com S L1_LANE4N_R 24 57
C S
L1_LANE4P_R 25 42 M
TG17 56 C
S 2 M
AM_DEBUG_UART_TX_CON 26 5 TG16 55
SAM_DBG4_SL1_CONFIG1_CON
27 62 M
TG15 54
S
28 72 M
TG14 53
L1_LANE2N_R 29 82 M
TG13 52
S
L1_LANE2P_R 30 92 M
TG12 51
S 2 M
31 0 TG11 50
3 M
L1_LANE1N_R 32 1 TG10 49
S 3 M
3P3V L1_LANE1P_R 33 2 TG9 48
+ S 3 M
34 3 TG8 47
3 M
L1_LANE0N_R 35 4 TG7 46
+3P3VSB S 3 M
L1_LANE0P_R 36 5 TG6 45
S 3 M
7105 37 6 TG5 44
R 3 M
100K 38 7 TG4 43
[70,76] L1_HPD1B 3 M
7103 0201S_P28-W35 S 39 8 TG3 42
U 3 M
0201S_P33-W39 9 40 9 TG2 41
3 M
7103 0.1u 10V L_AUX_DN_C 1 CC 7104 0 TG1
[10] L_AUX_DN C S V U 4 M
S 2 1+ 3 L1_LANE4N A1 P_O P_I A2 L1_LANE4N_R
D S D D S
0201S_P33-W39 2+ + B1 M_I B2 L1_LANE4P_R
D D D S
7104 0.1u 10V S
L_AUX_DP_C 7 M_O C2 X912045-001
[10] L_AUX_DP C 1- L1_LANE4P D
S 6 D 5 S D
2- - I
D D C1
P_CONFIG1 0 ND
D 1 G
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S 4
8 E ND
O G 7105 7106 7104
+3P3VSB C C R
TS3USB30E 0.1u 0.1u 100K
0201S_P28-W35 ND
DNP DNP G
R7106 Note: IP3319CX6 D+ and D- is interchageable

10K GND GND
DNP GND
DP_EN
R7107
0
B B
GND
+1P8V +3P3V
R7110 R7102 +3P3VSB

10K 10K
DNP ALL
U7110 7109
U
3 4 USB3_SL1_RXN4_R TP7101 5 7101
R 0 SAM_DBG_RX_FILT 1 8 AM_DEBUG_UART_RX_CON
S
[24] USB3_SL1_RXN4 0nH VCC [29,33,34,76] SAM_DBG_RX 7103 0 SAM_DBG_TX_FILT 2 1I 1
O 7 AM_DEBUG_UART_TX_CON
S
R 2I
I O
2
USB3_SL1_RXP4_R [29,33,34,76] SAM_DBG_TX L1_DP_HPD_BUF
S 3 O 6 AM_DBG2_SL1_DP_HPD_CON
S
2 1 [10] 4 2
[24] USB3_SL1_RXP4 SL_DP_HPD O I P_CONFIG1
D 4 3I 3
O 5 AM_DBG4_SL1_CONFIG1_CON
S
L7105 1 4I 4
O 9
C7110 ND
G PAD
10V 0.1u 3 NC1 ND
G
ALL GND 7125
R 7113
R 12p
74AUP1G07GX 100K 1M ND
G
C7101 0.1u USB3_SL1_TXN4_C 3 4 USB3_SL1_TXN4_R ALL

[24] USB3_SL1_TXN4
0nH
C7102 0.1u USB3_SL1_TXP4_C 2 1 USB3_SL1_TXP4_R
[24] USB3_SL1_TXP4
L7106 ND
G ND
G
A USB3_SL1_RXP4_R A
USB3_SL1_TXN4_R
7107
[24] USB2_SL1_DN 2 L 1 USB2_SL1_D-_R
0nH 2.5GHZ USB3_SL1_TXP4_R
3 4 USB2_SL1_D+_R
[24] USB2_SL1_DP USB3_SL1_RXN4_R
3 2
K1
K1
K1
K1
4 1
K
0 DNP RN7107 D7119 D7106 D7117 D7102 D7104 D7109

PESD5V0H1BSF
PESD5V0H1BSF PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
PESD5V0H1BSF
K2
K2
K2
K2
2
K
GND GND GND
5 4 3 2
5 4 3 2 1
3P3VA
+ TP7202
+3P3V_HPD
R
7202 0.01 P
+
3P3V_HPD_VIN Imax=165uA
07132016
TP7201
P 7201 3P3V_HPD_OCFLAG P7204
C + T
1u
3P3VA
+ 3P3V_HPD
+
ND
G 7201 7201
R
499K A1 U A3
B1 IN_A1 OUT_A3 B3
VIN_B1 VOUT_B3
3P3V_HDP_EN V V
C3 1
+ N CFLAGB C
O O
A2 7202 7239
D 3P3V_HPD_ILIMIT C2 ND_A2 B2 C R D
+ SET GND_B2 1u 499K
I G
FPF2495UCX
D
7204 ND
7201 R G
[35,76] L1_HPD2_EN# 20K
G Q ND
S
G ND
S G
7206
R ND
499K G
ND
ND G
G
+
VCC_EDP_BKLT_IN +VCC_EDP_BKLT_OUT
Imax=0.16A
7227 0 0603 VCC_EDP_BKLT_IN
07132016
R + 7201
L VCC_EDP_BKLT_OUT
5VSB KLT_SW +
+ B
1/10W
C 10uH 7201 C
F
DNP
7228 0 0603 7210 7213 7205
R C C C 0.75A
10u 10u 10u
1/10W M1116198-001
7206 7207 7208
C C C
ND ND ND
VCC_BKLT G G G
+ 7209 2.2u 2.2u 2.2u
C
0.22u 50V 50V 50V
7204
C
B
KLT_BST_SW
1u ND ND ND
G G G
ND
G
U7202
7207 10 7226 DNP 0 1 18

R R CC UT
7233 V O
R
10K 24
7218 IN 20 7229
C V R
_BKLT_CTRL_R KLT_PW M_R W
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L 7209 1K B 5 S 47
R WM
1u P
21 KLT_BST
[76] KLT_PWM_R ST B
B B
[76] BKLT_EN
GND
BKLT_EN_R R7208 1K BKLT_EN 2 N ED8
8 KLT_FB8_R
B 7231
R 0
KLT_FB8 [57,76]
E L 9 KLT_FB7_R 7230 0 B
2
ED7 B R KLT_FB7 [57,76]

6 L 10 KLT_FB6_R
B 7223 0 B
0 ED6 KLT_FB5_R R KLT_FB6 [57,76]
G
7 A L 11 7222 0 B
5
1 ED5 B R KLT_FB5 [57,76]

Q7204A A L 12 KLT_FB4_R
B 7221
R 0 B
KLT_FB4 [57,76]
ED4 KLT_FB3_R
G
L 13 B 7220 0 B
R KLT_FB3 [57,76]
Q7204B 6 1 R7203 0 BKLT_SCL 4 ED3
L 14 KLT_FB2_R
B 7219
R 0 B
[35] SAM_PANEL_SCL CL ED2 KLT_FB2 [57,76]
D S R7210 0 BKLT_SDA 3 S
DA
L
ED1
15 KLT_FB1_R
B 7218
R 0 B
KLT_FB1 [57,76]
3 4 S L B
[35] SAM_PANEL_SDA 23 22
D S
T
F C22
N 19
C19
N 17
25 C17
N
B B
GND_EP
A 16
R7224 GND
R7225 0 P
0 DNP
ALL
C7203 ND
G P3376AGR-0300
M ND
G
2.2u
DNP
10V
7-bit I2C Address = 0x28

GND GND
PM_BKLT_IN+ [28]
DG2723 AND MP3376 ARE 1.8V LOGIC ON EN, PWM AND I2C
PM_BKLT_IN- [28]
C7221 10u
DBG_T
R7240 +VCC_EDP_BKLT_IN
47 0 7234
R
+VSYS DBG_T 0
Q7203 +VCC_EDP_BKLT_IN_REG PTP7204 R7241 3P3VSB
+ ALL
DBG_T
PTP7203
2 3 R7217 0.02
S D 7220
C
DBG_TS
0.1u
G
R7213 C7215 DNP

7204
U
1
200K 1000p R7216 R7215 9

DD
V
5.1K 5.1K ND
G
C7216 7
[35] SAM_LCD_BKLT_EN SD1p
H
+VCC_EDP_BKLT_IN_DRI 0.1uF 1 KLT_EN_MUX0
B DNP 7250
R KLT_EN_R
B
DNP 5 p
D
[10,34,72] PCH_LCD_BKLT_EN SD2p
H 8
+VCC_EDP_BKLT_IN_DISC p
S
R7214 GND Q7202B [35]
6
SAM_LCD_BKLT_EN SAM_BKLT_CTRL_PWM SD1m
H 2 _BKLT_CTRL_MUX _BKLT_CTRL_R
3
100K L 0DNP 7251

R L
4 m
D
[10,72] PCH_BKLT_CTRL_PWM SD2m
D
A H 10 7237 DNP
R 0 A
Sm C
P H_SAM_INST_ON [22,34]
R7235 +VCC_EDP_BKLT_IN_DRI_R 5 3
G ND
G
0 Q7202A 7205
R 7232
R
+3P3V_PANEL +1P8VSB
6
ALL 100K 100K DG2723DN-T1-E4 7236

R
U7205 DNP 47K
S
DNP
D
74AUP1G08GX DNP
22K +VCC_EDP_BKLT_IN_R
4
R7211 DNP 2 5
G 2 VCC 4L_BKLT_CTRL R7256 ALL 0 L_BKLT_CTRL_R
[10,34,72] PCH_LCD_BKLT_EN ND
G
1 A Y
[10,72] PCH_BKLT_CTRL_PWM ND
G ND
G
B 3 C7211
S
ND
G
R7212 C7214 GND 0.1u
1
100K GND R7255 R7254 10V

DNP 0.1u 100K 100K
DNP ALL ALL
GND
GND GND GND GND
5 4 3 2
5 4 3 2 1
D D
C C
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B B
A A
5 4 3 2
5 4 3 2 1
KBTP CONNECTOR 1P8VA

+
1P8VSB
+
Pin1 Top Left 7401 5V_KIP

[76] P8V_KIP
1 7414
0R
DNP
7415
0R
ALL
J +
D D
IP_FPC_CONN_DET_B# PINS REVERSED
0 7403
[58] IP_FPC_DET_B# R K 2 1 P8V_KIP
K 2 1 7418 ALL 0
[29,76] IP_SWD_CLK 4 3 1 R
K 6 4 3 5 IP_SWD_DIO [29]
[29] IP_TRACE_SWO 6 5 K
AM_KIP_RST# [29,35]
108 7
K
IP_FPC_CONN_DET_A# 7401 0 S IP_FPC_DET_A# [58]
[34,74,76] K AM_KIP_UART_TX 7427 100 IP_PWR_SW_N 12
80 7 9
11 K R 7414 7404
S
[31,33,34] W RBTN#_1V8 K 12 19 K AM_KIP_UART_RX [34,74]
R D
PESD5V0F1USF315 C 1u
6.3V
P 1 1 S
7421 7402
K
14 13 R499K U
NX3P1108UK
A
7408
TG2 TG1 DNP
K
7405 16 MTG3 15 ALL BGA4_2X2_P98XP98XP59_P5
D7407
C MTG4
K
D
1000p 7417 0 A1 A2 ND
D7405
M M OUT IN
K
R G
D7409
DF40B-12DS-0.4V(51) V V
DNP
A
D7413
7403 B1 B2 1K 7416
PESD3V3U1UL315
ND N IP_LS_EN [35]
10V C0.1u R
A
G E K
PESD3V3U1UL315
A
DBG_D
ND
NP G
D NP ND [76] IP_LS_EN_R
NP D G K
D NP
D NP
D
C C
1P8VSB
+
7435
C
0.1u
U7410
6.3V
DBG_D 8
CC
V
1P8VSB ND
+ G 1
7 Y AM_KIP_UART_RX_DBG [29,33]
1 S
[34,74] AM_KIP_UART_RX 6 A
7402 S 1
R B 5
100K 1
Y AM_KIP_UART_TX_DBG [29,33]
DBG_D 2 S
3
[34,74,76] AM_KIP_UART_TX 2 A
S 2
[34] LADE_UART_DBG_EN B 4
B 2
ND
G
N74AUP2G08RSER
S ND
X912843-001 G
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DBG_D
KIP UART Debug gated Sniffer (Dual AND gate, )

Place U7410 close to J7401 UART lines to minimize stubs
B B
A A
5 4 3 2
5 4 3 2 1
D D
C C
B
5 4 3 2
5 4 3 2 1
MTP7606
RGB_LED_A_P [54]
MTP7674 +5V_KIP
APU_TCK [10,18]
MTP7631 MTP7635
APU_TDI [10,18] P
MTP7669 W R_SL1
APU_TDO [10,18] +VDD_BATA_PACK
MTP7607 PW R_SL1_F
APU_TMS [10,18]
MTP7655
MTP76195 APU_TRST# [10,18] MTP7626 M M
APU_DBREQ# [10,18] TP76154 TP76162
M
TP76155 M
TP76163
MTP7619 +1P2V_DUAL MTP7691 MTP7633 MTP7959 M
TP76156 M
TP76164
SPI_CLK_R1 [21] RTD3_CAM_PW REN [22,54]
MTP7656 MTP7650 MTP7610 M
TP76157 M
TP76165
MTP7657 SPI_MOSI_R1 [21] MTP7604 MTP7688 MTP7660 M M
SPI_MISO_R1 [21] TP76158 TP76166
MTP7639 MTP7614 MTP7643 MTP7680 M
TP76159 M
TP76167
SPI_W P_IO2_R1 [21] I LED_C_N [54]
R
D MTP7613 MTP7668 MTP76112 M
TP76160 M
TP76168 D
MTP7671 SPI_HOLD#_IO3_R1 [21] +V_VDDQ_VTT MTP76111 MTP76113 M M
SPI_CS#0 [20,21] TP76161 TP76169
MTP7644 MTP7618 MTP7605
I LED_A_P [54]
R
MTP7679 MTP7640 MTP7622
+VDDP
MTP7672
3P3_CAM [54] Place close to J7101
MTP7690
EDP_I2C_INT [22,57] Place close to J7702
MTP7659 MTP7625 MTP7661
KIP_SW D_CLK [29,74] CAM_IR_STB [54]
MTP7684 +3P3VSB
1P8V_KIP [74]
MTP7664
CAM_IR_STB_R [54]
MTP7667 MTP7681
SAM_KIP_UART_TX [34,74]
MTP7645
SL1_EN_N [63] P lace Close(Under) to JP4001
MTP7616 GND MTP Close to J5401 M
TP76190
+5VSB
MTP7620 MTP7685 G ND MTP Close to J5401
SEN_HALL_INT#_S [34,54]
MTP7648
MTP76131 G ND MTP close to U5505 A
GND
MTP7677
teknisi indonesia
SEN_HALL_INT#_N [34,54]
MTP76132 GND MTP close to J5701
+VDDPSB
MTP7682 MTP7627
SAM_FLASH_UEFI [21,35]
MTP7628 MTP76134 GND MTP close to J5401
+VCC_RTC PW RBTN#_1V8_FILT [31]
C MTP7654 MTP76100 MTP76135 GND MTP close to J7701 C
PMI_I2C_SDA [22,28,33] VOL_UP#_FILT [31]
MTP7647
PMI_I2C_SCL [22,28,33]
VOL_DOW N#_FILT [31]
MTP7636
+1P8VSB MTP76110 MTP76138 GND MTP close to J7701
SAM_SW D_SW O [29,33,34]
MTP7642
SAM_SW D_CLK [29,33,34]
MTP7658 MTP7652 MTP7663 MTP76139 GND MTP close to J7701
BKLT_PW M_R [72] SAM_SW D_DIO [29,33,34]
MTP7608
BKLT_EN [72]
+1P8V SL1_HPD2 [70,71]
MTP7697
SL1_HPD1A [70,71]
MTP7694 MTP76104
BKLT_FB8 [57,72] SL1_HPD1B [70,71]
MTP7695
BKLT_FB7 [57,72]
MTP7696 MTP7693 MTP76170
BKLT_FB6 [57,72]
MTP7923 MTP76173 BAT_LDO_PACK [70]
BKLT_FB5 [57,72]
MTP7649 MTP76171
BKLT_FB4 [57,72]
MTP7699
BKLT_FB3 [57,72]
MTP7670 MTP76172
BKLT_FB2 [57,72] +2P5VPP SL1_HPD2_EN#_MTP
MTP7927 MTP76174 R7601 1K
BKLT_FB1 [57,72] SL1_HPD2_EN# [35,72]
MTP7634
B
MTP7653
MTP7676
PMI1_I2C_SCL_R [28]
PMI1_I2C_SDA_R [28]
MTP76114
+VBUS_P0_CONN
MTP76176
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+3P3V_PANEL
+VSYS
EXT_DC_IN
MTP7646
MTP7698
DDR_PGD_SIL [58]
+1P2V_DDR_PG [58,60]
G
ND
B
MTP7609 MTP76115 MTP76182

+3P3V_PANEL_EN [65] MTP76116 MTP76183 +3P3VA MTP76102
+3P3V EDP_I2C_SCL [57]
MTP7602
PCH_SAM_SNSR_SDA [33,35]
MTP76117 MTP76184 MTP7662
EDP_I2C_SDA [57]
DV change:
MTP76118 MTP76185 +3P3V_SSD_CON In RAFLA this Signal
MTP7666 MTP76119 MTP76186 +3P3V_BB0 MTP76103 will be pulled "LOW" via 1K resistor
PCH_SAM_SNSR_SCL [33,35] SAM_PIO0_3 [34]
MTP76187 MTP76105
SAM_PIO0_4 [34]
MTP7673 MTP76106 M
TP76196
SLG_PW RBTN# [58] +VCC_EDP_BKLT_OUT SAM_PIO0_5 [34] F
PC_DET_LOGIC_OVERRIDE# [33,58]
MTP76107
SAM_PIO0_6 [34]
MTP7630 MTP7615
SOC_SENSOR_ACS_SDA [22,54] SAMRTS_PCHCTS [20,29,33,34]
MTP76120 MTP76108
TCON_VENDOR_ID [20,57]
MTP7683 MTP76121 MTP7689
SOC_SENSOR_ACS_SCL [22,54] PCHRTS_SAMCTS [20,29,33,34]
+1P8V_AUDIO
MTP7603 MTP76141
SAM_RESET# [29,33,34,58]
MTP76175 M
TP76197
+3P3V SL1_PSU_DET [34,70] H
_PROCHOT# [10,63]
MTP76122
MTP76123 HP_MIC_LR_CON [41] MTP76126
HPOUT_R_CON [41] USB2_USBA_DN_CONN [45]
MTP76124 MTP7621 MTP76127 MTP76177
HPOUT_L_CON [41] USB2_USBA_DP_CONN [45] BATEN_PULSE_CONN [70]
MTP76125 MTP76178
HPOUT_JD [40,41] BAT_SMCLK [70]
CON2_VBUS MTP76179
+APU_VDDCORE BAT_SMDATA [70]
MTP76128 MTP76180
BATA_DET#_CON [70]
MTP76129 MTP76181
DMIC1_SDA_DSP [43,54] BAT_SHUTDOW N# [33,58,70]
MTP76130 MTP7637 MTP76188
DMIC1_SCL_DSP [43,54] +APU_VDDSOC KIP_LS_EN_R [74]
MTP76146 TCP0_CONN_CC1 MTP76189
[77] KIP_EN [64]
A MTP76147 USB2_TCP0_CONN_A_DP A
[77]
MTP76142 MTP7665 MTP76148 USB2_TCP0_CONN_A_DN
SPK_R+_CON [41] [77]
MTP76143 MTP76149 TCP0_CONN_SBU1 MTP76191
SPK_R-_CON [41] [77] PCH_DBG_TX [20,29,33]
MTP76144 +5V_KIP MTP76192
SPK_L+_CON [41] PCH_DBG_RX [20,29,33]
MTP76145 MTP76193
SPK_L-_CON [41] SAM_DBG_TX [29,33,34,71]
MTP7632 +1P8VA MTP76150 TCP0_CONN_SBU2 MTP76194
[77] SAM_DBG_RX [29,33,34,71]
MTP76151 USB2_TCP0_CONN_B_DN [77]
MTP76152 USB2_TCP0_CONN_B_DP [77]
MTP7692 MTP76153 TCP0_CONN_CC2 [77]
+5V_AUDIO
MTP7624
5 4 3 2
5 4 3 2 1
3P3V_PD_OUT
+
7708
C
100K
100K
1u 6.3V
201S_P28-W35
201S_P28-W35
201S_P35-W35
0
7709
7711
A3 7703
U
0
SYS
R
V
A2 A1
C1 ON_CC1 CP0_CONN_CC1
T
[79] CP0_CC1
T C C
B2 B1
C2 ON_CC2 CP0_CONN_CC2
T
[79] CP0_CC2
T C C
C2 C1
D BU1 ON_SBU1 CP0_CONN_SBU1
T D
[29] CP0_SBU1
T S C
D2 D1 CP0_CONN_SBU2
[29] CP0_SBU2 BU2 ON_SBU2 T
T S C
CP0_SBUEN
D3 C3 CP0_FLG
T BUEN LAG T
S F
B3
ND
G
1M
0201S_P28-W35
1M
0201S_P28-W35
NX20P0407UK
ALL
R7708
R7702
VBUS_P0_CONN
+
7701
J
A1
A2 ND_A1
CP0_TX_CONN_P0
T G
X1p
CP0_TX_CONN_N0 A3 T
T X1m
A4 T
A5 BUS_A4
CP0_CONN_CC1
T V
C1
[76] CP0_CONN_CC1
T A6 C
SB2_TCP0_CONN_A_DP
U p_A
[76] SB2_TCP0_CONN_A_DP
U A7
+3P3VSB SB2_TCP0_CONN_A_DN
U D
m_A
[76] SB2_TCP0_CONN_A_DN
U CP0_CONN_SBU1 A8 D
[76] CP0_CONN_SBU1 T BU_A
T A9 S
A10 BUS_A9
CP0_TXRX_CONN_N1
T V
X2m
CP0_TXRX_CONN_P1 A11 R
T X2p
A12 R
C7707 C7702 C7709 C7703 C7701 ND_12
10V 0.1u 10V 0.1u 10V 0.1u 10V 0.1u 10u 6.3V G
0201S_P33-W39 0201S_P33-W39 0201S_P33-W39 0201S_P33-W39 0402S_P7-W70
B12
[76] TCP0_CONN_SBU2 TCP0_CONN_SBU2
B11 ND_B12 1
7702 CP0_TXRX_CONN_P0
T G
5 U X1p TG1
USB2_TCP0_CONN_B_DN
1 [76] USB2_TCP0_CONN_B_DN B10 2
RD0_SWAP W AP CC_1 USB2_TCP0_CONN_B_DP CP0_TXRX_CONN_N0
T R
X1m M
TG2
S VCC_6 6 [76] USB2_TCP0_CONN_B_DP B9 R M 3
TCP0_CONN_CC2 BUS_B9 TG3
7 20 [76] TCP0_CONN_CC2 B8 4
RD0_SLP_S0# LP_S0# V
CC_20 C
TP0_CONN_SBU2 V
BU_B M
TG4
S VCC_28 28 SB2_TCP0_CONN_B_DN B7 S M 5
U m_B TG5
14 V B6 D M 6
C RD0_VIO_SEL IO_SEL SB2_TCP0_CONN_B_DP
U p_B TG6 C
V C B5 D M 7
se 25V cap on the connector side to protect pin short to VBUS
U TP0_CONN_CC2 C2 TG7
9 40 CP0_TXRX_RT_P1 B4 C M 8
[24] TCP0_TXRX_P1 C7729 0.22u TCP0_TXRX_C_P1 RX2p RX2p T R7772 2.2 TCP0_TXRX_RT_P1_RC 7738
C 0.33u 25V 0201 BUS_B4 TG8
10 URX2n DRX2n 39 CP0_TXRX_RT_N1 B3 V M 9
[24] TCP0_TXRX_N1 C7726 0.22u TCP0_TXRX_C_N1 T R7773 2.2 TCP0_TXRX_RT_N1_RC 7745
C 0.33u 25V 0201 CP0_TX_CONN_N1
T
B2 X2m TG9 10
+3P3VSB U D CP0_TX_CONN_P1
T T
X2p M
TG10
TCP0_TX_C_P1
12 37 TCP0_TX_RT_P1 TCP0_TX_RT_P1_RC
B1 T M 11
[24] TCP0_TX_P1 C7722 0.22u 13 TX2p TX2p 36 TCP0_TX_RT_N1 R7774 2.2 7737
C 0.22u 25V 0201 ND_B1 TG11
C7732 0.22u TCP0_TX_C_N1 UTX2n DTX2n R7775 2.2 TCP0_TX_RT_N1_RC 7743
C 0.22u 25V 0201 G M
[24] TCP0_TX_N1 U D
19 30 TCP0_TXRX_RT_P0
C7725
C7724
00p
00p
M1084960-001
R7734 [24] TCP0_TXRX_P0 C7736 0.22u TCP0_TXRX_C_P0 RX1p RX1p R7768 2.2 TCP0_TXRX_RT_P0_RC 7719
C 0.33u 25V 0201
18 URX1n DRX1n 31 TCP0_TXRX_RT_N0
100K C7733 0.22u TCP0_TXRX_C_N0 R7769 2.2 TCP0_TXRX_RT_N0_RC 7721 0.33u 25V 0201
1
[24] TCP0_TXRX_N0 C
DNP
DNP
0201S_P28-W35 U D
10%
10%
TCP0_TX_C_P0 16 33 TCP0_TX_RT_P0 TCP0_TX_RT_P0_RC
[24] TCP0_TX_P0 C7734 0.22u
15 TX1p TX1p 34 TCP0_TX_RT_N0 R7770 2.2 7720
C 0.22u 25V 0201
C7730 0.22u TCP0_TX_C_N0 U D R7771 2.2 TCP0_TX_RT_N0_RC 7718
C 0.22u 25V 0201
[24] TCP0_TX_N0 TX1n TX1n
C7710
C7717
C7711
C7706
U D R7730 2M
PTVS24VS1UR
0.1u 10V TCP0_AUX_DP_R 24 8 RD0_DIR0
C7704 R7747 2M
K
[10] TCP0_AUX_DP UXp IR0
0.1u
0.1u
0.1u
0.1u 10V TCP0_AUX_DN_R 25 A D 11 RD0_DIR1 7756
[10] TCP0_AUX_DN C7705 UXn IR1 R
A D D7707 39.2K
D7717
RD0_I2C_EN 17 27
2C_EN BU1 TCP0_BB_SBU1 [29] D7703 D7710 D7716 D7718 D7712 7714
D 0201 1% 5V
3 5V
3 5V
3
0.1u
I S 26
R7751 BU2 TCP0_BB_SBU2 [29] D7711
35
A
100K RD0_A0 S 5V
3
EQ0/A0
K2
K2
K2
K2
K2
K2
K2
K2
0201S_P28-W35 RD0_A1 2 U 21 RD0_FLIP
R7704 0 TP7716
K1
EQ1/A1 LIP/SCL
220K
220K
220K
220K
220K
220K
220K
220K
U F 22 RD0_CTL0 APU_PD_SCL [24,79]
TL0/SDA R7705 0
K1
K1
K1
RD0_DEQ0 38 C APU_PD_SDA [24,79]
EQ0
D7702
29 23 RD0_CTL1
DESD24VF1BL
ESD24VF1BL
RD0_DEQ1 D TP7715 PESD5V0H1BSF
EQ1 TL1
D7708
D7709
7715
LL
ALL
ALL
GND D C X941484-001
R7779
R7776
R7777
R7778
R7780
R7781
R7784
R7783
3 32 RD0_HPDIN
A
RD0_CFG0 FG0 PDIN R7761 0
TYPEC0_HPD [10,79]
K1
K1
K1
K1
K1
K1
K1
K1
4
LL
RD0_CFG1 C H hanged
C to X941484-001 @ EV2.1
P
FG1
K2
C 41
A
to increase stand-off voltage to 5V, NP D
D NP D
NP D
NP
PAD
K2
K2
K2
M above operation voltage of interface
TUSB1044RNQ
B
7 bit I2C address 0x0FH
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[29]
[29]
TCP0_DBG0_A_DP
TCP0_DBG1_A_DN
R7749
R7750
0
0
TCP0_DBG0_A_DP_R
TCP0_DBG1_A_DN_R
4
1
L7708 3
2
DLP11TB800UL2L
SB2_TCP0_CONN_A_DP
U
SB2_TCP0_CONN_A_DN
U B
7721 PESD5V0H1BSF
D
2 3 2
K 1
K
1 4
7720 PESD5V0H1BSF
D
RN7704 0 DNP 2
K 1
K
+3P3VSB +3P3VSB +3P3VSB +3P3VSB +3P3VSB +3P3VSB +3P3VSB
R7753 0 TCP0_DBG2_B_DP_R 4 3 SB2_TCP0_CONN_B_DP

U
10K
1K
1K
1K
1K
1K
1K
[29] TCP0_DBG2_B_DP L7707
R7754 0 TCP0_DBG3_B_DN_R 1 2 SB2_TCP0_CONN_B_DN

U
[29] TCP0_DBG3_B_DN
R7723
R7752
R7714
R7710
R7760
R7740
R7739
DLP11TB800UL2L
7719 PESD5V0H1BSF
D
DNP
RD0_I2C_EN RD0_SLP_S0# RD0_FLIP RD0_A0 RD0_DEQ0 RD0_CFG0 RD0_DIR0 2 3 2

K 1
K
1 4
7722 PESD5V0H1BSF
D
0
RN7703 0 DNP 2
K 1
K
R7720
R7744
R7701
R7707
R7725
R7748
R7755
+3P3V_DEBUG
DNP
DNP
DNP
DNP
DNP
DNP
DNP
7750
C
0.1u
7704
U
9 10V
+3P3VSB +3P3VSB +3P3VSB +3P3VSB +3P3VSB +3P3VSB +3P3VSB +3P3VSB 1 VCC
2 D1+ 3
D2+ D+ SB2_TCP0_DP
U [24]
7
1K
1K
1K
1K
1K
1K
1K
1K
6 D1- 5
D2- D- SB2_TCP0_DN
U [24]
10
R7713
R7703
R7706
R7727
R7745
R7722
R7726
R7712
[79] PD_USB2_MUX_FLIP S 4
8
DNP
DNP
RD0_SWAP RD0_VIO_SEL RD0_CTL0 RD0_A1 RD0_DEQ1 RD0_CFG1 RD0_DIR1 RD0_CTL1 +3P3V_DEBUG OE GND
TS3USB30E
A A
0
R7758
100K
1%
R7737
R7732
R7757
R7719
R7721
R7738
R7743
R7724
0201 USB2_TCP_MUX_EN#
DNP
DNP
DNP
DNP
DNP
DNP
DNP
[29] MUX0_EN# G
Q7701
R7759
S
100K
1%
0201
5 4 3 2
5 4 3 2 1
D D
C C
B
A A
5 4 3 2
5 4 3 2 1
+5VSB EXT_DC_IN +VBUS_P0_CONN

DBG_TS 0603S_P6-W100
R7957 0.01
K
C7943 + C7909 D7905
7906
7913
150u 4.7u RB520CS3002L
7919
20% +C C7944 1u 1u
C
10V 22u 25V 25V
A
25V 10u
DNP 35V
D +3P3VSB +3P3VA +5VSB D
PLACE
ONE CAP Place C7919 close to U7902
U7902 3P3V_PD_OUT 1P8V_PD_OUT
PER PIN 11-12 13-14 + +
R7975 0 4.7u P_HV1 BUS1
10V P V DBG_S
1-2 3-4
DNP 20% P_HV2 BUS2 7962
R 0.01
7911
P V 0402S_P5-W65
C
25 35
ALL
A2 U7907 A1 P
P_CABLE DO_1V8
L
R7973 0 IN OUT 3P3V_PD_VIN R7960 DBG_TS 0.1 5 9 7901
C
V V 0603 3P3V_PD_VIN_R IN_3V3 DO_3V3 C7910
R7974 0 V L 10u 6.3V 4.7u
B2 B1 44
N ND C7908 [35] SAM_PD_HRESET
RESET 0402S_P7-W70 0402S_P65-W65
DNP C7921 E G 10u 6.3V H 20% 10V
1u NX3P1108UK 0402S_P7-W70 CP0_CC1 [77]
6 T
0201 PD_ADCIN1 DCIN1 CP0_CC2 [77]
10 ADCIN2 T
20% PD_ADCIN2 7930
R to guarantee MISO is
A high for PD controller to 3P3V_PD_OUT
+
16 24 detect SPI flash
[35,63] R7931 DNP 0 SAM_SL1_PWR_EN_PD PIO0 _CC1
+1P8V_PD_OUT SAM_SL1_PWR_EN 17 GPIO1 C_CC2 26
TP7914 PD_GPIO1
18
TP7915 PD_GPIO2 GPIO2 C
30 GPD/GPIO3
[10,77] TYPEC0_HPD 31 HPIO4
TP7901 PD_GPIO4
21
7920
C
7903
7912
R7930
R7906
R7910
R7904 R7905 R7916 DNP 0 I2C3_SCL22 G
2C3_SCL/GPIO5 0.1u
50
10K
10K
10K
10K 10K TP7912 R7919 DNP 0 I2C3_SDA23 I
2C3_SDA/GPIO6 _USB_P/GPIO18 10V
53
R7903
0201S_P28-W35 0201S_P28-W35 I
2C3_IRQ*/GPIO7 C_USB_N/GPIO19 7901
U 8
220p
220p
10K
[29,37,79] PD_SAM_DBG_ACC_MODE I C D_SPI_SS#
TP7909 28 54
P 1 S# CC
PD_I2C13_SDA R7933 0 I2C1_SDA 2C1_SDA PIO20 C V
27 I GPIO21 55 2
3P3V_PD_EN R7977 1K PD_I2C13_SCL R7934 0 I2C1_SCL 2C1_SCL D_SPI_MISO
P O/SIO1 OLD# 7
I G S H
33 6 D
R7924 0 I2C2_SDA 2C2_SDA 3 P# CLK P_SPI_CLK
R7970 [29,33,35] SAM_PD_SDA 32 I 7 W S
R7921 0 I2C2_SCL 2C2_SCL RAIN2_1 52 4 5
100K [29,33,35] SAM_PD_SCL I DRAIN2_2 D
P_SPI_MOSI
29 56 9 ND I/SIO0
R7902
1% +1P8VA +3P3V_PD_OUT TP7902 PD_I2C1_IRQ# 2C1_IRQ* DRAIN2_3 G
PAD S
34 57
10K
0201 PD_SAM_INT#_CTLR I
2C2_IRQ* DRAIN2_4 E
ALL I D
36 8 W25X05CLUXIGTR
C TP7903 PD_SPI_MISO R7913 0 P0_SPI_MISO_R PI_MISO/GPIO8 RAIN1_1 C
37 SPI_MOSI/GPIO9 DRAIN1_2 15 NP
D
R7981 PD_SPI_MOSI R7908 0
0201S_P28-W35 P0_SPI_MOSI_R
R7980 S DRAIN1_3 19
R7925 38 58
10K 100K PD_SPI_CLK P0_SPI_CLK_R DRAIN1_4
R7909 0
39 PI_CLK/GPIO10
10K ALL 1% PD_SPI_SS# R7907 0 P0_SPI_SS#_R SPI_SS*/GPIO11 D
0201 S 20
ND1 45
TP7904 R7956 0 GND2
G
[77] PD_USB2_MUX_FLIP 40 GND3 46

TP7908 PD_GPIO12
41 PIO12 47
D S TP7906 GPIO13 GND4
[34] PD_SAM_INT#
TP7907
[24] TCP0_OC#
R7918 0 PD_PROCHOT# 42 GPIO14/PW M GND5 51
[10] BC_PROCHOT# 43 GPIO15/PW M G DBG_N
USB_PD_GPIO16 48 GPIO16/PEXT1
Q7901 TP7910 49 59
7984
R 0
SOTFL-3_1P3XP9XP55_P4 TP7911 USB_PD_GPIO17 G
PIO17/PEXT2 PAD_GND
G M
PTPS65987DDJRSHT 1P8VA
+
PD_I2C13_SDA M1107289-001
+5VSB
+3P3V_PD_OUT PD_I2C13_SCL
R7940 7945
C
+5VSB 0.1u
10K +3P3V_PD_OUT 7908
U 10V
ALL 5 DBG_D
R7941 CC
R7942 +3P3V_PD_OUT 2 V 4
[35] SAM_3P3V_PD_EN A Y P
10K [29,37,79] 1 3 3V_PD_EN
10K PD_SAM_DBG_ACC_MODE B 3
G
ND
ALL R7943 G
S D 74LVC1G32GX
10K M1004687-001
https://vinafix.com
DBG_D
G
R7945
Q7902 R7901
2K DNP 100K
SOTFL-3_1P3XP9XP55_P4 S D 7983
R 7982
R
1% 1%
[24,77] APU_PD_SDA 100K 100K
0201
Q7903 PD_ADCIN1 1% 1%
[24,77] APU_PD_SCL SOTFL-3_1P3XP9XP55_P4 PD_ADCIN2 0201 0201
DBG_D DBG_D
B B
R7912 R7911
12.1K 0
1% ALL
+3P3VSB
ADCIN1: INTERNAL BUS POWER

BP_NoWait => 0.86 divider
ADCIN2: I2C SETTINGS

I2C1 = 0x20
I2C2 = 0x38
SAM_PD_HRESET R7953 10K ALL
TCP0_OC# R7920 10K ALL
R7952 49.9K DNP
Vinafix.com
A A
PD_USB2_MUX_FLIP R7968 49.9K ALL
5 4 3 2
5 4 3 2 1
H8009
D SPACER,BRASS,TALL,THERMAL MODULE,SM SPACER,COPPER,SHORT,THERMAL MODULE,SM D
MP8003 MP8004
1
MP8005 1 1 1
M1100762-001 1 1
PIN,LOCATING,TIN,STEEL,SM
M1110434-001 M1110435-001 3.00X6.00 MM SLOT
H8001 SLOT, PTH, 3.00X6.00 MM, 4.30 MM CIRCLE PAD
1 MP8001 MP8002
MH3.8x2.5d H8010
Mounting Hole c3.8x2.5dmm 1 1
1 1
1
1
M1110434-001 M1110435-001
SPACER,BRASS,TALL,THERMAL MODULE,SM SPACER,COPPER,SHORT,THERMAL MODULE,SM
H8003 3.00X5.00 MM SLOT
SLOT, PTH, 3.00X5.00 MM
H8011
1
1
1
1
MTG_HOLE_4.3padx3drill
X8003
H8002 H8007 H
SIELD 3.00X4.90 MM SLOT
X8002 1 SLOT, PTH, 3.00X4.90 MM
X8001 SHIELD 2
1 1 SHIELD 1 3
1 1 1 2 4
2 3 5
3 4 6 H8012
MTG_HOLE_4.3padx3drill MTG_HOLE_4.3padx3drill 4 5 7
8 NP
H8004 H8008 M1110426-001 M1110427-001
09
NO-MSPN-00324
1
ZID = 000 ZID = 000 1 MTG HOLE NPTH 2.50mm Diameter
ZOD = 000 ZOD = 000
1 1 SHIELD,FENCE,SM,T1 SHIELD,FENCE,SM,T2
C 1 1 M1110429-001 C
ZID = 000
ZOD = 000
MTG_HOLE_4.3padx3drill MTG_HOLE_4.3padx3drill SHIELD,FENCE,SM,T3
H8005
X8004 X8005 X8006
1 SHIELD SHIELD HIELD
S
1 1 1 1
MTG_HOLE_4.3padx3drill M1110432-001 M1110815-001 M1110816-001

ZID = 00 ZID = 00 ZID = 00
ZOD = 00 ZOD = 00 ZOD = 00
SHIELD,FENCE,SM,T4 SHIELD,FENCE,T5,SM SHIELD,FENCE,T6,SM
X8008
X8007
SHIELD SHIELD
1 1
2
3
M1110431-001 M1110425-001
ZID = 000 ZID = 00
ZOD = 000 ZOD = 00
https://vinafix.com
SHIELD,FENCE,SM,T7
SHIELD,FENCE,SM,B1
B B
A A
5 4 3 2
5 4 3 2 1
D D
C C
https://vinafix.com
B B
A A
5 4 3 2
5 4 3 2 1
D D
C C
B
A A
5 4 3 2

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Surface Laptop 3 MB HOOK-P - DV

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5 4 3 2 1

03 BLOCK DIAGRAM 33 Debug Conn 63 CHARGER

12 APU(3)_DLS_POWER1 42 Audio Smart Amp 72 +3P3V_HPD/LCD backlight

22 APU(8)_SYS PWR CONTR, I2C, HDA 52 EMPTY 82 EMPTY

BUILD-OPT BOM Assy Remarks

Architectural Diagram Hook-D Connector to Chimera:

Power Monitor Components

USB2 SPI ALC 3300 R ALC1304M

KBTP USB2[0_0] USB2

GPIO SAM U SBC I2C

SIGNAL & RESET MAP

U6302 U6601+FET +APU_VDDCORE

U5902 U5204 +1P2V_CAM_R

PCH_VDD_PANEL_EN / U5705 +1P8V_PANEL LDO ; Iout = 0.45A

+3P3V_PANEL U5203 +2P8V_CAM_F

I2C & SMBUS Map

PD_I2C2_SDA Redriver 0x0F PwrMonitor4

Ambient Light Skin Temp U3400

Skin Temp Host Auth

PE Sensor Host Auth

[66] VIDSOUT U1002

VCC [35] SAM_PROCHOT

SP_TP_SMDP58 TP1002 H_PROCHOT# 2 4 Q1001

NC1 3 0.1u 10V

C 1347 C 1343 C 1336 C 1329 C 1340

C 1364 C 1360 C 1349 C 1358 C 1337

20% 20% 20% 20% 20%

[11,16] M_A_A[16:0] U1601A

ZQL F9 ZQU DDQ10

0.1u 10V TBL1601

[11,17] _B_A[16:0] [11,17] _B_A[16:0]

R1713 39 Z QL F9 Z QU V DDQ10 V SSQ10

[11,17] M_B_DIM0_CLK0 R1705 39 TBL1601

R1803 R1802 R1810 R1805

GND GND APU_DBREQ# [10,76]

WIFI AM4 BA153.3 OUTPUT

AY1 BC18 3.3 PD

+ 1P8VSB Debug UART

3.3V logic level

1:USE 48MHZ CRYSTAL CLOCK AND

place close to TPM and UEFI chip

B U2102 DNP 10K B

0 DBG_N SPI_CLK_R1 TS3A27518ERTW

A Populate for production only A

C2202 R2242 R2240 R2044

3.3 S5 PUAW8 A GPIO3 AW10 3.3 S5 PD M

TP2208 R2213 E GPIO42 A GPIO4/SATAE_IFDET P

R2234 49.9K ISH_SAM_INT 100K

XTAL FREQUENCY SELECTION

0 Default Integrated CNVi Enabled

AK7 USB3 SL40 T9 V2

[65] +3P3V_PANEL_EN_R R7 P _GPP_RXP[6]/SATA_RXP0 P _GPP_TXP[6]/SATA_TXP0 V3

2801 DBG_TS 0.1

Address(7b) = 0x10 Address(7b) = 0x12 GND

C2902 R2913 0 DBG_D C2901

R2917 R2916 R2915 R2914

3017 22.1 DNP 3059 DNP 0.1uF V16

NX3008NBKMB R TP3002 B1 J8 3053 3031 0.033u G7 V9

XTAL,SM,48 MHZ,10 PPM,7 PF,2X1.6X0.45MM 3066 3040 H34

0402 DNP NT_HV4

603 603 603 VDD_1V8_1 NT_LV8 5V_TS

80 pin Sense Connector ND

60 pin Drive Connector J

R 5809 0201 0 PIN17=PIN2PIN12PIN3*PIN6