Study on Performance Optimization in VLSI

Floor planning and Partitioning using Nature-

Inspired Algorithms
A Term paper Report

Submitted in partial fulfilment of the requirements for

the award of the degree of

Masters of Technology
in
VLSI
by

Velamala Pavan Kumar

Reg. No.: 2301080008

Under the supervision of

Dr. Aravindhan Alagarsamy
Associate Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Koneru Lakshmaiah Educational Foundation

Green Fields, Vaddeswaram, Guntur (Dist)- 522502
Andhra Pradesh, India.
May, 2024
 TITLE:
Study on Performance Optimization in VLSI
Floor planning and Partitioning using Nature-
Inspired Algorithms
 Koneru Lakshmaiah Educational Foundation
Green Fields, Vaddeswaram
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Declaration

The TERM PAPER PROJECT Report entitled “Study on Performance Optimization in

VLSI Floor planning and Partitioning using Nature-Inspired Algorithms” is a record of
bonafide work of Velamala Pavan Kumar, submitted in partial fulfilment for the award of
M.Tech in course of Term Paper In Sem 2 to K L Deemed to be a University. The results
embodied in this report have not been copied from any other department/University/Institute.

Velamala Pavan Kumar (2301080008)

 Koneru Lakshmaiah Educational Foundation
Green Fields,Vaddeswaram
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Certificate

This is to certify that the Term Paper Report entitled “Study on Performance Optimization
in VLSI Floor planning and Partitioning using Nature-Inspired Algorithms” is being
submitted by Velamala Pavan Kumar submitted in partial fulfilment for the award of M.Tech
in TERM PAPER REPORT to K L Deemed to be a University is a record of bonafide work
carried out under our guidance and supervision.

The results embodied in this report have not been copied from any other
department/University/Institute.

Signature of the Guide Signature of the Research Head

Name : Dr Aravindhan Alagarsamy Name: Dr P.Pardhasaradhi
Designation: Associate Professor Designation:Associate Professor
Affiliation: KLEF, Vijayawada. Affiliation: KLEF, Vijayawada
 Acknowledgement

I would like to express my special thanks of gratitude to my guide Dr. Aravindhan

Alagarsamy as well as our VLSI Cohort head who gave me the golden opportunity to do this
wonderful project on the topic “Study on Performance Optimization in VLSI Floor
planning and Partitioning using Nature-Inspired Algorithms,” which also helped me in
doing a lot of Research and i came to know about so many new things I am really thankful to
them.

Secondly I would also like to thank my research head Dr P. Pardhasaradhi and friends who
helped me a lot in finalizing this project within the limited time frame.

Best Regards,

Velamala Pavan Kumar (MTECH (VLSI))

 Abstract

Circuits partitioning assumes a vital part in designing very large scale integration (VLSI) chips.
Circuit partitioning is a critical step in the front end design. The interest in finding an optimal
solution for partitioning in VLSI circuits has been a hot issue now days. In VLSI circuit
partitioning, the issue of getting a minimum cut, less interconnects, low power, minimum delay
and less area is included. In partitioning, a circuit is recursively divided into several subcircuits
so that each can be efficiently and independently designed with the main objective of reducing
the cut-cost. Partitioning is a first step in the very large-scale integration (VLSI) physical design
process, With the advancement in technology, the design complexity is increasing and the
circuit size is getting larger and larger so the physical design becomes very important. Floor
planning is the starting point of VLSI physical design flow. It determines the locations and
dimensions of blocks in a chip so as to minimize the chip area and interconnect wirelengths
and all the other physical design steps such as placement, pin assignment, and routing depend
on its outcome. The partitioning determines the overall quality of the final layout, since the use
of an incorrect partitioning can degrade the performance of all subsequent phases of the
physical design process.

Keywords

Partitioning, floor planning, Cut Cost, Nature Inspired algorithms, Genetic Algorithm,
Simulated Annealing, Particle Swarm Optimization, Ant Colony Optimization.
 Contents

1. INTRODUCTION

1.1 Introduction to partitioning

1.2 Introduction to floor planning

2. LITERATURE SURVEY

3. NATURE INSPIRED ALGORITHMS

4. NATURE INSPIRED ALGORITHMS IN VLSI CIRCUIT PARTITIONING

5. NATURE INSPIRED ALGORITHMS IN VLSI CIRCUIT FLOOR

PLANNING

6. CONCLUSIONS
 1 INTRODUCTION
1.1 Introduction to partitioning
In the development of modern fabrication technology, the complexity of VLSI circuits design
increases drastically. To decrease the complexity of design in VLSI an effective method is used
in the circuit partitioning rule. The specific implementation is splitting the complex circuit into
several sub-circuits so that each sub-circuit can be designed independently. Due to the
substantial advances in very large-scale integration technology, integrated circuits have
become more and more complicated. This creates a great challenge for very large-scale-
integrated (VLSI) physical design automation. The advancement in VLSI semiconductor
technology has led to a phenomenal development in electronic systems, with the reduction in
device sizes, a very large number of transistors can fit onto a single chip. VLSI circuit
partitioning has various objectives. Two main objectives of VLSI circuit partitioning are the
minimization of cut cost and minimizing the number of interconnections. Optimizing one
design aspect may lead to performance degradation in others. The marketing window has
become very narrow such that delivering the product to market in the right time is a company
survival issue. Physical design has several stages. First of them is circuit partitioning whose
results will be used directly in placement, routine and other stages of physical design.
Therefore, circuit partitioning is a very important stage in the VLSI physical design. Circuit
partitioning has been proved to be NP-hard , and hence, it is very difficult to get the optimal
solution. Numerous optimization algorithms have been applied to solve partitioning problem.
According to the optimization strategy, these techniques are mainly classified into clustering
algorithms and iterative improvement algorithms which include simulated annealing procedure
, genetic algorithm ,Tabu Search heuristic algorithm and so on. However, these algorithms have
shortages of low efficiency and local optimum. Moreover, iterative improvement algorithms
have the problem of slow convergence.

As the density of chips escalates, several challenging issues, such as design simplicity, testing,
augmented delay, and area optimization of interconnects, occur requiring management in the
initial stage of the design process. Enhanced tools for the physical design are essential to
manage these challenges. The partitioning of the net-list of the circuit is a principal step in the
physical design of VLSI circuits. This comprises breaking down a circuit into subcircuits to
simplify the design, layout, and testing.
 1.2 Introduction to floor planning
The floor planning stage ensures that (1) every chip module is assigned a shape and a location,
so as to facilitate gate placement, and every pin that has an external connection is assigned a
location, so that internal and external nets can be routed.

The floor planning stage determines the external characteristics - fixed dimensions and external
pin locations - of each module. These characteristics are necessary for the subsequent
placement and routing steps, which determine the internal characteristics of the blocks.
Floorplan optimization involves multiple degrees of freedom; while it includes some aspects
of placement (finding locations) and connection routing (pin assignment), module shape
optimization is unique to floor planning. Floor planning with hard blocks is particularly
relevant when reusing pre-existing blocks, including intellectual property (IP). Mathematically,
this problem can be viewed as a constrained case of floor planning with soft parameters, but in
practice, it may require specialized computational techniques. There are two types of
floorplans.

Slicing Floorplan: Slicing structure can be obtained by repetitively cutting the floorplan
horizontally or vertically. Fig.1 shows the structure of slicing floorplan.

Non-Slicing Floorplan: Non slicing floorplan is more common than slicing floorplan. All the
children of the given cell cannot be obtained by bisecting the floorplan. This is called nonslicing
floorplan
fig 2.

Figure 1: slicing floorplan Figure 2: Non slicing floorplan

Area and shape of the global bounding box. The global bounding box of a floorplan is the
minimum axis-aligned (isothetic) rectangle that contains all floorplan blocks. The area of the
global bounding box represents the area of the top-level floorplan (the full design) and directly
impacts circuit performance, yield, and manufacturing cost. Minimizing the area of the global
bounding box involves finding (x,y) locations, as well as shapes, of the individual modules
such that they pack densely together. Beyond area minimization, another optimization
objective is to keep the aspect ratio of the global bounding box as close as possible to a given
target value. For instance, due to manufacturing and package size considerations, a square chip
(aspect ratio | 1) may be preferable to a non-square chip. To this end, the shape flexibility of
the individual modules can be exploited. Area and aspect ratio of the global bounding box are
interrelated, and these two objectives are often considered together. Total wirelength. Long
connections between floorplan blocks may increase signal propagation delays in the design.
Therefore, layout of high-performance circuits seeks to shorten such interconnects. Switching
the logic value carried by a particular net requires energy dissipation that grows with wire
capacitance. Therefore, power minimization may also seek to shorten all routes. A third context
for wirelength minimization involves routability and manufacturing cost. When the total length
of all connections is too high or when the connections are overly dense in a particular region,
there may not be enough routing resources to complete all connections. Although circuit blocks
may be spread further apart to add new routing tracks, this increases chip size and
manufacturing cost, and may further increase net length.

Representation Schemes for Floorplan:

i)Sequence Pair.

ii) Polish Notations.

iii) Bounded Slicing Grid (BSG).

iv) B* Tree (ordered binary tree).

v) Transitive Closure Graph (TCG).

floor planning determines the locations of modules so that goals like minimum area and
minimum total interconnect wirelength can be achieved. There are various heuristics and
metaheuristic Algorithms used with different representation methods (like-B*tree, O-tree,
CBL, Sequence pair etc). These algorithms are Genetic Algorithms, Simulated Annealing,
Particle Swarm Optimization, Ant Colony Optimization, Differential Evolution Algorithm etc.
 2 LITERATURE SURVEY

[1] A survey on an optimal solution for VLSI circuit partitioning in physical

design using DPSO & DFFA algorithms

The authors in [1], investigating an overview of getting a minimum cut using, a Discrete
Particle Swarm Optimization (DPSO) algorithm and a swarm based heuristic approach called
as Discrete Fire Fly Algorithm (DFFA). This paper provides a clear results comparison
between Genetic algorithm and DFFA. Experimental results shows that DPSO algorithm has
better performance of global searching and can obtain better partitioning results compared with
the conventional GA.

[2] An efficient VLSI circuit partitioning algorithm based on satin

bowerbird optimization (SBO)
The authors in [2] solved the circuit portioning problem is by splitting a set of vertices into
two or more subsets with the objective of reducing the number of interconnections between
them. Various bioinspired heuristic algorithms such as ant colony optimization, particle swam
optimization, the genetic algorithm, and the frefy algorithm are used to perform the
partitioning. Different performance parameters such as the minimum cut-cost,
interconnections, and time complexity are analysed using ISCAS’85 benchmark circuits such
as C17, C432 and C499, in addition to investigation of the delay and area. A novel partitioning
algorithm based on the SBO concept is also proposed and its performance parameters studied.
The comparative analysis reveals that the proposed SBO algorithm outperforms all the other
bioinspired algorithms.

[3] A Connectivity Based Clustering Algorithm With Application to VLSI

Circuit Partitioning
The goal of the suggested clustering method is to identify naturally occurring clusters in a
circuit, or collections of closely coupled cells. Thus, large-scale partitioning problems can be
made smaller using the suggested clustering strategy without sacrificing the quality of the
partitioning solution. The suggested clustering algorithm's performance is assessed on an
ISPD98 benchmark suite. The experimental findings demonstrate that the previously published
best partitioning solutions from cutting-edge partitioners are further improved by using the
suggested clustering approach.
[4] Partitioning Algorithm to Enhance Pseudo exhaustive Testing of Digital
VLSI Circuits
Contents : Digital VLSI circuits, partitioning, primary input cones and fanout (PIFAN),
pseudoexhaustive, testing.

The primary input cones and fanout partitioning algorithm has been demonstrated to be an
effective tool for partitioning of large combinational and scan-based sequential circuits for
pseudoexhaustive testing. ISCAS85 and ISCAS89 benchmark circuits containing up to 5597
gates have been successfully partitioned using the PIFAN algorithm; and, when compared with
other partitioning algorithms, PIFAN was superior. Future work to improve the PIFAN
algorithm includes automating the determination of an optimal P I value n. Additional work is
also needed to minimize the added hardware on real chips. In addition, further research is
needed to develop a concurrent testing strategy so that as many subcircuits as possible can be
tested in parallel.
[5] Multi-Way Partitioning of VLSI Circuits
Contents : K-VIA-FM, MCNC bench marks
The authors introduced a new natural metric, Via-Count, to better estimate inter-partition
delays for evaluating partitioning solutions. They presented K-VIA-FM, an algorithm that
iteratively improve solutions for the new metric. They compared the performance of K-VIA-
FM with other algorithms, both with respect to the new metric as well as the number of nets
cut. In fact, their results show that in multi-partitioning cases, minimizing the number of vias
reduced the number of nets cut. Future work will explore network flow-based approaches to
optimize the new metric. Also, we hope to use signal directionality information to incorporate
a better delay estimating gain computation model into the partitioning phase. Another potential
direction is to compare actual routing results when using existing partitioning algorithms
against K-VIA-FM.

[6] Multio bjective algorithm for k-way equipartitioning of a point set

Contents: Multi objective algorithm for k-way equipartitioning of a point set
The authors of this work talked about a class of applications that deal with partition
identification among a group of physical elements. These applications have the distinguishing
quality that separates them from in addition to the conventional condition of equipartition, a
number of other goals need to be maximized. One of the application domains where the
suggested technique is tried is the identification of flip-flop partitions to help with clock tree
synthesis in the low power design of nanoscale integrated circuits. Findings on many artificial
data sets and reference circuits from the CAD VLSI field demonstrate that evolutionary
algorithms are an efficient method for multiobjective optimization.
[7] Evolutionary algorithms for VLSI multi-objective netlist partitioning
Contents: Genetic Algorithms (GAs), Tabu Search (TS) and Simulated Evolution (SimE),
Multi-objective; Fuzzy logic; Netlist partitioning, PowerFM

The authors in [7] iterative algorithms for multi-objective optimization namely GA, TS and
SimE for VLSI partitioning were proposed. For most of the circuits, SimE achieved
significantly better results than TS and GA. For the large circuits, the superiority of SimE in
achieving higher quality solutions is highlighted. This is attributed to the smart strategy of the
algorithm in selecting badly assigned cells and attempting to assign them in better partitions.
Further, they compared the results of iterative heuristics with the modified FM algorithm,
named PowerFM, which targets power optimization. It was observed that SimE performs better
than PowerFM in terms of delay DðpsÞ and the number of net cuts Cut for all benchmark
circuits

Limitations: PowerFM performs better in terms of power dissipation PðspÞ up to circuit

S2081 when compared to SimE. For larger sized circuits (from S3330 to S15850) SimE
outperforms PowerFM in terms of all three, delay, number of net cuts, and power dissipation

[8] A Novel Approach to find the best fit for VLSI Partitioning - Physical
Design
Contents: memetic algorithm, genetic algorithm, delay, cut size, benchmarks.

The experimental results which obtained by authors in [8] states that it will compare the
performance of a pure genetic algorithm to a memetic technique that combines GA with simple
local search techniques Simulated Annealing. This paper explores the advantage of memetic
algorithm which can be proven to seven times faster than the simple software genetic algorithm.
The implementation of multi objective in the algorithm enables us to get the near optimal
solution

Limitations: After a predetermined number of iteration by GA, local search is applied to few
random individual to get this optimal solution by Simulated Annealing.
[9] A New Efficient Layer Assignment Algorithm for Partitioning in 3D
VLSI Physical Design
Contents: Partitioning, Layer, Max-cut, Wire length, Adjacency matrix.
The authors in this paper have considered the problem of layer assignment for partitioning in
3D VLSI physical design and developed an efficient algorithm for solving the same. In case of
3D partitioning, they have to assign the final partitions obtained for a given initial partition to
different layers, and for that purpose they have to take care of the interconnections among the
non-adjacent layers. Here they also reduce the total wire length among non-adjacent layers, as
reduction of interconnection among non-adjacent layers also reduces the total wire length. they
have also computed some experimental results, and these results are interesting in comparison
to other layer assignment algorithms, like EV, the matrix algorithm. this algorithm will work
well in general for generating desired results for other benchmark instances
Limitations: This can be applicable for small scale circuits.

[10] VLSI Circuit Partition Using Simulated Annealing Algorithm

Contents: Simulated Annealing, circuit partitioning,
The Authors in [10] proposed that two-way partitioning of a circuit represents as a graph, they
made using simulated annealing procedure. The parameters used in annealing process: initial
temperature, cooling rate and the time of a process, given as a number of calculations, are
changed and its influence on the cost function (number of nets cut by partition) are described.
With a proper choice of the initial temperature and the cooling rate thry can obtain a good, not
necessarily the best solution, not spending too much time to find it out. Procedure was tested
on an example with 1000 components connected by 300 nets. They conclude that all parameters
depend on a circuit itself (its size and number of interconnections).
Limitations: the obtained solution will be close to optimal but no exact.
[11] A Survey on VLSI Floor planning: Its Representation and Modern
Approaches of Optimization
Contents : Floor planning, B* Tree, Sequence Pair, Particle Swarm Optimization,
Genetic Algorithm, Differential Evolution.
The authors says that so far that DE algorithm based on Sequence Pair has been effective in
solving area optimization problem in Floorplan , while PSO based on B* Tree also gives good
results and is a good option. For multi-objective Area and Wirelength optimization PSO based
approaches have yielded better results so far. Some of the new hybrid versions of these could
be a very good option for floorplan optimization. As VLSI Floor planning is a NP hard problem.
 3 NATURE INSPIRED ALGORITHMS
an algorithm is a step-by-step procedure of providing calculations or instructions. Many
algorithms are iterative. The actual steps and procedures depend on the algorithm used and the
context of interest. However, in this book, we mainly concern ourselves with the algorithms
for optimization, and thus we place more emphasis on iterative procedures for constructing
algorithms.

Simulated Annealing

The simplest stochastic algorithm is probably the so-called simulated annealing, developed by
Kirkpatrick et al. in 1983 based on the characteristics of the metal annealing process. From the
current solution or state xi , a new solution xj is accepted with a probability.

The original article by Kirkpatrick et al. demonstrated how to solve very challenging problems.
However, generating new solutions xj from the current solution may depend on the
implementation and problem of interest. Whatever the ways of generation might be, such
generations of new solutions form a Markov chain, or more specifically, a random walk.
Therefore, the main operator is to generate new solutions by random walks, and consequently
randomization acts as a mutation or explorative search mechanism. Selection is achieved by
testing whether a solution is getting better (smaller for a minimization problem). Strictly
speaking, simulated annealing is not an evolutionary algorithm, and thus there is no crossover
operator in this algorithm. In addition, exploitation is relatively weak because the acceptance
is carried out by a probability condition. That is why simulated annealing often converges very
slowly in practice, though it is good at exploration and often has a good property of finding the
global optimality at the expense of a large number of function evaluations.

Genetic Algorithms

Genetic algorithms(GA), developed by John Holland , essentially form the foundations of

modern evolutionary computing. GA has three key genetic operators: crossover, mutation, and
selection, as discussed earlier. Though there are no explicit mathematical equations in the
original genetic algorithm, it did provide detailed procedures and steps on how to generate
offspring from parent solutions/strings. Crossover helps exploit and enhance the convergence.
From empirical results and theoretical studies, all suggest a relatively higher probability pc for
crossover in the range of 0.6 to 0.95, whereas the mutation probability pm is typically very
low, around 0.001 to 0.05. These values correspond to a high degree of mixing and exploitation
and a relatively lower degree of exploration. In practice, this means that genetic algorithms can
often converge well and in many cases the global optimality can be achieved easily. The
selection or survival of the fittest provides a good mechanism to select the best solution; elitism
can guarantee that the best solution will remain in the population, which will enhance the
convergence of the algorithm. However, the global optimality will be reachable under certain
conditions, and mutation can be considered a double edged sword; it can increase the
probability of finding the global optimality while at the same time slowing down the
convergence.

Differential Evolution

Differential evolution (DE) was developed by R. Storn and K. Price in 1996 and 1997. In fact,
modern DE has strong similarity to the traditional mutation operator in the traditional pattern
search. In fact, the mutation in DE can be viewed as the generalized pattern search in any
random direction (xp − xq ) by

xi = xr + F(xp − xq ),

where F is the differential weight in the range of [0, 2]. Here r, p, q,i are four different integers
generated by random permutation. In addition, DE also has a crossover operator that is
controlled by a crossover probability Cr ∈ [0, 1], and the actual crossover can be carried out in
two ways: binomial and exponential. Selection is essentially the same as that used in genetic
algorithms. It is to select the most fit, and, for the minimization problem, the minimum
objective value.

Ant and Bee Algorithms

Ant algorithms, especially the ant colony optimization developed by M. Dorigo , mimic the
foraging behaviour of social ants. Primarily, all ant algorithms use pheromone as a chemical
messenger and the pheromone concentration as the indicator of quality solutions to a problem
of interest. From an implementation point of view, solutions are related to the pheromone
concentration, leading to routes and paths marked by the higher pheromone concentrations as
better solutions to questions such as discrete combinatorial problems. Looking closely at ant
colony optimization, we see that random route generation is primarily mutation, whereas
pheromone-based selection provides a mechanism for selecting shorter routes. There is no
explicit crossover in ant algorithms. However, mutation is not as simple an action as flipping
digits in genetic algorithms; the new solutions are essentially generated by fitness-proportional
mutation.

Both ACO and ABC use only mutation and fitness-related selection, and they can have good
global search ability. In general, they can explore the search space relatively effectively, but
convergence may be slow because it lacks crossover, and thus the subspace exploitation ability
is very limited. In fact, the lack of crossover is very common in many metaheuristic algorithms.
In terms of exploration and exploitation, both ant and bee algorithms have strong exploration
ability, but their exploitation ability is comparatively low. This may explain why they can
perform reasonably well for some tough optimization, but the computational efforts, such as
the number of function evaluations, can be very high.

Particle Swarm Optimization

Particle swarm optimization (PSO) was developed by Kennedy and Eberhart in 1995 based on
swarm behaviour, such as fish and bird schooling in nature. In essence, the position and
velocity of a particle, xi and vi , respectively, can be updated as follows:

where E1 and E2 are two random vectors and with each entry taking the values between 0 and
1. The parameters α and β are the learning parameters or acceleration constants, which can
typically be taken as, say, α ≈ β ≈ 2. By comparing the previous equations with the pattern
search in Section 2.3, we can see that the new position is generated by a pattern-search-type
mutation, whereas selection is implicitly done by using the current global best solution g∗
found so far as well as through the individual best x∗ i . However, the role of individual best is
not quite clear, though the current global best seems very important for selection, as is shown
in the accelerated particle swarm optimization. Therefore, PSO consists of mainly mutation
and selection. There is no crossover in PSO, which means that PSO can have high mobility in
particles with a high degree of exploration. However, the use of g∗ seems strongly selective,
which may be like a double-edged sword. Its advantage is that it helps speed up the
convergence by drawing toward the current best g∗, while at the same time it may lead to
premature convergence, even though this may not be the true optimal solution of the problem
of interest.

The Firefly Algorithm

The firefly algorithm (FA) was developed by Xin-She Yang in 2008 and is based on the
flashing patterns and behaviour of tropical fireflies. FA is simple, flexible, and easy to
implement. The movement of a firefly i is attracted to another, more attractive (brighter) firefly
j as determined by

One novel feature of FA is that attraction is used, the first of its kind in any SI based algorithm.
Since local attraction is stronger than long-distance attraction, the population in FA can
automatically subdivide into multiple subgroups, and each group can potentially swarm around
a local mode. Among all the local modes, there is always a global best solution that is the true
optimality of the problem. FA can deal with multimodal problems naturally and efficiently.

The Flower Algorithm

The flower pollination algorithm (FPA) was developed by Xin-She Yang in 2012, inspired by
the flower pollination process of flowering plants. It has been extended to multiobjective
optimization problems and found to be very efficient. For simplicity, we use the following four
rules:

1. Biotic and cross-pollination can be considered global pollination process, and pollen
carrying pollinators move in a way that obeys Lévy flights (Rule 1).

2. For local pollination, abiotic pollination and self-pollination are used (Rule 2).

3. Pollinators such as insects can develop flower constancy, which is equivalent to a

reproduction probability that is proportional to the similarity of two flowers involved (Rule 3).

4. The interaction or switching of local pollination and global pollination can be controlled by
a switch probability p ∈ [0, 1], with a slight bias toward local pollination (Rule 4).

Selection is achieved by choosing the best solutions and passing them on to the next generation.
It also explicitly uses g∗ to find the best solution as both selection and elitism. There is no
explicit crossover, which is also true for many other algorithms such as particle swarm
optimization and harmony search.
 4 NATURE INSPIRED ALGORITHMS IN VLSI CIRCUIT PARTITIONING
Circuits partitioning assumes a vital part in designing very large scale integration (VLSI) chips.
Circuit partitioning is a critical step in the front-end design. The interest in finding an optimal
solution for partitioning in VLSI circuits has been a hot issue now days.

The use of the genetic algorithm (GA) to address the circuit partitioning problem (CPP) is
summarized below. The GA begins with an original population of partitions. An ofspring
population of partitions is generated in each generation using a crossover operation between
the two par ent partitions at a particular crossover site. The mutation operation is also applied
by modifying the genetic structure of some chosen partitions in the parent population of each
generation. A set of partitions is then chosen from the origi nal and ofspring populations to
act as the original popula tion for the next generation. This procedure is continued for several
generations. Finally, the best partition is obtained from the population and picked as the fnal
result of the CPP.

Fig. 3: The GA process for circuit partitioning

firefly algorithm

Yang from Cambridge University proposed the frefy algorithm (FA), a new metaheuristic
motivated by the behavior of frefies. It is a Nature-inspired algorithm that was initially
developed to solve optimization problems. The use of the FA for solving the circuit partitioning
problem is proposed herein. This section summarizes several aspects of the algorithm. The
solution architecture for circuit partitioning is based on the transformation depicted in Fig. 4,
where a solution instance represents a frefy. Any frefy representation contains the elements of
an array that describes a gate (node), where the array size is the total number of vertices (nodes)
of the CPP. In the case of bipartitioning, the frst half of the original array elements are
designated the value 0 corresponding to partition 1 while the other half are designated the value

1 corresponding to the other partition, fulflling the balance constraint based on the total size of
the array.

Fig.4 The FA process for circuit partitioning

particle swarm optimization

PSO is a computation method based on evolution, formulated by Kennedy and Eberhart . It is

inspired by the social behavior of animals, namely focking birds and schooling fsh, termed
swarm theory. In the PSO algorithm, the prospective solutions, which are termed “par ticles,”
circle the exploration space to determine an opti mum particle through cooperation and
competition. The model starts with a random population of particles.

satin bowerbird optimization

In the SBO algorithm, adult males start to construct a bower (nest) using various objects from
their environment during the breeding period. They use all kinds of things, namely twigs, fruits,
flowers, and gleaming materials, plus theatrical gestures that display all parts of their body to
allure females. Because of the charm of the bower and theatrical gestures displayed by a male,
females are allured its bower. Male birds instinctively exercise and also imitate other males to
construct their bower.
5. NATURE INSPIRED ALGORITHMS IN VLSI CIRCUIT FLOOR
PLANNING

3D floor planning with the help of hybrid multi-verse optimizer. The nodes of the two modules
were used to optimize the designing problems in the manufacturing of the IC. This optimization
process was mainly used in the floor planning designing process. The presented method was
used to decrease the wire length and the area in the 3D IC circuits.

optimization of TSV Aware 3D IC Partitioning and decreased the area of the IC. The method
was used to optimize the area and the through-silicon-via (TSV). Moth flame optimization
approach was used to optimize the above issue. The area was minimized efficiently.

An effective circuit partitioning algorithm with the satin bowerbird optimization (SBO). While
designing the VLSI circuits, the partitioning was the first step. Then the design process consists
of the floor planning, placement, pin assignment, and routing based on the results. The
presented method used to minimize the cut cost and time complexity through the benchmark
circuits such as area, power and delay performance was evaluated.

The particle swarm optimizing (P-PSO) algorithm was used for the optimization of floor
planning and area. The fabrication was based on the performance, size, yield, and reliability.
The presented method was used to reduce non-polynomial hard then optimize the problems
based on the P-PSO algorithm. The experimental results show the reduced delay and size.

A heuristic approach to evaluate the performance of optimization algorithms in VLSI floor

planning for ASIC Design. The aim was to investigate certain approaches which add to the
problem of managing alignment limitations, like excellent position, optimal region, brief
runtime. To address the VLSI Floor Plan problem, numerous scientists suggested various
heuristic algorithms as well as unique metaheuristic algorithms. Simulated Annealing, ant
colony optimization, tab search, genetic optimization algorithm were solved. The presented
model provides higher area value but the wire length was low.

A VLSI Floor planning utilizing nature-inspired Hybrid Optimization approach. The dual
objective floor planning was presented, wherein lessening floor plan area together with routing
wire length. To the intention, bio-inspired optimization approaches were considered which was
either populationor intelligence-based. It provides higher delay and takes longer time to
complete the action.
Multiple objective optimizations for energy with heat-aware VLSI floor planning depending
on improved firefly optimization. To upgrade the floor planning performance along minimal
energy consumption, heat generation, the presented MOFO-FP method was used. The aim was
to decrease the heat production; space occupied, wire length along fixed and activated by
energy and heat-aware firefly optimization (EHAFO) approach. The results reveal that it
attained better outcome in area but delay was high.

A nature-inspired optimization algorithm for VLSI fixed-outline floor planning. For

manipulating floor plan optimization issue, the “Lion Optimization Algorithm” (LOA) was
considered for nonslicing floor plans containing soft modules along the constraints of fixed-
outline. Several GAs were created to address VLSI floor plan optimization issues, but they still
used a weighted sum technique with single goal optimization and have not yet attempted
crossover between two B * tree structures. The power of B * tree crossover operator for multi-
objective floor planning issue was illustrated. It provides higher area with lower delay but the
computation time was high.

A comparative study of moth-flame along whale optimization for optimum spur gear. The
presented algorithms were employed to enhance the spur gear design. The aim was to decrease
the overall weight of the pair of spur gear. The optimization issue was subject to limitation on
major kinematic and geometric situations together with the resistance of gear system. It
provides higher wire length with lower delay. However, this model attained lower performance
due to high complexity.

A comparison of metaheuristic optimization approaches for handling constrained mechanical

designing optimization issues. The characteristics of 9 metaheuristic algorithms were analyzed:
salp swarm, multi-verse optimizer, moth-flame optimizer, atom search optimization,
ecogeography-based optimization, queuing search, equilibrium optimizer, evolutionary
strategy, hybrid self-adaptive orthogonal genetic. It provides higher area with lower delay, but
time complex of floor planning was not decreased.

A comparison of the algorithms of political optimization, Archimedes optimization and Levy

flight for designing optimization in industry. It focused on lessening product costs by utilizing
the presented algorithms in the process of product development.
 6 conclusions
Optimal Partitioning and Floor Planning for the VLSI Circuit Design depending on Nature
inspired algorithms gives a minimum cut cost circuits and area efficient chips. Nature-inspired
algorithms excel in searching large solution spaces efficiently, which is crucial for the intricate
and high-dimensional problems in VLSI circuit design. The circuit portioning problem is
solved by splitting a set of vertices into two or more subsets with the objective of reducing the
number of interconnections between them. Various bioinspired heuristic algorithms such as ant
col ony optimization, particle swam optimization, the genetic algorithm, and the firefly
algorithm are used to perform the partitioning. Different performance parameters such as the
minimum cut-cost, interconnections, and time complexity are analysed. These algorithms can
adapt to various constraints and objectives, making them versatile tools for different aspects of
VLSI design.