Introduction to CMOS VLSI Design

Lecture 18: Design for Low Power

David Harris

Harvey Mudd College Spring 2004

Outline
q q q q Power and Energy Dynamic Power Static Power Low Power Design

18: Design for Low Power

CMOS VLSI Design

Slide 2

Power and Energy

q Power is drawn from a voltage source attached to the VDD pin(s) of a chip. q Instantaneous Power: P(t ) = iDD (t )VDD q Energy: q Average Power:

E = P ( t )dt = iDD (t )VDD dt

0 0

Pavg

E 1 = = iDD (t )VDD dt T T 0

18: Design for Low Power

CMOS VLSI Design

Slide 3

Dynamic Power
q Dynamic power is required to charge and discharge load capacitances when transistors switch. q q q q One cycle involves a rising and falling output. On rising output, charge Q = CVDD is required On falling output, charge is dumped to GND VDD This repeats Tfsw times iDD(t) over an interval of T
fsw
18: Design for Low Power CMOS VLSI Design

Slide 4

Dynamic Power Cont.

Pdynamic =

VDD iDD(t)

fsw
18: Design for Low Power CMOS VLSI Design

Slide 5

Activity Factor
q Suppose the system clock frequency = f q Let fsw = f, where = activity factor If the signal is a clock, = 1 If the signal switches once per cycle, = Dynamic gates: Switch either 0 or 2 times per cycle, = Static gates: Depends on design, but typically = 0.1 q Dynamic power:
18: Design for Low Power

Pdynamic = CVDD 2 f
CMOS VLSI Design Slide 7

Short Circuit Current

q When transistors switch, both nMOS and pMOS networks may be momentarily ON at once q Leads to a blip of short circuit current. q < 10% of dynamic power if rise/fall times are comparable for input and output

18: Design for Low Power

CMOS VLSI Design

Slide 8

Example
q 200 Mtransistor chip 20M logic transistors Average width: 12 180M memory transistors Average width: 4 1.2 V 100 nm process Cg = 2 fF/m

18: Design for Low Power

CMOS VLSI Design

Slide 9

Dynamic Example
q Static CMOS logic gates: activity factor = 0.1 q Memory arrays: activity factor = 0.05 (many banks!) q Estimate dynamic power consumption per MHz. Neglect wire capacitance and short-circuit current.

18: Design for Low Power

CMOS VLSI Design

Slide 10

Static Power
q Static power is consumed even when chip is quiescent. Ratioed circuits burn power in fight between ON transistors Leakage draws power from nominally OFF devices
Vgs Vt

I ds = I ds 0 e

nvT

Vds vT 1 e

Vt = Vt 0 Vds +
18: Design for Low Power

s + Vsb s

)
Slide 12

CMOS VLSI Design

Ratio Example
q The chip contains a 32 word x 48 bit ROM Uses pseudo-nMOS decoder and bitline pullups On average, one wordline and 24 bitlines are high q Find static power drawn by the ROM = 75 A/V2 Vtp = -0.4V

18: Design for Low Power

CMOS VLSI Design

Slide 13

Leakage Example
q The process has two threshold voltages and two oxide thicknesses. q Subthreshold leakage: 20 nA/m for low Vt 0.02 nA/m for high Vt q Gate leakage: 3 nA/m for thin oxide 0.002 nA/m for thick oxide q Memories use low-leakage transistors everywhere q Gates use low-leakage transistors on 80% of logic
18: Design for Low Power CMOS VLSI Design Slide 15

Leakage Example Cont.

q Estimate static power:

18: Design for Low Power

CMOS VLSI Design

Slide 16

Low Power Design

q Reduce dynamic power : C: VDD: f: q Reduce static power

18: Design for Low Power

CMOS VLSI Design

Slide 19