2.

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND

DEMULTIPLEXER

Aim:

To design and implement multiplexer and De-multiplexer using logic gates and

studyofiC 74150 and IC 74154.

Apparatus Required:

|SI.No. Component Specification Qty.

1. 3 VP AND GATE IC 7411 2

2 ORGATE IC 7432

3. NOT GATE IC7404

2. IC TRAINER KIT 1

3.
PATCH CORDS 32

Theory:
MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a smaller

number of channels or lines. A digital multiplexer is a combinational circuit that selects

binary information from one of many input lines and directs it to a single output line. The

selection of a particular input line is controlled by a set of selection lines. Normally there

are 2 input line and n selection lines whose bit combination determine which input is

selected.

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to multiplexer function. It takes

information from one line and distributes it to a given number of output lines. For this

reasen, the demultiplexer is also known as a data distributor. Decoder can also be used

as demultiplexer.
 In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates.
The dataselect lines enable only one gate at a time and the data on the data input line will

pass through theselected gate to the associated data output line.

Block Diagram for 4:1 Multiplexer:

DO 4x1 DATA OIP

DATAIP D1
D2 MUX
D3-

$1 $0
DATA SELECT

Function Table:

S1 SO INPUTS Y
DO DOS1
SO
D1 D1 S1 S0

0 D2 D2S1 SO
D3 D3 1 SO

Y DO S1' so' +D1 S1' S0+ D2 S1 S0' +03 S1 SO

Circuit Diagram For Multiplexer

S1 DO D1 D2 D3

7404 7404

74LS11

7432

74LS11
Y

7432

74LS11

7434

74L311

Truth Table:

S1 SO Y= OUTPUT
0 DO

D1

D2

D3
Block Diagram for 1:4 Demultiplexer:

1x4
DO
DATAUP DEMUX
D1
DATA OIP
D2
> D3

$1 so
DATA SELECT

Function Table

SO INPUT

X DO -XS1
SO'
X D1 =XST SO
X-D2 XS1 SO
1 X D3=XS1 SO

Y XS1' s0 +XS1' S0+X$1 SO +XS1 S0

Logic Diagram for Demultiplexer

s1 UP

7 7404 7404

DO

74L311

D1

74LS11

D2

74LS1l

D3

74LS11

Truth Table

INPUT OUTPUT

$1 SO /P DO D1 D2 D3
 0 0

0 0 0 0

1 U

Pin Diagram for IC 74150:

E7 1 24 VCC
2 23 E8

E5 22 E9

E4 4 21E10
20 E11
E3 5

19 E12
E2

E1 18E13
EO 17E14
ST 16E155
15 A
10
14- B
D
11
GND12 13 C
Pin Diagram for IC 74154:

Q0 1
24vcc
01 2
23 A

02

03 4
20-H D
Q4 5

Q5 19FE2
18 FE1
Q6

Q7
17015
16 Q14
08 9

Q9 10 15Q13
14 012
Q10-11
Q11
GND12 13

Procedure
Connections are given as per circuit diagram.
i) Logical inputs are given as per circuit diagram.

(i) Observe the output and verify the truth table.

Result:
Thus, the multiplexer and De-multiplexer was designed using logic gates and implement.