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MC33274ADG
MC33274ADG
NCV33272A, NCV33274A
Single Supply,
High Slew Rate,
Low Input Offset Voltage
Operational Amplifiers http://onsemi.com
MARKING
The MC33272/74 series of monolithic operational amplifiers are
DIAGRAMS
quality fabricated with innovative Bipolar design concepts. This dual
and quad operational amplifier series incorporates Bipolar inputs DUAL
along with a patented Zip−R−Trim element for input offset voltage 8
reduction. The MC33272/74 series of operational amplifiers exhibits PDIP−8 MC33272AP
low input offset voltage and high gain bandwidth product. P SUFFIX AWL
Dual−doublet frequency compensation is used to increase the slew rate CASE 626 YYWWG
8
while maintaining low input noise characteristics. Its all NPN output 1 1
stage exhibits no deadband crossover distortion, large output voltage
swing, and an excellent phase and gain margin. It also provides a low 8
SOIC−8 33272
open loop high frequency output impedance with symmetrical source 8 D SUFFIX ALYWx
and sink AC frequency performance. 1 CASE 751 G
1
Features
x = A for MC33272AD/DR2
• Input Offset Voltage Trimmed to 100 mV (Typ) = N for NCV33272ADR2
• Low Input Bias Current: 300 nA
QUAD
• Low Input Offset Current: 3.0 nA 14
• High Input Resistance: 16 MW PDIP−14 MC33274AP
P SUFFIX AWLYYWWG
• Low Noise: 18 nV/ √ Hz @ 1.0 kHz CASE 646
• High Gain Bandwidth Product: 24 MHz @ 100 kHz 14 1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
PIN CONNECTIONS
DUAL QUAD
CASE 626/751 CASE 646/751A/948G
VCC 4 11 VEE
(Top View)
5 10
+ +
Inputs 2 − 2 3 − Inputs 3
6 9
Output 2 7 8 Output 3
(Top View)
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC to VEE +36 V
Input Differential Voltage Range VIDR Note 1 V
Input Voltage Range VIR Note 1 V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Maximum Junction Temperature TJ +150 °C
Storage Temperature Tstg −60 to +150 °C
ESD Protection at Any Pin Vesd V
− Human Body Model 2000
− Machine Model 200
Maximum Power Dissipation PD Note 2 mW
Operating Temperature Range MC33272A, MC33274A TA −40 to +85 °C
NCV33272A, NCV33274A −40 to +125
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Either or both input voltages should not exceed VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).
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MC33272A, MC33274A, NCV33272A, NCV33274A
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics Figure Symbol Min Typ Max Unit
Input Offset Voltage (RS = 10 W, VCM = 0 V, VO = 0 V) 3 |VIO| mV
(VCC = +15 V, VEE = −15 V)
TA = +25°C − 0.1 1.0
TA = −40° to +85°C − − 1.8
TA = −40° to +125°C (NCV33272A) − − 2.5
TA = −40° to +125°C (NCV33274A) − − 3.5
(VCC = 5.0 V, VEE = 0)
TA = +25°C − − 2.0
Average Temperature Coefficient of Input Offset Voltage 3 DVIO/DT mV/°C
RS = 10 W, VCM = 0 V, VO = 0 V, TA = −40° to +125°C − 2.0 −
Input Bias Current (VCM = 0 V, VO = 0 V) 4, 5 IIB nA
TA = +25°C − 300 650
TA = Tlow to Thigh − − 800
Input Offset Current (VCM = 0 V, VO = 0 V) |IIO| nA
TA = +25°C − 3.0 65
TA = Tlow to Thigh − − 80
Common Mode Input Voltage Range (DVIO = 5.0 mV, VO = 0 V) 6 VICR V
TA = +25°C VEE to (VCC −1.8)
Large Signal Voltage Gain (VO = 0 V to 10 V, RL = 2.0 kW) 7 AVOL dB
TA = +25°C 90 100 −
TA = Tlow to Thigh 86 − −
Output Voltage Swing (VID = ±1.0 V) 8, 9, 12 V
(VCC = +15 V, VEE = −15 V)
RL = 2.0 kW VO + 13.4 13.9 −
RL = 2.0 kW VO − − −13.9 −13.5
RL = 10 kW VO + 13.4 14 −
RL = 10 kW VO − − −14.7 −14.1
(VCC = 5.0 V, VEE = 0 V) 10, 11
RL = 2.0 kW VOL − − 0.2
RL = 2.0 kW VOH 3.7 − 5.0
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MC33272A, MC33274A, NCV33272A, NCV33274A
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics Figure Symbol Min Typ Max Unit
Slew Rate 18, 33 SR V/ms
(Vin = −10 V to +10 V, RL = 2.0 kW, CL = 100 pF, AV = +1.0 V) 8.0 10 −
VCC
− +
Vin Vin
+
Sections VO
B C D
VEE
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MC33272A, MC33274A, NCV33272A, NCV33274A
V,
P(MAX),
0 −5.0
−60 −40 −20 0 20 40 60 80 100 120 140 160 180 −55 −25 0 25 50 75 100 125
D
400 600
350 VCC = +15 V
IB, INPUT BIAS CURRENT (nA)
200 300
150
VCC = +15 V 200
100 VEE = −15 V
TA = 25°C 100
I
I
50
0 0
−16 −12 −8.0 −4.0 0 4.0 8.0 12 16 −55 −25 0 25 50 75 100 125
VCM, COMMON MODE VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 4. Input Bias Current versus Figure 5. Input Bias Current
Common Mode Voltage versus Temperature
ICR INPUT COMMON MODE VOLTAGE RANGE (V)
VCC 180
VCC −0.5 VCC
VCC = +15 V
VCC = +5.0 V to +18 V VEE = −15 V
VEE +1.0 120 RL = 2.0 kW
VEE = −5.0 V to −18 V
VEE DVIO = 5.0 mV f = 10 Hz
VEE +0.5 DVO = −10 V to +10 V
VO = 0 V
V,
A,
VEE 100
−55 −25 0 25 50 75 100 125 −55 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
Figure 6. Input Common Mode Voltage Figure 7. Open Loop Voltage Gain
Range versus Temperature versus Temperature
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MC33272A, MC33274A, NCV33272A, NCV33274A
VCC 15
28 120
CMR, COMMON MODE REJECTION (dB)
VCC = +15 V
24 100 VEE = −15 V
VO , OUTPUT VOLTAGE (Vpp )
TA = −55°C VCM = 0 V
20 TA = 125°C
80 DVCM = ±1.5 V
16
60
12 VCC = +15 V −
DVCM ADM DVO
VEE = −15 V
RL = 2.0 kW 40 +
8
AV = +1.0
DVCM
4 THD = ≤1.0% 20 CMR = 20Log X ADM
TA = 25°C DVO
0 0
1.0 k 10 k 100 k 1.0 M 1 0M 10 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
Figure 12. Output Voltage versus Frequency Figure 13. Common Mode Rejection
versus Frequency
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MC33272A, MC33274A, NCV33272A, NCV33274A
120 120
+PSR, POWER SUPPLY REJECTION (dB)
60 VCC 60 VCC
− −
ADM DVO ADM DVO
40 40 TA = 125°C
+ +
VEE VEE
20 DVO/ADM 20 DVO/ADM
+PSR = 20Log −PSR = 20Log
DVCC DVEE
0 0
10 100 1.0 k 10 k 100 k 1 .0 M 10 100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
Figure 14. Positive Power Supply Rejection Figure 15. Negative Power Supply Rejection
versus Frequency versus Frequency
SC OUTPUT SHORT CIRCUIT CURRENT (mA)
60 11
VCC = +15 V
VEE = −15 V 10 TA = +125°C
CC SUPPLY CURRENT (mA)
50
VID = ±1.0 V 9.0
Sink RL < 100 W TA = +25°C
40 8.0
Source Sink TA = −55°C
30 7.0
Source 6.0
20
5.0
I,
10
4.0
|I|,
0 3.0
−55 −25 0 25 50 75 100 125 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
TA, AMBIENT TEMPERATURE (°C) VCC, |VEE| , SUPPLY VOLTAGE (V)
Figure 16. Output Short Circuit Current Figure 17. Supply Current versus
versus Temperature Supply Voltage
1.15 50
GBW, GAIN BANDWIDTH PRODUCT (MHz)
VCC = +15 V
SR, SLEW RATE (NORMALIZED)
− VEE = −15 V
1.1 VO
+ 40 f = 100 kHz
DVin 2.0kW 100 pF RL = 2.0 kW
1.05 CL = 0 pF
30
1.0
VCC = +15 V 20
0.95 VEE = −15 V
DVin = 20 V
10
0.9
0.85 0
−55 −25 0 25 50 75 100 125 −55 −25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
Figure 18. Normalized Slew Rate Figure 19. Gain Bandwidth Product
versus Temperature versus Temperature
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MC33272A, MC33274A, NCV33272A, NCV33274A
25 80 25 80
20 100 20 100
φ, PHASE (DEGREES)
1A
A V , VOLTAGE GAIN (dB)
20 100 12 0
120 Gain Margin
280
2B − Gain (RL = 2.0 kW, CL = 300 pF) Phase Margin
−30 0
3.0 4.0 6.0 8.0 10 20 30 1.0 10 100 1000
f, FREQUENCY (MHz) CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 22. Open Loop Voltage Gain and Figure 23. Open Loop Gain Margin and Phase
Phase versus Frequency Margin versus Output Load Capacitance
12 60
m OPEN LOOP GAIN MARGIN (dB)
CL = 10 pF
CL = 10 pF
φ m, PHASE MARGIN (DEGREES)
10 50
CL = 100 pF
8.0 CL = 100 pF 40 CL = 300 pF
6.0 CL = 300 pF 30
CL = 500 pF
4.0 CL = 500 pF 20
VCC = +15 V
A,
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MC33272A, MC33274A, NCV33272A, NCV33274A
15 60 160
Gain Margin Driver Channel
Phase Margin
RL = 2.0 kW
9.0 40 140 DVOD = 20 Vpp
VCC = +15 V TA = 25°C
6.0 VEE = −15 V 30 130
RT = R1+R2
VO = 0 V
3.0 TA = 25°C 20 120
A,
−
0 R1 VO 10 110
Vin +
R2
0 100
1.0 10 100 1.0 k 10 k 100 1.0 k 10 k 100 k 1.0 M
RT, DIFFERENTIAL SOURCE RESISTANCE (W) f, FREQUENCY (Hz)
Figure 26. Phase Margin and Gain Margin Figure 27. Channel Separation
versus Differential Source Resistance versus Frequency
50
THD, TOTAL HARMONIC DISTORTION (%)
1.0
AV = +1000 VCC = +15 V
10 AV = 10 AV = 1.0
VO = 2.0 Vpp VCC = +15 V
TA = 25°C VEE = −15 V
0.001 0
10 100 1.0 k 10 k 100 k 10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
Figure 28. Total Harmonic Distortion Figure 29. Output Impedance versus Frequency
versus Frequency
pA/ √ Hz )
nV/ √ Hz )
50 2.0
n INPUT REFERRED NOISE VOLTAGE (
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MC33272A, MC33274A, NCV33272A, NCV33274A
60
VCC = +15 V
VEE = −15 V
30
20
10
0
10 100 1000
CL, LOAD CAPACITANCE (pF)
Figure 32. Percent Overshoot versus
Load Capacitance
O OUTPUT VOLTAGE (5.0 V/DIV)
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 2.0 kW
V,
V,
TA = 25°C CL = f
VCC = +15 V
O OUTPUT VOLTAGE (50 mV/DIV)
V,
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MC33272A, MC33274A, NCV33272A, NCV33274A
ORDERING INFORMATION
Device Package Shipping †
MC33272AD SOIC−8
MC33272ADG SOIC−8 98 Units / Rail
(Pb−Free)
MC33272ADR2 SOIC−8
MC33272ADR2G SOIC−8 2500 / Tape & Reel
(Pb−Free)
MC33272AP PDIP−8
MC33272APG PDIP−8 50 Units / Rail
(Pb−Free)
NCV33272ADR2* SOIC−8
NCV33272ADR2G* SOIC−8 2500 / Tape & Reel
(Pb−Free)
MC33274AD SOIC−14
MC33274ADG SOIC−14 55 Units / Rail
(Pb−Free)
MC33274ADR2 SOIC−14
MC33274ADR2G SOIC−14 2500 / Tape & Reel
(Pb−Free)
MC33274AP PDIP−14
MC33274APG PDIP−14 25 Units / Rail
(Pb−Free)
NCV33274AD* SOIC−14
NCV33274ADG* SOIC−14 55 Units / Rail
(Pb−Free)
NCV33274ADR2* SOIC−14
NCV33274ADR2G* SOIC−14
(Pb−Free) 2500 / Tape & Reel
NCV33274ADTBR2G* TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV prefix for automotive and other applications requiring site and control changes.
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MC33272A, MC33274A, NCV33272A, NCV33274A
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45 _ A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0_ 8 _ 0 _ 8 _
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0 4.0
0.275 0.155
0.6 1.270
0.024 0.050
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MC33272A, MC33274A, NCV33272A, NCV33274A
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
F L C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
N C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
−T− J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING L 0.290 0.310 7.37 7.87
PLANE
K J M −−− 10 _ −−− 10 _
H G D 14 PL N 0.015 0.039 0.38 1.01
M
0.13 (0.005) M
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MC33272A, MC33274A, NCV33272A, NCV33274A
TSSOP−14
CASE 948G−01
ISSUE B
ÉÉÉ
ÇÇÇ
MILLIMETERS INCHES
−V− K1 DIM MIN MAX MIN MAX
ÇÇÇ
ÉÉÉ
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE
SOLDERING FOOTPRINT*
7.06
0.65
PITCH
14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS
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MC33272A, MC33274A, NCV33272A, NCV33274A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−A− 2. CONTROLLING DIMENSION: MILLIMETER.
14 8 3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B− 5. DIMENSION D DOES NOT INCLUDE
P 7 PL DAMBAR PROTRUSION. ALLOWABLE
0.25 (0.010) M B M DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.
G MILLIMETERS INCHES
R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
−T− F 0.40 1.25 0.016 0.049
K M J
SEATING D 14 PL G 1.27 BSC 0.050 BSC
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
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MC33272A, MC33274A, NCV33272A, NCV33274A
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX NOTES:
8 5
CASE 626−05 1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
ISSUE L 2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
−B− 3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 4
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
F B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
NOTE 2 −A− D 0.38 0.51 0.015 0.020
L F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
C K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M −−− 10 _ −−− 10_
−T− J N 0.76 1.01 0.030 0.040
SEATING N
PLANE
M
D K
H G
0.13 (0.005) M T A M B M
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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