DC – Router Top

remove_design -all
set search_path {/home/cad/eda/SYNOPSYS/Design_compiler/syn/T-2022-03-
SP4/libraries/syn}
set target_library {lsi_10k.db}
set link_library "* lsi_10k.db"

analyze -format verilog {../rtl/router_fifo.v ../rtl/router_sync.v ../rtl/router_fsm.v

../rtl/router_reg.v ../rtl/router_top.v }

elaborate router_top

link
#source router.con
check_design

current_design router_top

compile_ultra
#compile_ultra -no_autoungroup

#report_timing -path full > timing_report_top.txt

write_file -f verilog -hier -output router_netlist.v

LINT REPORT

#Liberty files are needed for logical and physical netlist designs
#set search_path "./"
#set link_library " "

set_app_var enable_lint true

configure_lint_setup -goal lint_rtl

configure_lint_tag -enable -tag "W241" -goal lint_rtl

configure_lint_tag -enable -tag "W240" -goal lint_rtl

#analyze -verbose -format verilog "../rtl/file.v"

analyze -verbose -format verilog

"../rtl/router_fifo.v../rtl/router_fsm.v../rtl/router_reg.v../rtl/router_sync.v../rtl/router_top.v"

elaborate top_module_name

check_lint

report_lint -verbose -file report_lint_router.txt