Introduction to Verilog

A Beginner's Guide to Digital Design

Trainers
Imtiaz Ahmed Abdullah Ifrit
Design Verification Engineer Design Verification Engineer
Neural Semiconductor Ltd Neural Semiconductor Ltd
 Topics – Session 2
1. Simulating RTL using Testbench.
2. Finite State Machines.
3. Waveform-Based Debugging.
4. Design Guidelines.
5. Examination – Session 2.
6. Further Guidance.

Fig 1: https://tremend.com/blog/advanced-technologies/functional-verification-lifting-the-veil/
Simulating RTL using Testbench
Introduction to Testbench

Why do we need it? Testbench DUT

1. Simulate & Verify: Testbench controls inputs, 1. Generate the

and checks outputs for functionality. stimulus
2. Push & Probe: Exercises DUT with various 2. Drive stimulus to
scenarios, and injects errors to test robustness. DUT.
Processing of
3. Collect stimulus
3. Pass/Fail & Debug: Compares results, and stimulus according
from DUT after
helps identify and fix errors in DUT. to specifications
processing.
4. Repeat & Automate: Enables consistent, happens here.
4. Checking if the
automated testing for reliability. stimulus meets
5. Catch Early & Save: Tests design early to the expected
detect and fix issues before physical requirement.
implementation.
 Example: RTL -> Arithmetic logic unit (ALU)

Problem Statement Code

Design an Arithmetic Logic Unit that can perform 4 basic

operations (Add, Subtract, Multiply, Division) between two
2-bit inputs depending on an Operation Code. For the
division operation make sure the larger number gets
divided by the smaller number.

Design Consideration
1. Combinational logics are needed here because we
expect that as soon as inputs change, the output will
also change.
2. A checker is needed for identifying the largest input
before division operation only.
Example: Testbench -> Arithmetic logic unit (ALU)
Code
Problem Statement
Write a testbench that will check all four operations of the
Arithmetic Logic Unit RTL.

Design Consideration
1. Connect DUT properly with the testbench.
2. Ensure results checking for all four operations.
3. Ensure proper driving of stimulus and collect output
properly.
Example: Results -> Arithmetic logic unit (ALU)

Waveform

Output
Finite State Machines
Understanding State and State Machines
State
Imagine a traffic light. A Finite State Machine (FSM) is
like that light for any system. The FSM can be in just
one situation at a time, like the light being red, yellow,
or green. Each situation, or state, has its own thing,
like the light showing red means stop, yellow means
caution, and green means go.
Use Cases:
- Performing specific actions or calculations.
- Generating outputs based on inputs.
- Waiting for certain events or inputs.
State Machine
Imagine you're training a dog with clear commands. A
Finite State Machine (FSM) is like a set of those
commands for a machine (or even a computer
program!). The machine follows these instructions one
step at a time, like waiting for a treat (state). Each step
tells the machine what to do next, depending on what it
"sees" (conditions). For example, if the dog sits (input),
it gets a treat (output).
Why are FSMs useful?
Simple and clear: They make complex systems easier to
understand because everything is broken down into
defined steps.
Flexible: You can easily add new steps (states) if the
machine needs to do something more complicated.
Reliable: Since there's a clear path to follow, FSMs help
machines react to situations in a predictable way.
Mealy and Moore State Machine
Moore Machine (Reliable but chatty):
1. Thinks about the current situation (state) and decides what to do
(output).
2. It doesn't change its mind based on what's happening now
(input).
3. It performs tricks (output) on clear commands (state) and ignores
distractions (input). (It doesn't depend on input)
Fig: Moore Machine 4. Advantages: Easy to understand and predict, reliable outputs.
5. Disadvantages: More “tricks” (states) are needed to handle
situations.
Mealy Machine (Flexible but can be glitchy):
1. Look at the current situation (state) and what's happening right now
(input) to decide what to do (output).
2. Can change its mind mid-trick if things happen unexpectedly (like
the input changes).
3. Like a dog that might adjust its trick (output) based on a hand signal
(input) while following the main command (state).
4. Advantages: Needs fewer "tricks" (states) to handle situations.
5. Disadvantages: Outputs might be less predictable, more prone to Fig: Mealy Machine
mistakes (glitches).
Mealy vs Moore State Machine

No Moore Machine Mealy Machine

1 Outputs are a function of the current state only. Outputs are a function of the current state and inputs
Also.

2 As output is the function of the current state it is stable Output is the function of the current state and inputs so
for one clock cycle it may change during the state and hence may or
may not be stable for one clock cycle
3 Output is stable for one clock cycle and not prone to Output may change multiple times depending on
glitches or spikes changes in the input and hence prone to glitches or
hazards
4 It requires more number of states compared to Mealy The Mealy machine needs at least one state less
machine compared to the Moore machine

5 STA is easy as combinational paths between the STA is complex as combinational paths are
registers are shorter relatively larger area compared to Moore machine

6 Higher operating frequency compared to Mealy Less operating frequency compared to Moore machine
machine
 Example : Understanding APB protocol

APB FSM

Master Slave

R
S E
WRITE E C
N E
D I Memory
READ E V
R E
R

Ref: https://verificationforall.wordpress.com/apb-protocol/
 Example: Understanding APB Signals

Signal Source Width Description

PSELx Master 1 Select. Master determines which slave to
select.
PENABLE Master 1 Enable. It indicates the second and
subsequent
cycles of an APB transfer.
PWRITE Master 1 Direction. High means write operation and low
means read operation
PADDR Master ADDR_WIDTH Address. It defines in which address to write
into and read from.
PWDATA Master DATA_WIDTH Write Data.

PRDATA Slave DATA_WIDTH Read Data.

PREADY Slave 1 Ready. It is used to extend an APB transfer by

the slave.
Ref: https://developer.arm.com/documentation/ihi0024/latest/
 Example: APB protocol (RTL) Code

Problem Statement
Design an RTL containing a memory that can store value.
You will have to write the RTL with proper logic. Data from
master to slave will follow APB protocol.

Design Consideration
1. Communicating using APB protocol.
2. Completing Write and Read operation without errors.

Ref: https://github.com/kumarraj5364/AMBA-APB-PROTOCOL/tree/main
Waveform Based Debugging
Ideal Waveform: APB
APB operations
Operations
1. WRITE: Sending data from the master device to a slave device on the bus
2. READ: Requesting data from a slave device and receiving it on the master device.

Task : Write and Read operation

Ideal Waveform: APB
APB States
States
1. IDLE: The bus is inactive, and waiting for a transfer request.
2. SETUP: The master selects a slave and initiates the transfer.
3. ACCESS: Data is exchanged between the master and slave.

Write and Read operation

Erroneous Waveforms : APB
Task: Find the errors

Fig: Expected waveform (No Slave Error)

Fig: Slave error with write and read operation

Erroneous Waveforms : APB
Task: Find the errors

Fig: Expected waveform

Fig: Error with state transition

Design Guidelines
Unintentional Latches in the Design

RTL Synthesized Result

Here, b_in didn’t have any assignment in the else

condition, resulting in an unintentional latch.
Use of If-Else Versus Case Statements : Case Statement

RTL

Synthesized results

Thus, the ‘case’ construct generates parallel hardware.

So, it is preferred for defining FSM for flexible flow of
present state to next state.
Use of If-Else Versus Case Statements : If-Else Statement

RTL
Synthesized results

A nested ‘if-else’ structure generates

priority logic. The functionality using
‘if-else’ described here gives the least
priority to ‘d_in[3]’ and gives ‘d_in[0]’
the highest priority.
Missing ‘Default’ Clause in Case

RTL
Synthesized results
If-Else with Else Missing

RTL

Synthesized Result

An else is missing in the nested if the hardware inference

generates combinational multiplexers with the latches.

The latches are inferred due to missing ‘else’ in the ‘if-else’

statement.

The synthesized output will be similar to the missing “

default” case
Ordering of Non-blocking Assignments

Multiple non-blocking assignments

Synthesized Result
Latch vs Flip flop
Flip-Flop (Edge Sensitive)

Latch (level Sensitive)

Synchronous vs Asynchronous Reset : (Synchronous D Flip-Flop)

RTL Synthesized Circuit

Synchronous vs Asynchronous Reset : (Asynchronous D Flip-Flop)

RTL Synthesized Circuit

Guidelines for Modeling Synchronous Designs

1. To describe the functionality of synchronous designs, use the nonblocking

assignments.
2. Do not use the latch-based designs as latches are transparent for half a clock
cycle.
3. Use the pipelined stages to improve the design performance.
4. Use the synchronous reset signals as they are not prone to glitches or spikes.
5. If asynchronous signals are used then use the dual-stage synchronizers to
synchronize the internally generated resets.
6. Use clock gating cells for low-power design.
Guidelines for Modeling Asynchronous Designs

1. If asynchronous reset signals are used, then use the dual edge synchronizer to
synchronize the internally generated reset signals.
2. Avoid use of driving the flip-flop output to the asynchronous reset of the
subsequent flip-flop as this can have race conditions.
3. Avoid the use of an asynchronous pulse generator as it creates issues in the design
and timing closure and even during the place and route.
4. If power consumption is the goal then only use the efficient ripple counter, but
there is performance degradation while using the ripple counters due to the
cumulative delay effect or the cascaded delay due to the individual propagation
delay of the flip-flop.
Examination – Session 2
 Examination Overview

1. MCQ 10%
2. Short Questions 10%
3. Fixing Code Errors 20%
4. Design an RTL 30%

Session 2 70%

Form Link: https://forms.gle/Ppwwxwg8tHYGMwHTA

Further Guidance
 Resources

Review these resources and practice writing RTL for different scenarios for
better understanding.

1. Reference Book: Digital Logic Design Using Verilog by Vaibbhav Taraate.

2. Try to synthesize simple Verilog code to learn how designs get interpreted.
(Use Yosys from EDA Playground if no synthesis tool is available)
3. Practice Verilog Codes:
a. https://hdlbits.01xz.net/wiki/Problem_sets
b. https://github.com/OrsuVenkataKrishnaiah1235/RTL-Coding
c. https://github.com/raulbehl/100DaysOfRTL
THANK YOU