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Recent advances in memory technology

Conference Paper · May 2013

DOI: 10.1109/ASMC.2013.6552766

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 Recent Advances in Memory Technology

Dick James
Chipworks Inc.
Ottawa, Canada
djames@chipworks.com

Abstract— In the last five years we have seen remarkable

advances in the density of commodity memory devices, both
NAND flash and DRAM. NAND flash has now migrated to the
1x-nm era, and DRAM is has reached the 2x-nm node.
To achieve this level of integration the manufacturers have had to
adopt both new materials and processes, and also were the first
users of advanced lithographic techniques such as immersion
lithography and double patterning.
Chipworks, as a supplier of competitive intelligence to the
semiconductor and electronics industries, monitors the evolution
of chip processes as they come into commercial production.
Chipworks has obtained parts from the leading edge
manufacturers, and performed structural analyses to examine
the features and manufacturing processes of the devices.
The paper reviews some of the different flash and DRAM
memory structures produced recently, and looks at the details of
the memory cells.
Keywords—memory; DRAM; flash memory; embedded memory

I. INTRODUCTION
We have reviewed both flash memory [1] and DRAM [2]
before at ASMC, but the sector is still evolving at a steady rate
and it seems appropriate to provide an update – after all, we are
now in the era where flash memory is well under $1/gigabyte,
and similarly dynamic memory is less than $1/gigabit.
NAND flash memory cells have shrunk amazingly in lateral
dimensions to get to the 1x-nm node, but not vertically until
lately; performance requirements have made it very difficult to
reduce the tunneling oxide and inter-poly dielectric layer
thicknesses. The lateral shrink has forced changes in the
dielectric separating adjacent cells, and the first application of
‘air-gap’ technology has actually been in the flash memory
arena, not the interconnect stack of logic processes.
DRAM technology faced different challenges to reduce the
cell area. Recessed metal gate transistors have been introduced
and modifications have been made to the capacitor dielectrics.
II. FLASH MEMORY
A. Samsung K9GBG08U0M 32-GbMLC 35-nm NAND Flash
Samsung’s 35-nm NAND flash was released in 2009, with
a die size of 168 mm2. It utilized three levels of metal with
Figure 1. General structure of Samsung 32 Gb 35-nm NAND Flash
tungsten (W) source-lines, copper (Cu) bitlines, and an
aluminum (Al) bus layer. Fig. 1 shows a SEM image of the
general structure.
The flash cell stack (Fig. 2a) is conventional with a tunnel
oxide ~8 nm thick, and a composite ONONO
(oxide/nitride/oxide/nitride/oxide) inter-poly dielectric ~15 nm
thick. Wordline (floating gate - FG) pitch is 70 nm, FG length
is ~43 nm x ~36 nm wide, bitline pitch is ~82 nm and the cell
size is ~0.006 µm2. FG height is ~89 nm.
Three layers of polysilicon are used, two for the control
gate (CG) and a single layer for the floating gate. In Fig. 2b the
wrapping of the control gate around the floating gate can be
seen, and the detail of the inter-poly dielectric layers (in the
insert).
B. SanDisk/Toshiba SDIN4C2-8G 32-Gb MLC 32-nm NAND
Flash
Sandisk and Toshiba have a joint development agreement
for NAND flash memory, and this part was launched in 2009;
die size was 139 mm2. They also used the same three levels of
metal with top-level aluminum, copper bitlines, and tungsten at
the lowest level.

CG
FG
Figure 2a. TEM image of Samsung 35-nm flash cells (parallel to bitline)
Figure 2b. TEM image of Samsung 35-nm flash cells (parallel to wordline)
The Sandisk flash cell stack (Figs. 3a, b) is again
conventional, but employs only single polysilicon layers for
both floating and control gates, with nickel silicide on the
control gates, down to the interpoly dielectric in some areas.
The tunnel oxide is ~8 nm thick, and a thinner composite
NONON inter-poly dielectric ~12 nm thick. Wordline and
bitline pitch are both 64 nm, giving a cell size of ~0.004 µm2,
and the FG is ~32 nm long x ~24 nm wide. It appears that the
floating gates have been etched back a little, since each gate is
are ~3 nm narrower than the active silicon below it. The
floating gate height of ~85 nm (and therefore control gate
overlap) is comparable with the Samsung 35-nm part.
Sandisk/Toshiba also use high-voltage transistors with a gate
oxide thickness of ~38 nm.
CG
FG
Figure 3a. TEM image of Sandisk 32-nm flash cells (parallel to bitline)
CG
FG
Figure 3b. TEM image of Sandisk 32-nm flash cells (parallel to wordline)
C. Samsung K9HDG08U5A 32-Gb MLC 27-nm NAND Flash
Following the year-on-year cadence for flash generations,
Samsung’s introduced their 27-nm part in 2010; die size was
reduced to 119 mm2. Again, it utilized three levels of metal
with tungsten source-lines, copper bitlines, and an aluminum
bus layer.
Essentially it is a shrink of the earlier part, but there are
subtle differences. The aspect ratio of the floating gate (Figs.
4a, b) has been increased (~112 nm vs ~89 nm high), giving
greater overlap between the control gate and the floating gate;
the tunnel oxide thickness has been reduced to ~6.8 nm, and
the composite NONON (nitride/oxide/nitride/oxide/nitride)
inter-poly dielectric is also thinner at ~12 nm thick. Variations
in the STI depth in the array (not shown here) indicate that
double patterning has been used for the FG/STI etch. Wordline
pitch has shrunk to 54 nm, FG length is ~27 nm x ~25 nm
wide, bitline pitch is down to ~56 nm and the cell size is now
~0.003 µm2.
 CG

CG

FG
FG

Figure 5a. TEM image of Micron 25-nm flash cells (parallel to bitline)
Figure 4a. TEM image of Samsung 27-nm flash cells (parallel to bitline)

CG
CG

FG

FG

Figure 5b. TEM image of Micron 25-nm flash cells (parallel to wordline)

Figure 4b. TEM image of Samsung 27-nm flash cells (parallel to wordline)

Three layers of polysilicon are again used, two for the

control gate (CG) and a single layer for the floating gate; the
control gate is silicided with cobalt.
D. Intel/Micron 29F64G08ACME1 64-Gb MLC 25-nm NAND
Flash
Intel/Micron’s 25-nm was launched in 2010[3], but did not
reach volume production until a year later; density has
increased to 64 Gb, so die size was 166 mm2, which could be
viewed as an equivalent ~83 mm2 for a 32-Gb part. The upper
two levels of the three metals are copper, with tungsten bitlines
at the lowest level.
The gate stack has a simpler ONO interpoly dielectric,
~12 nm thick, and a ~9 nm tunnel oxide, but with a more
complex W/WN/dual polysilicon control gate layer above a
single polysilicon floating gate. The major distinguishing
Figure 5c. TEM image of Micron 25-nm flash bitlines
feature of this part is the use of ‘air gaps’ between the
wordlines (Fig. 5a) and bitlines (Fig. 5c) – taking advantage of
non-conformal oxide deposition to create voids that reduce
parasitic capacitance between the lines, and making this the
first use of air-gap technology in volume production in any
product.
Fig. 5b shows the wrap-around of the control gate over the
floating gates, and the alternating depth of the STI indicates the
use of double patterning for the STI and floating gates. It also
appears that the floating gate width has been reduced by
comparison with the substrate silicon.
 Wordline pitch is 50 nm, and bitline pitch is 58 nm, giving
a cell size of ~0.003 µm2, and the FG is ~31 nm long x ~20 nm
wide. Floating gate height of ~63 nm (and therefore control
gate overlap) is the smallest seen so far.

E. Toshiba TC58NVG6D2GTA00 64-Gb 24-nm NAND Flash

Toshiba/Sandisk also kept the yearly cadence for flash,
launching this in 2010, reaching volume production the CG
following year. with a die size of 150 mm2. We have a Al-Cu-
W three-metal stack similar to the other flash memories, and as
with the other ‘2x’-nm devices, double patterning of the
floating gates and STI is indicated by the STI profile (Fig. 6b).
No air gaps are used between the memory cells (Fig. 6a).
Again, the control and floating gates each use two layers of
poly; the control-gate polysilicon is silicided with nickel, as in
their 32-nm part, but this time down to the interpoly dielectric
in some areas. This interpoly dielectric is a ~11-nm thick FG
NONON, the tunnel oxide is ~8.5 nm thick, and the floating
gate height is 90 nm, so a control gate overlap slightly larger
than the 32-nm device – see Fig. 6b. The floating gates are also
etched back relative to the active silicon below, similar to the
32-nm; in this sample, they are ~4 nm narrower. Figure 6a. TEM image of Toshiba 24-nm flash cells (parallel to bitline)

We found a wordline pitch of ~52 nm, rather than the CG

expected 48 nm, and a bitline pitch also 52 nm, resulting in a
cell size of ~0.0027 µm2; FG dimensions are ~25 x 19 nm.

F. Hynix H27QCG8T2B 64-Gb MLC 21-nm NAND Flash

Hynix announced their ‘2y’-nm 64-Gb device in late 2011,
and we found it in the iPhone 5 the following fall. ‘2y’ turned
out to be 21-nm half-wordline pitch, giving a die size of
145 mm2. It uses the (now) conventional Al-Cu-W three-metal
stack, and double patterning of the floating gates and STI is
indicated by the STI profile (Fig. 7b).
FG
At this node the use of air gaps is mandatory, so in this part
we see it in the memory array (Fig. 7a) and possibly the M3
aluminum metal (Fig. 7c). The control and floating gates each
use two layers of polysilicon, with the lower layers highly
phosphorus-doped and cobalt silicide on the top poly. Floating
gate height is 58 nm, the interpoly dielectric is a ~13-nm thick Figure 6b. TEM image of Toshiba 24-nm flash cells (parallel to wordline)
NONO variant, and the tunnel oxide is ~7.6 nm thick – see Fig.
7b. The cell is square with wordline and bitline pitches of ~42
nm, resulting in a cell size of ~0.0018 µm2; FG dimensions are
~24 x 16 nm.

G. Samsung K9GCGD8U0A 64-Gb MLC 21-nm NAND Flash

Similarly we found the Samsung ‘2y’-nm 64-Gb device in
late 2012, again a 21-nm half-wordline pitch part, with a
similar die size of 142 mm2. It has the same basic structure as
the other Samsung flash memories with the Al-Cu-W three- Figure 6c. TEM image of Toshiba 24-nm flash metal 3 layer
metal stack, and as with the 27-nm device, double patterning of
the floating gates and STI is indicated by the STI profile (Fig.
8b).

CG
FG
Figure 7a. TEM image of Hynix 21-nm flash cells (parallel to bitline)
CG
FG
Figure 7b. TEM image of Hynix 21-nm flash cells (parallel to wordline)
Figure 7c. TEM image of Hynix 21-nm metal 3 layer
As expected we see air gaps between the memory cells
(Fig. 8a) and the M3 top metal (Fig. 8c). As in the Hynix part
above, the control and floating gates each use two layers of
poly, but here we have tungsten on the top polysilicon. The
interpoly dielectric is a ~13-nm thick NONON, and the tunnel
oxide is ~6.4 nm thick, and floating gate height is also 58 nm –
see Fig. 8b.
The cell is slightly off-square with wordline and bitline
pitches of ~42 and 44 nm, resulting in a cell size of
~0.0018 µm2; FG dimensions are ~24 x 18 nm.
CG
FG
Figure 8a. TEM image of Samsung 21-nm flash cells (parallel to bitline)
CG
FG
Figure 8b. TEM image of Samsung 21-nm flash cells (parallel to wordline)
Figure 8c. TEM image of Samsung 21-nm metal 3 layer
H. Toshiba THGBM4G7D2JBAIM 64-Gb MLC 19-nm NAND
Flash
This was the first ‘1x’-nm part to achieve volume
production, surfacing in early 2012, a 19-nm half-wordline
pitch part, with a die size of 130 mm2. It has the same Al-Cu-W
three-metal stack as most of the other flash memories, and as
with the ‘2x’-nm devices, double patterning of the floating
gates and STI is indicated by the STI profile (not shown).
As expected we see air gaps between the memory cells
(Fig. 9a), and they also in the M3 level. Again, the control and
floating gates each use two layers of poly, but the top
polysilicon is silicided with nickel as in their 32-nm and 24-nm
parts. The interpoly dielectric is a ~12-nm thick NONON, and
 CG

FG

Figure 10. Capacitor stack in Elpida 4-Gb 33-nm DRAM

Figure 9a. TEM image of Toshiba 19-nm flash cells (parallel to bitline)
CG
W/TiN wordline

FG

SiN
Figure 9b. TEM image of Toshiba 19-nm flash cells (parallel to wordline)
the tunnel oxide is ~6.7 nm thick, and floating gate height is
also ~81 nm – see Fig. 9b. It seems to be a feature of the
Toshiba/Sandisk parts that the floating gates are etched back (a)
relative to the active silicon below; they are again ~4 nm
narrower. bitline wordlines

The cell is rectangular with wordline and bitline pitches of

~38 and 52 nm, resulting in a cell size of ~0.0020 µm2;
however, due to the etch-back of FG width, FG dimensions are
~17 x 17 nm.
SiN SiN
III. DRAM

A. Elpida EDJ4208BASE 4-Gbit 33-nm DDR3 SDRAM

In the last few years DRAM technology has shrunk through
the 6x, 5x, and 4x-nm generations [2], on a roughly yearly
cadence, and at the time of writing we are in the 3x-nm node,
moving in to the 2x. Elpida produced this 33-nm device in
early 2011, with a die size of 69 mm2, with three aluminum (b)
layers plus the bitlines and wordlines.
The major changes in DRAM technology in recent years wordline
have been the adoption of buried wordlines (trench transistors)
and high-k dielectric materials for the storage capacitors.
(c)
Sinking the wordline below the substrate surface eliminates
stray capacitance between the wordline and contacts, and Figure 11. TEM images of W/TiN buried wordlines in Elpida 33-nm DRAM
reduces the bitline/wordline capacitance, ultimately lowering (a) parallel to wordline, (b) parallel to bitline, (c) plan-view
power consumption. This part exemplifies that trend; Fig. 10 shows the capacitor
stack with the buried wordline (BW) below it. Fig. 11(a)
 capacitors

wordlines

Figure 13. Samsung 32-nm 4-Gb DRAM capacitor stack

Figure 12. STEM plan-view image of Elpida 33-nm DRAM capacitor

illustrates the ‘finFET’ nature of the W/TiN wordline, bitlines

wrapping over a tapered channel; of course, it is not a true
finFET since the channel is unlikely to be fully depleted, and
the taper increases the width of the wordline transistor. The
gate oxide is ~5 nm thick. The bitline contacts can be seen in
Fig. 11(b) – the bitlines are formed of a W/WN/WSi/polySi wordline
stack, formerly used for the wordlines before the introduction
of BW technology.
The capacitor is similar to those described in the previous
paper [2], using titanium nitride (TiN) storage plates with a
TiN/SiGe common top plate. The high-k dielectric layer is a (a)
triple layer of zirconium oxide (ZrxOy), aluminum oxide
(AlxOy), and more ZrxOy (ZAZ).
bitline
ZrO2 has a native k-value of ~22, but if it crystallized, it can
go up to over 40. Unfortunately, then it becomes leaky because
of the grain boundaries, so the thin layer of aluminum oxide is
used to minimize leakage through the dielectric.
With the high-k dielectric the capacitor height is 1.4 µm.
Fig. 12 is a STEM plan-view section of the capacitor, showing
the thin-plus-thick ZrO2 layers with the thin AlO in between.
The cell size is ~100 x ~102 nm, giving a cell area of
~0.010 µm2.
(b)
B. Samsung K3PE7E700B 4-Gbit 32-nm Mobile DRAM
This part was again produced in early 2011, and marked
Samsung’s move to BW metal-gate technology. There are four wordline
metal layers in addition to the bitlines and wordlines, with
tungsten M1, copper M2 and M3, and aluminum M4.
Titanium nitride wordlines are used instead of W/TiN. The
cell layout is different from the Elpida part (see Fig. 10(c)) - the
active silicon regions overlap, so that one third of the wordline
length sits in isolation between the active areas (Fig. 13(c)).
This results in a smaller cell area of 0.0091 µm2, but die size is
larger at 79 mm2.
Fig. 14(a) shows the pseudo-finFET structure with the
(c)
tapered channel; the gate dielectric thickness varies between
~6–9 nm, but the sense amplifiers use a ~2.3 nm tox, and the Figure 14. Samsung 32-nm 4-Gb DRAM capacitor stack, (a) parallel to
wordline, (b) parallel to bitline, (c) plan-view
 wordline

Figure 15. STEM plan-view image of Samsung 32-nm DRAM capacitor

(a)

bitline

Figure 16. TEM image of Samsung 32-nm DRAM metal 4 layer

wordline drivers have a ~6.1 nm nitride oxide dielectric. The

bitlines (Fig. 14(b)) are a W/WN/TiN/WSi/polySi stack.
The capacitor height and structure are similar to the
previous device, at ~1.5 µm, with TiN plates and ZAZ
dielectric (see Fig. 15). Air gaps have arrived in DRAMs, as
seen in the metal 4 level (Fig. 16) – they are easier to introduce
with a subtractively-etched layer than the damascene technique
used for copper metal.

C. Micron MT41K512M8RH 4-Gbit 30-nm DDR3 SDRAM

Micron’s 3x device surfaced in the spring of 2012; it also
uses tungsten M1, copper M2 and M3, and aluminum M4. (b)

wordline

capacitors

(c)
Figure 18. Micron 30-nm 4-Gb DRAM capacitor stack, (a) parallel to
wordlines wordline, (b) parallel to bitline, (c) plan-view

Figure 17. Micron 30-nm 4-Gb DRAM capacitor stack


Figure 19. TEM plan-view image of Micron 30-nm DRAM capacitor
Figure 20. TEM image of Micron 30-nm DRAM metal 4 layer
Close examination of Fig. 17 reveals that there are no growth
striations in the thick oxide layers outside of the capacitor
array. This indicates that the mold oxide has been removed
inside the array only, using the dummy cell at the array edge as
an etch stop; a technique Micron has been using for quite a few
generations. The capacitor stack height is the smallest of the
devices reviewed here, at ~1.3 µm.
The active silicon layout is also different (Fig. 18(c)) –
instead of islands of silicon with a pair of wordlines, there are
stripes of silicon, and every third gate is an isolation gate. With
this layout we get a cell size of 0.0091 µm2 and a die size of
70 mm2.
Fig. 18(a) shows Micron’s version of the pseudo-finFET
structure with a trapezoidal channel; a W/TiN gate is used, with
a gate dielectric thickness of ~4–7 nm; the sense amplifiers also
use a ~2.3 nm tox. Unlike the other parts, the fill over the
wordlines is oxide, not nitride. The bitlines (Fig. 18(b)) are a
W/WN/W/TiN/polySi stack.
The capacitor stack (fig. 19) is essentially the same as the
others, but with Al detected at the extreme outer and inner
edges of the four ZrO2/TiN interfaces, and the top plate fill is
phosphorus-doped polySi, rather than boron-doped SiGe.
In parallel with their incorporation of air-gaps in their flash
products, Micron has used them in the high-density metal 4
areas in this DRAM (Fig. 20).
D. Samsung K4B4G084C 4-Gbit 26-nm DDR3 SDRAM
This device is the first entrant that we found in the 2x-nm
generation of DRAM memories. Packaging details are not part
of this paper, but this was the first DRAM chip that we found
that used copper pillars in a flip-chip package.
Initially it appeared to be a shrink of the previous
generation, but surprisingly for a leading edge part, there are
only three metal levels; tungsten M1, copper M2, and
aluminum M3. A close look at the ~1.6 µm-tall capacitor stack
shows that there are now two support layers holding the
individual capacitor stacks in place (Fig. 21).
support layer
support layer
capacitor
wordline
Figure 21. TEM image of capacitor stack in Samsung 4-Gb 26-nm DRAM
The metal gate material has been changed from TiN to
W/TiN, with a dielectric thickness of 4 – 6 µm. The bitline is
now a W/WN/W/TiN/WSi/polySi composite.
However, the layout of the active areas is similar to its 32-
nm predecessor, and the buried wordlines have the familiar
pseudo-finFET structure (see Fig. 22). Die area has shrunk to
~45 mm2 and cell size is 0.0062 µm2
The capacitor dielectrics have been modified slightly (Fig.
23), in that they are composed of a thin aluminum oxide layer
between a thick layer of zirconium oxide and a thinner layer of
aluminum zirconium oxide (compared with zirconium oxide
alone).
Fig. 24 shows the air-gaps in the high-density top metal
areas.
IV. SUMMARY AND CONCLUSIONS
We have reviewed a range of NAND flash memories
and DRAMs produced over the last four years.
We have catalogued eight examples of NAND-Flash cells,
ranging from the 35-nm to the 19-nm process generations.
The reduced pitches giving the density increases have
 W/TiN wordline
(a)
capacitors
wordlines
bitline
(b)
wordline
(c)
Figure 22. TEM images of W/TiN buried wordlines in Samsung 26-nm
DRAM (a) parallel to wordline, (b) parallel to bitline, (c) plan-view
incorporated process changes such as immersion
photolithography with double patterning, and a switch to air-
gap dielectrics.
Vertical dimensions have started to shrink, but only
slightly, since they are constrained by the operational needs of
storing charge on the floating gate. Historically, the tunnel
oxide has stayed in the 7 – 10 nm range, and we have now
moved to 6 – 9 nm. The interpoly dielectric stack was
consistently ~15 nm, and we are now seeing most parts at ~12
nm, possibly enabled by the migration from a simple ONO
stack to NONO or NONON.
The metal/silicide chosen for the control gates varies by
manufacturer; Toshiba uses nickel, Samsung liked cobalt for
their 35- and 27-nm parts, but switched to tungsten for the 21-
nm device; Micron used a W/WN stack, and Hynix preferred
cobalt.
View publication stats
Figure 23. STEM plan-view image of Samsung 26-nm DRAM capacitor
Figure 24. TEM image of Samsung 26-nm DRAM metal 3 layer
The 1x-nm generation seems to be the likely end for this
form of flash memory, but we will see – the tentative
successors such as vertically stacked cells have received
considerable publicity, but they are still in R&D status.
In the DRAM arena, we have looked at four DRAM cells
from the last two years. The notable change here has been the
adoption of buried wordline technology, so that all modern
DRAMs are now metal-gate devices.
The increase in dielectric constants given by the ubiquitous
use of ZAZ seems to be significant enough that capacitor
heights have remained in the 1.3 – 1.6 µm range, despite the
reduction in cell areas; the wordline gate oxide thicknesses
have also stayed in the 5 – 9 nm range. The bitlines have
evolved to use the former wordline stack, usually variations on
a W/WN/WSi multilayer structure.
We are now in the 2x-nm era of DRAMs; given the ability
of the ZAZ capacitor stack to scale, it seems likely that this
technology will get to the 1x-nm node in the next year or two.
REFERENCES
[1] Dick James, “Nano-Scale Flash in the Mid-Decade” ASMC 2007
[2] Dick James, “Recent Innovations in DRAM Manufacturing” ASMC
2010
[3] Kirk Prall and Krishna Parat, “25nm 64Gb MLC NAND Technology
and Scaling Challenges,” Trans. IEDM 2010, pp. 102–105