2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE)

Analysis of 32-Bit Multiply and Accumulate unit

(MAC) using Vedic Multiplier
2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE) 978-1-7281-4142-8/20/$31.00 ©2020 IEEE 10.1109/ic-ETITE47903.2020.413

* K.Lilly t S. Nagaraj $ B. Manvitha

(B.Tech) Associate Professor (B.Tech)
Dept. of ECE Department of ECE Dept. of ECE
SVCET,RVS NAGAR,Chittoor,AP SVCET, RVS Nagar, Chittoor, AP. SVCET,RVS NAGAR,Chittoor,AP
Email:lillyreddy05@gmail.com Email:nagarajsubramanyam@gmail.com Email:manvitha2799@gmail.com

§ K.Lekhya
(B.Tech)
Dept. of ECE
SVCET,RVS NAGAR,Chittoor,AP
Email:lekhyac222@gmail.com

Abstract—The most widely used operation in digital signal problems in geometry, calculus, conics, algebra, arithmetics.
processing is Multiply and Accumulate (MAC) unit. The area The figure 1 shows the 16 vedic sutras. A ll Vedic sutras listed
occupied by the MAC unit and the power consumed will largely below:
affect the performance and speed of the electronic system. So in
this paper we have proposed a 32-bit MAC using 32-bit array
multiplier and RCA (ripple carry adder) along with another
MAC using vedic multiplier and RCA. The paper also has S.NO SUTRA
another modified MAC unit which uses vedic multiplier and carry
save adder. All the MAC units are simulated using ModelSim 1 (AnurupYe)ShunyamanYat
software and synthesis is done using XILINX ISE DESIGN 2 chalana-Kalanabyham
SUITE. All the MAC implementations were compared with each 3 Ekadhikena Purvena
other for the area and delay. The proposed design of MAC 4 Ekanyunena Purvena
using vedic multiplier has less delay with respect to other MAC 5 Gunakasamuccayah
architectures. 6 Gunitasamuccayah
Index Terms—MAC unit, Vedic Multiplier, CSA, RCA, Verilog 7 Nikhilam-Navatashcaramam Dashatah
HDL, LUT. S Paraavartya-Yojayet
9 Puranapuranabyham
I. I n t r o d u c t io n 10 Sankalana-vyavakalanabhyam
11 Shesanyankena-Charamena
The recent scenario in VLSI designing is completely to­ 12 Shunyam-Saamyasamuccaye
wards designing low power and low area device which are also 13 Sopantyadvayamantyam
14
faster in nature, so there is a need that we should also reduce Urdhva-Tiryakbhyam
15 Vyashtisamastih
the delay in our designs. As the usage of wireless devices have 16 Yavadunam
increased at a very large rate. There is a high need for low
power consuming devices. Low power digital signal processors
can be designed and simulated using many techniques. Some Fig. 1. 16 VEDIC-SUTRAS
of the common operation done by them are multiplying and
accumilating(MAC) and Fast Fourier Transform (FFT). The
adders and multipliers plays a crucial role in these operations. In the 16 sutras, UrdhvaTiryagbhyam(UT) are used for mul­
Generally it is noted that the power consumed in a DSP (digital tiplication of any 2 numbers. Normally, UT sutra is preferred
signal processoimng ) unit completely depends on its MAC for tiny bit numbers. So, UT sutra is used in this project.
unit.
III. URDHVA TIRYAGBHYAM(UT)
II. VEDIC- MATHEMATICS
Urdhva Tiryagbhyam(UT) means vertically and crosswise,
Vedic- mathematics is an old approach that can be straightly we can multiply 2 numbers of any base with this sutra.
make use in different arms of maths in particularly arithmetic, Then plan of action for multiply 2 3-bit numbers say M[2:0],
algebra etc. It reduce the complex while calculating any N[2:0] and C[3:0] indicate the carry, Y[2:0] indicate the partial
results.[13] It can solve arithematic related problems in faster product output.
and easy way. It has 16 sutras that are used for solving Then the successive steps are to be followed:

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 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE)
step-1: C0Y0 = M0 NO
step-2: C1Y1 = (M0*N1) + (M1*N0) + CO
step-3: C2Y2 = (M0*N2) + (M1*N1) + (M2*N0) + C1
step-4: C3Y3 = (M1*N2) + (M2*N1) + C2
step-5: C4Y4 = (M2*N2) + C3
Hence, the final product = C4Y4Y3Y2Y1Y0
IV. MAC UNIT
The MAC includes of multiplier, adder and accumulator.
MAC unit operation is multiply and addition functions . MAC
have two stages , first stage performs product of the given
number and the resulting output is passed on to the second
stage, in that stage addition and accumulate takes place. Above
stages are executed in single round [9] . The 32-bit MAC unit
is designed by 16-bit multiplier. Similarly 16-bit multiplier
designed by taking two 8-bit multipliers and 8-bit multiplier
is designed by using two 4-bit multipliers and 4-bit multiplier
is designed with two 2-bit multipliers. The figure 2 shows
MAC unit.
V. V e d i c M u l t ip l ie r
Vedic multiplier uses UT sutra for multiplication operation
of MAC unit. The vedic multiplier is independent to the
processor clock frequency because the intermediate products
and their resultant sum are parallely calculated. The figure
6 shows 32x32 Vedic Multiplier. Let two 8-bit numbers
represented as MH ML and NH NL .Where the most
significant 4-bits are MH and NH and the least significant
4-bits are ML and NL of an 8-bit number. When the numbers
are multiplied according to Urdhava Tiryagbhyam (vertically
and crosswise) method, we get,
MH ML
NH NL
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(MH x NH) + (MH x NL+ NH x ML) + (ML x NL).
[4]In a line both sides of the digits are multiplied to
obtain the result, which is added to the foregoing carry,
when there are more lines also. Similarly same procedure
follows for 16-bit and 32-bit. Proposed 32-bit multiplier The
32-bit vedic multiplier is designed by four 16 bit vedic
multipliers.Here the inputs a[31:0] and b[31:0] and split into
a[15:0],a[31:16],b[15:0]and b[31:16] respectively and give as
inputs to the multipliers and the ultimate result is a 64- bit
number.
VI. RIPPLE CARRY ADDER
In [7] combinational circuits RCA is one of them.N full
adders are cascaded in parallel way to add two n-bit binary
numbers. RCA also called as n-bit parallel adder. The figure 3
shows logic circuit of 4-bit RCA . In RCA cout of frist stage
is given input for next stage as cin. In Mathematics, any two
4-bit binary numbers A3A2A1A0 and B3B2B1B0 are added
as shown below:
C3 C2 C l CO Cin
B3 B2 B1 BO
+ A3 A2 A l AO
S4 S3 S2 S I SO
Fig. 4.
V II. CARRY-SAVE ADDER
CSA is used for addition of 3 or more n-bit numbers. Here,
the 3 inputs are converted to 2 outputs where 1 output indicate
sum and the other one represents carry [5]. The figure 5 shows
the architecture of CSA . To get the final sum shift the carry
to left by one bit place then attach the most significant bit of
sum with zeros.
V III. M e t h o d o l o g y
The 32-bit MAC(Multiply & Accumulate ) unit is designed
using array multiplier (AM) and RCA then vedic multiplier
is replaced with array multiplier (AM) and CSA is used in
the place of RCA. Then we replace the CSA again with RCA
. The speed and area of 32-bit MAC is compared with array
 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE)

TABLE I
Co mp a r it iv e A n a l y s is o f D if f e r e n t MAC A r c h it e c t u r e s in
TERMS OF DELAY AND AREA

SNO MAC Unit Delay(in LUT’s

ns)
1 32-bit MAC using array 123.988 2373
multiplier,RCA
2 32-bit MAC using vedic 85.209 3782
multiplier,CSA
3 32-bit MAC using vedic 82.911 3637
multiplier,RCA

Fig. 5. CSA ARCHITECTURE

Fig. 8. Output of 32-bit MAC Unit using Vedic Multiplier and RCA

multipier using ripple carry adder, vedic multiplier using RCA

and vedic multiplier using CSA.

IX. Re s u l t s

We have proposed 32-bit vedic multiplier which is imple­

mented in verilog HDL and it is imitate in Modelsim. Xilinx
tool is used for synthesis of 32-bit MAC unit. For comparison a
ordinary 32-bit array multiplier (AM) using full-adders is also Fig. 9. Outputs 32bit MAC Unit using Vedic Multiplier and CSA
constructed. The result of a 32-bit Multiply and Accumulate
unit using CSA and vedic multplier is shown in figure 7. Figure
8 shows the result of MAC of 32-bit using vedic mulitplier
and RCA and figure 9 shows the result of 32-bit MAC using
array multiplier (AM) and RCA. Synthesis report of area and
delay of MAC units with respective multiplier is shown in the
table I. The figure 10 and figure 11 represents the area and
delay plots of MAC units.

Fig. 7. Output of 32-bit MAC Unit using Array Multiplier and RCA Fig. 10. Comparision of Delay

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 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE)

Re f er enc es

Fig. 11. Comparision of Area
X. Co n c l u s io n
In this paper 32-bit (MAC unit) was constructed using (VM)
Vedic multiplier and CSA. It depends on Urdhva Tiryagb-
hyam(uT) sutra and simulation is done using verilog HDL.
It was observed that the MAC unit using vedic multiplier and
RCA was 33 percentage efficient compared with other MAC
units in terms of delay. The MAC unit designed using array
muliplier and RCA was 37 percent efficent when compared
with other MAC units in terms of area. The Multiply and
Accumulating unit arranged with vedic multiplier. It can be
used in DSP applications to improve the performance.
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[13] Sheetal N. Gadakh,Amitkumar Khade,” Design and Optimization of 1616
[14] Sridhar, K; Nagaraj, S; Tech, M; High Speed IEEE-754 Double
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