Proceedings of the International Conference on Sustainable Computing and Data Communication Systems (ICSCDS-2023)
IEEE Xplore Part Number: CFP23AZ5-ART; ISBN: 978-1-6654-9199-0
High Security and Low Power AES Crypto
Processor Security Algorithm for Image Encryption
2023 International Conference on Sustainable Computing and Data Communication Systems (ICSCDS) | 978-1-6654-9199-0/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICSCDS56580.2023.10105112
Dr.N.SENTHILKUMAR
Assistant Professor
Department of Electronics and Communication
Engineering
M.Kumarasamy College of Engineering
Karur-639113, India
senthilkumarn.ece@mkce.ac.in
S SASIKUMAR
Department of Electronics and Communication
Engineering
M.Kumarasamy College of Engineering
Karur-639113, India
sasikumarsanjay11042002@gmail.com
P SRIDHAR
Department of Electronics and Communication
Engineering
M.Kumarasamy College of Engineering
Karur-639113, India
sridharpandiyan04@gmail.com
Abstract—Data encryption specifications include the
Advanced Encryption Standard (AES) algorithm. This
AES algorithm has been incorporated into both hardware
and software, making it one of the most used forms of
encryption technologies. A symmetric cryptography
method with adequate security uses Field Programmable
Gate Arrays (FPGA). The proposed design includes 8bit (1-
byte) data route and 5 main blocks. The Key Register and
State Register are the register banks to store text files,
credential keys, and intermediate data. Shift Rows are
added to the State Register to reduce an area. The Mix
Column will be changed to an 8bit data route. has four
internal registers, each of which can send and receive 8
bits, an 8-bit or 1- byte block that is designed for Mix
Columns. Additionally, the key expansion and encryption
phases employ shared optimized Sub-Bytes. To make
different Sub-Bytes more efficient, we combine and
streamline them. To cut down on power usage, the design
makes use of the clock gating technique. AES architecture
for a 128- bit image-based image encryption system is
presented in this work. Verilog HDL, Model sim 6.4.c was
used to implement this design in an FPGA XC3S 200 TQ-
144. To synthesize Xilinx to tool is being used.
Keywords—Power Analysis Attack (PAA), Advanced
Encryption Standard (AES), Field Programmable Gate
Array (FPGA), MATLAB.
I. INTRODUCTION
The encryption is used to a crypto system or cypher
to prevent anybody other than preventing the intended
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d licensed use limited to: Vignan's Foundation for Science Technology & Research (Deemed to be University). Downloaded on September 20,2023 at 10:07:59 UTC from IEEE Xplore. Restrictio
A SATHISH
Department of Electronics and Communication
Engineering
M.Kumarasamy College of Engineering
Karur-639113, India
sathishjsags@gmail.com
S SATHEESH
Department of Electronics and Communication
Engineering
M.Kumarasamy College of Engineering
Karur-639113, India
satheeshsrinivasan001@gmail.com
recipient(s) from accessing or using the encrypted data.
A crypto system can be utilized to encrypt a message [1].
Only when the proper algorithm and keys are used to
decode the communication can the recipient see its
encrypted contents. The primary use of cryptography is
the transmission of private data via computer networks.
When a document is encrypted, a key and a
mathematical method are applied to turn it from clear
text into crypto-text [2]. Crypto-text cannot be read if the
reader does not possess the decryption key. It was
commonly accepted that DES was no longer reliable due
to advances in computer processing power. The main
objective NIST's to provide an alternative to DES that
US government agencies could use for non-military
information security applications [3]. The fact that
NIST's work would benefit businesses and other non-
government users and that it would be broadly embraced
as a commercial standard was obviously understood. The
(NIST) invited professionals having knowledge of data
security and cryptography from throughout participating
in the selection process from across the globe and
discussion. Five encryption methods were selected for
study. The AES algorithm still frequently used today
onwards. NIST formally approved the AES algorithm for
encryption in the year 2000, and FIPS-197 was then
published as a government standard. On the NIST
website, you may view the whole FIPS-197 standard. As
was to be predicted, a large number of manufacturers of
encryption- related hardware and software now provide
AES encryption. The block cypher AES and encryption
1251
 Proceedings of the International Conference on Sustainable Computing and Data Communication Systems (ICSCDS-2023)
IEEE Xplore Part Number: CFP23AZ5-ART; ISBN: 978-1-6654-9199-0

algorithm using a cipher key and done some several outcome, Add Round Key receives the results
rounds of encryption. A block cypher, a type of byte by byte [10]. The data path for the Key-
encryption technology, only one set of information is Register does not need to be 32 bits longer than
encrypted at a time. The block size for our basic AES the data path for 32bit mixing columns, nor is it
encryption is 128 bits, or 16 bytes [4]. The word required to store the outcomes in the registers.
"rounds" is denoting ten to fourteen times that the data is
encrypted and decrypted throughout the encryption  The clock gating approach is used in various
process, according to the size of the key. portions of the plan to lower the amount of
energy used, which results in a lower power
consumption [11].
II. EXISTING SYSTEM In regard to factors of the design, we employ to
minimize dynamic power usage by using the clock gating
It makes use of the SDRR (Secure Double Rate
approach. Individual clock gating is performed for the
Registers) in a well-known AES-128 architecture to
State Register and internal registers of the Mix Columns.
increase the cryptographic hardware's resilience to
For example, State Register and Mix Columns clock is
current PAAs [5]. Combinational and sequential logics
turned off Since these two blocks aren't used during the
are both kept secure by the interleaved processing of real
essential stage of growth, energy must be conserved.
and random data in the AES-128 employing SDRR,
which is when the most power is saved [12]. Fig 2 shows
which uses a combinational approach to analyze random
the proposed system's block diagram.
data constantly throughout the clock cycle [6]. Fig 1
shown the block diagram of existing model.

0 1
Input Plain Text Sub Bytes State Register Mix Columns Output
Add Round 1 0
Key
Mix
Sub bytes Shift Rows
SDRR SDRR
Column
SDRR SDRR
OUT 2
RNG

Cipher Text
RNG

Input Key RCON

CK

0
SEL

RNG
SEL

SEL
CK

CK

Plain Text Round sell

Round_sel2 Key Register
1 OUT 1 CNTL
Real data
Random data
RNG SDRR
Round Key
Control
CK
Unit

SEL

Fig 2: Block Diagram of Proposed System

Fig 1: Shown the Block diagram of Existing Model
A. Algorithm

III. PROPOSED SYSTEM

The masked clock gating and the AES core are PLAIN TEXT PLAIN TEXT
applied in the AES implementation to create the
encryption masks. 128bit encryption is performed using Add Round Key
Add Round key
Round 10

the masked AES core. Relative to a fully folded in half Sub Bytes Sub Bytes
implementation, in order to conserve space, the
Round 1

Shift Rows Shift Rows

procedure is carried out in 10 cycles, computing 1 round Mix Columns
ENCRYPTION

DECRYPTION

every cycle. The figure below shows the suggested Add Round key
Add Round key
Round 9

masked AES. Masking the real data with a random Inv Mix Columns
mask first (plaintext). The "Nano AES core" is then fed Inv Sub Bytes
Sub Bytes
the mask and the masked plaintext, encrypting the Inv Shift Rows
Round 9

masked data using the secret key. The cipher-text is Shift Rows
delivered to the module [7]. It is meant to be generated Mix Columns
Add Round key
alongside the findings that were masked.
Round 1

Add Round key Inv Mix Columns

0
 In an effort to minimize the amount of logic Sub Bytes Inv Sub Bytes
Round 10

required, State Register holds information on the Shift Rows Inv Shift Rows
Shift Rows [8]. Add Round key Add Round Key

 After optimizing it, we distribute the Block of CIPHER TEXT

sub bytes to the phases of key expansion and
encryption [9]. Fig 3: Algorithm of Proposed system

 Considering the topology, a stream of 8bit data, A block cypher with symmetric iteration is the
we construct an 8-bit block that is ideal for Add- Pipelined algorithm. The lengths of the block and key
Round-Key with 8 bit input and output. As an can be 128, 192, or 256 bits. The AES was required to

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d licensed use limited to: Vignan's Foundation for Science Technology & Research (Deemed to be University). Downloaded on September 20,2023 at 10:07:59 UTC from IEEE Xplore. Restrictio
 Proceedings of the International Conference on Sustainable Computing and Data Communication Systems (ICSCDS-2023)
IEEE Xplore Part Number: CFP23AZ5-ART; ISBN: 978-1-6654-9199-0

create a symmetric block cypher with a block size of 128

bits by the NIST. Variations of Pipelined that can
function on greater block sizes will not be included in
the actual standard as a result of this requirement.
Additionally, Pipelined provides a customizable number
of rounds or iterations: 10, 12, and 14 for keys with
lengths of 128, 192, and 256, respectively. The data
block is viewed by the transformations in Pipelined as a
rectangular array with four columns and four-byte
vectors. A rectangular array of 4-byte vectors is also
thought of as the key; the number of columns depends on
the key length.
B. Software Requirements
This work provides a 128-bit AES architecture for
image cryptography. Verilog HDL is used to implement
this design in the FPGA XC3S 200 TQ-144. Modelsim
6.4.c is used to simulate it [13], and the Xilinx tool is
used to reprocess it. In Synthesis Process will generate
RTL Viewer and Technology Viewer. X power Tool
performs power calculations. MATLAB Tool is used
for image processing [14].
Fig 5: encryption and decryption
C. Application Block Diagram
Fig 6: Plaintext and Ciphertext
As shown Fig 3 Using the proposed scheme as a
base, A decryption technique will be created. The basis B. Xilinx device utilization summary of encryption
for encryption and decryption will be images [15]. For module
this process, MATLAB and VLSI will be combined (Fig
4). This is devise utilization summary for the proposed
encryption algorithm, here we show number of registers
used, number of LUT occupied [18-19], Slices and all
AES Decryption
AES Encryption (Fig 7).

Plain Text Cipher Text Plain Text

Encryption Decryption

Fig 4: Application Block Diagram

IV. RESULTS
A. Simulation result of Encryption & Decryption
This is Encryption & Decryption Simulation Result.
Plaintext is Primary Input Data and Key is Key for
Encryption Process. Ciphertext is Encrypted Output.
Key1 to Key 10 are the Generated key for Each Round
by Key Generation Unit [16]. This waveform Simulated
by Modelsim Tool and we can give the Input based on
Binary Number and we Showed op as Hexa Decimal
format [17] in the Fig 5 and Fig 6 shows our Encrypted
plaintext and Ciphertext.
Fig 7: Devise utilization Summary for the Proposed Encryption
C. RTL VIEW OF AES MAIN MODULE
This is RTL View of Proposed Design. RTL Means
Register transfer Level. Here the Verilog HDL Code is
converted as Schematic View [20]. It shows Each and
Every individual Module as internal module. Various
design blocks. It caused the area of the Spartan 3 xc3s
200 tq144 board to be reduced by 30% (Fig 8).

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 Proceedings of the International Conference on Sustainable Computing and Data Communication Systems (ICSCDS-2023)
IEEE Xplore Part Number: CFP23AZ5-ART; ISBN: 978-1-6654-9199-0

V. CONCLUSION
The Nano AES symmetric cryptography technique is
used in many applications and networks with a high
quality of security. As a result, AES is a practical
algorithm for little IoT devices. For IoT devices with
constrained resources, this study has developed a
compact AES architecture in this study. The architecture
included two specified register banks with an 8bit data
path in order to save simple text, interim results, and
keys. Shift-Rows were executed within the State-
Register to lessen the amount of logic needed.
Additionally, the design shared improved Sub-Bytes
with the encryption and key expansion phases. In
addition, this study has created Mix-Columns, a suitable
Fig 8: RTL View of proposed system
block for low- area design, using an output and input of
D. COMPARISION TABLE 8 bits. To decrease the amount of space and energy used,
this study has employed the clock gating method in
As shown in Fig 9, area has been reduced by using various design blocks. It caused the area of the Spartan 3
the proposed clock gating technique. xc3s 200 tq144 board to be reduced by 30% is set up
to issue an alert in the event of emergency.
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