The DMA controller-8257

 It has been developed for 8085/8086/8088 microprocessor-based systems. It

is a device dedicated to perform a high speed data transfer between memory
and IO device.
 The 8257 has four channels and so it can be used to provide DMA to four
IO devices. It cannot be connected in cascade like the 8237 and it has less
features than the 8237.
 For each DMA channel an address register and a count register has been
dedicated to store the memory address and the count value for the number of
bytes to be read/write by DMA respectively.
 Apart from these dedicated registers, the 8257 has mode set and status
registers.
 The 8237 is a 40-pin IC and available in Dual In-line Package (DIP). The
pin configuration of the 8257 is shown in Fig. given below.
 A brief description about the pins and signals of the 8257 are listed in Table
given below

Fig. Pin configuration of 8257

Features of 8257
 It has four independent DMA channels to service four IO devices.
 Each channel is independently programmable to transfer up to 64 kb of
data by DMA.
 Each channel can independently perform read transfer, write transfer and
verify transfer
Functional Block Diagram of 8257
 The functional block diagram of 8257 is shown in Fig. given below. The
functional blocks of 8257 are the data bus buffer, read/write logic, control
logic and four numbers of the DMA channels.

Fig. : Functional block diagram of DMA controller 8257.

 Each channel has two programmable 16-bit registers. One register is used to
program the starting address of the memory location for DMA data transfer
and another register is used to program a 14-bit count value and a 2-bit code
for the type of DMA transfer (Read/Write/Verify transfer).
 The address in the address register is automatically incremented after every
read/write/ verify transfer. The format of the count register is shown in Fig.

(a)

 In read transfer, the data is transferred from the memory to the IO device. In
write transfer, the data is transferred from the IO device to memory.
Verification operations generate the DMA addresses without generating the
DMA memory and IO control signals.
 Apart from the address and count registers of each channel, the 8257 has a
mode set register and status register. The mode set register is used to
program various features of 8257 and the status register can be read to know
the terminal count status of the channels.
 The registers of 8257 are selected for read/write operation during the
slave/programming mode by sending a 4-bit address to 8257 through A0 -
A3 lines.
 The internal addresses of the registers of 8257 are given in Table-
Table: The internal registers of 8257

.
While programming 16-bit register the low byte has to be send first and then the
high byte. Internally, the loading of low byte and high byte into 16-bit register are
taken care by a first-last flip-flop.

The mode set register is used to program the following features of 8257 :
 Enable/disable a channel.
 Fixed/rotating priority.
 Stop DMA on terminal count.
 Extended/normal write time.
 Auto reloading of channel-2

 The format of the control word to be loaded in the mode set register of the 8257
is shown in Fig. (b).
 The bits B0, B1, B2 and B3 of the mode set register are used to enable/disable
channel-0, 1,2 and 3 respectively. A one in these bit position will enable a
particular channel and a zero will disable

 The format of status register of 8257 is shown in Fig. (c). The processor can read the
status of 8257 during slave mode to know the terminal count status of the channels.
  The bits B0, B1, B2 and B3 of the status register indicate the terminal count
status of channels-0, 1, 2 and 3, respectively.
 A one in these bit positions indicate that the particular channel has reached
terminal count. These status bits are cleared after a read operation by the
microprocessor. Bit B4 of the status register is called update flag and a one in
this bit position indicates that the channel-2 registers has been reloaded from
channel-3 registers in the auto load mode of operation.

DMA Operation in 8086 using 8257

 In the slave mode the microprocessor sends control word to mode register
and programs the count and address registers of the required DMA channels.

 Once the 8257 is programmed, it will keep on checking the DMA request
input from the IO devices. Whenever a DMA request is made by an IO
device, the DMA operation is performed. The various steps of the DMA
operation are as follows :

1. When a peripheral device require a DMA, it will assert the DRQ signal high.
2. When the DRQ of a channel is asserted high and if the channel is enabled
then the 8257 will assert HRQ (HOLD Request) as high.
3. When the 8086 processor receives a high signal on its HOLD pin, it will
complete the current instruction execution and then drive all its tristate
(address, data and control) pins to high impedance state and send an
acknowledge signal to 8257 by asserting the HLDA signal as high.
4. When the 8257 receives an acknowledge signal from 8086, the 8257 will
send an acknowledge signal to the peripheral which requested the DMA, by
asserting the DACK signal as low.
5. The 8257 asserts AEN high, which enable the DMA memory address latches
and disables the processor address latch. Then the 8257 outputs low byte
DMA address on A0-A7 lines and high byte DMA address on D0 - D7 lines.
Also the ADSTB signal is asserted high to latch this address into external
latches. Once the address is output on the address lines the content of
address register is incremented by one and the count register is decremented
by one.
6. Also the 8257 asserts appropriate read and write control signal to perform
DMA transfer from the peripheral to the memory.
7. After performing one-byte transfer steps 5 and 6 are repeated again and
again, until the terminal count (i.e., until the count reaches zero).