Received: 13 July 2023 Revised: 29 October 2023 Accepted: 29 December 2023

DOI: 10.1002/jnm.3210

RESEARCH ARTICLE

Adaptation and comparative analysis of HSPICE level-61

and level-62 model for a-IGZO thin film transistors

Divya Dubey | Manish Goswami | Kavindra Kandpal

Department of Electronics and

Communication Engineering, Indian
Institute of Information Technology
Allahabad, Prayagraj, India
Correspondence
Kavindra Kandpal, Department of
Electronics and Communication
Engineering, Indian Institute of
Information Technology Allahabad,
Prayagraj 211015, India.
Email: kavindra@iiita.ac.in
Abstract
This paper presents a Computer-aided design (CAD) model for a-IGZO thin
film transistors (TFTs) by adapting SPICE level-61 RPI a-Si: H (Hydrogenated
Amorphous Silicon) TFT model and level-62 RPI Poly-Si (Poly Silicon) TFT
model. This work provides a complete understanding of SPICE level-61 and
62 model parameters, which must be tuned for a-IGZO TFT simulation. The
adapted SPICE models of level-61 and level-62 could model all regions of oper-
ation of the TFT, that is, above-threshold and below-threshold regions.
Adapted RPI poly-Si model also shows the kink effect in ZnO thin film transis-
tors (TFTs) due to the recombination of electron–hole pairs in the channel via
boundary trap states present in the poly-Si TFTs thereby increasing the drain
current in the transistors above pinch-off region. The extracted performance
parameters of the adapted models were found to be contiguous with experi-
mental results. The maximum deviation in the subthreshold slope is approxi-
mately 5 mV/decade for level-61 a-Si TFT, and for level-62 poly-Si TFT,
deviation in the subthreshold slope is even less, that is, 0.2 mV/decade. The
experimental and simulated characteristics, extracted on-to-off ratio, negative
bias reverse saturation current, and threshold voltage were almost similar.
However, an average deviation of 2.4% and 2.27% was observed in the output
characteristics of the adapted level-61 and level-62 models, respectively.

KEYWORDS
AM-OLED, amorphous-indium-gallium-zinc-oxide (a-IGZO), flexible displays, HSPICE
Level-61, HSPICE level 62, Rensselaer Polytechnic Institute (RPI), SPICE models, thin-film
transistor (TFT)

1 | INTRODUCTION

Nowadays, transparent TFTs are emerging as a prominent technology in display electronics. In retrospect, oxide semi-
conductors have been widely used for flexible and transparent flat-panel displays. As compared to different channel
materials for TFTs such as a-Si: H, low-temperature poly-Si (LTPS), organic semiconductors, and poly-Si, oxide semi-
conductors such as amorphous indium gallium zinc oxide (a-IGZO) are emerging as an alternate of TFT based display
technology, on account of possessing relatively higher mobility, low thermal budget requirement, increased transpar-
ency in the visible spectrum owing to wide energy bandgap (3.5 eV), high conductivity due to large carrier concentra-
tion (>1019 cm
3) and surface uniformity.1 As oxide semiconductors are mostly n-type2 only, they result in higher static
power dissipation due to direct current flow during the steady-state operation. However, the numerous advantages of

Int J Numer Model. 2024;37:e3210. wileyonlinelibrary.com/journal/jnm © 2024 John Wiley & Sons Ltd. 1 of 23
https://doi.org/10.1002/jnm.3210
2 of 23 DUBEY ET AL.

oxide semiconductors are nurturing suffice their wide usability for TFT displays and overcome their limitations. An
accurate and efficient model of TFTs is required to design and analyze circuits and systems in the SPICE (Simulation
Program with Integrated Circuit Emphasis) circuit simulators. A proper approach is required to model TFTs, which
should capture the effect of their physical and material properties on the device's performance.
The basic bottom gate a-IGZO TFT structure is shown in the Figure 1, The amorphousy IGZO channel layer is used
for the carrier transport between the source and drain in the TFT like a conventional MOSFET. However, a-IGZO TFT
operates in accumulation mode, and MOSFET operates in inversion. Due to its cost-effectiveness, TFTs are primarily
used in the display industries. TFTs are meant to drive OLEDs and control which pixel to turn OFF or ON based on the
pattern we want to display on the AMOLED screens.
Various researchers have studied ZnO TFTs device physics. Torricelli et al.2 proposed the Multiple-Trapping and
Release Model (MTR) to explain charge transport behavior through the semiconducting metal oxide channel. Figure 2
describes the mechanism of the MTR modeling approach. The electrons (represented by the orange circles) are trapped
in the localized states (defined in the Figure by the blue dashed lines). Trapped electrons get excited to the conduction
band edge upon thermal excitation. The MTR model considers the transport of the charge carriers through the
delocalized states present in the conduction and valence bands as electrons and holes, respectively.3 Localized states in
the bandgap consist of two categories of defect states: tail states and deep states. Deep states exist in the center of the
bandgap, while tail states exist near the conduction band and valence band. Zinc atoms act as the donor atom, which
donates electrons to the oxygen atoms and becomes ionized, creating the tail states. The oxygen atom acts as an accep-
tor atom, which accepts electrons from the metal ions and makes deep states in the middle of the bandgap. Deep states
determine the threshold voltage, while the tail states near the conduction band determine the field-effect mobility.
Charge carriers in the conduction band (delocalized states) get trapped into the localized states within the bandgap and
then released upon thermal excitation back into the delocalized states above the mobility edge. Activation energy
needed for releasing deep-state carriers is more than the shallow states (tail states).
The density of states (localized states) within the bandgap can be modeled to show the double exponential distribu-
tion for deep states and tail states, having both acceptor and donor-type atoms.2 The double exponential distribution
function follows as below:

FIGURE 1 Basic TFT structure.

FIGURE 2 Mechanism showing MTR transport model.

DUBEY ET AL. 3 of 23

E
E   E
EC 
C
g ðE Þ ¼ N deep ek Tdeep þ N tail e k T tail ð1Þ

Ndeep and Ntail are the deep and tail states corresponding to the conduction band edge EC. Tdeep and Ttail are the
characteristic temperatures corresponding to the deep and tail states.4 Figure 3 shows the localized state's distribution
according to the double exponential function mentioned in Equation (1). Following parametric values have been
assumed while plotting DOS expression in Equation (1): Ndeep = 1  1011 cm
2 eV
1, Tdeep = 3480 K,
Ntail = 2.85  1014 cm
2 eV
1, Ttail = 675 K.4 Ec for a-IGZO is taken to be 3.4 eV. The curves for deep states and tail
states intersect at about 2.6 eV. This transition point is defined to be as E = 0 eV in the Valence band.
Several other mechanisms for modeling the oxide TFT are also proposed.5,6 These charge transport models help to
define threshold voltage, carrier densities, the density of states (DOS), etc., by deciding their dependence on the key
parameters and material properties. Hence, such mechanisms help frame the compact and easy yet complete descrip-
tive model for the device.
Kandpal et al.7 proposed a CAD-compatible adapted SPICE level-3 model for oxide semiconductors. The model
applies to oxide-semiconductor-based TFTs built upon any channel or dielectric material. However, the model is unable
to detect the effect of density of localized states present in the forbidden bandgap of the thin film, the kink effect in the
poly-Si TFT, the effect of temperature on the device transfer characteristics, the DIBL effect, and the effect of variations
in the threshold voltage and mobility, both in a-Si and poly-Si. Hence, some alternative models are required, rep-
roducing these effects on the TFTs' performance characteristics in the simulation environment.
Sungsik Lee et al.8 designed a physical model to define the current–voltage relationship in the subthreshold region
of the amorphous oxide TFTs. The overall current in the model is the harmonic mean of the diffusion and drift cur-
rents. Diffusion current, prevailing in the region close to the flat-band gate voltage, is exponential due to deep interfa-
cial states. The drift current component appears when the gate voltage reaches the threshold voltage, following the
power law due to localized deep states. The proposed model, though convenient to use and contiguous to the experi-
mental characteristics, is compact and only defines the behavior of the TFT in the subthreshold regime.
Hossain et al.9 modeled the grain boundary (GB) present in the polycrystalline structure of InGaZnO in the form of
multiple grain boundaries parallel to the oxide-channel thickness and perpendicular to the charge transport through
it. If the grain boundary trap density increases, threshold voltage increases and subthreshold swing degrades. Increased
GB trap density results in more trapping of the carriers. Therefore, the number of available carriers for the conduction
reduces. This results in a higher turn-on voltage or threshold voltage. Increased GB traps also increase the bulk charge
factor as the change in surface potential reduces for a given change in the VGS. Therefore, it results in the degraded sub-
threshold swing. In the Hossain et al.9 model, the defects in the InGaZnO channel are localized in the grain boundary,
having their peak value in the middle of the bandgap. But, this model is not justified for any random orientation of the

FIGURE 3 Density of states of the localized states plotted against the energy.
4 of 23 DUBEY ET AL.

grain boundaries within the channel. Also, it doesn't account for the tunneling phenomenon due to the thin grain
boundaries and lacks experimental validation. Hence, the application of this model offers limitations.
Piero Migliorato et al.10 suggested a systematic approach for the parameter extraction of a-IGZO TFT. The process
followed consecutively, extracting the key parameters step-by-step from the fabricated TFT's I–V and C–V characteris-
tics. Flat-band voltage, carrier concentration, the density of deep gap states, shallow donor concentration, and tail states
were extracted sequentially by the method proposed in Reference [11]. As this method extracted the tail state incor-
rectly, it was deduced in the last by matching the extracted value to the experimental data. Later, the extraction of
parameters in the same sequential fashion was done for different TFT device models fabricated in the same run. The
simulated transfer characteristics obtained by the extracted parameters and the experimental transfer characteristics for
different fabricated TFT devices were in agreement with each other, validating the earlier approach to be applicable
across several material-based TFTs. The method also incorporates the effect of Negative Bias under Illumination Stress
(NBIS) effect. The a-IGZO TFT model, developed using this systematic approach, is accurate and effective but requires
more parameters to be extracted.
Jingrui Guo et al.12 proposed a simplified model for independent dual-gate amorphous Indium Gallium Zinc Oxide
thin-film transistors (a-IGZO TFTs). This model is thoroughly tested and validated using device measurements based
on surface potential. It considers various transport mechanisms and accurately predicts device characteristics depen-
dent on temperature and traps. Most notably, the research shows how this model can be used to design circuits com-
pensating for threshold voltage variations, providing valuable insights for future IGZO-based circuit design and
performance predictions. However, the model is implemented in Verilog-A and tested in a CAD environment. In his
other work, Jingrui Guo et al.12 also proposed a new model for dual-gate a-IGZO TFTs, considering various transport
theories and surface potentials. This model, developed using the Schroder method,13 accurately describes the
transport mechanism under different temperature and gate voltage conditions. It integrates percolation conduction,
trap-limited conduction, and variable range hopping in extended and localized states. The model incorporates a unified
formulation for front and back surface potentials, ensuring accuracy across all operation modes. Validation through
simulations and experiments shows excellent agreement and compensates for threshold variations. However, the con-
straint of the model is its utilization of Verilog-A, which makes it device-specific without Process Voltage and Tempera-
ture (PVT) analysis.
Ashima Sharma et al.14 have introduced an analytical model that describes amorphous In-Ga-Zn-O thin-film tran-
sistors based on device physics. The model incorporates key physical parameters, including subgap density-of-states
(DOS), making it valuable for optimizing fabrication. It considers various states, including delocalized free band, deep
trap, and tail trap states, making it valid for the entire operational range. They extract these physical parameters using
a least square (LSQ) curve-fitting approach and validate the model by comparing its predictions to measured device
characteristics. The model accurately predicts the I-V characteristics of long-channel devices and is further enhanced to
account for contact voltage drop in short-channel devices. It successfully replicates measured responses in long- and
short-channel oxide TFTs with varying channel lengths, showcasing an average error of less than 3%. This versatile
model allows for designing oxide TFT-based circuits with different channel lengths using a single set of physical param-
eters in circuit simulation. Although valuable in its analytical approach, the presented model possesses inherent limita-
tions stemming from the necessary simplifications and assumptions about device behavior. While enabling tractable
analysis, these simplifications introduce uncertainties regarding the model's accuracy across diverse experimental
setups. Notably, the model performs commendably predicting short-channel devices by incorporating contact voltage
drop considerations. However, the real-world complexities, such as variations in contact resistances, pose potential
challenges that could impact the precision of its predictions in practical applications. Moreover, the model's applicabil-
ity beyond the specified channel lengths and widths lacks explicit discussion, raising concerns about its versatility
across different device configurations.
Various Verilog-A models have been developed for a-IGZO TFTs,15,16 for example, Shabanpour et al.17 adapted the
technology-dependent, RPI a-Si Verilog-A model for a-IGZO based TFTs with the limitations that, the device dimen-
sions are not easily scalable. Besides, the Verilog-A model imposes restrictions as the analysis such as PVT (PreSure-
Voltage-Temperature) analysis, corner analysis, and yield estimations are not possible using it. Hence, there arises the
necessity of realizing the model for a-IGZO TFTs, which captures all the significant effects on the performance of
the TFTs in the simulation environment, models the characteristics of the device in all the regions of the operation,
incorporates the random orientation of the grain boundaries into the model and address nearly all the significant
parameters of the a-IGZO TFT device in simulating the circuits.
DUBEY ET AL. 5 of 23

Therefore, in this paper, we have adapted the level-61 a-Si TFT model and the level-62 poly-Si TFT model to repro-
duce the behavior of experimental characteristics of a-IGZO TFTs. Both these models are developed by RPI originally
for a-Si: H TFT and poly-Si TFT. The experimental data used for a-IGZO TFTs have been taken from18,19 for model cali-
bration. The adapted a-IGZO TFT model matches the TFT performance parameters extracted from the experimental
data, includes all the regions of operation of a-IGZO TFTs, requires minimum parameter extraction, and allows all
types of analysis (corner, PVT, etc.). The adapted models not only replicate the behavior of a-IGZO TFTs but also cap-
ture the effect of deep and tail states on various regions of the operation of the oxide TFT using the MTR model. With
the MTR model applied for the analytical and behavioral modeling of the TFT, the computational time is not
sacrificed.20 Moreover, the comparison between both types of model adaptation (level-61 and level-62) is made to eluci-
date the usability of the adapted models in the circuit design simulation. Figure 4 gives the flowchart process flow for
model adaptation and is discussed in subsequent sections of the manuscript.

2 | ADAPTATION OF a-IGZO TFT U SING LEVEL-61 RPI a-Si TFT M ODEL

Rensselaer Polytechnic Institute has developed a-Si:H TFT based AIM-SPICE level 15 or HSPICE level 61 MOSFET
model. The model is based on the crystalline MOSFET model. It is a 3-terminal model and does not include a body ter-
minal. The simulation does not add a parasitic drain-body and source-body diode to the model.21 This charge control
model accommodates the induced charges in the localized states within the bandgap and correctly simulates the cur-
rent conduction in TFTs in all the regions of operation.
Table 1. shows the critical parameters of the SPICE level-61 a-Si model and the description of these parameters. The
standard symbols for the key parameters are mentioned within the small brackets beside their description. Table 2 lists
the different model parameters affecting the key performance parameters of the TFT. Apart from these key model
parameters, parameters related to AC analysis such as parasitic capacitances (CGSO and CGDO in farads per meter
channel width), channel resistance (RD and RS in ohms), etc., and other process corners should be taken into account
to make the model more accurate.
Figure 5 shows the equivalent model of level-61 RPI a-Si. It consists of a dependent current source, gate-to-source,
and gate-to-drain capacitances. The AC equivalent model is inherently according to the convention of the transmission
line,22 and it does not incorporate the additional sub-transistors. The schematic shows three terminals of the TFT circuit
with the body terminal shorted to the source terminal. Cgs and Cgd are the gate-to-source capacitance and the gate-
to-drain capacitance, respectively.

2.1 | Analytical equations governing different regions of operation in a-IGZO TFTs

This section provides the set of equations for the conduction of the drain current, following the different regions of
operation of the a-Si TFT.

2.1.1 | Subthreshold regime

Below threshold voltage, fermi-level residing in the deep localized states.21 Equations (2) to (4)23 gives the empirical
equations for the leakage current induced by the holes under the negative gate-to-source voltage. The equations
governing this phenomenon are:

I Ieakage ¼ I hl þ I min ð2Þ


 

V DS V GS
I hl ¼ IOL exp
1 exp
ð3Þ
VDSL VGSL

I min ¼ SIGMA0  V DS ð4Þ

6 of 23 DUBEY ET AL.

Device physics of
amorphous and Experimental
polycrystalline oxide characteristics of a-
TFTs IGZO TFTs

Setting up SPICE model

parameters for below
threshold region and
calibration with
experimental characteristics
If No

If No

Are the parameters

Are the parameters
for sub-threshold
for off-current viz. If Yes
slope viz. – (VMIN,
– (VTO) for a-Si
Δ, GMIN) for a-Si
and (VTO, I0 ,I00,)
and (ETA) for
for poly-Si poly-Si properly
properly tuned? tuned?

If Yes

Setting up model parameters

corresponding for above
threshold and transfer
characteristics.

Are the parameters

If No
for ON-current viz. –
If Yes (γ, μ, VAA and αSAT)
SPICE LEVEL-61 and LEVEL-62 for a-Si and (μ1,
models are ready to use
MMU, ASAT) for
poly-Si properly
tuned?

FIGURE 4 Flowchart depicting the process flow of model adaptation for a-IGZO TFT.

where Ihl is the leakage current due to negative gate bias, Imin is the component of the leakage current due to the
poor resolution of the measuring device, IOL is leakage scaling constant zero-bias leakage current parameter in
amperes, VDSL is hole-leakage current drain voltage parameter in volts, VGSL is hole-leakage current gate voltage
DUBEY ET AL. 7 of 23

TABLE 1 Key SPICE parameters of HSPICE level-61 model.

Regimes of
operation Affecting key parameters Description
Above- ALPHASAT (αSAT), GAMMA (γ), Saturation Modulation Parameter (αSAT), Power law mobility parameter (γ),
threshold MUBAND (μ) (m2/V s), VTO (V) Conduction band mobility (μ), Zero-bias threshold voltage (VTO)
regime
Below- DELTA (Δ), GMIN (m
3 eV
1), VMIN Transition width parameter (Δ), Minimum density of deep states (GMIN),
threshold (V) Convergence parameter (VMIN)
regime

TABLE 2 Key SPICE parameters of HSPICE level-61 model affecting different performance parameters of TFT.

Performance
parameters Level-61 model parameters
S (subthreshold slope) Parameters related to the leakage current and density of states, for example, GMIN, VMIN, and DELTA (Δ).
Ion/Ioff (on-to-off current ALPHASAT (αSAT), Mobility related parameters, for example, GAMMA, MUBAND (μ), VAA, and zero-bias
ratio) threshold voltage VTO
μFE (field-effect GAMMA (γ), MUBAND, VAA
mobility)
VT (threshold voltage) VTO, KVT, TNOM

Ids
Source Drain

Cgs Cgd

Gate

FIGURE 5 Schematic for level-61 TFT model for a-Si.

parameter in volts, EL is the activation energy of the hole leakage current in eV, VTO is zero-bias threshold voltage
in volts, and SIGMA0 is minimum leakage current parameter in amperes. IOL is the minimum value of the leakage
current. VDSL and VGSL account for dependency on the VDS and VGS. SIGMA depends on the measuring instru-
ment resolution.24 EL thermally activates the leakage current with activation energy within 0.5–1 eV for a-Si, as
per the experimental data23 Using the level-61 RPI model, we select EL to be 0.35 eV for the adapted model for
a-IGZO.
To have minimum leakage current, we can effectively change VTO, as all other parameters are process dependent.
VTO can effectively change the off current in the leakage regime. But, as per the simulation, not much difference can
be observed in the log ID–VGS characteristics by varying VTO. Hence, to control ION/IOFF ratio, parameters bringing sig-
nificant changes in the ION current should be used as the critical modulating parameter. Low off-current means less
leakage current and less static power dissipation in the device.
Furthermore, in the subthreshold regime, the location of Fermi level lies away from the conduction band. The
applied gate bias in this region induces sheet electron carriers nsb, to accommodate into the states occupied by
the acceptor atoms. Therefore, the position of the Fermi level is decided by deep donor trap states. The exponential
expression mentioned below states such dependency of the Fermi level on the trap states g(E)23:
8 of 23 DUBEY ET AL.

h i
ðE
EFO Þ
gðEÞ ¼ go e ð5Þ
E DD

where EDD is the characteristic energy of the deep trap states. EFO and go are the energy relative to the fermi level posi-
tion at the zero-bias and zero-bias density of states, respectively.
The equations applicable in this region are:

W
I sub ¼ q μn nsb vdse ð6Þ
L



 2 V 0
t m  V gfbe EPSI ð V e Þ W
I sub ¼ q μn nso   vdse ð7Þ
TOX VO EPS L

V e
DEFO
nso ¼ N c  tm e V th ð8Þ
Vo

qffiffiffiffiffiffiffiffiffiffiffiffiffiffi
where N c ¼ 3  1025 m
3 ; V e ¼ 2:V
2V o
V ; t m ¼
th V o EPS
2 q GMIN
th

2 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3

2ffi
VMIN 4 V gfb V gfb
V gfbe ¼ 1þ þ Δ2 þ –1 5 ð9Þ
2 VMIN VMIN

and V gfb ¼ V gs
VFB

where TOX = dielectric thickness; EPSI and EPS are the insulator and a-Si permittivities, respectively; VO = EDD/q;
Ve = 2Vth Vo (2VO
Vth); Vth = thermal voltage; nsb = electron sheet carrier density, which depends on the material
properties and density of deep states25,26; nso = dark sheet carrier density; tm = charge channel thickness. nso and tm
are the functions of material parameters. From the above equations, we can clearly see that the subthreshold current
can be effectively controlled by tm and Vgfbe, which are dependent on VMIN, Δ and GMIN.
GMIN is the minimum density of deep states (DOS). DOS is extracted from the subthreshold region of the transfer
characteristics of the TFT.21 A significant change in the subthreshold slope (S) is observed due to GMIN parameter.
VMIN and Δ account for very minor changes in the S. Figure 6 reveals that S degrades as the GMIN value increases. A

FIGURE 6 Effect of GMIN parameter on the sub-threshold slope.

DUBEY ET AL. 9 of 23

FIGURE 7 Vth shift observed due to different GMIN values.

lower value of S is desirable as it results in a high ION/IOFF ratio and better performance. Figure 7. depicts an increase
in the threshold voltage as the GMIN value is reduced.
The subthreshold slope or swing in the amorphous silicon devices, modeling the subthreshold slope in terms of
interface traps,27 is given below:


dV GS kT CD þ C it
S ≈ ln10  ð10Þ
dðlog I D Þ q Cox

where k = Boltzmann constant; q = electronic charge; T = temperature; COX = gate-oxide capacitance; CD = depletion
capacitance; Cit = q NS is capacitance associated with the charging of the semiconductor-dielectric interface traps;
NS = density of states at the interface. Modeling the subthreshold slope in terms of interface trap states and deep-bulk
states, as a generalized expression,28 is given below:
 
kT q  TOX pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
S≈ 1þ EPS  N bs þ qN ss ð11Þ
q  logðeÞ EPSI

S (Subthresholg-Slope/Subthresholg-Swing) is related to Nbs (deep bulk states) and NS (interface states), under the
assumption that both Nbs and NS are energy independent. Nbs and NS cannot be determined separately using
Equation (11). The Equation (11) suggests that subthreshold slope can be effectively controlled using Nbs and NS, by set-
ting their upper limits.29

2.1.2 | Above threshold regime

Shur et al.,23 proposed the above threshold conduction current for a-Si TFTs in both the linear and the saturation
region, and is given by the following equations:
8

>
> W V DS
< μFET COX  V GS
V th
V DS for V DS < αSAT ð V GS
V th Þ
L 2αSAT
Ia ¼ ð12Þ
>
: μFET COX W  ðV GS
V th Þ2 αSAT
>
for V DS ≥ αSAT ð V GS
V th Þ
L 2

γ
V GS
V th
μFET ¼ μ  ð13Þ
VAA
10 of 23 DUBEY ET AL.

αnew ¼ αSAT þ KASAT ðTEMP
TNOMÞ ð14Þ

where COX = gate capacitance; W = channel width; L = channel length; αsat ¼ saturation parameter and it provides
detail about the variation of depletion charge through the channel; αnew = value of saturation parameter depending on
the temperature. μFET is the field-effect mobility, and it depends on the gate voltage, and VAA is the characteristic volt-
age for field-effect mobility in volts.
Drain current for any TFTs, in both the saturation and linear regimes, depends on the μFET and αSAT. μFET can be
controlled using γ, μ and VAA.21,24 Hence, the on-current can effectively be modulated using γ, μ, VAA and αSAT.
Parameters γ and μ affect the on-current significantly. As the γ value increases, on current reduces, as shown in
Figure 8. As the μ increases, on-current increases, as shown in Figure 9. Parameters VAA and αSAT, affect the conduc-
tion current the least. A high ION/IOFF ratio is desired, as it increases the performance of the device owing to the low
leakage current.
Finally, in a-Si TFT, the threshold voltage is modeled as

V T ¼ VTO þ KVT ðTEMP
TNOMÞ ð15Þ

FIGURE 8 Effect of GAMMA (γ) parameter on the on-current.

FIGURE 9 Effect of MUBAND (μ) parameter on the on-current.

DUBEY ET AL. 11 of 23

where KVT = Threshold voltage temperature coefficient in (V/ C); TNOM = Parameter measurement temperature in
( C); VTO = Zero-bias threshold voltage in volts; TEMP = operating temperature. Hence, the threshold voltage in a-Si
can be controlled using VTO, TEMP and TNOM.
Equation (15) explicitly describes the behavior of threshold voltage VT according to the temperature variations, evi-
dent in Figure 10. VT increases as the temperature rises from 25 to 150 C. Also, from Figure 10, we can see that as the
gate-to-source bias VGS becomes negative, it doesn't affect the leakage current. Therefore, the model cannot predict
the increasing nature of leakage current for the negative values of gate-to-source voltage even when the drain-to-source
voltage is high (VDS = 5 V).30

2.1.3 | DIBL effect

Figure 11 shows the Drain Induced Barrier Lowering (DIBL) effect in the a-Si-based TFT, as the threshold voltage is
reducing with the increasing values of drain bias predominantly for the smaller channel lengths (L) (≤0.5 μm).31 The
phenomenon of the DIBL effect can be understood as when the drain potential is increased, the depletion region near

FIGURE 10 Temperature dependence of threshold voltage for TFT for VDS = 5 V.

FIGURE 11 DIBL effect.

12 of 23 DUBEY ET AL.

the drain gets closer to the depletion region near the source. Hence, more electric field penetrates the source. Penetra-
tion of the significant electric field lowers the barriers on the source side. It facilitates the source terminal to inject more
carriers into the reduced channel. Consecutively, low gate potential is required to establish the channel for the carrier
conduction through it. Hence, the threshold voltage is thus reduced.

3 | ADAPTATION OF a-IGZO TFT U SING LEVEL-62 RPI POLY-Si

TFT M ODEL

AIM-SPICE level 16 model or HSPICE level-62 is the RPI-SPICE model which is defined for Poly-Si TFT. The model is
based on the polycrystalline MOSFET model. It is a 3-terminal model and does not include a body terminal. The simu-
lation does not add a parasitic drain-body and source-body diode to the model.21 This model design is independent of
the channel length. The model accurately defines devices in the wide geometry range, as the parameters are automati-
cally scaled.
Table 3 shows the key parameters of the poly-Si model, with their remarks on how they affect different regimes of
TFT operation. The standard symbols for the key parameters are mentioned within the small brackets beside their
description, which we will be using to define their equations in different regimes of the characteristic curves.
Table 4. suggests the specific parameters of the level-62 model correspondingly affecting various performance
parameters of the TFT.
Figure 12 shows the equivalent circuit. It includes field effect mobility as a function of gate bias. The design does
not depend on the channel length. This model correctly simulates current conduction in all four regions of operation.

TABLE 3 Key SPICE parameters of HSPICE level-62 model.

Regimes of operation Affecting Key Parameters Description

Above-threshold regime MU0 (μ1), MU1 (μ2) High field mobility (μ1), Low field mobility parameter (μ2)
Below-threshold regime ETA, MMU Subthreshold ideality factor (ETA), Low field mobility exponent (MMU)

TABLE 4 Key SPICE parameters of HSPICE level-62 model affecting different performance parameters of TFT.

Performance parameters Level-62 model parameters

S (subthreshold slope) ETA, MMU
Ion/Ioff (on-to-off current ratio) I0, I00, ASAT, MMU, MU0
μFE (field-effect mobility) MMU, MU0, MU1
VT (threshold voltage) –

FIGURE 12 Schematic for level-61 TFT model for a-Si.

DUBEY ET AL. 13 of 23

3.1 | Analytical equations governing different regions of operation in a-IGZO TFTs

3.1.1 | Subthreshold regime

The leakage regime or subthreshold leakage current is modeled using the thermionics field emission (TFE) of carriers
through the grain boundary trap states.32,33 The equations governing this phenomenon are:

 
q  BLK  V DS
I Ieakage ¼ I0  W eff exp
1  ðX TFE þ X TE Þ þ I diode ð16Þ
kT

where I0 is the leakage scaling constant, BLK gives information on barrier lowering, XTFE is the emission rate from an
effective single trap level located at midgap and XTE provides the rate of only-thermal emission.30




E B qV
Idiode ¼ I00  W eff  exp 1
exp
DS ð17Þ
kT kT

Effectively leakage current or off current can be controlled by setting I0 and I00 SPICE parameters to corresponding
levels. Moreover, the model follows a diffusion-like model for the subthreshold region. In this regime, the induced
charge is trapped in deep acceptor states.21,23 The equations applicable in this region are:



W 2 V GT V DS
I sub ¼ μn  Cox V sth exp 1
exp
ð18Þ
L V sh V sth

V sth ¼ ETA  V th , V th ¼ kB  TEMP=q

Cox ¼ εi =TOX

V GT ¼ V GS
V T

where μn is subthreshold mobility, ETA is the subthreshold ideality parameter, Vth is the thermal voltage, Vsth is the
equivalent thermal voltage, and TOX is the thin-oxide thickness. As the SPICE level 62 model is defined for Poly-Si
TFT, equivalent oxide thickness (EOT) will be used in place of TOX. The EOT of a high-k gate dielectric is the thickness
required by SiO2 to achieve the same voltage modulation effect or the same equivalent capacitance density.34 EOT is
given by

κSiO2
EOT ¼ TOX ð19Þ
κ ox

where TOX is the physical thickness of the dielectric, κSiO2 is the relative permittivity of SiO2 and κox is the relative per-
mittivity of high-k dielectric. Subthreshold slope in silicon MOSFET devices is given by35


dV GS kT CD
S  ln 10  ≈ ln10  1 þ ð20Þ
dðln I D Þ q Cax

where CD is the depletion capacitance.

Also, using Equation (18), subthreshold slope can be written as:

S ¼ ETA  VT  ln 10 ð21Þ

The above equation suggests that the subthreshold ideality factor (ETA) can effectively control the subthreshold
slope.
14 of 23 DUBEY ET AL.

3.1.2 | Above threshold regime

For the above threshold (VGT >0), the conduction current is given by the following equations:
8

> W V 2DS
>
< μFET Cox V GT V DS
for V DS < αsat V GT
L 2αsat
Ia ¼ ð22Þ
>
> W V 2GT αsat
: μFET Cox for V DS ≥ αsat V GT
L 2

1 1 1
¼ þ ð23Þ
μFET μ1 μ2 ð2V GT =V sth ÞMMU

LASAT
αsat ¼ ASAT

DASATðTEMP
TNOMÞ ð24Þ
L

where μFET is gate-voltage dependent field effect mobility. It takes into account the effects of trap states. αsat provides
detail about the variation of depletion charge through the channel. In SPICE model parameters, μ1 and MMU are high
field mobility and low field mobility exponent. ASAT is the Vsat proportionality constant, DASAT is the ASAT tempera-
ture coefficient, LASAT is the coefficient for length dependence of ASAT, and TNOM is the temperature at which
parameters are measured.
Effective mobility is extracted from experimental results and μ1, MMU are set to appropriate values. As gate bias
voltage is increased, there is an increase in the effective mobility in Poly-Si TFT. Also, αsat It depends on channel length,
so its value needs to be tweaked as per different channel lengths of TFT. Finally, in Poly-Si TFT, the threshold voltage
is modeled as

AT  V 2DS þ BT
V T ¼ V TX
ð25Þ
L

Equation (2) indicates a decreased threshold voltage with the reduced channel length. For adapting the model for
oxide TFT, values of A and B are tuned to set it ready for almost all channel lengths.

3.1.3 | Kink regime

The output characteristics of poly-ZnO TFTs display an unusual current increase, known as the ‘kink effect,’ at high
drain voltages. This effect is attributed to the high electric field in the saturation region, caused by the relatively higher
supply voltages used in poly-ZnO TFT circuits. This causes increased charge density in the accumulated charge carriers
due to impact ionization near the drain's pinch-off region. As per the charge sheet approach, the applied electric field
has horizontal and vertical components.36 The kink effect is more prominent at lower gate voltages due to the higher
horizontal electric field. As the gate voltage increases, the vertical component becomes dominant, decreasing the kink
current. Also, the grain size in the polysilicon channel impacts the kink effect phenomenon. Smaller grain sizes result
in more grain boundaries, increasing trapped charge density and intensifying the avalanche effect. Larger grain sizes
reduce traps, decreasing the electric field and avalanche effect. The Kink effect, influenced by impact ionization and
gate length, is related to the channel's impact ionization and carrier trapping.37,38 The rapid rise in drain current with
increased drain bias in the saturation regime is critical. The excess current in short-channel poly-Si and poly-ZnO thin-
film transistors (TFTs) remarkably shows the kink effect. This excess current, caused by impact ionization and ampli-
fied by parasitic bipolar transistor action, scales almost inversely with the square of the gate length (L2).39
Figure 13 shows the sharp increase in the drain current as the drain bias increases while TFT operates in the satura-
tion region. This regime comes into the picture under substantial drain biases for Poly-Si TFT. Level 62 models the kink
effect as impact ionization in the pinch-off region and adds the positive feedback Ikink impact ionization current to the
original drain current. The governing equations for the kink effect are:
DUBEY ET AL. 15 of 23

FIGURE 13 Kink effect and kink regime.


VKINK
I kink ¼ Akink I a ðV DS
V DSAT Þexp
ð26Þ
V DS
V DSAT


1 LKINK MK
Akink ¼ , V DSAT ¼ αsat V GT ð27Þ
VKINK L

where LKINK is the kink effect constant, MK is the kink effect exponent and VKINK is the kink effect voltage.

4 | C ALIBRATION OF THE ADAPTED SPICE M ODELS

To ensure the correctness of the adaptation method, the adapted level-61 RPI a-Si and level-62 RPI poly-Si adapted
models are calibrated against two experimental IGZO TFTs.18,19 W. Muhammad Hilmi bin Wan et al.,18 fabricated
a-IGZO TFT using Al2O3 as a gate dielectric with a physical thickness (tOX) of 25 nm in a flexible 50 μm thick polymide
substrate. The thermal budget used in the TFT fabrication was less than 150 C. The aspect ratio used for the fabricated
TFT device is 280 μm/6 μm. Performance parameters reported by the authors from the experimental data18 are field
effect mobility (μeff) as to be 14 cm2/V s, threshold voltage (VT) as to be 0.97 V, a subthreshold slope (S) as to be
140 mV/dec, and, an on-to-off current ratio (ION/IOFF) of the order 109. Samanta et al.19 fabricated a flexible a-IGZO
TFT using high-k dielectric material, HfO2, with a physical thickness (tOX) of 10 nm. The aspect ratio used for the fabri-
cated TFT was 10 μm/5 μm. Performance parameters reported by the authors from the experimental data19, are field
effect mobility (μeff) as to be 55.3 cm2/V s, threshold voltage (VT) as to be 1.5 V, a subthreshold slope (S) as to be
70.2 mV/dec, and, an on-to-off current ratio (ION/IOFF) of the order greater than 109.

4.1 | Model validation for level-61 RPI a-Si TFT model

Figure 14A,B and C,D shows the adaption of the simulated characteristics of level-61 a-Si TFT against the a-IGZO TFT
for References [18] and [19], respectively.
Parameter extraction is required to analyze the adapted model in terms of its degree of agreement with the experi-
mental performance parameters. Threshold voltage and field-effect mobility are deduced from the linear region of the
transfer characteristic of TFT and subthreshold-slope from the linear region of the corresponding log plot.
For the adapted RPI level-61 a-Si model, the performance parameters as compared to that available from the experi-
mental data,18 are extracted as field-effect mobility around 9.3 cm2/V s, threshold voltage as 1 V, subthreshold-slope
around 140 mV/dec, and ION/IOFF around 1.169  109. Also, the performance parameters for the adapted RPI level-61
16 of 23 DUBEY ET AL.

F I G U R E 1 4 Experimental and simulated characteristics of a-IGZO TFT using level-61 a-Si TFT: (A) transfer characteristics,18
(B) output characteristics,18 (C) transfer characteristics,19 (D) output characteristics.19

a-Si model, as compared to that available from the experimental data,19 are extracted as field-effect mobility around
32.2 cm2/V s, threshold voltage as 1.5 V, subthreshold-slope around 65 mV/dec, and ION/IOFF around 1.126  109.
Hence, the adapted a-Si model performance parameters align closely with the performance parameters experimentally
derived for the a-IGZO TFTs.
For Reference [18], Figures 15–18, help suggest how we have deduced the performance parameters for the simu-
lated TFT model, from the logarithmic plot of the transfer characteristics. Figure 15 shows the deduction of the trans-
conductance parameter gm, by performing the first-order differentiation of ID–VGS characteristic of the adapted a-Si
TFT model. The peak value of the ID–VGS characteristic's second-order derivative curve provides the threshold voltage.
Figure. 16 shows the extraction of field-effect mobility at different drain voltages. Figure 17 deduces the subthresh-
old slope from log ID–VGS characteristic. Figure 18 extracts the on-to-off current ratio.

4.2 | Model validation for level-62 RPI poly-Si TFT model

Figure 19A,B and C,D shows the calibration of a-IGZO TFT with the experimental work of References [18,19], respec-
tively. Extracted parameters for the adapted RPI level-62 poly-Si model are found to be as field-effect mobility around
12.8995 cm2/V s, threshold voltage at 0.85 V, subthreshold-slope around 140 mV/dec, and ION/IOFF
around 7.49  109, against the experimental parameters derived for Reference [18]. Hence, the adapted a-Si model
DUBEY ET AL. 17 of 23

FIGURE 15 Extraction of the transconductance parameter and the threshold voltage for adapted a-Si TFT model against experiment.18

FIGURE 16 Extraction of the field-effect mobility for adapted a-Si TFT model against experiment.18

performance parameters, lie in close agreement to the performance parameters experimentally derived for the flexible
a-IGZO TFT. Also, the extracted parameters for the adapted RPI level-62 poly-Si model, as compared to the perfor-
mance parameters available from the experimental data,19 are found to be as field-effect mobility around 49.8 cm2/V s,
threshold voltage at 1.38 V, subthreshold-slope around 70 mV/dec, and ION/IOFF around 0.89  109. Hence, the
adapted poly-Si model performance parameters align closely with the performance parameters experimentally derived
for the a-IGZO TFTs. For experimental work Reference [18], Figures 20–23 show how to deduce the performance
parameters for the simulated TFT model, from the logarithmic plot of the transfer characteristics. Figure 20 shows the
deduction of the transconductance parameter gm, by performing the first-order differentiation of ID–VGS characteristic
of the adapted a-Si TFT model. The peak value of the ID–VGS characteristic's second-order differentiation curve pro-
vides the threshold voltage.
Figure 21 shows the extraction of field-effect mobility at different drain voltages. Figure 22 deduces the subthreshold
slope from log ID–VGS characteristic. Figure 23 extracts the on-to-off current ratio.
When compared to other available models,7,12,14 the proposed adapted model addresses key effects, specifically the
DIBL and the Kink Effect, and includes DOS model for trap states evident in amorphous and poly-crystalline channel
materials. Jingrui Guo et al.12 used an analytical surface potential-based compact model. However, as the employed
model is the Verilog-A model, various analyses, including PVT and Corner analyses, are not possible using this model.
Sharma et al.14 utilizes physical and analytical modeling. This model helps design TFT circuits with different channel
18 of 23 DUBEY ET AL.

FIGURE 17 Extraction of the subthreshold slope for adapted a-Si TFT model against experiment.18

FIGURE 18 Extraction of the on-to-off current ratio for adapted a-Si TFT model against experiment.18

lengths using unified parameters. However, the limitation of the model above is that it sets a specific limitation on the
channel-length range (L = 2–20 μm). Kandpal et al.7 employ a physical and empirical modeling approach for a-IGZO
SPICE model adaptation. This model is versatile for all oxide TFTs regardless of channel or dielectric material. How-
ever, the model doesn't significantly address the key effects such as the kink effect, deep and tail trap states. The
adapted model proposed in this work integrates behavioral and analytical modeling techniques, showcasing its versatil-
ity and flexibility in the modeling process. Moreover, the adapted model supports various analyses, including PVT and
Corner analyses. The adapted model requires minimum parameter extraction, making it efficient and practical. More-
over, it applies to all kinds of a-IGZO-based circuits, indicating its universal applicability.

5 | COMPARISON OF THE ADAPTED MODEL W ITH

E X PER IM E NTA L WOR K

Tables 5 and 6 compare the different performance parameters for adapted level-61 a-Si and level-62 poly-Si, respec-
tively, against the experimental characteristics.18,19 For level-61 a-Si TFT, the maximum deviation in the subthreshold
DUBEY ET AL. 19 of 23

F I G U R E 1 9 Experimental and simulated characteristics of a-IGZO TFT using level-62 poly-Si TFT depicting kink effect: (A) transfer
characteristics,18 (B) output characteristics,18 (C) transfer characteristics,19 (D) output characteristics.19

FIGURE 20 Extraction of the transconductance parameter and the threshold voltage for adapted poly-Si TFT model against
experiment.18

slope is approximately 5 mV/decade, and for level-62 poly-Si TFT, the divergence in the subthreshold slope is about
0.2 mV/decade, respectively. Also, an average variation of 2.4% and 2.27% was observed in the output characteristic of
20 of 23 DUBEY ET AL.

FIGURE 21 Extraction of the field-effect mobility for adapted poly-Si TFT model against experiment.18

FIGURE 22 Extraction of the subthreshold slope for adapted poly-Si TFT model against experiment.18

adapted level-61 and level-62 models, respectively. Hence, the drain current versus gate-source voltage curve, and the
drain current versus drain-source voltage plot, for the experimental data and the adapted model can be argued to have
good accordance with each other, with relatively more accuracy in the adapted poly-Si TFT.
Both models show a good match with experimental works. The adapted level-62 poly-Si TFT model for a-IGZO TFT
has not been developed to date, to the author's best knowledge. Also, the adapted level-61 a-Si TFT model for a-IGZO
TFT provides relatively more accurate characteristics than the previous calibration methods. However, the adapted
models have certain limitations. The adapted SPICE Level-61 and Level-62 do not include the random orientation of
grain boundaries and distribution of the grain boundaries physically present in the polycrystalline channel layer. More-
over, both models define the traps using the density of states for all different kinds of channel materials like amor-
phous, nanocrystalline, and polycrystalline. The adapted model does not include the effect of Positive and negative bias
temperature stress and illumination stress on TFT performance. Moreover, The nature of traps is mostly assumed to be
acceptor type. However, in the physical scenario, they could be donor-type, affecting VT and SS differently. Therefore,
the researchers can consider these limitation while they improve or devise new compact models for oxide TFTs.
For the short channel devices, due to the tunneling phenomenon, electron–hole pairs are produced close to the high
electric field area of the drain terminal under the large applied drain-to-source potential bias. This results in the a-Si
DUBEY ET AL. 21 of 23

FIGURE 23 Extraction of the on-to-off current ratio for adapted poly-Si TFT model against experiment.18

TABLE 5 Comparison of the extracted parameters of the level-61 a-Si TFT model adapted for two experimental works viz.18,19

Performance Level-61 a-Si TFT model Level-61 a-Si TFT model

parameters Experiment18 adapted against18 Experiment19 adapted against19
μeff 14 cm2/V s 9.3 cm2/V s 55.3 cm2/V s 32.2 cm2/V s
VT 0.97 V 1V 1.5 V 1.5 V
S 140 mV/dec 140 mV/dec 70.2 mV/dec 65 mV/dec
ION/IOFF 10 9
1.169  10 9
>10 9
1.126  109

TABLE 6 Comparison of the extracted parameters of the level-62 poly-Si TFT model adapted for two experimental works viz.18,19

Performance Level-62 poly-Si TFT model Level-62 poly-Si TFT model

parameters Experiment18 adapted against18 Experiment19 adapted against19
μeff 14 cm2/V s 12.8995 cm2/V s 55.3 cm2/V s 49.8 cm2/V s
VT 0.97 V 0.85 V 1.5 V 1.38 V
S 140 mV/dec 140 mV/dec 70.2 mV/dec 70 mV/dec
ION/IOFF 10 9
7.49  10 9
>10 9
0.89  109

TFT experiencing a kink-effect, which is accompanied by a sudden increase in drain current and a decrease in thresh-
old voltage.31 Kink-effect is also evident in the poly-Si TFTs, but the avalanche effect predominates it.36,40,41 The grain
boundaries in the poly-Si thin film account for the creation of traps that contribute to the trap carriers in the
space-charge region. As a result avalanche generation effect is prominent in the poly-Si TFT structure. But the adapted
level-61 a-Si TFT model does not assist with the kink-effect modeling, which is accurately aided by using the
adapted level-62 poly-Si TFT model. Hence, to account for the kink effect in the computation of circuit-design simula-
tors, adapted level-62 poly-Si TFT model is more relevant.

6 | C ON C L U S I ON

The level-61 a-Si TFT and level-62 poly-Si TFT models are successfully adapted for a-IGZO TFTs. Such adapted models
can be directly used for circuit design simulators for all types of a-IGZO-based circuits. The consistency of the adapted
model characteristics with the fabricated a-IGZO device characteristics validates the adapted models.
22 of 23 DUBEY ET AL.

A C K N O WL E D G M E N T S
This work is supported by IIITA seed money project IIITA/RO/323/2021.

DATA AVAILABILITY STATEMENT

Data sharing is not applicable to this article as no new data were created or analyzed in this study.

ORCID
Kavindra Kandpal https://orcid.org/0000-0002-2683-2230

R EF E RE N C E S
1. Fortunato E, Barquinha P, Martins R. Oxide semiconductor thin-film transistors: a review of recent advances. Adv Mater. 2012;24:2945-
2986. doi:10.1002/ADMA.201103228
2. Torricelli F, Smits ECP, Meijboom JR, et al. Transport physics and device modeling of zinc oxide thin-film transistors - part II: contact
resistance in short channel devices. IEEE Trans Electron Devices. 2011;58:3025-3033. doi:10.1109/TED.2011.2159929
3. Modern Semiconductor Devices for Integrated Circuits—Chenming Hu. https://www.chu.berkeley.edu/modern-semiconductor-devices-
for-integrated-circuits-chenming-calvin-hu-2010/
4. Torricelli F, Meijboom JR, Smits E, et al. Transport physics and device modeling of zinc oxide thin-film transistors part I: Long-Channel
devices. IEEE Trans Electron Devices. 2011;58:2610-2619. doi:10.1109/TED.2011.2155910
5. Kimura M. Features and applications of various TFTs—Si based matured TFTs and oxide semiconductor based transparent TFTs. IEEE
Photonic Society 24th Annual Meeting, PHO 2011, 557–558; 2011. doi:10.1109/PHO.2011.6110669
6. Nishii J, Hossain FM, Takagi S, et al. High mobility thin film transistors with transparent ZnO channels. Jpn J Appl Phys Part 2: Lett.
2003;42:L347. doi:10.1143/JJAP.42.L347/XML
7. Kandpal K, Gupta N. Adaptation of a compact SPICE level 3 model for oxide thin-film transistors. J Comput Electron. 2019;18:1037-
1044. doi:10.1007/s10825-019-01344-0
8. Lee S, Jeon S, Nathan A. Modeling sub-threshold current-voltage characteristics in thin film transistors. IEEE/OSA J Disp Technol. 2013;
9:883-889. doi:10.1109/JDT.2013.2256878
9. Hossain FM, Nishii J, Takagi S, et al. Modeling and simulation of polycrystalline ZnO thin-film transistors. J Appl Phys. 2003;94:7768-
7777. doi:10.1063/1.1628834
10. Chowdhury MDH, Migliorato P, Jang J. Light induced instabilities in amorphous indium-gallium-zinc-oxide thin-film transistors.
ApPhL. 2010;97:173506. doi:10.1063/1.3503971
11. Migliorato P, Chowdhury MDH, Um JG, Seok M, Martivenga M, Jang J. Characterization and modeling of a-IGZO TFTs. IEEE/OSA J
Disp Technol. 2015;11:497-505. doi:10.1109/JDT.2014.2328335
12. Guo J, Zhao Y, Yang G, et al. Analytical surface potential-based compact model for independent dual gate a-IGZO TFT. IEEE Trans Elec-
tron Devices. 2021;68:2049-2055. doi:10.1109/TED.2021.3054359
13. Cordero A, Neta B, Torregrosa JR. Memorizing Schröder's method as an efficient strategy for estimating roots of unknown multiplicity.
Mathematics. 2021;9:2570.
14. Sharma A, Bahubalindruni PG, Bharti M, Barquinha P. Physical parameters based analytical I-V model of long and short channel
a-IGZO TFTs. Solid State Electron. 2022;192:108273. doi:10.1016/J.SSE.2022.108273
15. Jeon YW, Hur I, Kim Y, et al. Physics-based SPICE model of a-InGaZnO thin-film transistor using Verilog-A. J Semicond Technol Sci.
2011;11:153-161. doi:10.5573/JSTS.2011.11.3.153
16. Moldovan O, Castro-Carranza A, Cerdeira A, et al. A compact model and direct parameters extraction techniques for amorphous
gallium-indium-zinc-oxide thin film transistors. Solid State Electron. 2016;126:81-86. doi:10.1016/J.SSE.2016.09.011
17. Shabanpour R, Meister T, Ishida K, et al. A transistor model for a-IGZO TFT circuit design built upon the RPI-aTFT model. In: Proceed-
ings—2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017, Institute of Electrical and Electronics Engi-
neers Inc. (pp. 129–132); 2017.
18. Muhammad Hilmi Bin Wan, W., Fazlida, W., Muhammad Hilmi Bin Wan Zaidi, W., Costa, J., Member, S., Pouryazdan, A., Fazlida
Hanim Abdullah, W., Münzenrieder, N.: Flexible IGZO TFT Spice model and design of active strain compensation circuits for bendable
active matrix arrays flexible IGZO TFT SPICE model and design of active strain-compensation circuits for bendable active matrix arrays.
19. Samanta S, Chand U, Xu S, et al. Low subthreshold swing and high mobility amorphous indium-gallium-zinc-oxide thin-film transistor
with thin HfO2 gate dielectric and excellent uniformity. IEEE Electron Device Lett. 2020;41:856-859. doi:10.1109/LED.2020.2985787
20. Desai MS, Kandpal K, Goswami R. A multiple-trapping-and-release transport based threshold voltage model for oxide thin film transis-
tors. J Electron Mater. 2021;50:4050-4057. doi:10.1007/S11664-021-08907-7/FIGURES/7
21. hspice_mosmod – [PDF Document]. https://vdocuments.net/hspicemosmod.html?page=1
22. Greve DW, Hay VR. Interpretation of capacitance-voltage characteristics of polycrystalline silicon thin-film transistors. J Appl Phys.
1998;61:1176-1180. doi:10.1063/1.338164
23. Shur MS, Slade HC, Jacunski MD, Owusu AA, Ytterdal T. SPICE models for amorphous silicon and polysilicon thin film transistors.
J Electrochem Soc. 1997;144:2833-2839. doi:10.1149/1.1837903/XML
24. Eldo Device Equations Manual. 1995.
DUBEY ET AL. 23 of 23

25. Shur MS, Slade HC, Ytterdl T, et al. Modeling and scaling of a-Si:H and poly-Si thin film transistors. MRS Online Proc Library (OPL).
1997;467:831-842. doi:10.1557/PROC-467-831
26. Slade HC, Shur MS, Deane SC, Hack M. Physics of below threshold current distribution in a-Si:H TFTs. MRS Online Proc Library (OPL).
1996;420:257-262. doi:10.1557/PROC-420-257
27. Chung YJ, Kim JH, Kim UK, Ryu M, Lee SY, Hwang CS. Study on the existence of abnormal hysteresis in Hf-in-Zn-O thin film transis-
tors under illumination. Electrochem Solid St. 2011;14:H300. doi:10.1149/1.3589244/XML
28. Neudeck GW, Malhotra AK. An amorphous silicon thin film transistor: theory and experiment. Solid State Electron. 1976;19:721-729.
doi:10.1016/0038-1101(76)90149-0
29. Rolland A, Richard J, Kleider JP, Mencaraglia D. Electrical properties of amorphous silicon transistors and MIS-devices: comparative
study of top nitride and bottom nitride configurations. J Electrochem Soc. 1993;140:3679-3683. doi:10.1149/1.2221149
30. Jacunski MD, Shur MS, Owusu AA, Ytterdal T, Hack M, Iniguez B. Short-channel DC SPICE model for polysilicon thin-film transistors
including temperature effects. IEEE Trans Electron Devices. 1999;46:1146-1158. doi:10.1109/16.766877
31. Qu JT, Zhang HM, Xu XB, Qin SS. Study of drain induced barrier lowering (DIBL) effect for strained Si nMOSFET. Procedia Eng. 2011;
16:298-305. doi:10.1016/J.PROENG.2011.08.1087
32. Bhattacharya SS, Banerjee SK, Nguyen BY, Tobin PJ. Temperature dependence of the anomalous leakage current in polysilicon-
on-insulator MOSFET's. IEEE Trans Electron Devices. 1994;41:221-227. doi:10.1109/16.277375
33. Wu IW, Lewis AG, Huang TY, Jackson WB, Chiang A. Mechanism and device-to-device variation of leakage current in polysilicon thin
film transistors. Tech Dig Int Electron Devices Meet. 1990;867–870. doi:10.1109/IEDM.1990.237025
34. Kandpal K, Gupta N. Investigations on high-j dielectrics for low threshold voltage and low leakage zinc oxide thin-film transistor, using
material selection methodologies. J Mater Sci: Mater Electron. 2016;27:5972–5981. doi:10.1007/s10854-016-4519-0
35. Rudan M. Physics of semiconductor devices. Phys Semicond Devices. 2015;1–649:155–174. doi:10.1007/978-1-4939-1151-6/COVER
36. Bindra S, Haldar S, Gupta RS. Modeling of kink effect in polysilicon thin film transistor using charge sheet approach. Solid State Elec-
tron. 2003;47:645-651. doi:10.1016/S0038-1101(02)00337-4
37. Owusu AA, Jacunski MD, Shur MS, Ytterdal T. Spice model for the kink effect in polysilicon TFTs. Proc Electrochem Soc. 1997;96:23.
38. Armstrong GA, Brotherton SD, Ayres JR. A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator
transistors. Solid State Electron. 1996;39:1337-1346. doi:10.1016/0038-1101(96)00030-5
39. Valletta A, Gaucci P, Mariucci L, Fortunato G, Brotherton SD. Kink effect in short-channel polycrystalline silicon thin-film transistors.
Appl Phys Lett. 2004;85:3113-3115. doi:10.1063/1.1806252
40. Chung D, Choi B-D, Park S-G. A new model for kink-effect in poly-silicon thin-film transistors.
41. Liu TC, Kuo JB. Grain boundary-related kink effects of poly-Si TFTs. In 2012 IEEE International Conference on Electron Devices and
Solid State Circuit, EDSSC 2012. 2012. doi:10.1109/EDSSC.2012.6482891

How to cite this article: Dubey D, Goswami M, Kandpal K. Adaptation and comparative analysis of HSPICE
level-61 and level-62 model for a-IGZO thin film transistors. Int J Numer Model. 2024;37(2):e3210. doi:10.1002/
jnm.3210.