Class 2 - 3 - A Top Level View of Computer Functions Adn Interconnection

Class 2 - 3
Computer Organization and

Architecture 1
3 SKS
Dr. Eng. Tati Erlina, MIT/Nefy Putri Novani, MT
For the Glory of the Nation

+
Class 2
A Top Level View of A Computer
Function and Interconnection
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights

reserved.
+
Computer Components
• Contemporary computer designs are based on
concepts developed by John von Neumann at the
Institute for Advanced Studies, Princeton
• Referred to as the von Neumann architecture and
is based on three key concepts:
• Data and instructions are stored in a single read-
write memory
• The contents of this memory are addressable by
location, without regard to the type of data
contained there
• Execution occurs in a sequential fashion (unless
explicitly modified) from one instruction to the next
• Hardwired program
• The result of the process of connecting the various
For the Glory of the Nation components in the desired configuration
reserved.
+ Data
Sequence of
arithmetic
and logic
functions
Results
(a) Programming in hardware
Hardware
and Software Instruction Instruction
Approaches codes interpreter
Control
signals
General-purpose
Data arithmetic Results
and logic
functions
(b) Programming in software
For the Glory of the Nation Figure 3.1 Hardware and Software Approaches
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Software
• A sequence of codes or instructions
• Part of the hardware interprets each instruction
and generates control signals Software
• Provide a new sequence of codes for each new
program instead of rewiring the hardware
Major components:
• CPU I/O
• Instruction interpreter Components
• Module of general-purpose arithmetic and logic
functions
• I/O Components
• Input module
+ • Contains basic components for accepting data
and instructions and converting them into an
internal form of signals usable by the system
• Output module
• Means of reporting results

reserved.
Memory Memory buffer
address register register (MBR)
(MAR) • Contains the data to
• Specifies the be written into
address in memory memory or receives
for the next read or the data read from
write memory
I/O address I/O buffer

register (I/OAR) register (I/OBR)
• Specifies a • Used for the
particular I/O device exchange of data
+ between an I/O
module and the
CPU

reserved.
CPU Main Memory
0
System 1
2
PC MAR Bus
Instruction
Instruction
Instruction
IR MBR
I/O AR
Data
Execution
unit Data
I/O BR
Data
Data
I/O Module n–2

n–1
PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register

Figure 3.2 Computer Components: Top-Level View
reserved.
Fetch Cycle Execute Cycle
Fetch Next Execute

START HALT
Instruction Instruction
Figure 3.3 Basic Instruction Cycle


reserved.
+ Fetch Cycle
• At the beginning of each instruction cycle the
processor fetches an instruction from memory
• The program counter (PC) holds the address of the instruction to
be fetched next
• The processor increments the PC after each instruction fetch so

that it will fetch the next instruction in sequence
• The fetched instruction is loaded into the

instruction register (IR)
• The processor interprets the instruction and performs the
required action
reserved.
Action Categories
• Data transferred • Data transferred to
from processor to or from a peripheral
memory or from device by
memory to transferring between
processor the processor and
an I/O module
Processor- Processor-
memory I/O
Data
Control
processing
• An instruction may • The processor may

specify that the perform some
sequence of arithmetic or logic
execution be altered operation on data

reserved.
0 3 4 15
Opcode Address
(a) Instruction format
0 1 15
S Magnitude
(b) Integer format
Program Counter (PC) = Address of instruction

Instruction Register (IR) = Instruction being executed
Accumulator (AC) = Temporary storage
(c) Internal CPU registers
0001 = Load AC from Memory

0010 = Store AC to Memory
0101 = Add to AC from Memory
(d) Partial list of opcodes
For the Glory of the Nation Figure 3.4 Characteristics of a Hypothetical Machine
reserved.
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 0 PC 300 1 9 4 0 3 0 1 PC
301 5 9 4 1 AC 301 5 9 4 1 0 0 0 3 AC
302 2 9 4 1 1 9 4 0 IR 302 2 9 4 1 1 9 4 0 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 2
Step 1 Step 2
300 1 9 4 0 3 0 1 PC 300 1 9 4 0 3 0 2 PC
301 5 9 4 1 0 0 0 3 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 5 9 4 1 IR 302 2 9 4 1 5 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3 3+2=5
941 0 0 0 2 941 0 0 0 2
Step 3 Step 4
300 1 9 4 0 3 0 2 PC 300 1 9 4 0 3 0 3 PC
301 5 9 4 1 0 0 0 5 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 2 9 4 1 IR 302 2 9 4 1 2 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 5
Step 5 Step 6
Figure 3.5 Example of Program Execution

(contents of memory and registers in hexadecimal)
reserved.
Instruction Operand Operand
fetch fetch store
Multiple Multiple
operands results
Instruction Instruction Operand Operand

Data
address operation address address
Operation
calculation decoding calculation calculation
Return for string

Instruction complete, or vector data
fetch next instruction

Figure 3.6 Instruction Cycle State Diagram
reserved.
Program Generated by some condition that occurs as a result of an instruction
execution, such as arithmetic overflow, division by zero, attempt to
execute an illegal machine instruction, or reference outside a user's
allowed memory space.
Timer Generated by a timer within the processor. This allows the operating
system to perform certain functions on a regular basis.
I/O Generated by an I/O controller, to signal normal completion of an
operation, request service from the processor, or to signal a variety of
error conditions.
Hardware failure Generated by a failure such as power failure or memory parity error.
Table 3.1
Classes of Interrupts

reserved.
User I/O User I/O User I/O
Program Program Program Program Program Program
1 4 1 4 1 4
I/O I/O I/O

Command Command Command
WRITE WRITE WRITE
5
2a
END
2 2
Interrupt Interrupt
2b Handler Handler
WRITE WRITE 5 WRITE 5
END END
3a
3 3
3b
WRITE WRITE WRITE
(a) No interrupts (b) Interrupts; short I/O wait (c) Interrupts; long I/O wait
= interrupt occurs during course of execution of user program

Figure 3.7 Program Flow of Control Without and With Interrupts
User Program Interrupt Handler
i
Interrupt
occurs here i+1

Figure 3.8 Transfer of Control via Interrupts
reserved.
Fetch Cycle Execute Cycle Interrupt Cycle
Interrupts
Disabled
Check for
Fetch Next Execute
START Interrupt;
Instruction Instruction Interrupts Process Interrupt
Enabled
HALT
Figure 3.9 Instruction Cycle with Interrupts


reserved.
Time
1 1
4 4
I/O operation
I/O operation;
processor waits 2a concurrent with
processor executing
5 5
2b
2
4
I/O operation
4 3a concurrent with
processor executing
I/O operation;
processor waits 5
5 3b
(b) With interrupts

3
(a) Without interrupts
For the Glory of the Nation Figure 3.10 Program Timing: Short I/O Wait
reserved.
Time
1 1
4 4
I/O operation; 2 I/O operation

processor waits concurrent with
processor executing;
then processor
waits
5
5
2
4
4
3 I/O operation
concurrent with
I/O operation; processor executing;
processor waits then processor
waits
5
5
3 (b) With interrupts
(a) Without interrupts
For the Glory of the Nation Figure 3.11 Program Timing: Long I/O Wait

Instruction Operand Operand
fetch fetch store
Multiple Multiple
operands results
Instruction Instruction Operand Operand

Data Interrupt
address operation address address Interrupt
Operation check
calculation decoding calculation calculation
No
Instruction complete, Return for string interrupt
fetch next instruction or vector data
Figure 3.12 Instruction Cycle State Diagram, With Interrupts

reserved.
Interrupt
User program handler X
Interrupt
handler Y
(a) Sequential interrupt processing
Interrupt
User program handler X
Interrupt
handler Y
(b) Nested interrupt processing

Figure 3.13 Transfer of Control with Multiple Interrupts

Printer Communication
User program
interrupt service routine interrupt service routine
t=0
15
0 t=
t =1
t = 25
t= t = 25 Disk
40 interrupt service routine
t=
35
Figure 3.14 Example Time Sequence of Multiple Interrupts


+ I/O Function
• I/O module can exchange data directly with the processor
• Processor can read data from or write data to an I/O
module
• Processor identifies a specific device that is controlled by a
particular I/O module
• I/O instructions rather than memory referencing instructions
• In some cases it is desirable to allow I/O exchanges to occur

directly with memory
• The processor grants to an I/O module the authority to read
from or write to memory so that the I/O memory transfer can
occur without tying up the processor
• The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
• This operation is known as direct memory access (DMA)
reserved.
Read Memory
Write
N Words
Address 0 Data
Data N–1
Read I/O Module Internal

Write Data
External
Address M Ports Data
Internal
Data Interrupt
Signals
External
Data
Instructions Address
Control
Data CPU Signals
Interrupt Data
Signals
For the Glory of the Nation Figure 3.15 Computer Modules

reserved.
The interconnection structure must support the following types
of transfers:
Memory Processor I/O to or

to to I/O to Processor from
processor to I/O
processor memory memory
An I/O
module is
allowed to
exchange
Processor Processor data directly
reads an Processor reads data Processor with
instruction writes a unit from an I/O sends data memory
or a unit of of data to device via to the I/O without
data from memory an I/O device going
memory module through the
processor
using direct
memory
access

A communication pathway Signals transmitted by any
connecting two or more one device are available for
devices reception by all other
• Key characteristic is that it is a devices attached to the bus
shared transmission medium • If two devices transmit during the
same time period their signals will
overlap and become garbled
Typically consists of Computer systems contain
Bus
multiple communication a number of different buses
lines that provide pathways
• Each line is capable of transmitting between components at
Intercon
signals representing binary 1 and
binary 0 various levels of the
computer system hierarchy
-nection
System bus
• A bus that connects major computer The most common
components (processor, memory, computer interconnection
I/O) structures are based on the
use of one or more system
buses

Data Bus
• Data lines that provide a path for moving data among
system modules
• May consist of 32, 64, 128, or more separate lines
• The number of lines is referred to as the width of the data
bus
• The number of lines determines how many bits can be
transferred at a time
• The width of the data bus
is a key factor in determining overall
system performance

reserved.
+ Address Bus Control Bus
• Used to designate the source or

• Used to control the access
destination of the data on the
data bus and the use of the data and
address lines
• If the processor wishes to
read a word of data from • Because the data and address
memory it puts the lines are shared by all
address of the desired components there must be a
word on the address lines means of controlling their use
• Width determines the maximum • Control signals transmit both
possible memory capacity of the command and timing
system information among system
modules
• Also used to address I/O ports
• The higher order bits are • Timing signals indicate the
used to select a particular validity of data and address
module on the bus and information
the lower order bits select
a memory location or I/O
• Command signals specify
operations to be performed
port within the module
CPU Memory Memory I/O I/O
Control lines
Address lines Bus
Data lines
Figure 3.16 Bus Interconnection Scheme

reserved.
+ Point-to-Point Interconnect
Principal reason for change At higher and higher data
was the electrical rates it becomes
constraints encountered increasingly difficult to
with increasing the perform the synchronization
frequency of wide and arbitration functions in a
synchronous buses timely fashion
A conventional shared bus

on the same chip magnified
the difficulties of increasing Has lower latency, higher
data rate, and better
bus data rate and reducing scalability
bus latency to keep up with
the processors

reserved.
+ Quick Path Interconnect
QPI
nIntroduced in 2008
nMultiple direct connections
n Direct pairwise connections to other components eliminating
the need for arbitration found in shared transmission systems
nLayered protocol architecture
n These processor level interconnects use a layered protocol
architecture rather than the simple use of control signals found
in shared bus arrangements
nPacketized data transfer
n Data are sent as a sequence of packets each of which includes
control headers and error control codes

I/O device
I/O device
I/O Hub
DRAM
DRAM
Core Core
A B
DRAM
DRAM
Core Core
C D
I/O device
I/O device
I/O Hub
QPI PCI Express Memory bus

Figure 3.17 Multicore Configuration Using QPI
reserved.
Packets
Protocol Protocol
Routing Routing
Flits
Link Link
Physical Phits Physical
For the Glory of the Nation Figure 3.18 QPI Layers

reserved.
COMPONENT A
Intel QuickPath Interconnect Port
Fwd Clk
Rcv Clk
Transmission Lanes Reception Lanes
Fwd Clk
Rcv Clk
Reception Lanes Transmission Lanes
Intel QuickPath Interconnect Port

COMPONENT B
Figure 3.19 Physical Interface of the Intel QPI Interconnect


reserved.
#2n+1 #n+1 #1 QPI
lane 0
bit stream of flits #2n+2 #n+2 #2 QPI

lane 1
#2n+1 #2n #n+2 #n+1 #n #2 #1
#3n #2n #n QPI

lane 19
Figure 3.20 QPI Multilane Distribution


reserved.
+
QPI Link Layer
• Performs two key • Flow control function

functions: flow control • Needed to ensure that a
and error control sending QPI entity does not
• Operate on the level overwhelm a receiving QPI
of the flit (flow control entity by sending data faster
unit) than the receiver can process
the data and clear buffers for
• Each flit consists of a more incoming data
72-bit message
payload and an 8-bit
error control code • Error control function
called a cyclic • Detects and recovers from
redundancy check
(CRC) bit errors, and so isolates
higher layers from
experiencing bit errors

reserved.
+
QPI Routing and Protocol Layers
Routing Layer Protocol Layer
• Used to determine the • Packet is defined as the unit of transfer

course that a packet will • One key function performed at this level
traverse across the available is a cache coherency protocol which
system interconnects deals with making sure that main
• Defined by firmware and memory values held in multiple caches
describe the possible paths are consistent
that a packet can follow • A typical data packet payload is a block
of data being sent to or from a cache

reserved.
+ Peripheral Component Interconnect (PCI)
• A popular high bandwidth, processor independent bus

that can function as a mezzanine or peripheral bus
• Delivers better system performance for high speed I/O
subsystems
• PCI Special Interest Group (SIG)
• Created to develop further and maintain the
compatibility of the PCI specifications
• PCI Express (PCIe)
• Point-to-point interconnect scheme intended to replace bus-based
schemes such as PCI
• Key requirement is high capacity to support the needs of higher data
rate I/O devices, such as Gigabit Ethernet
• Another requirement deals with the need to support time
dependent data streams
reserved.
Core Core
Gigabit PCIe
Memory
Ethernet
Chipset
PCIe–PCI PCIe
Memory
Bridge
PCIe
PCIe PCIe
Switch
PCIe PCIe
Legacy PCIe PCIe PCIe

endpoint endpoint endpoint endpoint

Figure 3.21 Typical Configuration Using PCIe
reserved.
Transaction layer
packets (TLP)
Transaction Transaction
Data link layer

packets (DLLP)
Data Link Data Link
Physical Physical
Figure 3.22 PCIe Protocol Layers


reserved.
128b/ PCIe
B4 B0
130b lane 0
byte stream
128b/ PCIe
B5 B1
130b lane 1
B7 B6 B5 B4 B3 B2 B1 B0
128b/ PCIe
B6 B2
130b lane 2
128b/ PCIe
B7 B3
130b lane 3
Figure 3.23 PCIe Multilane Distribution


reserved.
D+ D–
8b
Differential
Scrambler Receiver
8b 1b Clock recovery
circuit
Data recovery
128b/130b Encoding circuit
130b 1b
Parallel to serial Serial to parallel
1b 130b
Transmitter Differential 128b/130b Decoding

Driver
128b
D+ D–
Descrambler
(a) Transmitter
8b
(b) Receiver

Figure 3.24 PCIe Transmit and Receive Block Diagrams

+
PCIe • Receives read and write requests from the software
above the TL and creates request packets for
transmission to a destination via the link layer
Transaction Layer • Most transactions use a split transaction technique
(TL) • A request packet is sent out by a source PCIe
device which then waits for a response called a
completion packet
n TL messages and some write transactions are

posted transactions (meaning that no response is
expected)
n TL packet format supports 32-bit memory

addressing and extended 64-bit memory
addressing

+
The TL supports four address spaces:
• Memory • I/O
• The memory space includes system • This address space is used for
main memory and PCIe I/O devices legacy PCI devices, with reserved
• Certain ranges of memory address ranges used to address
addresses map into I/O devices legacy I/O devices
• Configuration • Message
• This address space enables the TL • This address space is for control
to read/write configuration signals related to interrupts, error
registers associated with I/O handling, and power management
devices

reserved.
Table 3.2
PCIe TLP Transaction Types
Address Space TLP Type Purpose
Memory Read Request
Transfer data to or from a location in the
Memory Memory Read Lock Request
system memory map.
Memory Write Request
I/O Read Request Transfer data to or from a location in the
I/O
I/O Write Request system memory map for legacy devices.
Config Type 0 Read Request
Config Type 0 Write Request Transfer data to or from a location in the
Configuration
Config Type 1 Read Request configuration space of a PCIe device.
Config Type 1 Write Request
Message Request Provides in-band messaging and event
Message
Message Request with Data reporting.
Completion
Memory, I/O, Completion with Data
Returned for certain requests.
Configuration Completion Locked
Completion Locked with Data
Number
of octets
1 STP framing 1 Start
Appended by PL
2 Sequence number
DLLP
Created
by DLL
4
2 CRC
12 or 16 Header 1 End
Created by Transaction Layer
Appended by Data Link Layer
Appended by Physical Layer

0 to 4096 Data
0 or 4 ECRC
4 LCRC
1 STP framing
(a) Transaction Layer Packet (b) Data Link Layer Packet

For the Glory of the Nation Figure 3.25 PCIe Protocol Data Unit Format
reserved.
+
Summary A Top-Level View of
Computer Function
and Interconnection
Class 2
• Point-to-point interconnect
• Computer components • QPI physical layer
• Computer function • QPI link layer
• Instruction fetch and • QPI routing layer
execute • QPI protocol layer
• Interrupts
• I/O function • PCI express
• Interconnection structures
• PCI physical and logical
architecture
• Bus interconnection • PCIe physical layer
• PCIe transaction layer
• PCIe data link layer
reserved.

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Class 2 - 3

Computer Organization and

Dr. Eng. Tati Erlina, MIT/Nefy Putri Novani, MT

For the Glory of the Nation

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights

(a) Programming in hardware

Approaches codes interpreter

(b) Programming in software

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights

I/O address I/O buffer

For the Glory of the Nation

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights

I/O Module n–2

For the Glory of the Nation

Fetch Next Execute

Figure 3.3 Basic Instruction Cycle

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights

• The processor increments the PC after each instruction fetch so

• The fetched instruction is loaded into the

• An instruction may • The processor may

For the Glory of the Nation

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights

(a) Instruction format

(b) Integer format

Program Counter (PC) = Address of instruction

(c) Internal CPU registers

0001 = Load AC from Memory

(d) Partial list of opcodes

Figure 3.5 Example of Program Execution

Instruction Instruction Operand Operand

Return for string

For the Glory of the Nation

For the Glory of the Nation

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights

I/O I/O I/O

WRITE WRITE 5 WRITE 5

WRITE WRITE WRITE

= interrupt occurs during course of execution of user program

For the Glory of the Nation

For the Glory of the Nation

Figure 3.9 Instruction Cycle with Interrupts

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights

(b) With interrupts

(a) Without interrupts

I/O operation; 2 I/O operation

3 (b) With interrupts

(a) Without interrupts

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Instruction Instruction Operand Operand

Figure 3.12 Instruction Cycle State Diagram, With Interrupts

For the Glory of the Nation

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights

(a) Sequential interrupt processing

(b) Nested interrupt processing

For the Glory of the Nation

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 3.14 Example Time Sequence of Multiple Interrupts

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.