Chapter 5

Passive and Active Current Mirrors

1

5.1 Basic Current Mirrors

Design issues
Voltage headroom. ( 0 for ideal current source )
Output impedance. ( for ideal current source )
Supply, process, and temperature dependence.
Matching 2
1 𝑊 𝑅2
𝐼𝑜𝑢𝑡 ≈ 𝜇𝑛 𝐶𝑜𝑥 𝑉 − 𝑉𝑇𝐻
2 𝐿 𝑅1 + 𝑅2 𝐷𝐷
Depending on supply, process, and temperature.
The threshold voltage may vary by 100 mV from
wafer to wafer.
Both μn and VTH exhibit temperature dependence.
The issue becomes more severe as the device is
biased with a smaller overdrive voltage.
VTH variations larger % variations on Iout.
The gate-source voltage of a MOSFET is precisely defined, but its drain current is not.
→ Copying currents from a reference.
Chung-Yu (Peter) Wu 2018
 Chapter 5
Passive and Active Current Mirrors
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5.1 Basic Current Mirrors

For Iout = IREF

𝑉𝐺𝑆 = 𝑓 −1 𝐼𝑅𝐸𝐹
𝑓𝑓 −1 𝐼𝑅𝐸𝐹 = 𝐼𝑅𝐸𝐹

1 𝑊 2
1 𝑊 2
𝐼𝑜𝑢𝑡 𝑊 𝐿 2
𝐼𝑅𝐸𝐹 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝐼𝑜𝑢𝑡 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 =
2 𝐿 1
2 𝐿 2
𝐼𝑅𝐸𝐹 𝑊 𝐿 1
It allows precise copying of the current with
no dependence on process and temperature.
Current mirrors employ the same length for
all of the transistors so as to minimize errors
due to the side diffusion of the source and
drain areas.
𝐿𝑒𝑓𝑓 = 𝐿𝑑𝑟𝑎𝑤𝑛 − 2𝐿𝐷

Current ratio by only scaling the width of

transistors.
Chung-Yu (Peter) Wu 2018
 Chapter 5
Passive and Active Current Mirrors
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5.2 Cascode Current Mirror

Channel length modulation effect results in significant error in copying currents.
1 𝑊 2
1 𝑊 2
𝐼𝐷1 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 1 + 𝜆𝑉𝐷𝑆1 𝐼𝐷2 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 1 + 𝜆𝑉𝐷𝑆2
2 𝐿 1
2 𝐿 2

𝐼𝐷2 𝑊 𝐿 21+ 𝜆𝑉𝐷𝑆2

As = , for ID1 = ID2 , VDS1 must be equal to VDS2 .
𝐼𝐷1 𝑊 𝐿 1 1 + 𝜆𝑉𝐷𝑆1

Vb is chosen such that VY = VX .

𝑉𝑏 − 𝑉𝐺𝑆3 = 𝑉𝑌
𝑉𝑏 = 𝑉𝐺𝑆3 + 𝑉𝑌
𝑉𝑁 = 𝑉𝐺𝑆0 + 𝑉𝑋 = 𝑉𝑏
if 𝑊 𝐿 3 𝑊 𝐿 2
=
𝑊 𝐿 0 𝑊 𝐿 1

then VGS0 = VGS3 and VX = VY

Such accuracy is obtained at the cost of the voltage headroom consumed by M3.

Chung-Yu (Peter) Wu 2018

 Chapter 5
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5.2 Cascode Current Source

𝑉𝐺𝑆0 = 𝑉𝐺𝑆3 ⇒ 𝑉𝐺𝐷2 = 0 ⇒ 𝑉𝐷𝑆2 = 𝑉𝐺𝑆2 = 𝑉𝐺𝑆
The minimum allowable voltage at node P is equal to
𝑉𝑃 = 𝑉𝐺𝑆2 + 𝑉𝐷𝑆3 = 𝑉𝐺𝑆 + 𝑉𝐺𝑆0 − 𝑉𝑇𝐻
= 𝑉𝐺𝑆0 − 𝑉𝑇𝐻 + 𝑉𝐺𝑆 − 𝑉𝑇𝐻 + 𝑉𝑇𝐻
(Assume the same VTH in M0-M3) The
)(b)
The voltage of VN
𝑉𝑁 = 𝑉𝐺𝑆2 + 𝑉𝐺𝑆3 = 𝑉𝐺𝑆0 + 𝑉𝐺𝑆
For M2 to be in saturation region, Vb can be chosen
as low as
𝑉𝑏 = 𝑉𝐺𝑆3 + 𝑉𝐷𝑆2 = 𝑉𝐺𝑆3 + 𝑉𝐺𝑆 − 𝑉𝑇𝐻
𝑉𝑝 = 𝑉𝑏 − 𝑉𝑇𝐻 = 𝑉𝐺𝑆3 + 𝑉𝐺𝑆 − 2𝑉𝑇𝐻
Vp in Fig.5.11(a) is lower than that in Fig.5.11(b) by VTH.
But the output current does not accurately track IREF
(a)
Chung-Yu (Peter) Wu 2018
 Chapter 5
Passive and Active Current Mirrors
5

5.2 Cascode Current Mirror – Low-Voltage Cascode Current Mirror

To eliminate the accuracy-headroom trade-off.
For M2 to be saturated
VOV2 = 𝑉𝑏 − 𝑉𝐴 − 𝑉𝑇𝐻2 ≤ 𝑉𝑋 = 𝑉𝐺𝑆1 − 𝑉𝐴
⇒ 𝑉𝑏 − 𝑉𝑇𝐻2 ≤ 𝑉𝐺𝑆1
For M1 to be saturated
𝑉𝐺𝑆1 − 𝑉𝑇𝐻1 ≤ 𝑉𝐴 (= 𝑉𝑏 − 𝑉𝐺𝑆2 )
Thus
𝑉𝐺𝑆2 + 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1 ≤ 𝑉𝑏 ≤ 𝑉𝐺𝑆1 + 𝑉𝑇𝐻2
A solution exist if
𝑉𝐺𝑆2 + 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1 ≤ 𝑉𝐺𝑆1 + 𝑉𝑇𝐻2 ⇒ 𝑉𝐺𝑆2 − 𝑉𝑇𝐻2 ≤ 𝑉𝑇𝐻1
Size M2 such that the overdrive voltage is smaller than 𝑉𝑇𝐻1
Through proper ratio :
𝑉𝐺𝑆2 = 𝑉𝐺𝑆4 , 𝑉𝐺𝑆1 = 𝑉𝐺𝑆3
If 𝑉𝑏 = 𝑉𝐺𝑆2 + 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1 = 𝑉𝐺𝑆4 + 𝑉𝐺𝑆3 − 𝑉𝑇𝐻3 ,
⇒ 𝑉𝐴 = 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1
⇒ minumum 𝑉𝑃 = 𝑉𝑏 − 𝑉𝑇𝐻4 = 𝑉𝐺𝑆4 − 𝑉𝑇𝐻4 + (𝑉𝐺𝑆3 − 𝑉𝑇𝐻3 )
Headroom and 𝑉𝐴 = 𝑉𝐵 = 𝑉𝑏 − 𝑉𝐺𝑆2 = 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1 = 𝑉𝐺𝑆3 − 𝑉𝑇𝐻3 ⇒ 𝐼𝑜𝑢𝑡 = 𝐼𝑅𝐸𝐹
Chung-Yu (Peter) Wu 2018
 Chapter 5
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5.2 Cascode Current Mirror – Low-Voltage Cascode Current Mirror

Generation of biased voltage Vb
Through proper sizing on M5 and M2,
𝑉𝐺𝑆5 ≈ 𝑉𝐺𝑆2
𝑉𝐷𝑆6 = 𝑉𝐺𝑆6 − 𝐼1 𝑅𝑏 = 𝑉𝐷𝑆1 = 𝑉𝐴 = 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1
Through proper sizing on M6 and M1,
𝑉𝐺𝑆6 ≈ 𝑉𝐺𝑆1
⇒ 𝐼1 𝑅𝑏 = 𝑉𝑇𝐻6 = 𝑉𝑇𝐻1 I1 and Rb can be designed.
Some inaccuracy arises because M5 does not suffer
from body effect whereas M2 does. Similarly, M1 versus M6 .
I1Rb is not well controlled because of the variations of Rb.
The diode connected transistor M7 has a large W/L such that
𝑉𝐺𝑆7 ≈ 𝑉𝑇𝐻7
𝑉𝐷𝑆6 ≈ 𝑉𝐺𝑆6 − 𝑉𝑇𝐻7
𝑉𝑏 = 𝑉𝐺𝑆5 + 𝑉𝐺𝑆6 − 𝑉𝑇𝐻7 = 𝑉𝐺𝑆2 + 𝑉𝐺𝑆1 − 𝑉𝑇𝐻1
This circuit suffers from similar errors due to body effect
𝑉𝐺𝑆7 ≈ 𝑉𝑇𝐻7 is well controlled.
Chung-Yu (Peter) Wu 2018
 Chapter 5
Passive and Active Current Mirrors
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5.2 Cascode Current Mirror –

Wide-Swing Cascode using A Source Follower Level Shifter
Shift the gate voltage of M3 down with respect to VN by interposing a source follower.
Proper sizing MS
𝑉𝐺𝑆𝑠 = 𝑉𝑇𝐻3 = 𝑉𝑇𝐻𝑠
𝑉𝑁′ ≈ 𝑉𝑁 − 𝑉𝑇𝐻3
𝑉𝐵 = 𝑉𝐺𝑆1 + 𝑉𝐺𝑆0 − 𝑉𝑇𝐻3 − 𝑉𝐺𝑆3
= 𝑉𝐺𝑆1 − 𝑉𝑇𝐻3 (∵ 𝑉𝐺𝑆0 ≈ 𝑉𝐺𝑆3 𝑏𝑦 𝑠𝑖𝑧𝑖𝑛𝑔)
Ms is biased at a very low current density,
2𝐼
𝑉𝐺𝑆𝑠 − 𝑉𝑇𝐻𝑠 = ≈0
𝜇𝑛 𝐶𝑜𝑥 𝑊 𝐿
𝑉𝐺𝑆𝑠 ≈ 𝑉𝑇𝐻𝑠 = 𝑉𝑇𝐻3
M2 is at the edge of the saturation region.
Substantial current mismatch is introduced for
𝑉𝐷𝑆2 ≠ 𝑉𝐷𝑆1
If the body effect of M0, MS, and M3 is considered, it is difficult to guarantee that M2 operates in
saturation.
Chung-Yu (Peter) Wu 2018
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5.3 Active Current Mirror Loads

Current mirror can also process signals as active loads

𝑉𝑖𝑛
𝑀1 ≡ 𝑀2 , the signal voltage across gate and source of M1 or M2 is with grounded output.
2
𝐼𝑜𝑢𝑡 𝑔𝑚1 𝑉𝑖𝑛 2 𝑔𝑚1,2
𝑔𝑚1 = 𝑔𝑚2 𝐴𝑣 = 𝐺𝑚 𝑅𝑜𝑢𝑡 𝐺𝑚 = = =
𝑉𝑖𝑛 𝑉𝑖𝑛 2
The output impedance looking into the drain of M2 is
1 + 𝑔𝑚1,2 𝑟𝑜2 1 𝑔𝑚1,2 + 𝑟𝑜2 = 2𝑟𝑜2 + 1 𝑔𝑚1,2 ≈ 2𝑟𝑜2 ( =0, no body effect)
𝑔𝑚1,2
Thus, 𝑅𝑜𝑢𝑡 ≈ 2𝑟𝑜2 𝑟𝑜4 ⇒ 𝐴𝑣 ≈ 2 2𝑟𝑜2 𝑟𝑜4 If 𝑟𝑜4 → ∞ ⇒ 𝐴𝑣 ≈ 𝑔𝑚1,2 𝑟𝑜2
Chung-Yu (Peter) Wu 2018
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5.3 Active Current Mirror Loads

An Alternative Solution ( = 0 )
𝑉𝑜𝑢𝑡 𝑉𝑜𝑢𝑡 𝑉𝑃 𝑉𝑃 𝑅𝑒𝑞
= =
𝑉𝑖𝑛 𝑉𝑃 𝑉𝑖𝑛 𝑉𝑖𝑛 𝑅 + 1
𝑒𝑞 𝑔𝑚1

1 𝑟𝑜4 1 𝑟𝑜4
𝑅𝑒𝑞 ≈ + = 1+
𝑔𝑚2 𝑔𝑚2 𝑟𝑜2 𝑔𝑚2 𝑟𝑜2

1 𝑟𝑜4 𝑟𝑜4
𝑉𝑃 1 + 1 +
𝑔𝑚2 𝑟𝑜2 𝑟𝑜2
= = 𝑟
𝑉𝑖𝑛 1 1 𝑟 2 + 𝑜4
+ 1 + 𝑜4 𝑟𝑜2
𝑔𝑚1 𝑔𝑚2 𝑟𝑜2

𝑉𝑃 1
𝐼𝑓 𝑟𝑜4 ≪ 𝑟𝑜2 , ≈
𝑉𝑖𝑛 2
𝑟𝑜4
𝑉𝑜𝑢𝑡 1+
𝑟𝑜2 𝑔𝑚2 𝑟𝑜2 𝑔𝑚2 𝑟𝑜2 𝑟𝑜4 𝑔𝑚2
= 𝑟 ∙ 𝑟 = = 2𝑟𝑜2 𝑟𝑜4
𝑉𝑖𝑛 2 + 𝑜4 1 + 𝑜2 2𝑟𝑜2 + 𝑟𝑜4 2
𝑟𝑜2 𝑟𝑜4
Chung-Yu (Peter) Wu 2018
 Chapter 5
Passive and Active Current Mirrors
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5.3 Active Current Mirror Loads – Differential to Single-Ended Amplifier

Current combination utilizing current mirror.

Chung-Yu (Peter) Wu 2018

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5.3 Active Current Mirror Loads

5.3.1 Large-Signal Analysis

If Vin1 is much more negative than Vin2 , M1 is off and so are M3 and M4. Both M2 and M5
operate in deep triode region. Vout=0
For a small difference between Vin1 and Vin2 , M1 – M4 are saturated, providing a high gain.
The minimum input common-mode voltage level of Vin,CM = VGS1,2+VDS5,min.
VDS5,min : minimum VDS5 such that M5 SAT. The maximum value is VDD - |VGS3| - 𝑉𝑇𝐻2 .
With perfect symmetry, Vout = VF = VDD - |VGS3| . Gate and Drain of M4 are virtually short.
But Vout can vary a lot if device mismatches occur.
Chung-Yu (Peter) Wu 2018
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5.3 Active Current Mirror Loads

5.3.2 Small-Signal Analysis – First approach

𝑅𝑜2 = 𝑟𝑜2 + 1 + 𝑔𝑚2 𝑟𝑜2 1 𝑔𝑚1 ≈ 2𝑟𝑜2

For 𝑔𝑚1 = 𝑔𝑚2 = 𝑔𝑚 𝑔𝑚2 𝑟𝑜2 ≫ 1

⇒ 𝑅𝑜2 ≅ 2𝑟𝑜2
𝑣𝑥 𝑣𝑥 𝑣𝑥 𝑣𝑥
𝑖𝑥 = 𝑖 + 𝑖 + = 2𝑖 + =2 +
𝑟𝑜4 𝑟𝑜4 𝑅𝑜2 𝑟𝑜4
𝑣𝑥 𝑣𝑥
𝑖𝑥 = 2 +
𝑅𝑜2 𝑟𝑜4

𝑣𝑥
𝑅𝑜 ≡ = 𝑟𝑜2 𝑟𝑜4
𝑖𝑥

Chung-Yu (Peter) Wu 2018

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5.3 Active Current Mirror Loads

5.3.2 Small-Signal Analysis – First approach

M2 ground drain
M1 small drain impedance
P is virtually grounded (a) (b)

𝑉𝑖𝑛 −𝑉𝑖𝑛
𝐼𝑜𝑢𝑡 = 𝐼𝑑4 − 𝐼𝑑2 = 𝐼𝑑1 − 𝐼𝑑2 = 𝑔𝑚1 − 𝑔𝑚2
2 2
= 𝑔𝑚1,2 𝑉𝑖𝑛 𝑔𝑚1 = 𝑔𝑚2 = 𝑔𝑚1,2
𝐺𝑚 = 𝑔𝑚1,2 Vout from at M1 positive
in
𝐴𝑣 = 𝐺𝑚 𝑅𝑜 = 𝑔𝑚1,2 (𝑟𝑜2 𝑟𝑜4 ) Vout from in at M2 negative
Chung-Yu (Peter) Wu 2018
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5.3 Active Current Mirror Loads

5.3.2 Small-Signal Analysis – Second approach
𝑉𝑒𝑞 = 𝑔𝑚1,2 𝑟𝑜1,2 𝑉𝑖𝑛 𝑅𝑒𝑞 = 2𝑟𝑜1,2

𝑉𝑜𝑢𝑡 −𝑔𝑚1,2 𝑟𝑜1,2 𝑉𝑖𝑛

𝐼𝑋1 = 1
2𝑟𝑜1,2 +𝑔 𝑟𝑜3
𝑚3
The current flowing through 1 𝑔𝑚3 is mirrored
to the drain of M4.
𝑟𝑜3 𝑉𝑜𝑢𝑡
𝐼𝑋1 + 𝐼𝑋1 1 =−
𝑟𝑜3 + 𝑟𝑜4
𝑔𝑚3

1 1
2𝑟𝑜1,2 ≫ 𝑟𝑜3,4 and 𝑟𝑜3 ≫
𝑔𝑚3,4 𝑔𝑚3

𝑉𝑜𝑢𝑡
⇒ = 𝑔𝑚1,2 (𝑟𝑜1,2 𝑟𝑜3,4 )
𝑉𝑖𝑛
(a) (b)
Chung-Yu (Peter) Wu 2018
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5.3 Active Current Mirror Loads

5.3.3 Common-Mode Properties
vicm
i1 i2
2 RSS
Let ro1 ro 2 ro gm1 gm 2 gm

Ro1 Ro 2 ro 2 RSS 2 gm rO RSS

1
vg 3 i1 || rO 3
gm3
1
i4 gm 4vg 3 i1 g m 4 || rO 3
gm3

1 vo 1 ro 4 1
vO i4 i2 rO 4 i1 g m 4 || rO 3 i2 rO 4 Acm
gm3 vicm 2 RSS 1 g m 3 ro 3 2 g m 3 RSS
| Ad | CMRR g m ro g m 3 RSS
CMRR gm rO 2 || rO 4 2 gm3RSS
| Acm |
The active-loaded MOS differential amplifier has a low common mode gain and a high CMRR.
Chung-Yu (Peter) Wu 2018
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5.3 Active Current Mirror Loads

5.3.3 Common-Mode Properties -Under mismatched input transistors
RSS
VP Vin ,CM
𝑔𝑚1 is not equal to 𝑔𝑚2 : 1
RSS
g m1 gm2
Vin ,CM g m1 Vin ,CM gm2
I D1 g m1 Vin ,CM VP I D2 gm2 Vin ,CM VP
1 g m1 g m 2 1 g m1 g m 2
RSS RSS
g m1 g m 2 g m1 g m 2

1
I D4 I D1 || rO 3 g m 4
g m3

g m1 Vin ,CM rO 3 g m 2 Vin ,CM

V ID4 I D 2 rO 4 rO 4
out
1 g m1 g m 2 RSS r 1 1 g m1 g m 2 RSS
O3
g m3

Vin ,CM g m1 g m 2 rO 3 g m 2 / g m3
V out rO 4 Vout g m1 g m 2 rO3 g m 2 / g m3
1 g m1 g m 2 RSS 1
rO 3 Vin ,CM 1 g m1 g m 2 RSS
g m3

Chung-Yu (Peter) Wu 2018