Analog Mixed-Signal Simulation in

FE-I4 with Cadence AMS Designer

Vladimir Zivkovic
Nikhef institute
Amsterdam, The Netherlands

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 Outline
• Introduction
• Analog Mixed-Signal (AMS) Simulation
Framework in FEI4-A – proof of concept
• Further steps

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 Why AMS Simulation?
• Bridge the gap between system-level and
implementation
• Improve system and block performance analyses
– Addressing difficult to predict interactions e.g.
substrate, supplies,…
• Combine best known analog simulation
techniques with digital verification methodology
(within an EDA tool)
• Assists during analog verification steps
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 What is the AMS Simulation?
• Simulates a network that contains nodes and
branches of analog natures as well as ports of
models of discrete nature,
• Synchronizes the analog solver with Newton
methods (Spectre, UltraSim) and the digital
kernel with event driven simulator (ncsim),
• Supports modules described at various levels
of abstraction (netlists, behavioral models,
black-boxes).

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 AMS Designer Features
• A flow composed of several executables integrated in
Virtuoso custom IC design flow enabling AMS
simulation through the support of mixed-signal
behavioral languages (verilog.ams)
• Deals with schematics and text netlists
• Encompasses environment for simulation and
debugging
• Supports both analog and digital centric methodology
• Has three usage models
– Analog Design Environment (ADE)
– Hierarchy Editor (HED)
– Command line
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 Hierarchical Editor

• AMS simulations are set up

through the configuration
views of the cells
• Configuration view enables
selection of the module
instantiation abstraction.
All the way down to the
leaf cell instantiation

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 Digital vs AMS Designer Flow
Design Database
PDK
amsDirect
Config Schematic
Spectre CDF (netlister)
Models
Cdsglobals Behavioral
(vams)
Netlist
.v, .vams
Hdl.var .pak (inca_file)
ncvlog
Compiled models

Connect lib ncelab Simulation Snapshot

Connect
Modules
Spectre .scs
ncsim
Ultrasim (control
sim file)
views

simvision tcl

Wavescan AMS HED Plugin

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 AMS Simulation in FEI4
• An Example: FEI4-A Power up sequence
– All pads described with their schematic (transistor
level)
– FEI4_DIG schematic, with digital modules being
powered up described with verilog (after layout)
– FEI4_ANA black box
– Power-up sequence (testbench) in Verilog.AMS

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 Power-up Sequence
1) Initialization
2) VDDT3 <- 1.2
Wait 5us
3) RD1_bar
VDDD1 <- 1.2V
Wait 1us
RD1_bar
Wait 5us
4) RDA_bar
VDDA1 <- 1.65V
Wait 1us
RDA_bar
.
.
.

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 Top level configuration

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 Configuration with HED

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 AMS HED Plugin

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 Simulation Charts (I)

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 Simulation Charts (II)

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 Simulation Charts (III)

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 Further development
• Verify the remaining functionality/performance
that is not being checked – too late in FEI4-A ?
Postponed for the next version ? In any case, we
can agree on verification plan driven from the
top-level (self-checking test-benches) for at least
debug purposes.
• Couple the approach with OVM ?
• Expand the approach to include the elements of
the probe card and verify the test setup for AMS
circuits as well as the debug purpose?
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 Self-checking test-bench

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 Test Setup Validation
Power Power Power
trig trig

Pulse
trig
PCB vdda vdd1 vdd2
I/O trig
relay1 R R R
clkin R1
dig_out Logic
trig C1 FEI4-A Analyzer
Vsin C2 (various
vin_2 R
vout1
C3 abstraction
trig levels) vout2
Digitizer
C4
V sin R
vin_1 trig
R2 R3
trig
R5
GNDD GNDA
I/O
relay2
trig trig

Bench-test I/O I/O

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