2021F-BCE-242 DAWOOD M.

SHOAIB

LAB # 03:
To design, implement & simulate Flouting point
multiplication and division through Data Flow Modeling
Floating-Point Multiplication:
Verilog Module code:

RTL Schematic:

SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY

2021F-BCE-242 DAWOOD M. SHOAIB

Verilog Test Fixture:

SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY

2021F-BCE-242 DAWOOD M. SHOAIB

Floating-Point DIVISION:
Verilog Module code:

RTL Schematic:

SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY

2021F-BCE-242 DAWOOD M. SHOAIB

Verilog Test Fixture:

SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY

2021F-BCE-242 DAWOOD M. SHOAIB

CONCLUSION:
In this lab, I learn how to design, implement & simulate Flouting point multiplication
and division through Data Flow Modeling.

SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY