3.2. Timer/Counters Microcontroller 8051 has two 16-bit timer / counter registers. They are timer 0 and timer 1. Both can be configured to operate either as timers or event counters. In the timer function, the register is incremented every machine cycle. That means, in timer operation it counts the machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency (fosc/12). In the counter function, the register is incremented in response to “1 to 0” transition at its corresponding external input pin TO or T1. In this function the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one machine cycle and a’ low in the next machine cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes atleast 2 machine cycles (24 oscillator periods) to recognize a “1 to 0” transition. The maximum count rate is 1/24 of the oscillator frequency (fosc/24). In addition to the timer or counter selection, Timer O and Timer 1 have four operating modes. The timer/counters are divided into two 8-bit registers called the timer low (THO, TLO) and timer high (TH1, TL1) bytes. All timer/counter actions are controlled by bit status in the timer mode control register (TMOD), the timer /counter control register (TCON) and certain program instructions.3.2.1, TMOD register TMOD Is an B bit SFA register, It is only a byte addressable register. The timer or counter function i, selected by the control bits C/T, The operating modes are selected by the bit pairs M1 and MO, GATE input is Used for selecting the timer/counter control in either hardware vy software. TMOD register format is shown below. (MSB) D7 D6 05 D4 D3 b2 Pa one 5 TIMER 1 TIMER O Di DO (48 GATE: Timer/counter Gating control. When GATE=1, Tirer/ Counter “X” is enabled only while INTX pin is high (Hardware control) and TAX (in TCON register) is set. When GATE =, Timer/Counter “X” will run only while TRX = 1 (Software control). CF = It is “1” for counter operations, and “O” for timer operations. MI: Mode selector bit MO =: Mode selector bit. The description of mode selection is shown below :- 13-bit Timer/counter (TLx serves as 5-bit prescalar)prme fe 8-bit auto reload Timor/Counter (Timer 0) TLO is an 8-bit timer/ counter, controlled by the standard timer 0 control bits. THO is an 8-bit timer/counter, only controlled by timer 1 control bits. Timer 1 is not operated in mode 3. 3.2.2, TCON register TCON register is an 8 bit, byte / bit addressable register. This register contains Timer overflow flags, Run control bits, External interrupts type control bits and External interrupts flag bits: The format of TCON register is shown below. (MSB) D7 “D6 D5 D4 D3 D2 D1 DO(LSB) ITO [Symbol Functions TFX Timer X over flow flag bit. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to its interrupt routine. TRX “Timer X run control bit. Set/Cleared by software, to turn ON/OFF the timer/counter. IEX External interrupt X edge flag. Set/Cleared by hardware, when external interrupt edge is detected. Cleared, when interrupt is processed. ITX Interrupt X type control bit. Set/Cleared by software, to specify falling edge/low level triggered external interrupts.3.2.3, Operating modes of timer/counter The timercounter registers of miorocontrollor Ay, operates any one of its four operating modes i) MODE 0 (13 bit Timer/ Counter) Sintering GATE p INTi PIN, Fig. 3.2 Timer/Counter 1 mode 0 : 13 bit Simer/Counter ‘cin this mode; the timer register is configured as bit register. -The functional diagram of Mode O operation fy timer/counter 1 is. shown jn the fig.3.2. The C/T bit in THOS register can be used to set the register either timer or coun' As the count rolls aver from all 1s to all Os, it sets timer interrupt flag TF1 in TCON register. The counted inp: is enabled to Timer 1. when TR1 = 1 and either GATE =0% INT1 =1. When GATE = 1, the Timer is controlled by exterra input INT1, to_facilitate pulse width measurernent. V\ GATE=0, the timer/counter activates only in software. TR14 a control bit in TCON and GATE is in TMOD. The 13 bit register consists of all 8 bits of TH1 2% the lower 5 bits of TL1. Mode 0 operation is same for Time’ 0 and Timer 1.ii) MODE 1 (16 bit Timer/Counter) roa yr res Loo esn| arin Interrupe Control GATE p NTI pty Fig. 3.3 Timer/Counter 1 mode 1 : 16 bit Timer/Couater Mode 1 is similar to mode 0 except that the timer register is being run with all 16 bits. The functional block diagram of mode 1 operation for timer 1 is shown in the fig.3.3. iii) MODE 2 (8 bit auto reload timer/counter) osc |= 222 cro oo Ll | | TF " io aby Interrupe TUPI } ca ‘ontrol TRL ee Z Noi RELOAD GATE TR Big INTI PIN Fig. 3.4 Timer/Counter | mode 2 : 8 Bit auto-reload ‘Timer/Counter Mode 2 configures the timer register as an 8 bit timer/ counter (TL1) with automatic reload. The functional block diagram of mode 2 operation for Timer 1 is shown in the fig.3.4,3.12 In this mode, overflow from TL1, not only sets TF1 but also reload TL1 with the contents of TH1, which is preset by software, The reload leaves TH1 unchanged. iv) MODE 3 (Two 8 bit timer/counters) a om Ti Fogo} {ais L{ 10 TOPL. | CT=1 [Control ‘TRO —_— ——_ S Whipw f Interrupt GATE Tuo 1H. fo (8BiH) Interrupt Fig. 3.5 Timer/Counter 0 mode 3 : Two 8 bit Timer/Counter Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1,= 0. Timer 0 in Mode 3 establishes TLO and THO as two separate timer/counters. The functional block diagram for Timer/counter 0 in mode 3 is shown in the fig.3.5. _____ TLO uses the Timer 0 control bits : C/T, GATE, TRO, INTO and TFO. THO is locked in to timer and takes over the use of TR1 and TF1 from Timer 1. Thus THO now controls Timer 1 interrupt. No interrupts will be generated by timer 1 while timer 0 is using the TF1 overflow flag.