2023 Silicon Nanoelectronics Workshop, Kyoto, Japan
Green Laser Crystallized Poly-Si Thin-film Transistor and CMOS
Inverter using HfO2-ZrO2 Superlattice Gate Insulator
and Microwave Annealing for BEOL Applications
Chih-Hsiang Chang, Siao-Cheng Yan, Chong-Jhe Sun, Ming-Yueh Huang, Bo-An Chen,
Xin-Chan Zhong, Yi-Wen Lin, and Yung-Chun Wu*
Dept. of Engineering and System Science, National Tsing Hua Univ., Taiwan,
*
E-mail: ycwu@ess.nthu.edu.tw
Abstract — We report the BEOL compatible
poly-Si thin-film transistor (TFT) below 400°C by
green laser crystallization and microwave annealing.
The TEM image reveals the HfO2-ZrO2 superlattice
(SL-HZO) structure of the dielectric layer. The p-
type device shows good electrical properties,
including ION/IOFF ratio > 106, subthreshold swing (SS)
= 75 mV/dec, and low DIBL = 24.18 mV/V.
Furthermore, we demonstrate the characteristics of
the CMOS inverter and the voltage transfer curve
(VTC) indicates the acceptable voltage gain.
I. INTRODUCTION
With the increasing demand for high-performance
electric devices in the market, the use of multi-layer
stacking has become crucial. As a result, the thermal
budget issue is extremely important. The high process
temperature for the second layer in 3-D integration [1]-
[2] can cause degradation or even failure of the
components and metal wires located in the bottom layer.
Therefore, in this study, we propose the BEOL
compatible poly-Si TFT utilized by green laser
crystallization [3]-[5] and microwave annealing [6] to
reduce the thermal budget and achieve compatibility
with the backend processes.
II. DEVICE FABRICATION
The key process flow is shown in Fig. 1(a). The
devices were fabricated on a 50-nm-thick poly-
Si/SiO2/Si substrate. First, 50 nm Į-Si was crystallized
into poly-Si by green laser scanning. Then, the active
region was defined by e-beam lithography (EBL) and
reactive-ion etching (RIE). After RCA cleaning, 12 nm
SL-HZO was deposited by ALD. Next, the TiN gate
electrode was deposited by sputtering. The source/drain
regions were doped by self-aligned phosphorus ion
implantation with 1 u 15 cm–2 dosage and 12 keV for n-
type devices, and doped by boron difluoride ion
implantation with 1 u 15 cm–2 dosage and 22 keV for p-
type devices. The crystallization of dielectric layer and
dopant activation were implemented by microwave
annealing for 100 secs. The whole process temperature
of the poly-Si TFT can be controlled below 400°C.
III. RESULTS AND DISCUSSION
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Fig. 1(b) shows the TEM image of the poly-Si TFT.
Fig. 1(c) shows the enlarged TEM images of SL-HZO
thin film of gate insulator stacks. Fig. 2 shows the EDS
mapping of the element distribution, and the elements in
the dielectric layer are Hf, Zr, and O. Fig. 3 (a) plots the
transfer ID–VG curves (almost hysteresis-free) of the
poly-Si TFT with WCh = 300 nm and LG = 80 nm at VD
= –0.1 V. The average SS of the poly-Si TFT is 75
mV/decade, and ION/IOFF is 1.6 × 106. Fig. 3 (b) shows
the DIBL characteristic of the device between VD = –
0.1V and –0.5V. The device owns a low DIBL value =
24.18 mV/V. Fig. 4 shows the transfer ID–VD curves of
the poly-Si TFT with WCh = 300 nm and LG = 80 nm at
increasing VOV (VG – VTH) values from 0 to –1.3V. The
maximum drain current is around  ȝ$ȝP. Fig. 5
shows the transconductance (Gm) characteristic of poly-
Si TFT extracted from the ID–VG curves at VD = –0.1V
and VD = –1V. We obtain the maximum Gm = 149 nS at
VD = –0.1V and Gm = 602 nS at VD = –1V. Fig. 6 shows
the ID–VG curves for pFET and nFET with the same
dimensions at VD = |0.1 V|. Fig. 7 shows the VTC and
voltage gain for the poly-Si TFT CMOS inverters from
VDD = 0.8V to 1.6V. It can be seen the VTC shift to rightġ
due to the mismatch of VTH values.ġThe largest voltage
gain of 36 V/V is obtained, which is acceptable
compared to conventional SPC poly-Si devices [7].
IV. CONCLUSION
In this work, BEOL compatible poly-Si TFTs with
12 nm-thick SL-HZO were fabricated. The SL-HZO
film was analysed by TEM & EDS. The electrical
properties of the p-type device are remarkable. The
CMOS inverter was also fabricated and characterized.
The low process temperature of below 400°C of the
poly-Si TFTs shows a promising path for low-
temperature 3-D integrated circuit applications.
ACKNOWLEDGMENT
The authors would like to thank the National Science and Technology
Council, Taiwan, for supporting this research under NSTC 109-2221-E-007-
031-MY3.
REFERENCES
[1] Chih-Chao Yang et al. , IEEE, 2015. [2] Chih-Chao Yang et al. , IEDM,
2013. [3] Chih-Chao Yang et al. , IEDM, 2018. [4] Hao-Tung Chung et al. ,
EDL, 2021. [5] Y.-J. Ye, et al., IEDM, 2021. [6] K. Endo et al. , VLSI-TSA,
2016. [7] Po-Jung Sung et al. , IEEE TED, 2020.
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 2023 Silicon Nanoelectronics Workshop, Kyoto, Japan

Fig. 1. (a) Process flows of the poly-Si TFT. (b) TEM image of poly-Si Fig. 2. Two-dimensional energy-dispersive
TFT (WCh = 322 nm). (c) Enlarged TEM image of the gate insulator X-ray spectroscopy mapping of the element
stacks and interfacial layer (SL-HZO = 11.6 nm, SiO2 IL = 1.3 nm). distribution on the dielectric layer.
(a) ((b)
Wch = 300 nm
VT = 0.103V
LG = 80 nm
VOV = 0 ~ -1.3V
step = -0.2 V

Wch = 300 nm
LG = 80 nm
VD = -0.1V Wch = 300 nm
SSmin for = 75 mV/dec LG = 80 nm
SSmin rev = 74 mV/dec DIBL = 24.18 mV/V

Fig. 3. (a) ID–VG curve of poly-Si TFT at VD = –0.1V with hysteresis free. (b) The Fig. 4. The transfer ID–VD curves
DIBL characteristic of the device between VD = –0.1V and VD = –0.5V. of the poly-Si TFT with different
VG – VTH values.

VT = 0.013V VD = -0.1V Wch = 300nm VDD = 0.8 ~1.6V

LG = 60nm Step = 0.4V
Max gain = 36V/V
VT = 0.804V
VD = 0.1V

Wch = 300nm Wch = 300nm

LG = 80 nm LG = 60nm

Fig. 5. The transconductance Fig. 6. ID–VG curve of the CMOS Fig. 7. Voltage transfer curve of
characteristic of the device extracted inverter at VD = |0.1 V|. inverter from VDD =0.8V to 1.6V.
from ID–VG curve.

32
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