1764
6, JUNE 2019
Design of an Always-On Deep Neural
Network-Based 1-μW Voice Activity Detector
Aided With a Customized Software Model
for Analog Feature Extraction
Minhao Yang , Member, IEEE, Chung-Heng Yeh, Yiyin Zhou , Joao P. Cerqueira , Student Member, IEEE,
Aurel A. Lazar , Life Fellow, IEEE, and Mingoo Seok , Senior Member, IEEE
Abstract— This paper presents an ultra-low-power voice
activity detector (VAD). It uses analog signal processing for
acoustic feature extraction (AFE) directly on the microphone
output, approximate event-driven analog-to-digital conversion
(ED-ADC), and digital deep neural network (DNN) for
speech/non-speech classification. New circuits, including the
low-noise amplifier, bandpass filter, and full-wave rectifier con-
tribute to the more than 9× normalized power/channel reduction
in the feature extraction front-end compared to the best prior
art. The digital DNN is a three-hidden-layer binarized multilayer
perceptron (MLP) with a 2-neuron output layer and a 48-neuron
input layer that receives parallel event streams from the ED-
ADCs. To obtain the DNN weights via off-line training, a cus-
tomized front-end model written in python is constructed to
accelerate feature generation in software emulation, and the
model parameters are extracted from Spectre simulations. The
chip, fabricated in 0.18-μm CMOS, has a core area of 1.66 ×
1.52 mm2 and consumes 1 μW. The classification measurements
using the 1-hour 10-dB signal-to-noise ratio audio with restaurant
background noise show a mean speech/non-speech hit rate of
84.4%/85.4% with a 1.88%/4.65% 1-σ variation across ten dies
that are all loaded with the same weights.
Index Terms— Analog signal processing, approximate
quantization, bandpass filter (BPF), binarized neural network
(BNN), classification, computer-aided design, event driven,
feature extraction, full-wave rectifier (FWR), hardware/software
co-design, integrate and fire (IAF), Internet of Things (IoT),
low-noise amplifier (LNA), machine learning, multilayer
perceptron (MLP), ultra-low power (ULP), voice activity
detection (VAD), wearable electronics.
Manuscript received August 22, 2018; revised November 14, 2018; accepted
January 9, 2019. Date of publication April 18, 2019; date of current version
May 24, 2019. This paper was approved by Associate Editor Dennis Sylvester.
This work was supported in part by the Swiss National Science Founda-
tion (SNSF) Early Postdoc Mobility Fellowship, in part by the Columbia
University Research Initiatives in Science and Engineering (RISE), and in part
by Air Force Office of Scientific Research (AFOSR) under Grant FA9550-
16-1-0410. (Corresponding author: Minhao Yang.)
M. Yang is with the Institute of Microengineering, EPFL, 2000 Neuchatel,
Switzerland (e-mail: yangmh.ic@gmail.com).
C.-H. Yeh, Y. Zhou, J. P. Cerqueira, A. A. Lazar, and M. Seok are with
the Department of Electrical Engineering, Columbia University, New York,
NY 10027 USA.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2019.2894360
0018-9200 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO.
I. I NTRODUCTION
A voice activity detector (VAD) distinguishes speech from
the background noise. In the era of Internet of Things (IoT),
VADs have become increasingly important in audio systems:
they are often used for power gating of functional blocks
with more advanced inference capabilities such as speaker
and speech recognition for significant power saving [1], [2].
Therefore, as an always-on sensing unit, a VAD should pro-
vide sufficient classification accuracy with minimum power
consumption. A conventional digital-intensive VAD as shown
in Fig. 1(a) is composed of a low-noise amplifier (LNA),
an analog-to-digital converter (ADC), a digital acoustic feature
extraction (AFE) block, and a digital classifier. The state-of-
the-art VAD including the AFE and classifier consumes 22 μW
in 65-nm LP CMOS [2]. Further power reduction can resort to
analog signal processing (ASP) leveraging its superior power
efficiency under the condition of low-to-medium signal-to-
noise ratio (SNR) [3], which is, indeed, the case with inference
sensing like a VAD.
For AFE, the research in ASP has been ongoing for
over three decades. Early works focused on using switched-
capacitor (SC) circuits to implement spectrum analysis in
parallel architectures [4]–[7]. The neuromorphic approach of
silicon cochlea design started in Carver Mead’s lab in the
late 1980s serves the purpose of signal magnitude estimation
of each frequency channel in continuous time while taking
other bio-mimicking factors into account [8]–[18]. In par-
ticular, some of the designs encode extracted features into
multi-channel parallel asynchronous event streams [12], [16],
simulating the spike trains that are encoded in the cochlea
and propagate on the auditory nerve fibers down to the prime
auditory cortex. A possible analog-intensive VAD architec-
ture taking biomimetic inspiration is depicted in Fig. 1(b).
Here the features are extracted in the analog domain, and
then encoded by event-driven ADCs (ED-ADCs) into parallel
events. The necessity and advantages of using approximate
ED-ADCs in contrast to conventional clocked ADCs with high
signal-to-noise-and-distortion ratio (SNDR), as will become
clear later, are the combined functions of integration and
YANG et al.: DESIGN OF AN ALWAYS-ON DEEP NEURAL NETWORK-BASED 1-μW VAD 1765

Fig. 1. (a) Conventional digital-intensive and (b) analog-intensive signal

processing chain in a VAD.

quantization, the flexibility and convenience of frame shifting,

and the high area and power efficiency. Recent exemplary
works emphasize the ultra-low-power (ULP) design for IoT,
e.g., the 128-channel AFE plus ED-ADCs in [19] consumes
only 55 μW.
The problem of any analog AFE design is the plague
of performance variation caused by device mismatch, which Fig. 2. VAD front-end design flow with a customized software model.
is aggravated in subthreshold region for ULP [20]. One
common coping method is the equalization technique widely
The normalized power per channel of the front-end in
adopted in the digitally assisted ADCs [21], [22]. The idea
this paper is more than 9× smaller than the latest silicon
of using polynomials to compensate the analog non-idealities
cochlea [19]. This power reduction is partly attributed to:
like mismatch and nonlinearity is feasible in ADC design
first, no opamp is used in the AFE and ED-ADC of the new
because the learning of the polynomial coefficients requires
design; second, the input-referred noise (IRN) requirement of
only a small pool of training samples and takes merely tens
the bandpass filter (BPF) in the AFE is relaxed thanks to the
of milliseconds [22].
LNA in front of the BPF bank. A multilayer perceptron (MLP),
In inference applications, a similar concept was conceived
a type of fully connected DNN, is employed as the classifier
by exploiting the powerful learning capacity of a classifier
for VAD. To significantly reduce the computational load
model, e.g., support vector machine (SVM) [23] or deci-
in conventional floating-point DNNs, the recently published
sion tree (DT) [24]. It was demonstrated that even with
binarized neural network (BNN) [26] with binary weights and
extreme non-idealities in feature extraction, after chip-specific
activations is employed for ULP. In several image datasets,
training, the classification accuracy can be restored to be
BNNs have shown less than 1% accuracy degradation [26],
close to software emulation. However, this chip-wise training
and our simulation shows similar results for VAD, while the
scheme is not feasible because the training samples are usu-
energy per MAC operation in DNN is inversely proportional to
ally of large amount for machine learning models, implying
the bit width [27]. Digital implementation was chosen for exact
time-consuming per-chip feature measurements and training
software-to-hardware mapping, allowing us to focus on the
procedures, and consequently results in high production cost,
challenge of the approximate computing nature of the front-
e.g., the computational VAD work in [25] shows that in the
end feature extraction.
noise-independent training, a 35-hour-long noisy speech is
used to train the boosted deep neural network (DNN) model.
II. S YSTEM D ESIGN AND M ODELING
To alleviate the costly post-fabrication effort, we believe it is
advisable to control the classification degradation at the design The system architecture of the VAD is shown in Fig. 3. Input
time. To this end, we build a python model for the front-end audio signals are amplified by LNA, and then analyzed by
including the LNA, the analog AFE, and the ED-ADC, with 16 parallel channels. Each channel contains a BPF, a full-wave
parameters extracted from post-layout Spectre simulations. rectifier (FWR), and an integrate-and-fire (IAF) encoder as the
Acoustic features can be extracted much faster with the model ED-ADC. The central frequencies of the BPFs across channels
running on GPU compared to transistor-level simulations. The are geometrically scaled from about 100 to 5 kHz. The features
model-generated features are then used as the input of a DNN generated after the FWR are encoded into asynchronous events
model for supervised training. If the classification accuracy by the IAF, and then sent to the digital BNN. The event
in model testing using features extracted from the model sequence ideally can be described by the following equation:
with added parameter variation has too much degradation,  t j +1
1
the variation is reduced under the accuracy becomes accept- | f v→i (v oBPF_k (t))|dt = Vrefdn (1)
Cint t j
able. The front-end circuits are then redesigned to conform
to the variation constraints in order to meet the accuracy where t j is the time stamp of the j th event, v oBPF_k is the BPF
requirement. The design flow described above is illustrated in output voltage in channel k, f v→i is the voltage-to-current
Fig. 2. This design flow can help avoid excessively reducing conversion function, and Cint and Vrefdn are the integration
the AFE variation, which is at the cost of silicon area [20]. capacitance and the threshold voltage of IAF, respectively.

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1766
Fig. 3. VAD system architecture using analog acoustic feature extraction and digital classification, with event-driven analog-to-digital conversion.
The time interval between two adjacent events is the function
of the integrated v oBPF_k .
In audio signal processing, a frame length of 25 ms is
typically used, with a 10-ms frame shift. Abiding by this
convention, one input neuron in BNN has the value of the
event number (EN) accumulated in a 25-ms window, which
can be seen as the quantized area under the waveform of
the rectified v oBPF_k within 25 ms. Incorporating multiple
contextual neighboring frames can improve the classification
accuracy [25]. As a tradeoff between the accuracy and power,
only two instead of more neighboring frames are used, i.e., to
classify frame n, frame (n −3), n, and (n +3) are used together
as the input, and hence, the number of input neurons is 3×
the front-end channel number. Because this scheme utilizes
frames in the future, it results in latency, which is 30 ms in
the case here. Latency is an important metric in applications
like VAD-assisted hearing aids [28], which requires careful
tradeoff with accuracy and power.
Assuming a passive microphone that gives a 30-μVrms
output signal at a 65-dB sound pressure level (SPL) for a
normal loudness conversation at 1-m distance [24], and a
minimum 10-dB SNR at the input of the VAD system, an IRN
of 10 μVrms needs to be achieved. A maximum LNA gain
of 42 dB and a maximum BPF gain of 18 dB ensure a more
than 50 dB dynamic range (DR) of the FWR output current
with a 10-pA leakage current. The event number within a
25-ms frame is designed to be nominally less than 255 in
response to speech, i.e., 8 bit, even though the theoretical max
is about 900 given the 5-nA max value of f v→i , 0.9-pF Cint ,
and 0.15-V Vrefdn in (1).
The audio dataset we use is built on the Aurora4 corpus [29].
Three hundred clean utterances with a 16-kHz sampling rate
and a 16-bit resolution are randomly selected from Aurora4 as
the basis for the training dataset, and another 30 and 300 clean
utterances for the development and test dataset [25]. The
utterances in each dataset are concatenated. The total length of
the training and development audio is about 37 and 3 minutes,
respectively. An additional non-speech section is added to
the test audio to balance the speech and non-speech periods,
so the test audio has a total length of about 1 hour. The
noise corpus DEMAND contains 18 different noise scenarios
including metro and restaurant [30]. Noise audio of different
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 6, JUNE 2019
scenarios is mixed with the clean speech at different SNR
levels using the noise mixing software program downloaded
from aurora.hsnr.de.
The acoustic features for off-line training of the BNN are
generated by the customized front-end python model. The
LNA is modeled by a high-pass and a low-pass transfer
function. An extra low-pass transfer function is added to model
the LNAs larger than 20 dB/decade roll-off. The BPFs are
modeled by 2nd-order bandpass transfer functions with geo-
metrically scaled central frequencies. The FWRs are modeled
by the transfer functions of the output current in relation to
the input voltage. The IAF models the integration of input
current on a capacitor, and whenever the capacitor potential
exceeds a predefined threshold, the capacitor voltage is reset
to 0 and an event is generated. We fit the models of all the
building blocks with parameters from Spectre simulations with
non-idealities considered, such as the frequency dependency
of the FWR transfer functions, the finite bandwidth of the
comparator in IAF, etc. To demonstrate the efficacy of our
AFE model, we show in Fig. 4(a) the comparison of the
extracted features, i.e., EN along the frame sequence, using
both the python model and the transient Spectre simulation
with an utterance from Aurora4 shown in Fig. 4(c) as the input.
The two sets of features almost overlap in all 16 channels.
Fig. 4(b) shows the small differences between the two sets of
features.
The off-line training of the BNN classifier uses the features
generated by the python model. The BNN has three hidden
layers, and each has 60, 24, and 11 neurons, respectively. The
number of hidden layers and neurons is heuristically selected
for best possible hit-rate performance within the power budget.
The activations of the two output neurons are compared with-
out binarization to classify a frame as either a voice or a noise
frame. The optimization algorithm is the modified stochastic
gradient descent for BNN [26]. For training, the feature frames
are randomly shuffled, but the contextual window including
frames n − 3, n, and n + 3 is maintained. The important
training parameters are: batch size 200, learning rate 0.0003,
number of epochs 2000, dropout rate of hidden neurons 0.2.
The BNN models are separately trained for each noisy speech
with a specific noise type and SNR value. This is called noise-
dependent training [25], in contrast to the noise-independent
YANG et al.: DESIGN OF AN ALWAYS-ON DEEP NEURAL NETWORK-BASED 1-μW VAD 1767

Fig. 4. (a) Comparison of the 16-channel acoustic features in event number (EN) over a frame sequence generated by the customized python model (red
hollow circle) and by the post-layout transient Spectre simulation (black line). (b) EN difference (EN). (c) Audio waveform of the utterance that is selected
from the Aurora4 corpus, and used to generate the features (maximum amplitude normalized to 1).

Fig. 5. LNA block diagram. Fig. 6. Removal of one tail current of the inverter-based input stage.

training where the goal is that a VAD can be used in any

noise scenario and in a wide range of SNR conditions without
changing the classifier parameters. Arguably the latter may
require much larger network size and training datasets.
III. C IRCUIT I MPLEMENTATION
A. Biasing Circuits
A subthreshold proportional-to-absolute-temperature cir-
cuit [31] with a 33-M off-chip resistor generates the main
bias current of 1.62 nA at room temperature, and this current is
distributed to all the analog building blocks. The geometrically
scaled bias currents for the BPFs are generated by the pFET-
based current divider similar to the one used in [19].
B. Low-Noise Amplifier
The block diagram of the ac-coupled LNA is shown
in Fig. 5. It consists of the main amplification path and the
dc-servo loop (DSL) path. The closed-loop gain is determined
by the capacitance ratio Cin /Cfb . Cin is made programmable to
accommodate a large range of SPL, and accordingly the gain
can be adjusted from 24 dB to 42 dB with a 6-dB step. For
a 42-dB maximum gain, a two-stage amplifier is needed in the
main path to have a sufficient dc open-loop gain, and its stabil-
ity requires compensation. Recently, some ULP designs place
the dominant pole at the output of the 2nd stage [32], [33] to
avoid the power waste in pushing the non-dominant pole of
the 2nd stage for enough phase margin (PM) in compensation
schemes like Miller compensation, and analysis shows that
this method cannot achieve minimal power consumption in
our design with the specified gain-bandwidth product (GBW).
As a result, the dominant pole is still placed at the output of
the 1st stage.
An inverter-based input stage has long been used to improve
the noise efficiency factor (NEF) of amplifiers. Two tail current
sources are normally required, one for the bias current, and
the other for the common-mode feedback (CMFB) [32]–[36],
as shown on the left side of Fig. 6. It is desirable to remove

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1768 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 6, JUNE 2019

Fig. 7. Schematic of the main amplifier in the LNA.

one tail current for extra voltage headroom that is important for
robust operation over process, voltage and temperature (PVT)
variations under a low supply voltage. One possibility is to
remove Mtail , bias the gate of M p at a different dc from Mn ,
and ac couple the input signal like in [37]. However, in the
audio frequency range, this requires the use of pseudo-resistors
whose resistance is highly susceptible to PVT variations, and
consequently the associated high-pass corner frequency and
the recovery time of the amplifier from any common-mode
disturbance are poorly defined [33].
Another possibility is to remove Ibias , as shown on the right
side of Fig. 6. Due to the lack of current source for Mn ,
the input dc voltage, which is the output dc voltage of the
Fig. 8. Simulated frequency response of the main amplifier in the LNA
DSL amplifier, needs to be set to the trip point of the inverter. with (top) and without (bottom) the positive feedback networks.
This trip point can be provided by a replica inverter, as shown
in Fig. 7. The replica inverter is composed of M0 and M1 ,
which are compound transistors and topologically match with
the input transistors M2 –M5 but with scaled sizes to reduce the
bias current. The trip point voltage Vb is tied to the body of
M2 –M5 to avoid large width that can lower the non-dominant
pole frequency [38] and elevate the IRN of the LNA [39]
due to parasitic capacitance. The use of compound transistors
is for the pseudo-cascode compensation [40], [41] using Cc
and Rc , instead of the Miller compensation, for higher PM
and unity-gain frequency. To reduce the bias current of the 2nd
stage, we use the positive feedback via C f and R f adapted Fig. 9. Schematic of the DSL amplifier in the LNA.
from the bandwidth enhancement techniques [42], [43] to have
sufficient PM. The simulated frequency response of the main
The output dc voltage is set to Vb via its CMFB amplifier com-
amplifier and the LNA at a 42-dB gain in Fig. 8 shows the
posed of M4 –M9 . The amplifier is biased at the picoampere
efficacy of the positive feedback used in conjunction with the
level to give a well-defined high-pass corner frequency of the
pseudo-cascode compensation. The 3-dB bandwidth of the
LNA less than 100 Hz. The stability of the closed loop formed
main amplifier increases by 3.3× and the PM is improved
by the main and DSL amplifiers is guaranteed by the very low
from 20◦ to 56◦ . The bandwidth of the LNA is improved from
frequency of a dominant pole at the node v x .
2.5 kHz to 6.1 kHz with a steeper roll-off near the low-pass
corner frequency. The output dc is set to Vmid , i.e., VDD/2 via
the CMFB amplifier composed of M9 –M13 , and Rcm C. Bandpass Filter
and Ccm . The pseudo-resistor Rcm with symmetric resis- In off-line MLP training using the features generated by the
tance [19] is implemented with two pFETs connected as M14 front-end python model, we found that the classification results
and M15 . are satisfying with low quality factors and low-BPF orders,
The DSL amplifier is shown in Fig. 9. Its input and output and hence, we did not choose to use the source-follower-based
are the output and input of the main amplifier, respectively. 4th-order BPF in [19] which can synthesize high quality factor

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YANG et al.: DESIGN OF AN ALWAYS-ON DEEP NEURAL NETWORK-BASED 1-μW VAD 1769

Fig. 11. Simulated differential SSF-based BPF output noise spectral density
Fig. 10. Schematic of the SSF-based BPF with output buffer and input dc of channel 15 at Vout .
bias. The fabricated circuit is a differential version.

but requires voltage sum using a power-consuming opamp

to transform a low-pass transfer function to a bandpass one.
The new 2nd-order BPF circuit shown in Fig. 10 is based on
the super-source-follower (SSF) topology, which together with
its mutants, including the self-coupled source follower and the
flipped source follower, have been used to construct power-
efficient low-pass filters [44]–[46]. Gigahertz BPFs that are Fig. 12. (a) Single-ended 2-T current rectifier. (b) Direct cross-coupled
topologically similar to the BPF shown in Fig. 10 but utilize a current rectifier. (c) AC-coupled cross-coupled current rectifier.
transistor’s source as the input terminal can be found in [47]
and [48]. The transfer functions HBPF (s), central frequency f 0 ,
where i n M0 , i n M1 , i n0 , and i n1 are the noise current sources
quality factor Q, and peak gain A0 are derived as
of M0 , M1 , I0 , and I1 , respectively, and HLPF (s) in (4) is
C2 1
v out sg HLPF (s) = . (5)
HBPF (s) = = − C C m2 C (2) s 2 gC1 Cg 2 + s gC1 + 1
v in s 2 gm11 gm2
2
+ s gm21 + 1 m1 m2 m2
 
1 gm1 gm2 gm2 C2 C2 The simulated output noise spectral density of channel 15
f0 = , Q= , A0 = (3) with an f0 around 5 kHz shown in Fig. 11 verifies the
2π C1 C2 gm1 C1 C1
transfer function of each noise source. Overall, v n ,out has a
low-pass characteristic, but the most significant in-band noise
where gm1 and gm2 are the transconductance of M0 and M1 ,
is contributed by M0 and I0 . The output-referred noise (ORN)
respectively. In subthreshold, gm1 and gm2 are proportional to
at v obuf integrated from 10 Hz to 500 kHz is simulated to be
I0 and I1 –I0 , respectively. The Q and A0 are thus determined
about 111 μVrms . The periodic steady-state simulations show
by the current and capacitance ratio.
that the output signal swing is about 89 mVrms for a 5% total
The dc voltage of v out is susceptible to the Vth variation
harmonic distortion (THD), and DR is computed to be 58 dB.
of M1 and so is the dc voltage of v x to the Vth variation of
The DR of the BPFs across all channels is larger than 55 dB
M0 with a fixed input dc. This can cause serious headroom
in simulation.
problems for a large signal swing. A simple compensation
scheme uses the diode-connected M3 with its source connected
to a reference voltage Vrefup . The input dc of M0 is the gate D. Full-Wave Rectifier and Integrate-and-Fire Event Encoder
voltage of M3 , and the input to the BPF is ac-coupled. The In contrast to rectifiers widely used in energy harvesting,
pseudo-resistor Racin has the same implementation as the one precision rectifiers aim to precisely realize the mathematical
shown in Fig. 7. To drive the input capacitance of the FWR, function y = |x|(x, y R). For inference sensing applications,
a source-follower buffer is used. The input is ac-coupled, the exact mathematical rule in signal transformation is unim-
and the input dc is set to ground for sufficient output swing portant provided that the relevant information is not lost,
over PVT. The pseudo-resistor Racout is implemented with because a machine learning model like MLP can learn and
two pFETs configured as M4 and M5 . Because the signal adapt to any deterministic mapping. But in our model-based
transient at its terminal connected to Cacout can go below design, for the convenience of model construction and the AFE
ground, the topology of Racin is not used. variation control, we chose to use a precision rectifier.
The output noise v n,out of the SSF-based BPF core at the The MOSFET-only precision rectifiers can be categorized as
node v out can be derived as the voltage mode and the current mode depending on whether
 the signal being rectified is voltage or current. The voltage
1 g2  2  mode uses simple comparators and switches [49], [50], but is
v n,out = 2 i n2M0 · HBPF
2 2
(s) + m1 · i n M1 + i n1
2
· HLPF
2
(s)
gm1 2
gm2 not suitable here because the input signal can be much smaller
 2
than the comparator’s input offset, which can be as large as
gm1 tens of millivolts without offset calibration. Besides, voltage
+ i n0
2
· HLPF(s) + |HBPF (s)| (4)
gm2 has to be converted to current for easy implementation of

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1770
Fig. 13. Schematic of (a) FWR and IAF and (b) pseudo-resistor Rfb that is composed of eight diode-connected pFETs connected in series.
the integration in (1), motivating direct rectification in current
domain. One simple 2-T current-mode topology is shown in
Fig. 12(a) [51], [52]. It has several issues in robust low-voltage
design.
First, input current i in is normally realized by an operational
transconductance amplifier (OTA). For a 1000-fold change
of i in , the source voltages of Mn and Mp in subthreshold,
i.e., the OTA output, have a voltage swing of 178 mVpk at
room temperature, pushing the transistors in the OTA output
stage to the verge of the linear region with a 0.6-V supply.
This problem can be circumvented by the cross-coupling
topology shown in Fig. 12(b). The swing is reduced to 99 mV
with a subthreshold slope factor κ = 0.8 [53]. Second,
the parasitic capacitance at node v causes the delay and hence
distortion in current transmission because it takes time to
charge v and turn on Mn /Mp [54]. This dead-zone problem
can be mitigated by using a feedback amplifier to reduce the
swing of v [55]. However, the feedback requires an amplifier
with high GBW, leading to high power consumption. A low-
power solution is to weakly bias Mn and Mp in dc. As shown
in Fig. 12(c), the gates of Mn and Mp are dc-biased and
the differential transient signals are ac-coupled. Third, as a
voltage-controlled current source, the OTA is normally in
open loop, because any feedback can compromise the output
impedance, but the output dc offset current can significantly
reduce the DR of the rectifier. Dedicated circuits for automatic
offset current calibration are at the cost of extra power and
area [54]. As shown in the complete schematic of the FWR and
IAF in Fig. 13(a), here we employ simple dc feedback through
the pseudo-resistor Rfb , which has much larger impedance
than the OTA output impedance. The dc offset current is thus
eliminated.
The input dc of the OTA is set to half Vmid to have sufficient
voltage headroom for its input stage. Rfb is composed of eight
diode-connected pFETs in series, as shown in Fig. 13(b).
Racrec is the same as Rcm in Fig. 7. The dc bias voltages
Vbiasn and Vbiasp are generated by the scaled replica of the
cross-coupled rectifier using transistors M4 and M5 , whose
source voltages are set to Vmid , the same as the OTA output
common-mode voltage. The simulation results in Fig. 14 show
the transient waveform of i rec with a 20-mVpk sinusoidal
input to the OTA at the frequencies of 100 Hz and 5 kHz.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 6, JUNE 2019
Fig. 14. Simulated irec using the direct and ac-coupled cross-coupled rectifier
with a sinusoidal input at 100 Hz (black) and 5 kHz (red).
It is obvious that the dead-zone distortion is alleviated using
the ac-coupled topology compared to the direct cross-coupled
one, especially in the 5-kHz case. Small-signal ac simulation
shows that the transconductance of the OTA is about 103 nS,
which is in agreement with the 2-nA peak current in the
ac-coupled case. The cause of the much decreased peak current
in the direct cross-coupled case is the much smaller quiescent
leakage current. Because the ratio of the maximum to the
minimum i rec becomes larger, the output swing of the OTA
increases, and gets clipped under a 0.6-V supply.
The dead-zone problem is further mitigated by reducing
the parasitic capacitance at v out , i.e., minimizing the size of
M0 –M3 in Fig. 13 and the width of the transistors at the
output of the OTA [54]. However, small size is in conflict
with the requirement of small output conductance and small
output voltage and current offset caused by mismatch. Cascode
is used to solve this dilemma. In particular, the common-
source transistors M8 , M9 , M14 , and M15 in Fig. 15 have large
size to guarantee small current mismatch, and the cascode
transistors M10 –M13 have small size to minimize the parasitic
capacitance. M14 and M15 are guaranteed to be at the verge
of saturation over PVT because of the biasing scheme of M12
and M13 .
The IAF shown in Fig. 13 integrates the i rec on the capac-
itor Cint . Whenever v int crosses the threshold Vrefdn , M6 is
turned on and v int is reset to ground. After the delay of
the continuous-time comparator, M6 is turned off, and the
integration starts again. This IAF functions as an area-efficient
and power-efficient ED-ADC for approximate quantization.
Non-idealities like the finite bandwidth of the comparator
YANG et al.: DESIGN OF AN ALWAYS-ON DEEP NEURAL NETWORK-BASED 1-μW VAD
Fig. 15. Schematic of OTA in FWR.
Fig. 16. Block diagram of the binarized MLP.
and the input-slope-dependent delay are not detrimental; they
are included in the front-end model, and the MLP can adapt
accordingly through training.
E. Binarized Multilayer Perceptron
The block diagram of the digital binarized MLP is illus-
trated in Fig. 16. Ripple counters are used as the interface
between the asynchronous feature extraction front-end and the
synchronous inference computing. Nine-bit counters, one more
bit than the specified 8 bits, are used in case of overflow. Three
counters are used for each channel. Each counter counts events
in a 25-ms window, and three counters work in a cyclic way
with a 10-ms shift. The features of one frame are stored in a
16×9 block of the data memory DMEM. Because three frames
are needed for one classification, as discussed in Section II,
the features, e.g., in block 0, block 3, and block 6, are used
to classify the frame with its features stored in block 3. Old
features are overwritten by the new ones, e.g., the features of
the 8th frame would be written into block 0, and so on. The
1-b weights stored in the weight memory WMEM are obtained
from off-line training, and they are loaded through a scan chain
when the chip is powered up before normal operations. Both
DMEM and WMEM use latch-based design to work robustly
under a low supply voltage. The addresses for the memories
and the control signals for the counters and the computing
engine are generated by the controller block.
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1771
The 100 classification/s throughput requires that all opera-
tions of add and accumulation need to finish within 10 ms,
and a clock of 500 kHz is thus sufficient for using one single
accumulator. Given the fact that only the 1st hidden layer
has 9-bit input, and other layers have 1-bit input, part of the
register is clock-gated for power saving. The full register and
a 15-bit adder are used for the 1st hidden layer computation
indicated by l1 , and 7 bits of the full register and a 7-bit
adder are used for the subsequent layers. The input operand
of the accumulator is selected via a mux according to the
weight value w. For the 1st hidden layer, the input feature d9
is selected if w = 1, and otherwise its complement is selected.
For the rest of the hidden layers, 0, +1, or −1 is selected
depending on both w and the activation of the previous layer.
The activation function hard sigmoid HS(•) is simply the
inversion of the sign bit of the register after completing the
accumulation of each neuron, and the 1-bit activation values
are stored in an 84-bit register file. HS(•) is not applied to the
output layer. Instead, the difference of the accumulated values
of the two output neurons is computed, controlled by lo2 , and
the sign bit is the class, 1 for speech and 0 for non-speech.
IV. E XPERIMENTAL R ESULTS
The chip was fabricated in 1P6M 0.18-μm CMOS. The
microphotograph of the die is shown in Fig. 17 with the
building blocks labeled. The core area is 1.66×1.52 mm2 . The
simulated power breakdown of the front-end at 0.6 V is shown
1772 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 6, JUNE 2019

Fig. 17. Die microphotograph with building blocks and dimension labeled.

Fig. 19. Measured transfer functions (top) and input-referred noise spectral
density (bottom) of the LNA in four different gain settings.

Fig. 18. Simulated power breakdown of the feature extraction front-end.

in Fig. 18. A significant amount of current is consumed by the

OTA in the FWR for sufficient current DR, and alleviating the
dead-zone phenomenon. More power saving can be achieved
by scaling the OTA current in low-frequency channels like in Fig. 20. Harmonic distortion of the LNA at a gain 11 measured with a
the BPF bank. We did not choose to pursue this because of the 700-Hz fundamental tone.
extra complexity in sizing of the OTA transistors and scaling
the Cint in the IAF. Using Keithley 2401, the measured front-
end power is about 380 nW, close to the simulated 373 nW.
The measured MLP power at 0.55 V is about 630 nW. The
power consumption of the entire VAD system is 1.01 μW.

A. Feature Extraction Front-End

The measured power consumption of the LNA is about
87 nW under a 0.6-V supply. Using the dynamic signal
Fig. 21. Measured CMRR and PSRR at the highest gain of the LNA.
analyzer SR780, the measured transfer functions and IRN
spectral density of the LNA at four different gain settings
are shown in Fig. 19. The increased noise floor as the gain TABLE I
decreases can be attributed to the decrease of the input N OISE AND H ARMONIC D ISTORTION P ERFORMANCE OF LNA
capacitance Cin shown in Fig. 5 [39]. The harmonics measured
with a 700-Hz fundamental tone at the highest LNA gain
is shown in Fig. 20 for a 1% THD. The calculated IRN
within the frequency range of 50–12.8 kHz, the NEF [56],
the power efficiency factor (PEF = NEF2 × VDD), and the
DR at 1% THD are listed in Table I. The measured common-
mode rejection ratio (CMRR) and power supply rejection
ratio (PSRR) at the highest LNA gain are shown in Fig. 21. bandpass characteristic. The rate of leakage events caused
The frequency response of the whole feature extraction by the leakage dc component of i rec shown in Fig. 14(a)
front-end, from the input of the LNA to the output of the can be derived from the saturated EN per frame at high
IAF, is shown in Fig. 22. The differential input amplitude frequencies beyond 10 kHz. The highest leakage event rate
is 0.4 mVpk , and the gain code of the LNA is set to goes up to about 148 event/s, and the lowest leakage event rate
01. The feature is the EN per frame, and as mentioned in is about 70 event/s. Given a nominal 0.9-pF Cint in the IAF,
Section II, each frame has a duration of 25 ms. It is clear the corresponding leakage currents span from 9.5 to 20 pA,
that the features across the 16 channels exhibit the desired consistent with the designed values. The highest event rate can

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YANG et al.: DESIGN OF AN ALWAYS-ON DEEP NEURAL NETWORK-BASED 1-μW VAD
Fig. 22. Measured frequency response of the feature extraction front-end.
Fig. 23. Measured speech/non-speech hit rate using the 10-dB noisy speech
in a restaurant noise scenario, and 5-dB noisy speech in a metro noise scenario.
The same weights trained offline are used for MLP in each case.
go up above 10 kevent/s, giving a DR at the output of the IAF
around 40 dB.
B. Voice Activity Detection System
A 1-hour-long test audio, the same noisy speech used in the
neural network inference in software simulation, is supplied to
the LNA input through PCIe-6323 generated using LabVIEW.
The audio rms amplitude is about 200 μV, and the LNA
gain code is set to 10. Two cases are tested, the 10-dB
SNR noisy speech in a restaurant noise scenario, and the
5-dB SNR noisy speech in a metro noise scenario. In each
case, the same weights are used for the on-chip MLP for
all the ten test chips, eliminating the costly chip-wise feature
measurement and classifier training in contrast to [23], [24].
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1773
Fig. 24. (a) Clean speech sample and label sequence. (b) Corresponding
metro 5-dB noisy speech sample and measured classification sequence.
The measured speech and non-speech hit rates of the ten
test chips and the simulated hit rate are shown in Fig. 23.
The method of calculating speech and non-speech hit rates is
referred to the definition of true positive and true negative
in the two-class classification [57]. The mean speech and
non-speech hit rates, μS and μNS , and the corresponding 1-σ
variations, σS and σNS , are given in the plot. It is interesting
to see the measurement points have somewhat similar tradeoff
between speech and non-speech hit rates as the points on the
receiver operating characteristic (ROC) curve [57]. Overall,
the software simulation result using the customized feature
extraction front-end software model is a good prediction of
the measured system classification performance.
To visualize the real-time classification process, frac-
tions of the temporal classification sequence are shown
in Fig. 24 together with the metro 5-dB noisy speech
waveform. The clean speech and label sequence are also
shown. Compared to the label, the measured classification
sequence exhibits sporadic misclassification. In retrospect,
instead of directly comparing the activations of the output
neurons, adding a posterior handling block with sliding win-
dow smoothing of the activations before decision threshold
may reduce this type of sporadic error and hence improve the
overall classification performance [58].
V. C ONCLUSION AND D ISCUSSION
The design of a 1-μW voice activity detector using ana-
log feature extraction and digital classification is elaborated
in this paper. The low power consumption is achieved by
leveraging the power/energy efficiency of ASP and BNN.
As shown in Table II, compared to the best prior work on
analog feature extraction front-end, this work is more than
9× power efficient. Compared with the most power-efficient
1774 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 6, JUNE 2019

TABLE II
C OMPARISON OF AFE

TABLE III
C OMPARISON OF AUDIO C LASSIFICATION S YSTEMS

digital implementation of BPF based on the charge-recovery
design [59], this work including other building blocks besides
BPF shows 5× higher power efficiency when the frequency
range is equalized.
Table III shows the comparison of this VAD with the other
audio classification systems. While our design consumes the
lowest power among VAD, it is fair to also consider the
classification rate. The 32-nm VAD [1] has slightly better
energy efficiency in terms of class/W/s. However, it may not
be the best choice for minimized power consumption in low-
throughput real-time intelligent sensing applications, because
the energy efficiency decreases quickly with the power supply
voltage below 0.65 V due to leakage as indicated in the mea-
surement, even though the design already uses ULP transistors
with extremely low leakage and ultra-high Vth [1]. Techniques
like transistor sizing and power gating can further suppress
leakage current, but the energy efficiency can hardly get better
than the optimized peak value at 0.65 V. The system in [60]
for acoustic object detection consumes only 12 nW, but the
system bandwidth is less than 500 Hz, and the classification
rate is too low for VAD. The systems in [61] and [62] based on
spiking NNs are not very energy efficient. The reason is that
IBM’s TrueNorth is more of a general purpose platform that
can support various NN algorithms. The digital VAD in [2] is
used to power-gate the automatic speech recognizer. It actu-
ally implemented three different algorithms: energy-based
(EB, 8.5 μW), harmonicity (HM, 24.4 μW), and modulated
frequency with NN (MF + NN, 22.3 μW). It is reported that
MF + NN gives the best performance. With no fast Fourier
transform (FFT), the EB algorithm consumes 3× less power
than the other two FFT-based ones, and HM consumes more
power than MF + NN because it takes two short-term FFT
per frame even though no NN computation is required. This
indicates the power-hungry nature of the conventional digital
FFT approach for frequency analysis.
With the help of the customized feature extraction front-end
model during the design time, we are able to use the same
classifier parameters for all test chips without costly chip-wise
feature measurement and classifier training, and relatively
small spread in speech and non-speech hit rates across dies

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YANG et al.: DESIGN OF AN ALWAYS-ON DEEP NEURAL NETWORK-BASED 1-μW VAD
is achieved, despite the fact that for high power efficiency,
the front-end is designed in deep subthreshold analog, which
is much more prone to PVT variations compared to the digital
counterpart. One open question is, is it possible to further
reduce the classification spread across dies by leveraging
the generalization capability of deep learning models without
increasing the area of the analog circuits for feature extraction?
As an initial attempt, we performed software emulation of the
VAD system with consideration of AFE parameter variation
during BNN training. In other words, we slightly modified the
flow shown in Fig. 2 so that the features for classifier training
are from both “model with fit parameter” and “model with
parameter variation.” Features generated from different sets
of “model with parameter variation” are used for inference.
Despite the 20× augmentation in training datasets, the relative
reduction of the hit rate variation is marginal: less than 10%
across several runs. Further studies need to be done to explore
the limit of this scheme for variation reduction.
ACKNOWLEDGMENT
The authors would like to thank N. Mesgarani, Y. Tsividis,
M. Verhelst, and X.-L. Zhang for the valuable discussion and
help.
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Minhao Yang (S’11–M’16) received the Ph.D.
degree in physics from ETH Zurich, Zürich,
Switzerland, in 2015.
He was a Post-Doctoral Researcher with Columbia
University, New York, NY, USA. He is currently
a Collaborateur Scientifique with EPFL, Lausanne,
Switzerland. His post-doctoral research was partly
supported by the Early Postdoc Mobility Fellow-
ship from the Swiss National Science Foundation.
His research interests include ultra-low-power (ULP)
inference sensing systems, event-driven sensors like
spiking silicon retina and cochlea, and spike coding and processing.
Chung-Heng Yeh received the B.S. degree in elec-
trical engineering from National Taiwan University,
Taipei, Taiwan, in 2010, and the M.S. degree in
electrical engineering from Columbia University,
New York, NY, USA, in 2013, where he is currently
pursuing the Ph.D. degree in electrical engineering.
His current research interests include information
processing in spike domain, large-scale neural sys-
tem emulation, and neural inspired algorithm.
Yiyin Zhou received the B.E. degree in electrical
engineering from Shanghai Jiao Tong University,
Shanghai, China, in 2007, and the M.S. and Ph.D.
degrees in electrical engineering from Columbia
University, New York, NY, USA, in 2009 and 2015,
respectively.
He is currently a Post-Doctoral Research
Scientist with the Department of Electrical
Engineering, Columbia University. He is an
active team member of the Fruit Fly Brain
Observatory Team, Columbia University,
and has co-organized three Fruit Fly Brain Hackathons. He is also
interested in massively parallel neural computation on high-performance
computing devices. His research interests include formal methods for
spike-time-based representation of sensory information and system
identification, and the logic of information processing of the fruit fly brain
on both neuroinformation processing and neural circuit levels.
Dr. Zhou received the Jury Award from the Department of Electrical
Engineering, Columbia University, in 2016, for outstanding achievement
by a graduate student in the area of systems, communications, and signal
processing.
YANG et al.: DESIGN OF AN ALWAYS-ON DEEP NEURAL NETWORK-BASED 1-μW VAD
Joao P. Cerqueira (S’17) received the B.S. degree
(Hons.) in electrical engineering from the University
of Brasília, Brasília, Brazil, in 2014, and the M.S.
degree in electrical engineering from Columbia
University, New York, NY, USA, in 2016, where he
is currently pursuing the Ph.D. degree in electrical
engineering.
His current research interests include
energy-efficient integrated circuits and computer
architecture.
Mr. Cerqueira received the Science Without
Borders Fellowship from CAPES, the Lemann Foundation Fellowship, and
the Qualcomm Innovation Fellowship.
Aurel A. Lazar (S’77–M’80–SM’90–F’93–LF’16)
was a Principal Investigator leading a number of
computer networking research groups in the Depart-
ment of Electrical Engineering, Columbia Univer-
sity, New York, NY, USA, for 20 years. He covered a
broad set of research topics/fields, including building
major switching hardware, architecting broadband
kernels for programmable networks, and creating
game theory models for resource allocation. He also
ran a networking start-up as a CEO. Some 15 years
ago, predicting that Moore’s law will soon reach
its limits, he switched his field of research to computational neuroscience
in search of principles of building cognitive machines, with capabilities
well beyond those powered by von Neumann architectures. He currently
leads research projects in computing with fruit fly brain circuits, in building
interactive computing tools for the Fruit Fly Brain Observatory and on creating
neuroinformation processing machines. His research has drawn support from
a number of funding agencies including the AFSOR, NIH, and NSF.
Dr. Lazar received the 2003 IFIP/IEEE Dan Stokesberry Memorial Award
in recognition of “the most distinguished technical contributions to the growth
and understanding of the field of network management.”
Authorized licensed use limited to: Johns Hopkins University. Downloaded on June 19,2024 at 02:08:56 UTC from IEEE Xplore. Restrictions apply.
1777
Mingoo Seok (S’05–M’11–SM’18) received the
B.S. degree (summa cum laude) in electrical engi-
neering from Seoul National University, Seoul,
South Korea, in 2005, and the M.S. and Ph.D.
degrees in electrical engineering from the University
of Michigan, Ann Arbor, MI, USA, in 2007 and
2011, respectively.
In 2011, he joined Texas Instruments Inc., Dallas,
TX, USA, as a Technical Staff Member. Since
2012, he has been with the Department of Electrical
Engineering, Columbia University, New York, NY,
USA, where he is currently an Associate Professor. His current research
interests include variation, voltage, aging, thermal-adaptive circuits and archi-
tecture, ultra-low-power (ULP) SoC design for emerging embedded sys-
tems, machine-learning VLSI architecture and circuits, and nonconventional
hardware design.
Dr. Seok received the 1999 Distinguished Undergraduate Scholarship
from the Korea Foundation for Advanced Studies, the 2005 Doctoral
Fellowship from the Korea Foundation for Advanced Studies, and the
2008 Rackham Pre-Doctoral Fellowship from the University of Michigan,
the 2009 AMD/CICC Scholarship Award for picowatt voltage reference
work, the 2009 DAC/ISSCC Design Contest for the 35-pW sensor platform
design, and the 2015 NSF CAREER Award. He has served as an Associate
Editor for the IEEE T RANSACTIONS ON C IRCUITS A ND S YSTEMS I
from 2013 to 2015 and the IEEE T RANSACTIONS ON V ERY L ARGE S CALE
I NTEGRATION S YSTEMS since 2015 and IEEE S OLID -S TATE C IRCUITS
L ETTERS since 2017.