Tessent

4-Pin TAP implementation flow 保存该页面

更新于 2014年6月12日

LV Flow
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知识库文章 ID#
MG586668
摘要
内容

We would like to remove the optional TRST TAP test port and make the
摘要
TRST an internal only signal driven from the POR. What is the flow to
make this happen? 详细信息

关联组件

详细信息
Tessent
MemoryBIST
All
Tessent LogicBIST

The "4-port" TAP implementation flow is supported. The 1149.1 Tessent SoCScan
standard does still REQUIRE that the "TRST" TAP pin exist and be Tessent
BoundaryScan
controlled by an internal POR signal. However, it does NOT need to
come from a Primary Port. So, that is the major thing to be mindful of. I
used the "car" testcase that is shipped with the Tessent tool to confirm 该文章是否有用？
that this worked. I made the following changes to the design:
是 否
1) Added the following to my "car" design -- removed the "TRST" port:
Please let us know
=================================================== your feedback about
this document
module car ( CK33, CK25, COORD0, COORD1, COORD2, COORD3, D1,
D2, D3, DIN, DOUT, 剩余 1500 字 提交

EN0, EN1, EN2, MODE, RESET, RF, SEL0, SEL1, TCK, TMS, TDI, TDO);

....

.....

......

POR POR_inst();

endmodule
module POR (ResetN);

output ResetN;

assign ResetN = 1'b1;

endmodule

====================================================

2) Added the following to my "car.etchecker" config file -- Let the tool

know that the TRST is connected internally:

###################################################

lv.JTAGOption -option TRST -connection car.POR_inst.ResetN

###################################################

3) Continue with the rest of the flow as normal. ETAssemble will

connect the TRST pin as specified in the .etchecker file.

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