Tessent

Creating a TDR inside the IJTAG 保存该页面

Network by reading in an
instrument ICL with DataInPort
and DataOutPort.
更新于 2022年8月12日

Tessent Shell Flow

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知识库文章 ID#
MG619993
摘要
内容

摘要

详细信息

相关文章

关联组件
This Support Kit shows how to create a TDR by reading in an
instrument ICL with DataInPort and DataOutPort. This is a part of the Tessent Shell
Environment
parent Support Kit MG619991: Three different methodologies to create
Tessent IJTAG
a TDR (Test Data Register) inside the IJTAG Network using the
DftSpecification. Tessent Scan

Tessent FastScan

At the end of this support Kit you should be able to do the following: 该文章是否有用？

是 否
Create a TDR to control or monitor the PLL instrument signals by
reading in a PLL instrument ICL with DataInPort and DataOutPort.
Please let us know
Set up the PLL by programming the TDR through a PDL and an iCall in a your feedback about
pattern set this document

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详细信息

Consider a PLL instrument in a design, for which a Test data

register (TDR) needs to be added to:
 Program the PLL using the CTRL[7:0] inputs
Reset the PLL using the RESET input
Check the PLL lock on the LOCK output

This TDR is to be accessed through an SRI (Scan Resource Instrument)

SIB, since the contents are not to be disturbed during scan test.

An instrument ICL and PDL is created for the PLL instrument, where the
inputs above are specified as DataInPort and DataOutPort as follows:

PLL.icl:
Module PLL {
DataInPort CTRL[7:0];
DataInPort RESET;
DataOutPort LOCK;

....

The PDL contains an iProc that sets the control signals and checks for
PLL lock.

PLL.pdl:
iProcsForModule PLL
iProc check_for_PLL_lock {} {
iNote "Setting up the PLL"
...
iWrite RESET 1
iApply
iRunLoop -time 250ns
iWrite RESET 0
iApply
iRunLoop -time 2000ns
iNote "Checking for PLL Lock"
iRead LOCK 1
iApply
}

These are read into Tessent with the commands:

read_icl PLL_mdl/PLL.icl
dofile PLL_mdl/PLL.pdl
The DftSpecification is created using the create_dft_specification
command below.
set spec [create_dft_specification]

Any instance of a module having a corresponding ICL module is, by

default, inserted into the IjtagNetwork wrapper of the DftSpecification
unless it is seen as being already connected to the network.
As a result, create_dft_specification infers the SRI SIB and the TDR to
control the PLL as reported by the command: report_config_data $spec
...
​ Sib(sri_local) {
Tdr(sri_tdr1) {
DataInPorts {
connection(0) : PLL_inst/LOCK;
}
DataOutPorts {
connection(0) : PLL_inst/RESET;
connection(1) : PLL_inst/CTRL[0];
connection(2) : PLL_inst/CTRL[1];
connection(3) : PLL_inst/CTRL[2];
connection(4) : PLL_inst/CTRL[3];
connection(5) : PLL_inst/CTRL[4];
connection(6) : PLL_inst/CTRL[5];
connection(7) : PLL_inst/CTRL[6];
connection(8) : PLL_inst/CTRL[7];
}
reset_value : 9'b000000000;
}
}
}
...

Click to download the Support Kit

Instructions: Create_tdr_from_module_icl_datain_and_dataout_ports_MG619993.pdf

Click to download the test

case: create_tdr_from_module_icl_datain_and_dataout_ports_MG619993.tar.gz

相关文章

Three different methodologies to create a TDR

(Test Data Register) inside the IJTAG Network using
the DftSpecification.
TROUBLESHOOTING
Three different methodologies are discussed on how to create a TDR
(Test Data Register) inside the IJTAG Network using the DftSpecification.

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