WDM OTN Clock Synchronization Feature Guide 12

WDM OTN
Clock Synchronization Feature

Guide
Issue 12
Date 2023-03-30
HUAWEI TECHNOLOGIES CO., LTD.

Copyright © Huawei Technologies Co., Ltd. 2023. All rights reserved.
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WDM OTN
Clock Synchronization Feature Guide About This Document
About This Document
The physical clock, IEEE 1588v2, and ITU-T G.8275.1/G.8273.2 features of the
WDM/OTN network support all-scenario, high-reliability, and high-performance
clock synchronization networks to provide clock synchronization for downstream
devices.
This document describes the clock functions of Huawei OSN series WDM/OTN
equipment, including application scenarios, technical principles, operation guide,
and capabilities of each equipment.
Related Versions
The following table lists the product initial versions to which this document can be
applied.
Product Name Start Version
OSN 9800 V100R001C20
OSN 8800 V100R002C00
OSN 6800 V100R005C00
OSN 1800 V100R003C05
For details about the specifications of this feature supported by each product
version, see:
● Physical-Layer Clock Feature Updates
● IEEE 1588v2 Feature Updates
● ITU-T G.8275.1/G.8273.2 Feature Updates
● 5.8 Feature Updates
Intended Audience
This document is intended for:
● Network planning and design engineers
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● Commissioning engineers
● Network monitoring engineers
● Data configuration engineers
● Network administrators
● Maintenance engineers
● Onsite maintenance engineers
Symbol Conventions
The symbols that may be found in this document are defined as follows.
Symbol Description
Indicates a hazard with a high level of risk which,

if not avoided, will result in death or serious
injury.
Indicates a hazard with a medium level of risk

which, if not avoided, could result in death or
serious injury.
Indicates a hazard with a low level of risk which,

if not avoided, could result in minor or moderate
injury.
Indicates a potentially hazardous situation which,

if not avoided, could result in equipment damage,
data loss, performance deterioration, or
unanticipated results.
NOTICE is used to address practices not related to
personal injury.
Supplements the important information in the

main text.
NOTE is used to address information not related
to personal injury, equipment damage, and
environment deterioration.
GUI Conventions
Convention Description
Boldface Buttons, menus, parameters, tabs, window, and

dialog titles are in boldface. For example, click
OK.
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Convention Description
> Multi-level menus are in boldface and separated

by the ">" signs. For example, choose File >
Create > Folder.
Public IP Address Usage Declaration

In this document, public IP addresses may be used in feature introduction and
configuration examples and are for reference only unless otherwise specified.
Change History
Updates between document issues are cumulative. The latest document issue
contains all the changes made in earlier issues.
Issue 12 (2023-03-30)
This issue is the twelfth official release. Compared with the last release, this
document is updated to match V100R022C10.
Topic Update Description
Type
2.4 Availability Modified Availability is updated to match V100R022C10.

3.4 Availability
4.4 Availability
Issue 11 (2022-10-30)
This issue is the eleventh official release. Compared with the last release, this
document is updated to match V100R022C00.
Type
2.4 Availability Modified Availability is updated to match V100R022C00.

3.4 Availability
4.4 Availability
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Issue 10 (2022-05-30)
This issue is the tenth official release. Compared with the last release, this
document is updated to match OSN 9800 V100R021C10SPC300 and OSN 1800
V100R021C10SPC300.
Type
2.4 Availability Modified Availability is updated to match OSN

3.4 Availability 9800/OSN 1800 V100R021C10SPC300.
4.4 Availability
3.3.1 Feature Modified The 1800 V Pro and 1800 II Pro chassis newly
Limitations support automatic compensation for ring
3.8.1.1 network delay offset and automatic single-fiber
Configuration bidirectional compensation.
Process
3.8.1.9
Configuring
Ring Network
Automatic
Compensation
2.2.2.3 New The description of preventing physical-layer

Preventing clock loops is added.
Physical Clock
Loops
5 High-Precision New The description of the high-precision clock

Clock synchronization solution is added.
Synchronization
Solution
2.2.3 Clock Modified The clock synchronization GE optical ports of

Source Port the OSN 9800 newly support the cascading
3.2.4 Time mode.
Source Port
4.2.2 Time
Source Port
3.8.1.1 Modified The guidance for setting the high-precision

Configuration clock mode is added.
Process
4.8.1.1
Configuration
Process
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Issue 09 (2021-11-30)
This issue is the ninth official release. Compared with the last release, this
document is updated to match OSN 9800 V100R021C00SPC300 and OSN 1800
V100R021C00SPC300.
Type

4.4 Availability
3.8.1.10.3 Modified The external time port of OSN 9800 newly

Parameters: supports transmission of G.8271 packets.
Clock
Synchronization
Attribute
4.8.1.11.4
Parameters:
Clock
Synchronization
Attribute
Issue 08 (2021-03-30)
This is the eighth official release. Compared with the last release, this document is
updated to match OSN 9800 V100R020C10SPC300 and OSN 1800
V100R020C10SPC300.
Type

4.4 Availability
2.2.3 Clock Modified The OSN 9800/OSN 1800 newly supports clock
Source Port synchronization GE optical ports.
3.2.4 Time
Source Port
4.2.2 Time
Source Port
2.5 Modified OSN 1800: Subracks that use the TMB1AUX

Specifications board support clock cascading between master
3.5 and slave subracks since V100R020C10.
Specifications
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Type
2.8.1.1 Modified/ OSN 1800:

Configuration New ● When the NE is configured with multiple
Process TMB1AUX boards or with both TMB1AUX
2.8.1.5 and TNF1AUX boards, one AUX board must
Configuring a be set as the main AUX board.
Main AUX Board ● The cascading modes of the clock
2.8.1.7 synchronization GE optical ports on the
Configuring the TMB1AUX board need to be set.
Cascading
Status of a
Clock GE Optical
Port
4.8.1.11.4 Modified The OSN 1800 and ports newly support the T-
Parameters: TC working mode and the external time port
Clock newly supports G.8271 packets.
Synchronization
Attribute
Updates in Issue 07 (2020-11-30)

This issue is the seventh official release. Optimized the document structure and
descriptions.

This issue is the sixth official release. Added the availability of new boards.

This issue is the fifth official release.
● Added the OptiX OSN 9800 M05 subracks to support physical-layer clocks,
IEEE 1588v2, and ITU-T G.8275.1/G.8273.2.
● Added the 1800 II Pro subracks to support physical-layer clocks, IEEE 1588v2,
and ITU-T G.8275.1/G.8273.2.
● Added the 1800 V Pro subracks to support physical-layer clocks, IEEE 1588v2,
and ITU-T G.8275.1/G.8273.2.

This issue is the fourth official release. Some descriptions in this document are
revised.

This issue is the third official release.
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● Added the OptiX OSN 9800 M12 series subrack to support physical-layer
clocks, IEEE 1588v2, and ITU-T G.8275.1/G.8273.2.
● Added the TNU4CTU system control boards of the OSN 9800 U type series
subracks to support physical-layer clocks, IEEE 1588v2, and ITU-T G.8275.1.
● Added the 1800 II TP subracks to support physical-layer clocks, IEEE 1588v2,
and ITU-T G.8275.1/G.8273.2.
● Added the configuration guide for NCE.

This issue is the second official release.
● Added the OSN 9800 P series subrack to support physical-layer clocks, IEEE
1588v2, and ITU-T G.8275.1.
● Added the TNU2CTU and TNS2CTU system control boards of the OSN 9800 U
series subrack to support physical-layer clocks, IEEE 1588v2, and ITU-T G.
8275.1.
● When equipped with the TNU2CTU or TNS2CTU board, the OSN 9800 U
series subracks support clock cascading between master and slave subracks.
● The line boards of OSN 1800 V are added to support IEEE 1588v2.
● The OSN 1800 V supports the configuration of the position and frame format
of PTP clock packets.
● The OSN 1800 V supports automatic compensation upon a fiber cut on a ring
network and single-fiber bidirectional asymmetric compensation when the
system control board is UXCMS.

This issue is the first official release.
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WDM OTN
Clock Synchronization Feature Guide Contents
Contents
About This Document................................................................................................................ ii

1 Overview of Clock Synchronization.................................................................................... 1
1.1 Why Does the WDM/OTN Network Need Clock Synchronization?....................................................................... 1
1.2 Clock Synchronization Requirements of Service Networks...................................................................................... 3
1.3 Frequency Synchronization Solutions...............................................................................................................................5
1.4 Phase Synchronization Solutions....................................................................................................................................... 7
1.5 E2E WDM/OTN Clock Solution........................................................................................................................................... 9
2 Physical Clocks (OTN & Packet & SDH)...........................................................................11

2.1 Introduction of Physical Clocks (OTN, Packet, and SDH)....................................................................................... 11
2.2 Principles.................................................................................................................................................................................. 12
2.2.1 Building the Master-Slave Clock Hierarchy.............................................................................................................. 12
2.2.2 Clock Protection................................................................................................................................................................. 13
2.2.2.1 Stop SSM Protocol and Start Standard SSM Protocol....................................................................................... 14
2.2.2.2 Start Extended SSM Protocol and Clock Source ID............................................................................................ 16
2.2.2.3 Preventing Physical Clock Loops............................................................................................................................... 18
2.2.2.3.1 Preventing Clock Loops on a Ring Network......................................................................................................19
2.2.2.3.2 Preventing Clock Loops on a Chain Network................................................................................................... 23
2.2.3 Clock Source Port.............................................................................................................................................................. 28
2.2.4 Synchronous Ethernet...................................................................................................................................................... 38
2.3 Dependencies and Limitations......................................................................................................................................... 41
2.3.1 Feature Limitations........................................................................................................................................................... 42
2.3.2 Affected Features...............................................................................................................................................................49
2.3.3 Mutually Exclusive Features........................................................................................................................................... 49
2.4 Availability............................................................................................................................................................................... 49
2.4.1 OSN 9800 Universal Platform Subrack Hardware and Version Support........................................................ 50
2.4.2 OSN 9800 P Series Hardware and Version Support.............................................................................................. 50
2.4.3 OSN 9800 U Series Hardware and Version Support............................................................................................. 51
2.4.4 OSN 9800 M Series Hardware and Version Support.............................................................................................55
2.4.5 OSN 8800 Hardware and Version Support............................................................................................................... 59
2.4.6 OSN 6800 Hardware and Version Support............................................................................................................... 62
2.4.7 OSN 1800 V Hardware and Version Support........................................................................................................... 64
2.4.8 OSN 1800 II Enhanced Hardware and Version Support.......................................................................................68
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2.4.9 OSN 1800 I Enhanced Hardware and Version Support........................................................................................72

2.4.10 OSN 1800 I&II Compact Hardware and Version Support................................................................................. 73
2.4.11 OSN 1800 V Pro Hardware and Version Support................................................................................................ 75
2.4.12 OSN 1800 II Pro Hardware and Version Support.................................................................................................79
2.4.13 OSN 1800 II TP Hardware and Version Support.................................................................................................. 82
2.4.14 OSN 1800 I Compact Hardware and Version Support....................................................................................... 85
2.5 Specifications.......................................................................................................................................................................... 86
2.6 Feature Updates.................................................................................................................................................................... 89
2.6.1 OSN 9800 Feature Updates........................................................................................................................................... 89
2.6.2 OSN 8800&6800 Feature Updates.............................................................................................................................. 93
2.6.3 OSN 1800 Feature Updates........................................................................................................................................... 98
2.7 Standard and Protocol Compliance..............................................................................................................................100
2.8 Configuration Guide (NCE)............................................................................................................................................. 100
2.8.1 Configuring Physical-Layer Clocks (OSN 1800/8800/9800Universal Platform Subrack/M Series/P
Series/(U Series: U2CTU/S2CTU/U4CTU/U5CTU))......................................................................................................... 100
2.8.1.1 Configuration Process................................................................................................................................................ 100
2.8.1.2 Configuring the Frequency Source Mode............................................................................................................ 104
2.8.1.3 Configuring the Synchronization Attributes of a Board................................................................................. 105
2.8.1.4 Configuring the Clock Center Subrack................................................................................................................. 106
2.8.1.5 Configuring a Main AUX Board.............................................................................................................................. 107
2.8.1.6 Configuring External Clock Ports........................................................................................................................... 108
2.8.1.7 Configuring the Cascading Status of a Clock GE Optical Port.....................................................................110
2.8.1.8 Configuring Clock Attributes................................................................................................................................... 111
2.8.1.9 Configuring Clock Source Protection.................................................................................................................... 116
2.8.1.10 Querying Clock Synchronization Status............................................................................................................ 118
2.8.1.11 Querying the Clock View........................................................................................................................................ 119
2.8.1.12 Configuring Clock Source Switching................................................................................................................... 120
2.8.1.13 Configuring Clock Attributes of Boards to Implement Synchronous Ethernet Transparent
Transmission................................................................................................................................................................................ 122
2.8.1.14 Configuring the ST2/AST4/AST2 Board to Transparently Transmit Clock Signals.............................. 123
2.8.1.15 Parameters: Physical Clock (OSN 1800/8800/9800Universal Platform Subrack/M Series/P
2.8.1.15.1 Parameters: Frequency Source Mode............................................................................................................. 124
2.8.1.15.2 Parameters: Clock Attribute Configuration................................................................................................... 125
2.8.1.15.3 Parameters: Clock Port Link............................................................................................................................... 128
2.8.1.15.4 Parameters: System Clock Source Priority List.............................................................................................129
2.8.1.15.5 Parameters: Priority for PLL Clock Sources of 1st External Output......................................................131
2.8.1.15.6 Parameters: Priority for PLL Clock Sources of 2nd External Output.................................................... 133
2.8.1.15.7 Parameters: Clock Subnet................................................................................................................................... 136
2.8.1.15.8 Parameters: Clock Source Quality.................................................................................................................... 140
2.8.1.15.9 Parameters: Manual Setting of Quality Level 0.......................................................................................... 143
2.8.1.15.10 Parameters: SSM Output Control.................................................................................................................. 145
2.8.1.15.11 Parameters: Clock ID Status............................................................................................................................ 145
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2.8.1.15.12 Parameters: Clock Source Reversion Parameter....................................................................................... 146

2.8.1.15.13 Parameters: Clock Source Switching............................................................................................................. 149
2.8.1.15.14 Parameters: Clock Synchronization Status................................................................................................. 150
2.8.1.15.15 Parameters: Clock Source Switching Conditions.......................................................................................156
2.8.1.15.16 Parameters: Phase-Locked Source Output by External Clock.............................................................. 158
2.8.1.15.17 Parameters: Clock Signal Pass-through....................................................................................................... 163
2.8.2 Configuring Physical Clocks(OSN 9800 U Series: U1CTU/S1CTU)................................................................. 163
2.8.2.2 Configuring Transport Clock Attributes of Boards........................................................................................... 165
2.8.2.4 Configuring Clock Source Attributes..................................................................................................................... 167
2.8.2.5 Configuring the Clock Source Protection............................................................................................................ 171
2.8.2.6 Querying Clock Synchronization Status............................................................................................................... 173
2.8.2.7 Querying Clock Tracing Status................................................................................................................................ 173
2.8.2.8 Configuring Clock Source Switching..................................................................................................................... 174
2.8.2.9 Configuring Board Attributes to Implement Synchronous Ethernet Transparent Transmission.......175
2.8.2.10 Parameters: Physical Clock(OSN 9800 U Series: U1CTU/S1CTU).............................................................176
2.8.2.10.6 Parameters: Clock Source Reversion Parameter..........................................................................................184
2.8.2.10.7 Parameters: Clock Source Switching............................................................................................................... 187
2.8.2.10.8 Parameters: Clock Synchronization Status.................................................................................................... 188
2.8.2.10.9 Parameters: Phase-Locked Source Output by External Clock................................................................ 190
2.9 Configuration Guide (U2000)........................................................................................................................................ 193
2.9.1 Configuring Physical Clocks (OSN 1800/8800/9800 Universal Platform Subrack/M Series Subrack/P
Series Subrack/(U Series Subrack: U2CTU/S2CTU/U4CTU)).......................................................................................193
2.9.1.2 Configuring the Frequency Source Mode............................................................................................................ 195
2.9.1.4 Configuring the Clock Center Subrack................................................................................................................. 198
2.9.1.6 Configuring Clock Source Attributes..................................................................................................................... 201
2.9.1.8 Viewing Clock Synchronization Status................................................................................................................. 208
2.9.1.9 Viewing the Clock Tracing Status........................................................................................................................... 209
2.9.1.10 Configuring Clock Source Switching................................................................................................................... 209
2.9.1.11 Configuring Board Attributes to Implement Synchronous Ethernet Transparent Transmission.... 211
2.9.1.12 Configuring the ST2/AST2/AST4 Board to Transparently Transmit Clock Signals.............................. 212
2.9.1.13 Parameters: Physical Clock (OSN 1800/8800/9800 Universal Platform Subrack/M Series
Subrack/P Series Subrack/U Series Subrack: U2CTU/S2CTU/U4CTU)..................................................................... 214
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2.9.1.13.2 Parameters: Clock Attribute Configuration................................................................................................... 214
2.9.1.13.9 Parameters: Manual Setting of Quality Level 0.......................................................................................... 232
2.9.1.13.10 Parameters: SSM Output Control.................................................................................................................. 234
2.9.1.13.11 Parameters: Clock ID Status............................................................................................................................ 234
2.9.1.13.12 Parameters: Clock Source Reversion Parameter....................................................................................... 235
2.9.1.13.13 Parameters: Clock Source Switching............................................................................................................. 238
2.9.1.13.14 Parameters: Clock Synchronization Status................................................................................................. 239
2.9.1.13.15 Parameters: Clock Source Switching Conditions.......................................................................................245
2.9.1.13.16 Parameters: Phase-Locked Source Output by External Clock.............................................................. 247
2.9.1.13.17 Parameters: Clock Signal Pass-through....................................................................................................... 252
2.9.2 Configuring Physical Clocks(OSN 9800 U Series: U1CTU/S1CTU)................................................................. 252
2.9.2.4 Configuring Clock Attributes................................................................................................................................... 257
2.9.2.6 Viewing Clock Synchronization Status................................................................................................................. 262
2.9.2.8 Configuring Clock Source Switching..................................................................................................................... 263
2.9.2.9 Configuring OTUs or Tributary Boards to Implement Synchronous Ethernet Transparent
Transmission................................................................................................................................................................................ 264
2.9.2.10 Parameters: Physical Clock (OSN 9800 U Series: U1CTU/S1CTU)........................................................... 265
2.9.2.10.6 Parameters: Clock Source Reversion Parameter..........................................................................................273
2.9.2.10.7 Parameters: Clock Source Switching............................................................................................................... 276
2.9.2.10.8 Parameters: Clock Synchronization Status.................................................................................................... 277
2.9.2.10.9 Parameters: Phase-Locked Source Output by External Clock................................................................ 279
3 IEEE 1588v2 (OTN & Packet)............................................................................................283

3.1 Introduction of IEEE 1588v2 (OTN & Packet)...........................................................................................................283
3.2 Principles............................................................................................................................................................................... 284
3.2.1 Building the Master-Slave Clock Hierarchy............................................................................................................ 284
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3.2.2 IEEE 1588v2 Clock Architecture..................................................................................................................................285

3.2.3 Clock Subnet and Clock Source ID in IEEE 1588v2..............................................................................................286
3.2.4 Time Source Port............................................................................................................................................................. 287
3.2.5 BMC Algorithm................................................................................................................................................................ 298
3.2.6 Delay Compensation...................................................................................................................................................... 301
3.2.7 IEEE 1588v2-Compliant Phase Synchronization................................................................................................... 303
3.2.8 IEEE 1588v2-Compliant Frequency Synchronization.......................................................................................... 305
3.3 Dependencies and Limitations....................................................................................................................................... 306
3.3.1 Feature Limitations.........................................................................................................................................................307
3.3.2 Affected Features............................................................................................................................................................ 316
3.3.3 Mutually Exclusive Features........................................................................................................................................ 318
3.4 Availability............................................................................................................................................................................ 319
3.4.1 License Support................................................................................................................................................................319
3.4.2 OSN 9800 Universal Platform Subrack Hardware and Version Support..................................................... 319
3.4.3 OSN 9800 P Series Hardware and Version Support............................................................................................ 320
3.4.4 OSN 9800 U Series Hardware and Version Support........................................................................................... 321
3.4.5 OSN 9800 M Series Hardware and Version Support.......................................................................................... 325
3.4.6 OSN 8800 Hardware and Version Support............................................................................................................ 329
3.4.8 OSN 1800 V Hardware and Version Support........................................................................................................ 333
3.4.9 OSN 1800 II Enhanced Hardware and Version Support.................................................................................... 336
3.4.10 OSN 1800 I&II Compact Hardware and Version Support............................................................................... 339
3.4.11 OSN 1800 V Pro Hardware and Version Support.............................................................................................. 341
3.4.12 OSN 1800 II Pro Hardware and Version Support.............................................................................................. 344
3.4.13 OSN 1800 II TP Hardware and Version Support................................................................................................ 347
3.4.14 OSN 1800 I Compact Hardware and Version Support.....................................................................................350
3.5 Specifications....................................................................................................................................................................... 352
3.6 Feature Updates.................................................................................................................................................................. 356
3.6.1 OSN 9800 Feature Updates......................................................................................................................................... 356
3.6.2 OSN 8800&6800 Feature Updates............................................................................................................................ 360
3.8.1 Configuring IEEE 1588v2 (OSN 1800/8800/9800Universal Platform Subrack/M Series/P Series/(U
Series: U2CTU/S2CTU/U4CTU/U5CTU))............................................................................................................................ 372
3.8.1.2 Enabling IEEE 1588v2................................................................................................................................................. 378
3.8.1.3 Setting the High-Precision Clock Mode............................................................................................................... 380
3.8.1.4 Configuring PTP NEs...................................................................................................................................................382
3.8.1.5 Configuring PTP Port Parameters.......................................................................................................................... 387
3.8.1.6 Configuring External Time Ports............................................................................................................................ 394
3.8.1.7 Querying Port Status.................................................................................................................................................. 398
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3.8.1.9 Configuring Ring Network Automatic Compensation.................................................................................... 399

3.8.1.10 Parameters: IEEE 1588v2 (OSN 1800/8800/9800Universal Platform Subrack/M Series/P Series/(U
3.8.1.10.3 Parameters: Clock Synchronization Attribute...............................................................................................403
3.8.1.10.4 Parameters: Clock Source at Port..................................................................................................................... 426
3.8.1.10.5 Parameters: PTP Clock Subnet.......................................................................................................................... 427
3.8.1.10.6 Parameters: BMC (Clock Subnet)..................................................................................................................... 428
3.8.1.10.7 Parameters: Basic Attribute................................................................................................................................ 432
3.8.1.10.8 Parameters: BMC (External Time Interface).................................................................................................433
3.8.1.10.9 Parameters: Cable Transmitting Distance..................................................................................................... 438
3.8.1.10.10 Parameters: 1588 Compensation Back Safe Password...........................................................................441
3.8.1.10.11 Parameters: MAC Address Configuration.................................................................................................... 444
3.8.2 Configuring IEEE 1588v2 (OSN 9800 U Series: U1CTU/S1CTU)..................................................................... 445
3.8.2.2 Enabling IEEE 1588v2................................................................................................................................................. 448
3.8.2.4 Configuring PTP Ports................................................................................................................................................ 453
3.8.2.8 Parameters: IEEE 1588v2 (OSN 9800 U Series: U1CTU/S1CTU)................................................................. 460
3.8.2.8.1 Parameters: Clock Synchronization Attribute................................................................................................. 460
3.8.2.8.2 Parameters: Clock Source at Port....................................................................................................................... 469
3.8.2.8.3 Parameters: Clock Subnet..................................................................................................................................... 469
3.8.2.8.4 Parameters: BMC (Clock Subnet)....................................................................................................................... 470
3.8.2.8.5 Parameters: Basic Attribute.................................................................................................................................. 475
3.8.2.8.6 Parameters: BMC (External Time Interface)................................................................................................... 477
3.8.2.8.7 Parameters: Cable Transmitting Distance........................................................................................................ 479
3.9.1 Configuring IEEE 1588v2 (OSN 1800/8800/9800 Universal Platform Subrack/M Series/P Series/ (U
Series: U2CTU/S2CTU/U4CTU))............................................................................................................................................ 481
3.9.1.2 Enabling IEEE 1588v2................................................................................................................................................. 486
3.9.1.6 Viewing Port Status.................................................................................................................................................... 506
3.9.1.8 Parameters: IEEE 1588v2 (OSN 1800/8800/9800 Universal Platform Subrack/M Series Subrack/P
Series Subrack/U Series Subrack: U2CTU/S2CTU/U4CTU).......................................................................................... 507
3.9.1.8.1 Parameters: Frequency Source Mode................................................................................................................ 508
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3.9.1.8.2 Parameters: Clock Port Link..................................................................................................................................508

3.9.1.8.5 Parameters: PTP Clock Subnet............................................................................................................................. 528
3.9.1.8.10 Parameters: 1588 Compensation Back Safe Password............................................................................. 543
3.9.1.8.11 Parameters: MAC Address Configuration...................................................................................................... 546
3.9.2 Configuring a IEEE 1588v2 Clock (OSN 9800 U Series: U1CTU/S1CTU)..................................................... 547
3.9.2.2 Enabling IEEE 1588v2................................................................................................................................................. 550
3.9.2.5 Configuring External Time Interfaces................................................................................................................... 560
3.9.2.6 Viewing the Clock Source Received at the Port................................................................................................ 562
3.9.2.8 Parameters: IEEE 1588v2 (OSN 9800 U Series: U1CTU/S1CTU)................................................................. 563
4 ITU-T G.8275.1/G.8273.2 (OTN & Packet) .................................................................... 585

4.1 Introduction of ITU-T G.8275.1/G.8273.2 (OTN & Packet).................................................................................. 585
4.2 Principles............................................................................................................................................................................... 587
4.2.1 Building the Master-Slave Clock Hierarchy............................................................................................................ 587
4.2.2 Time Source Port............................................................................................................................................................. 589
4.2.3 ITU-T G.8275.1 Time Synchronization Principles..................................................................................................601
4.2.4 ITU-T G.8275.1 Frequency Synchronization Principles....................................................................................... 603
4.2.5 Alternative BMC Algorithm......................................................................................................................................... 604
4.2.6 Delay Compensation...................................................................................................................................................... 607
4.3.1 Feature Limitations.........................................................................................................................................................610
4.3.2 Affected Features............................................................................................................................................................ 618
4.3.3 Mutually Exclusive Features........................................................................................................................................ 619
4.4 Availability............................................................................................................................................................................ 620
4.4.1 License Support................................................................................................................................................................620
4.4.2 OSN 9800 Universal Platform Subrack Hardware and Version Support..................................................... 620
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WDM OTN

4.4.4 OSN 9800 U Series Hardware and Version Support........................................................................................... 622
4.4.8 OSN 1800 V Hardware and Version Support........................................................................................................ 633
4.4.9 OSN 1800 II Enhanced Hardware and Version Support.................................................................................... 636
4.4.10 OSN 1800 I&II Compact Hardware and Version Support............................................................................... 639
4.4.11 OSN 1800 V Pro Hardware and Version Support.............................................................................................. 641
4.4.12 OSN 1800 II Pro Hardware and Version Support.............................................................................................. 644
4.4.13 OSN 1800 II TP Hardware and Version Support................................................................................................ 647
4.4.14 OSN 1800 I Compact Hardware and Version Support.....................................................................................650
4.5 Specifications....................................................................................................................................................................... 651
4.6 Feature Updates.................................................................................................................................................................. 656
4.6.2 OSN 8800&6800 Feature Updates............................................................................................................................ 660
4.8.1 Configuring ITU-T G.8275.1 (OSN 1800/8800/9800Universal Platform Subrack/M Series/P Series/(U
4.8.1.2 Enabling PTP................................................................................................................................................................. 673
4.8.1.3 Configuring the G.8275.1 Protocol........................................................................................................................ 676
4.8.1.4 Setting the High-Precision Clock Mode............................................................................................................... 677
4.8.1.9 Querying the Clock View.......................................................................................................................................... 692
4.8.1.10 Configuring Ring Network Automatic Compensation..................................................................................693
4.8.1.11 Parameters: ITU-T G.8275.1 (OSN 1800/8800/9800Universal Platform Subrack/M Series/P
4.8.1.11.1 Parameters: PTP Protocol.................................................................................................................................... 694
4.8.1.11.4 Parameters: Clock Synchronization Attribute...............................................................................................696
4.8.1.11.5 Parameters: Clock Source at Port..................................................................................................................... 710
4.8.1.11.6 Parameters: PTP Clock Subnet.......................................................................................................................... 711
4.8.1.11.7 Parameters: BMC (Clock Subnet)..................................................................................................................... 711
4.8.1.11.8 Parameters: Basic Attribute................................................................................................................................ 715
4.8.1.11.9 Parameters: BMC (External Time Interface).................................................................................................716
4.8.1.11.10 Parameters: Cable Transmitting Distance................................................................................................... 719
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WDM OTN
4.8.1.11.11 Parameters: MAC Address Configuration....................................................................................................722

4.8.1.11.12 Parameters: 1588 Compensation Back Safe Password...........................................................................723
4.8.2 Configuring ITU-T G.8275.1 (OSN 9800 U Series: U1CTU/S1CTU)................................................................726
4.8.2.2 Configuring the PTP Protocol.................................................................................................................................. 729
4.8.2.3 Enabling ITU-T G.8275.1............................................................................................................................................729
4.8.2.9 Parameters: ITU-T G.8275.1 (OSN 9800 U Series: U1CTU/S1CTU)............................................................ 739
4.8.2.9.1 Parameters: Global Configuration...................................................................................................................... 740
4.9.1 Configuring ITU-T G.8275.1 (OSN 1800/8800/9800 Universal Platform Subrack/M Series/P Series/(U
Series: U2CTU/S2CTU/U4CTU))............................................................................................................................................ 760
4.9.1.3 Enabling ITU-T G.8275.1............................................................................................................................................764
4.9.1.7 Viewing the Port Status............................................................................................................................................. 781
4.9.1.9 Parameters: ITU-T G.8275.1 (OSN 1800/8800/9800 Universal Platform Subrack/M Series Subrack/P
Series Subrack/U Series Subrack: U2CTU/S2CTU/U4CTU).......................................................................................... 783
4.9.1.9.1 Parameters: PTP Protocol...................................................................................................................................... 783
4.9.1.9.2 Parameters: Frequency Source Mode................................................................................................................ 783
4.9.1.9.3 Parameters: Clock Port Link..................................................................................................................................784
4.9.1.9.6 Parameters: PTP Clock Subnet............................................................................................................................. 797
4.9.1.9.10 Parameters: Cable Transmitting Distance..................................................................................................... 806
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WDM OTN
4.9.1.9.11 Parameters: MAC Address Configuration...................................................................................................... 809

4.9.1.9.12 Parameters: 1588 Compensation Back Safe Password............................................................................. 810
4.9.2 Configuring ITU-T G.8275.1(OSN 9800 U Series: U1CTU/S1CTU)................................................................. 812
4.9.2.3 Enabling ITU-T G.8275.1............................................................................................................................................816
4.9.2.7 Querying the Port Status.......................................................................................................................................... 825
4.9.2.9 Parameters: ITU-T G.8275.1 (OSN 9800 U Series: U1CTU/S1CTU)............................................................ 826
4.9.2.9.1 Parameters: Global Configuration...................................................................................................................... 827
5 High-Precision Clock Synchronization Solution...........................................................847

5.1 High-Precision Clock Synchronization Solution....................................................................................................... 847
5.2 Networking Schemes........................................................................................................................................................ 848
5.3 Typical Configuration Scenarios.................................................................................................................................... 851
5.3.1 Reference Clock Input.................................................................................................................................................... 851
5.3.1.1 Reference Clock Input on the M24 Subrack....................................................................................................... 852
5.3.1.2 Reference Clock Input on the M12 Subrack....................................................................................................... 852
5.3.1.3 Reference Clock Input on the P32/P32C Subrack............................................................................................. 853
5.3.1.4 Reference Clock Input on the U32E/U64E Enhanced Subrack..................................................................... 853
5.3.1.5 Reference Clock Input on the 1800 V Pro Subrack.......................................................................................... 854
5.3.2 Intra-Site Clock Synchronization................................................................................................................................ 854
5.3.3 Inter-Site Clock Synchronization................................................................................................................................ 856
5.3.4 Client-Side Clock Synchronization............................................................................................................................. 857
5.3.5 OLA Site Clock Schemes............................................................................................................................................... 858
5.4 Ports Supporting High-Precision Clock Synchronization.......................................................................................859
5.4.1 Dedicated PTP Synchronization Port (HP Optical Port).................................................................................... 859
5.4.2 High-Precision OSC Port (1506 nm/1514 nm)..................................................................................................... 860
5.4.3 Ethernet Service Port..................................................................................................................................................... 860
5.5 Specifications....................................................................................................................................................................... 861
5.6 Availability............................................................................................................................................................................ 863
5.6.1 License Support................................................................................................................................................................863
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WDM OTN
5.6.3 OSN 9800 U32E/U64E Subrack Hardware and Version Support....................................................................864

5.6.5 OSN 1800 V Pro Hardware and Version Support................................................................................................ 865
5.6.6 OSN 1800 II Pro Hardware and Version Support.................................................................................................866
5.6.7 OSN 1800 II TP Hardware and Version Support.................................................................................................. 867
5.6.8 OSN 1800 I Compact Hardware and Version Support....................................................................................... 867
5.8 Feature Updates.................................................................................................................................................................. 869
5.9 Configuration Guide.......................................................................................................................................................... 870
5.9.1 Setting the High-Precision Clock Mode...................................................................................................................870
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WDM OTN
Clock Synchronization Feature Guide 1 Overview of Clock Synchronization
1 Overview of Clock Synchronization
1.1 Why Does the WDM/OTN Network Need Clock

Synchronization?
To provide a synchronous clock source for mobile base stations, the entire
WDM/OTN transport network must support clock synchronization.
Mobile Backhaul Network Requires the WDM/OTN Network to Implement

Clock Synchronization
In a mobile backhaul network, clock synchronization must be strictly implemented
between base stations. Currently, there are multiple clock synchronization
solutions in the industry, such as GPS and IEEE 1588v2.
● Traditional GPS clock synchronization:
– High cost: Each base station must be configured with a GPS system.
– High failure rate: Each base station is configured with only one satellite
card (receiving GPS signals), which is not protected.
– Poor maintainability: If the GPS fails, you must replace the hardware
onsite, and remote maintenance cannot be performed.
● IEEE 1588v2 clock synchronization:
– Low cost: Only two GPS devices need to be configured to implement
clock synchronization on the entire network. The GPS system is not
required for each base station.
– High reliability: End-to-end clock protection can be configured.
– High maintainability: There is no construction restriction, deployment is
simple, and unified management is implemented using the NMS.
However, IEEE 1588v2 requires that all devices on a network support the IEEE
1588v2 protocol. Otherwise, the clock performance may not meet the clock
precision requirements of a wireless network if only simple transparent
transmission of time is implemented.
The WDM/OTN network itself does not need to implement clock synchronization.
To provide clock signals for a PTN/SDH network, the WDM/OTN network needs to
Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. 1

WDM OTN
obtain the active and standby clock sources from the building integrated timing
supply (BITS) system to implement clock synchronization on the entire network.
The PTN/SDH network needs only to use the clock source of the WDM/OTN
network to implement clock synchronization, and then provides the clock source
for base stations to achieve synchronization.
SDH Modernization Requires the WDM/OTN Network to Implement Clock

Synchronization
With the advent of 4K video, LTE/LTE-A, and cloud era, the demand for high
bandwidth is strong. The network bandwidth of existing SDH devices is low and
cannot satisfy the development requirements of new services. In addition, SDH
devices are old and have high power consumption and OPEX. Therefore, carriers
are in urgent need of reconstructing networks to improve customer experience.
Huawei's MS-OTN solution inherits all SDH capabilities and implements unified
transmission of TDM/OTN/PKT services. It also features ultra-high bandwidth,
simplified O&M, and future-oriented smooth evolution. It is the best solution for
SDH modernization.
The SDH network is a synchronous network. Therefore, when a WDM/OTN
network is used to replace the SDH network, SDH services are directly processed
as a part of the SDH network. Therefore, the WDM/OTN network must support
clock synchronization.
Architecture of a WDM/OTN Clock Synchronous Network

A complete clock synchronous network consists of clock sources, transmission
network, and base stations. Huawei WDM/OTN devices are located in the
transmission network.
● Clock source: Generally, one master and one slave BITS clock source devices
are configured on a clock synchronous network to implement backup.
● Transmission network: Common topologies of a transmission network are
ring, tree, chain, and mesh. Ring topologies are recommended for
transmission networks because a synchronous network requires network
protection. At the edge of the network, chain topologies can be used.
● Base station: A radio transceiver station transmits information between a
Node B and a mobile terminal through a mobile communication center.

WDM OTN
Figure 1-1 Architecture of the clock synchronous network
1.2 Clock Synchronization Requirements of Service

Networks
Clock synchronization includes both frequency synchronization and phase
synchronization. Frequency synchronization is the basis of phase synchronization.
That is, the frequencies of devices with synchronized phases are also synchronized.
● Frequency synchronization: Frequency synchronization means that different
signals have the same number of pulses within the same time interval, so that
all devices on the communication network run at the same rate.
● Phase synchronization: Phase synchronization means that not only signals
have the same number of pulses within the same time interval, but also the
start time and end time of each pulse are the same.

WDM OTN
Figure 1-2 Frequency synchronization and phase synchronization
With the development of wireless networks such as LTE TDD and LTE FDD, service
networks, especially radio access networks (RANs), have strict requirements on
Table 1-1 Clock synchronization requirements of mobile communication networks

Wireless Required Required Recommended Synchronization
Access Frequency Phase Mode of the Bearer Network
Mode Synchroniza Synchroni
tion zation
Precision Precision
GSM 0.05 ppm Phase Physical-layer clocks

synchroniz
ation is
not
required.
WCDMA 0.05 ppm Phase Physical-layer clocks

synchroniz
ation is
not
required.
TD- 0.05 ppm ±1.5 µs Physical-layer clocks + IEEE 1588v2/

SCDMA ITU-T G.8275.1/G.8273.2
CDMA200 0.05 ppm ±3 µs Physical-layer clocks + IEEE 1588v2/

0 ITU-T G.8275.1/G.8273.2
WiMax 0.05 ppm Phase Physical-layer clocks

FDD synchroniz
ation is
not
required.

WDM OTN
Wireless Required Required Recommended Synchronization

Access Frequency Phase Mode of the Bearer Network
Mode Synchroniza Synchroni
tion zation
Precision Precision
WiMax 0.011 ppm/ ±1 µs Physical-layer clocks + IEEE 1588v2/

TDD 3.5G, 7 ITU-T G.8275.1/G.8273.2
carrier wave
LTE FDD 0.05 ppm Phase Physical-layer clocks

synchroniz
ation is
not
required.
LTE TDD 0.05 ppm ±1.5 µs Physical-layer clocks + IEEE 1588v2/

ITU-T G.8275.1/G.8273.2
In addition to the communication network, billing systems and network

management systems also require phase synchronization.
Table 1-2 Phase synchronization requirements of other common systems
System Required Time Recommended

Synchronization Synchronization Mode
Precision of the Bearer Network
Billing system 500 ms IEEE 1588v2/ITU-T G.

8275.1/G.8273.2
Communication network 500 ms IEEE 1588v2/ITU-T G.

management system 8275.1/G.8273.2
Signaling system No.7 1 ms IEEE 1588v2/ITU-T G.

8275.1/G.8273.2
Positioning system 1 µs (equivalent to a IEEE 1588v2/ITU-T G.

positioning precision of 8275.1/G.8273.2
300 m)
1.3 Frequency Synchronization Solutions

This section describes the implementation modes and typical application scenarios
of frequency synchronization.
Solution Comparison
WDM/OTN devices support the following frequency synchronization solutions. You
are advised to use the same solution on an entire WDM/OTN network.

WDM OTN
● (Recommended) Physical-layer clock synchronization:

– The equipment directly recovers clock frequencies from physical signals
with high timeliness. The equipment hardware, however, must support
clock extraction. Therefore, each node must support the physical-layer
clock to implement frequency synchronization on the entire network.
– The performance is stable and reliable, and is not subject to network load
changes.
– The technology is mature, easy to implement, and easy to maintain.
● PTP frequency synchronization:
– PTP (IEEE 1588v2 or ITU-T G.8275.1) is used to implement frequency
synchronization based on the timestamps in Sync messages. It is a
frequency estimation and correction mode and has a lower real-time
synchronization precision than the physical-layer clock synchronization
mode.
– In addition, the synchronization is implemented hop by hop, which
requires that each node in the synchronization network must support
IEEE 1588v2/ITU-T G.8275.1/G.8273.2.
Frequency Source Input/Output

The WDM/OTN devices are interconnected with the BITS or PTN devices in the
following ways to implement frequency source input/output:
● (Recommended) 2M external clock port: When the frequency source needs to
be obtained from the BITS or the clocks of the master and slave subracks
need to be cascaded, the frequency source can be obtained through the 2M
external clock port.
● Ethernet port: When the WDM/OTN devices are interconnected with PTN
devices, SDH devices, or routers, you are advised to obtain the frequency
source from the Ethernet port.
Internal Frequency Synchronization of the WDM/OTN Network

● (Recommended) OSC mode: The optical supervisory channel (OSC) board is
used to transmit frequency information.
● ESC mode: The OTU board, tributary/line board, or packet service board is
used to transmit frequency information.
Typical Scenario
The following figure uses physical clocks as an example to describe the typical
scenario of frequency synchronization. In this scenario, all devices on the
WDM/OTN network must support physical clocks.

WDM OTN
Figure 1-3 Networking of a typical scenario
NOTE
The protection frequency tracing path shown in the preceding figure is an example of the
path for transmitting clock signals after the clock source is switched to the slave BITS
because the master BITS is faulty. The active and standby clock sources cannot be
concurrently transmitted on the network.
1.4 Phase Synchronization Solutions

This section describes the implementation methods and typical application
scenarios of phase synchronization.
Solution Comparison
WDM devices support the following phase synchronization solutions. You are
advised to use the same solution on an entire WDM/OTN network.
Frequency synchronization is the basis of phase synchronization. That is, the
frequencies of devices with synchronized phases must also be synchronized.
Table 1-3 Phase synchronization solutions

Solution Description
(Recommended) Physical The synchronization precision is high, and the

clock frequency bandwidth usage is low.
synchronization+IEEE 1588v2
phase synchronization
IEEE 1588v2 frequency and This solution features easy deployment and
phase synchronization simple O&M. Compared with physical clock
frequency synchronization+IEEE 1588v2 phase
synchronization, this solution provides lower
synchronization precision but requires higher
bandwidth usage.

WDM OTN
Solution Description
Physical clock frequency This solution applies only to the

synchronization + ITU-T G. telecommunication field. Compared with
8275.1 phase physical clock frequency synchronization+IEEE
synchronization 1588v2 phase synchronization, this solution uses
the BMCA algorithm to trace the Grand Master
clock on the shortest path, which ensures higher
synchronization precision and prevents reverse
tracing.
ITU-T G.8275.1 for frequency The BMCA algorithm is used to prevent reverse
synchronization and phase tracing.
synchronization
Phase Source Input/Output

The WDM/OTN devices are interconnected with the BITS or PTN devices in the
following ways to implement phase source input/output:
● (Recommended) 1PPS+TOD external time port: When the phase source needs
to be obtained from the BITS or the master and slave time subracks need to
be cascaded, the 1PPS+TOD external time port can be used to obtain the
phase source.
● Ethernet port: When the WDM/OTN devices are interconnected with PTN
devices, SDH devices, or routers, you are advised to obtain the phase source
from the Ethernet port.
Internal Phase Synchronization of the WDM/OTN Network

● (Recommended) OSC mode: The OSC board is used to transmit phase
information.
● ESC mode: The OTU board, tributary/line board, or packet service board is
used to transmit phase information.
NOTE
● ESC two-fiber bidirectional phase synchronization is easily affected by factors such

as protection switching and board delay difference. If the east-west delay offset is
too large, phase indicators change and deteriorate. As a result, frequent network
switching occurs and maintenance cannot be performed.
● In actual configuration, it is recommended that you configure frequency
synchronization and phase synchronization on the same port of a board. That is,
set OSC mode for both frequency synchronization and phase synchronization to
facilitate maintenance.
Typical Scenario
The following figure uses physical-layer clocks + IEEE 1588v2 as an example to
describe a typical scenario of phase synchronization. In this scenario, all devices on
the WDM/OTN network must support IEEE 1588v2.

WDM OTN
Figure 1-4 Networking of a typical scenario
NOTE
The phase tracing paths shown in the figure are used for reference only. On a practical
network, each NE determines the phase tracing paths based on algorithms.
1.5 E2E WDM/OTN Clock Solution

The following figure illustrates how Huawei WDM/OTN devices achieve end-to-
end (E2E) clock synchronization from the backbone layer to the access layer.
Figure 1-5 E2E clock networking diagram

WDM OTN
NOTE

WDM OTN
Clock Synchronization Feature Guide 2 Physical Clocks (OTN & Packet & SDH)
2 Physical Clocks (OTN & Packet & SDH)
2.1 Introduction of Physical Clocks (OTN, Packet, and

SDH)
WDM/OTN devices support physical-layer clocks, which can be used to implement
frequency synchronization. To implement phase synchronization, physical-layer
clocks must work with other features.
Description
In physical clock synchronization mode, WDM devices restore frequency signals
from physical signals such as Ethernet links, packet links, and SDH links to achieve
frequency synchronization between upstream and downstream devices. Physical
clocks require the device hardware to support clock extraction. Therefore, to
achieve network-wide frequency synchronization, each node must support
physical-layer clocks.
Application Scenario
Physical clocks can be used in the following scenarios:
● Physical-layer clock (OTN tributary): Supports synchronous Ethernet
processing and synchronous Ethernet transparent transmission to implement
frequency synchronization.
– Synchronous Ethernet processing: The system clock performs frequency
synchronization for upstream NEs one at a time. Synchronous Ethernet
processing can be used with IEEE 1588v2 to implement phase
synchronization.
– Synchronous Ethernet transparent transmission: It only transmits the
clock to the destination node to guarantee clock quality. This achieves
only internal free-run on an NE but no frequency synchronization with
the upstream NE. Synchronous Ethernet transparent transmission cannot
work with IEEE 1588v2 to implement phase synchronization.
● Physical clock (packet): On a packet network, packet boards can be used to
implement frequency synchronization.

WDM OTN
● Physical clock (SDH): In an SDH modernization scenario where the SDH

network must be synchronized, SDH boards can be used to implement
frequency synchronization for base stations.
Figure 2-1 Physical clock scenarios
NOTE
2.2 Principles
At the physical layer, clock reference information is transported to each control
point with high accuracy based on the master-slave relationship between nodes
and the clock synchronization mechanism.
2.2.1 Building the Master-Slave Clock Hierarchy

All NEs trace the same primary reference clock (PRC) through a specific clock
synchronization path, thereby implementing network-wide synchronization.
Clock sources can be traced correctly after physical clock synchronization is
implemented in master/slave synchronization mode. In this synchronization mode,
each slave clock usually needs to work in three modes, and clock source priorities
must be specified manually to ensure that clocks are traced level by level. In

WDM OTN
addition, clock loops can be prevented by expanding the synchronization status

message (SSM) protocol, therefore ensuring synchronization of physical clocks on
the entire network.
Master/Slave Synchronization Mode

The physical clock synchronization mode supported by the WDM/OTN equipment
is master/slave synchronization. In master/slave synchronization mode, clocks of
various levels are used. Clocks of each level are synchronized with clocks at higher
levels. On a network, clocks of the highest level are referred to as PRCs.
The main advantages of the master/slave synchronization mode are that the
network is stable, the networking is flexible, tree and star networking topologies
are applicable, the control is simple, and the network anti-jitter capability is good.
The main disadvantage is that this mode is sensitive to faults of PRCs and
transmission links. Once a PRC is faulty, the entire network is adversely affected.
Therefore, a PRC must have multiple backups to enhance reliability.
The system clock of the WDM/OTN equipment supports three working modes:
tracing mode, holdover mode, and free-run mode.
Working Mode of the Slave Clock

In master/slave synchronization mode, the slave clock can work in one of the
following modes:
● Tracing mode
It is a normal working mode, indicating that the local clock is synchronized
with the PRC. The tracing mode is the common working mode of transmission
network NEs.
● Holdover mode
After all external timing reference signals are lost, the slave clock node
changes to the holdover mode. The slave clock node uses the latest frequency
signals that are saved before the clock loss as the clock reference.
● Free-run mode
The slave clock node of an NE works in free-run mode when the slave clock
node loses all external timing reference signals and memories or runs in the
holdover mode for a long time.
2.2.2 Clock Protection

The WDM/OTN equipment supports clock source protection based on priorities,
synchronization status message (SSM) protection, and extended SSM protection.
Physical clock synchronization supports selecting and switching a clock source
under three SSM protocol modes:
● Non-SSM protocol
– When the SSM protocol is disabled, clock signals do not contain clock
quality information. Clocks are selected based on the specified clock
source priorities. In this mode, clock loops may occur.
– This mode is used on a non-ring network with multiple clock sources. The
clock source is selected according to the clock source priority list.

WDM OTN
● Standard SSM protocol

– When the standard SSM protocol is enabled, clock quality levels are used
to prevent clock loops.
– This mode is used on a non-ring network with multiple clock sources. The
clock signal carries quality information. It is used when the WDM/OTN
device interconnects with a third-party device.
● Extended SSM protocol
– When the extended SSM protocol is enabled, clock source IDs are
introduced to prevent clock loops.
– This protocol is applicable only to a ring network. It is a Huawei
proprietary protocol and cannot be used when the WDM/OTN device
interconnects with a third-party device. If the extended SSM protocol is
enabled on an NE, the standard SSM protocol can be configured on the
downstream NEs; however, if the standard SSM protocol is enabled on an
NE, the extended SSM protocol cannot be configured on the downstream
NEs. It is recommended that the extended SSM protocol be enabled on
ring networks.
NOTICE
It is recommended that two clock sources in different directions be configured for

a single site to implement protection. If a site is configured with three or more
clock sources, strictly check the clock tracing relationship during clock source
switching to prevent clock loops.
2.2.2.1 Stop SSM Protocol and Start Standard SSM Protocol

The WDM/OTN equipment supports clock source protection based on priorities,
stop SSM protocol, and start standard SSM protocol.
Stop SSM Protocol

A clock priority table is the basis of clock source selection and switching when the
SSM protocol is disabled. Each clock source listed in Figure 2-2 is assigned with a
unique priority. NEs select a clock source with the highest priority from the priority
table as their clock source.

WDM OTN
Figure 2-2 Clock source priorities when the SSM protocol is disabled
Start Standard SSM Protocol

Priorities of clocks traced by the NEs on a common WDM/OTN network can be
specified manually to provide clock synchronization and protection. However, in
some special OTN networks, clock loops may be generated if only clock priorities
are specified. To prevent clock loops, users need to enable the standard SSM
protocol.
Physical clocks can contain SSM bytes to determine the quality level of physical
clocks. Clock quality is identified by bit 5 to bit 8 in an SSM byte. A smaller value
represents a higher clock quality. Table 2-1 lists the meanings of the clock quality
bits in an SSM byte.
As the standard SSM protocol contains clock quality information, an NE can
automatically select a clock with the highest quality and priority after the
standard SSM protocol is enabled. The quality level of a clock source can be
specified manually according to Table 2-1. If the quality level of the clock source
is set to 0xff for an NE, clock quality is extracted automatically. With the clock
quality is set to 0xff, the NE selects a clock source among the available clock
sources based on the quality reported originally.
After the standard SSM protocol is enabled for an NE, automatic clock switching is
performed based on the following principles:
● The NE takes precedence to select a clock source with the highest quality
from the specified clock priority table.
● If there are multiple clock sources with the highest quality, then the NE
selects the clock source with the highest priority from them.
● The NE broadcasts the quality level of the selected clock source to the
downstream NEs using S1 bytes. Meanwhile, the NE informs the upstream
NEs of its clock quality using other S1 bytes along the reverse synchronization
path, telling the upstream NEs not to synchronize to its clock.

WDM OTN
Table 2-1 Meanings of bit values in an SSM message
SSM Code Quality Level
0x00 Do Not Use For Synchronization
0x02 G.811 Reference Clock
0x04 G.812 Transit Clock
0x08 G.812 Local Clock
0x0b Synchronous equipment timing source (SETS)
0x0f The clock signals are unavailable
0xff Automatic Extraction
2.2.2.2 Start Extended SSM Protocol and Clock Source ID

The WDM/OTN devices support the extended SSM protocol, so that clock source
ID can be used to prevent clock loops and implement clock source protection
based on priorities.
Extended SSM Protocol Enabled

Huawei has developed the extended SSM protocol by adding clock source IDs to
the standard SSM protocol. By using the extended SSM protocol, users can assign
any clock source an ID. The clock source ID of a synchronization source is
transmitted together with SSM bytes. The clock IDs and SSM bytes together
determine automatic clock switching. A clock source ID identifies whether the
clock is from the local NE. If the clock is from the local NE, the clock source is
considered invalid to prevent clock loops. The extended SSM protocol is mainly
used for interconnection of Huawei transmission devices.
After the extended SSM protocol is enabled for an NE, automatic clock switching
is performed based on the following principles:
● The NE takes precedence to select a clock source with the highest quality
from the specified clock priority table.
● If the ID of a clock source indicates that the clock source is synchronized to
the NE's clock, then the NE will not select this clock source to trace.
● If there are multiple clock sources with the highest quality, then the NE
selects the clock source with the highest priority from them.
● The NE broadcasts the quality and ID of the selected clock source to the
downstream NEs using S1 bytes. Meanwhile, the NE informs the upstream
NEs of its clock quality using other S1 bytes along the reverse synchronization
path, telling the upstream NEs not to synchronize to its clock.
Clock Source ID
For simple networks such as chain networks, only the clock priority table needs to
be configured for clock protection. Clock source protection is not required. For

WDM OTN
complex networks including ring networks and their derived networks such as
tangent and intersecting ring networks, the extended SSM protocol must be
enabled for clock source protection. To prevent clock loops, the clock source ID
must be configured.
● A clock source ID uses bit 1 to bit 4 of an SSM byte, and the value ranges
from 0x0 to 0xf. Basically, a clock source ID is used to distinguish the clock
information between local and other nodes to prevent a node from tracing
the clock signal that is locally transmitted and comes from the negative
direction. Hence, a timing loop is prevented.
● A value of 0 indicates that a clock source ID is invalid. Hence, the default
value of a clock source ID is 0 when an ID is not set for a clock source. When
enabling the extended SSM protocol, an NE does not select the clock source
whose ID is 0 as the current clock source.
● A clock source ID is a tag set for a reference timing source. The clock sources
at the same quality level that carry different IDs mean different timing signals
and are not different in priority levels and other aspects.
Set the clock source ID according to the following principles:
● Allocate a clock source ID to each external BITS device.
● Allocate a clock source ID to the internal clock source of each node that has
an external BITS device.
● Allocate a clock source ID to the internal clock source of each node that
enters into another ring network from one chain or ring network.
● Allocate a clock source ID to the line clock source of the node that enters into
another ring network from one chain or ring network when the line clock
source exists.
As shown in Figure 2-3, the PTN device obtains clock signals from the connected
BITS device and sends the clock signals to the connected product on the OTN
network over Ethernet services. Then, the product transmits the clock signals to
other devices on the network to implement frequency synchronization for the
entire network. All the NEs on the WDM/OTN network enable the extended SSM
protocol for clock source protection.
Figure 2-3 Clock source ID

WDM OTN
2.2.2.3 Preventing Physical Clock Loops

After a physical clock loop (clock tracing loop) occurs, the frequency offset of the
physical clock is excessively large. As a result, bit slips and bit errors may occur
during service transmission. Additionally, a large frequency offset may lead to
inaccurate PTP time synchronization and affect services of TDD base stations.
Therefore, the bearer network should be properly planned to prevent physical
clock loops.
Basic Concepts
The following concepts are used in this document:
● Physical clock loop: indicates the logical clock loop state where an NE traces
an external clock source but finally traces the NE itself. If configurations are
incorrect, it may occur in various scenarios such as physical ring, chain, and
mesh networking. Mutual clock tracing between two NEs is the simplest clock
loop.
● Bidirectional clock path: indicates the interconnection link between two NEs
that is configured as the clock source tracing path by both NEs. For example,
NE A and NE B are interconnected through link K. On link K, clock signals
may be transmitted from NE A to NE B or from NE B to NE A depending on
the network status.
● Unidirectional clock path: indicates the interconnection link between two NEs
that is configured as the clock source tracing path by only one NE.
Typical Scenario
Table 2-2 lists the protection capabilities and precautions when different clock
protocols are used on typical ring and chain networks. A mesh network can be
considered as multi-level logical ring networks. The scenario where only two NEs
are interconnected can be considered as a special case of a chain network.
Table 2-2 Typical clock networking scenarios
Clock Networking Capabilities Description

Protocol
Ring Chain
Standard ● Supports ring protection ● The first and last NEs can The standard SSM
SSM for clock paths. be connected to the protocol has good
protocol ● Supports master and master and slave BITS compatibility and is
slave BITS protection. devices separately for recommended when
protection. there is no special
For details, see Standard requirement.
SSM Protocol. ● Link fault protection is
not supported.
For details, see Standard
SSM Protocol.

WDM OTN
Clock Networking Capabilities Description

Protocol
Ring Chain
Extended ● Supports ring protection ● The first and last NEs can The extended SSM
SSM for clock paths. be connected to the protocol is complex
protocol ● Supports master and master and slave BITS to configure.
slave BITS protection. devices separately for Therefore, it is used
protection. only when necessary.
● Supports protection
against multi-point path ● Supports link fault
faults. protection.
For details, see Extended For details, see Extended
SSM Protocol. SSM Protocol.
Non-SSM ● Ring protection for clock ● Only supports protection Non-SSM protocol
protocol paths is not supported. for multiple clock links in applies only to
● Master and slave BITS one direction. simple networking.
devices cannot be ● Master and slave BITS
configured for two NEs devices cannot be
for protection. configured for two NEs
For details, see Non-SSM for protection.
Protocol. For details, see Non-SSM
Protocol.
2.2.2.3.1 Preventing Clock Loops on a Ring Network

On a physical ring network, clock source priorities should be properly configured
at key positions to prevent clock loops.
Standard SSM Protocol

When a ring network uses the standard SSM protocol, it supports ring protection
for clock paths and master and slave BITS protection. The basic configuration
principles are as follows:
● Only one link between two NEs can be configured as the clock source tracing
path. You are advised to configure a higher clock source priority for the link
with a shorter path to the reference clock source.
● The standard SSM protocol allows two NEs to connect to the master and
slave BITS devices separately for protection. For the NEs connected to external
active and standby clock sources, a bidirectional clock path must be
configured between the NEs to implement master and slave BITS protection.
● On the ring network, clock loop prevention points and links must be properly
planned. If an NE is connected to a BITS device, do not add its link for
connecting to the downstream NE to the clock source priority table.
● Bidirectional protection can be configured for all links except clock loop
prevention links on a ring network.
● If multiple links exist between two NEs, do not configure multiple paths on
one NE to trace the alternative clock source or configure the two NEs to use
different interconnection links to trace the alternative clock source.

WDM OTN
If clock links are correctly selected and clock source priorities are correctly
configured, services can be protected against a BITS fault or a link fault on the
ring network, as shown in Figure 2-4.
Figure 2-4 Example of correct ring network configuration (standard SSM protocol)
If the clock loop prevention links are not correctly configured on the ring network,
a loop may occur, as shown in Figure 2-5.

WDM OTN
Figure 2-5 Example of incorrect ring network configuration (standard SSM

protocol)
Extended SSM Protocol

When a ring network uses the extended SSM protocol, it supports the ring
protection for clock paths, master and slave BITS protection, and path protection
for multi-ring networking. In this case, each NE needs to allocate a clock source ID
to its internal clock source. Therefore, the supported network scale is limited. The
basic configuration principles are as follows:
● Set clock source IDs according to the following requirements. The extended
SSM protocol can prevent an NE from tracing its own internal clock.
– Allocate clock source IDs to all BITS clock sources. Clock source IDs are
unique to the extended SSM protocol. BITS clocks do not have any clock
source IDs, which need to be set on transmission NEs.
– At all the nodes that connect to BITS clock sources, allocate clock source
IDs to their internal clock sources.
– At all the nodes that receive clock signals from an upper-layer ring
network, allocate clock source IDs to their internal clock sources and the
line clock sources that are transmitted to the ring network.
● You are advised to configure only one bidirectional clock path between two
NEs on a ring network. If multiple clock paths are configured between two
NEs, configure clock source IDs for both NEs.
● Between the upper-layer ring network and the lower-layer ring network, only
unidirectional clock paths can be configured to prevent upstream NEs from
tracing the clocks of downstream NEs.

WDM OTN
Figure 2-6 Example of correct ring network configuration (extended SSM

protocol)
Non-SSM Protocol
When a ring network uses a non-SSM protocol, it does not support ring protection
for clock paths or master and slave BITS protection. In this case, you need to
divide the physical ring into two logical clock links. The basic configuration
principles are as follows:
● Only unidirectional clock paths can be configured. You can configure one or
two clock links on the ring.
● Two NEs cannot mutually use the peer NE as the alternative clock source.
● If multiple links exist between two NEs, you can plan multiple unidirectional
clock paths from the upstream NE to the downstream NE. The clock source
priority table can be configured to implement protection switching.
Figure 2-7 Example of correct ring network configuration (non-SSM protocol)

WDM OTN
2.2.2.3.2 Preventing Clock Loops on a Chain Network
Standard SSM Protocol

When a network uses the standard SSM protocol, the first and last NEs can
connect to the master and slave BITS devices separately for protection. The basic
configuration principles are as follows:
● Only one link between two NEs can be configured as the clock source tracing
path. The link can be configured as a bidirectional clock path. That is, add the
link to the clock source priority table in both directions.
● If multiple links exist between two NEs, do not configure multiple paths on
one NE to trace the alternative clock source or configure the two NEs to use
different interconnection links to trace the alternative clock source.
NOTE
If BITS protection is not required, multiple unidirectional clock paths can be configured
between two NEs. In this case, the SSM protocol does not take effect. For details, see
the scenario where a non-SSM protocol is used.
Configure only one bidirectional clock path between NEs, as shown in Figure 2-8.
The standard SSM protocol supports clock source protection switching based on
the clock source quality information and clock source priority table.
Figure 2-8 Example of correct chain network configuration (standard SSM

protocol)
If multiple clock paths are incorrectly configured between NEs, a clock loop may
occur when all external clock sources fail, as shown in Figure 2-9.

WDM OTN
Figure 2-9 Example of incorrect chain network configuration (standard SSM

protocol, BITS clock sources)
When the standard SSM protocol is used and no external BITS devices are
connected, multiple bidirectional clock paths cannot be configured between two
NEs either, and unidirectional clock paths with opposite tracing directions cannot
be configured on multiple links, as shown in Figure 2-13.

WDM OTN
Figure 2-10 Example of incorrect chain network configuration (standard SSM

protocol, internal clock sources)
Extended SSM Protocol

If clock source IDs are correctly configured, one or more bidirectional clock paths
can be configured between two NEs. The extended SSM protocol prevents an NE
from tracing its own clock by identifying clock source IDs. In this case, each NE
needs to allocate a clock source ID to its internal clock source. Therefore, the
supported network scale is limited.

WDM OTN
Figure 2-11 Example of correct chain network configuration (extended SSM

protocol)
Non-SSM Protocol
When a network uses a non-SSM protocol, only unidirectional clock link protection
is supported, and master and slave BITS protection cannot be configured on two
NEs. The basic configuration principles are as follows:
● Only unidirectional clock paths can be configured between two NEs, and the
two NEs cannot mutually use the peer NE as the alternative clock source.
That is, only the downstream NE can trace the clock of the upstream NE, and
the reverse path is not allowed.
● If multiple links exist between two NEs, you can plan multiple unidirectional
clock paths.
Configure only unidirectional clock paths between NEs, as shown in Figure 2-12.

WDM OTN
Figure 2-12 Example of correct chain network configuration (non-SSM protocol)
If a bidirectional clock path is incorrectly configured between NEs, a clock loop

may occur, as shown in Figure 2-13.

WDM OTN
Figure 2-13 Example of incorrect chain network configuration (non-SSM protocol)
2.2.3 Clock Source Port

Clock source information can be received through external clock ports and service
clock ports.
A clock source is a signal source containing reference timing information. Each NE

synchronizes its local clock phase to the reference timing using its phase-locked
loop (PLL), implementing clock synchronization.
The WDM/OTN equipment supports the following types of clock sources:

● External clock source: timing information that is extracted from 2 Mbit/s or 2
MHz signals received at an external clock port.
● OSC clock source: clock information that is extracted from OSC signal streams.
● Line clock source: a clock source that is extracted from line-side service signals
by boards that support physical clocks on the OTN network. The line clock
source uses electrical-layer boards to transmit clock information. In specific
scenarios, it is also called the ESC clock source.
● E1 tributary clock source: timing information that is extracted from E1 signal
streams.
● Synchronous Ethernet clock source: clock information that is extracted from
Ethernet signal streams.
● Clock synchronization GE optical port (Dedicated PTP Synchronization Port):
clock information that is extracted from Ethernet signal streams.

WDM OTN
● Internal clock source: a clock that is generated from free-run oscillation of the
built-in clock of an NE. The internal clock source has the lowest priority
among all clock sources.
Input and Output Ports
Table 2-3 Clock source port types

Clock Supported Port Mode Function
Source Port Format
Type
External 2.048 MHz or RJ45 or SMB ● Receives clock signals

clock port 2.048 Mbit/s from the BITS or other
signals devices that have the
compliant same port.
with ITU-T G. ● Cascades with other
703 in a devices of the same
synchronous type at the same site.
system
● Connects to lower-
layer PTN/MSTP
devices.
OSC clock OSC OSC optical port Supports clock

source dedicated synchronization with
port interconnected WDM
devices.
Line clock OTUk port, OTUk optical port, Supports clock

source STM-N port STM-N optical port/ synchronization with
electrical port, SDH interconnected OTN/SDH
virtual port devices.
Ethernet GE/10GE/ Ethernet optical port Connects to lower-layer

service port 25GE/50GE/ PTN/MSTP devices
100GE/200GE without restrictions on
Ethernet equipment room sharing
services and site sharing.
Clock Ethernet GE optical port Used for clock

synchroniza frame synchronization between
tion GE NEs or clock cascading
optical port between master and
slave subracks. Only clock
synchronization and time
synchronization are
supported. Ethernet
services cannot be
transmitted.

WDM OTN
External Clock Ports
Table 2-4 External clock and time ports

Product Type Board Name External Clock External Time
Port Port
OSN 9800 STG CLK TOD

universal platform
subrack
OSN 8800
universal platform
subrack
OSN 6800
OSN 9800 U EFI CLK1, CLK2 TOD1, TOD2

series/M24/P32/
P32C
OSN 9800 M12 AUX CLK&TOD CLK&TOD
OSN 9800 M05 CTU CLK&TOD CLK&TOD
OSN 8800 STI CLK1, CLK2 TOD1, TOD2

T32/T64
OSN 8800 T16 ATE CLK1, CLK2 TOD1, TOD2
OSN 1800 V F1AUX SYNC TOD0, TOD1
TMB1AUX/ CLK1/TOD1, CLK1/TOD1,

TMB2AUXa CLK2/TOD2, CLK2/TOD2,
CLK3/TOD3 CLK3/TOD3
OSN 1800 II F1AUX SYNC TOD0, TOD1

Enhanced
CLK3/TOD3 CLK3/TOD3
OSN 1800 I TMA1UXCL CLK/TOD/MON CLK/TOD/MON

Enhanced
OSN 1800 I&II TNF3SCC EXT2&CLK SW&RS485&TOD

Compact
(TNF3SCC)
OSN 1800 II TP TMB1SCC, EXT2&CLK SW&RS485&TOD

TMT1SCC

CLK3/TOD3 CLK3/TOD3
OSN 1800 I C TMC1SCC EXT2&CLK SW&RS485&TOD

WDM OTN

Port Port
OSN 1800 V Pro TMK5SXCH, CLK/TOD/RS-485 CLK/TOD/RS-485

TMK5XCH,
TMK6XCH,
TMK5UXCME,
TMK6UXCM,
TMK5XCSb

CLK3/TOD3 CLK3/TOD3
OSN 1800 II Pro F1AUX SYNC TOD0, TOD1

CLK3/TOD3 CLK3/TOD3
NOTE
The CLK&TOD, CLKn/TODn, CLK/TOD/MON, and CLK/TOD/RS-485 ports are external clock/
time composite ports. Therefore, you need to use transfer cables to separate CLK (external
clock) ports from TOD (external time) ports.
a: The AUX board of the OSN 1800 has use restrictions. For details, see use restrictions in
2.3.1 Feature Limitations.
b: The TMK5XCS board does not support PTP time synchronization. It can only use external
clock ports, but does not support external time ports.
NOTE
For the port description and pin definitions of each board, see the panel description of each
board in Hardware Description.
External Clock Connection Mode

The external clock port of a subrack supports two working modes:
● External clock mode: It is used to interconnect with BITS or other devices. The
output clock can be synchronized with the system clock of an NE or the line
source specified by the NMS. An external clock input port can participate in
clock source selection only after it is added to the system clock source priority
table.
● Cascading clock mode: It is used only for interconnection between multiple
subracks of WDM/OTN products and is always synchronized with the system
clock. When a port works in the clock cascading mode, the system
automatically determines the clock tracing relationship.
NOTE
On the NMS, set Enabled Status to specify different working modes. When this parameter
is set to Enabled, the cascading clock mode is used. When this parameter is set to
Disabled, the external clock mode is used.

WDM OTN
Table 2-5 Working modes of the clock ports

Working Supported Applicable Scenario Networking Diagram
Mode of Format
the Clock
Port
External All subracks Applies to scenarios Figure 2-14

clock mode work in the where WDM/OTN
(non- external clock equipment is
cascading mode. interconnected with
mode) external clock source
devices or
WDM/OTN NEs are
interconnected.
Clock Each subrack This mode is Figure 2-15

cascading works in recommended when
mode cascading master and slave
clock mode. subracks are
configured and the
subracks support the
clock cascading
mode.
NOTE
For details about
which products
support clock
cascading between
master and slave
subracks, see 2.5
Specifications.
NOTE
For the CLK&TOD composite port, a transfer cable is required to separate the CLK port from
the TOD port.
For boards that support multiple ports (CLK1/TOD1, CLK2/TOD2 ...), the cascading mode is
similar.

WDM OTN
Figure 2-14 Connection diagram of the external clock mode

WDM OTN
Figure 2-15 Connection diagram of the cascading clock mode
Clock Synchronization GE Optical Port

The clock synchronization GE optical port is also called the Dedicated PTP
Synchronization Port or HP optical port.
The clock synchronization GE optical port is used for BITS clock input, clock
synchronization between NEs, or clock cascading between master and slave
subracks. The clock synchronization GE optical port supports both physical clock
synchronization and PTP time synchronization, but does not support Ethernet
service transmission. Table 2-6 lists the names and types of the clock
synchronization GE optical ports.
Table 2-6 Clock synchronization GE optical ports
Product Type Board Name Port Name
OSN 1800 V Pro TMB1AUX, TMB2AUX HP1 (HP2), HP3 (HP4)

WDM OTN
OSN 1800 II Pro TMB1MD48AFS HP1 (HP2)

OSN 1800 II TP
OSN 1800 V
OSN 1800 II Enhanced
OSN 1800 V Pro TMK5SXCH, TMK5XCH, HP1 (HP2)a

TMK6XCH, TMK5UXCME,
TMK6UXCM, TMK5GSCC
OSN 9800 M24 TNG3CXP, TNG4CXP HP1 (HP2)
OSN 9800 M12 TMF1AUX, TMF2AUX01 HP1 (HP2)
OSN 9800 M05 TME1CTU, TME2CTU HP1 (HP2)
OSN 9800 M12 TME3CTU, TMF3AUX HP1

OSN 9800 M05
OSN 9800 M24 TNG2AST4, TNG2AST4E HP1 (HP2)

OSN 9800 M12
OSN 9800 M05
OSN 9800 U32/U64 TNU4CTU, TNU5CTU TX1/RX1, TX2/RX2
OSN 9800 P32/P32C TMP2CTU, TMP3CTU HP1 (HP2)

NOTE
a: The HP1 (HP2) port of the TMK5SXCH, TMK5XCH, TMK5UXCME, TMK6UXCM, and TMK5GSCC boards
supports the clock synchronization GE optical port function since V100R022C00SPC100.
The clock synchronization GE optical port supports two working modes:

● Non-cascading mode: This mode is used for interconnection between
WDM/OTN NEs or for clock/time synchronization between WDM/OTN NEs
and BITS/PTN/base station devices.
● Cascading mode: This mode is used only for interconnection between master
and slave subracks of WDM/OTN NEs to transmit system clock/time signals
between multiple subracks.
NOTE
The clock synchronization GE optical port can be set to the physical clock cascading mode
or PTP clock cascading mode. On the NMS, set Enabled Status to specify different working
modes. When this parameter is set to Enabled, the cascading mode is used. When this
parameter is set to Disabled, the non-cascading mode is used.
● The clock synchronization GE optical port of the OSN 1800 supports both
non-cascading and cascading modes.
● The clock synchronization GE optical port of the OSN 9800 in
V100R021C00SPC300 or earlier does not support the cascading mode and
cannot be used for clock cascading between master and slave subracks. It is
used only for interconnection between WDM/OTN NEs or for clock/time
synchronization between WDM/OTN NEs and BITS/PTN/base station devices.

WDM OTN
● The clock synchronization GE optical port of the OSN 9800 supports the
cascading mode and clock cascading between master and slave subracks since
V100R021C10SPC100.
The clock cascading and non-cascading modes can be set for different ports
separately.
● Figure 2-16 shows the fiber connections when both the cascading and non-
cascading modes are used.
● Figure 2-17 and Figure 2-18 show the fiber connections between NEs.
● Figure 2-19 and Figure 2-20 show the fiber connections for clock cascading
between master and slave subracks.
NOTE
When clock synchronization GE optical ports on system control boards or clock boards are
used for clock synchronization, the clock synchronization GE optical ports on both the active
and standby system control boards or clock boards must be used together to provide clock
protection.
Figure 2-16 Fiber connections of clock synchronization GE optical ports (cascading

mode and non-cascading mode)

WDM OTN
Figure 2-17 Fiber connections of clock synchronization GE optical ports (non-

cascading mode, active/standby protection)

cascading mode, first/last node protection)

WDM OTN

mode, active/standby protection)

mode, first/last node protection)
2.2.4 Synchronous Ethernet

Synchronous Ethernet is an Ethernet physical clock frequency synchronization
technology that directly extracts clock signals from the serial bit streams on
Ethernet lines and transmits the clock signals.
The following figure shows the advantages and limitations of synchronous
Ethernet.

WDM OTN
Figure 2-21 Advantages and limitations of synchronous Ethernet
Principle
Figure 2-22 shows the implementation principle of the synchronous Ethernet
function.
Figure 2-22 Implementation principle
When the Ethernet port functions as the clock source of the NE:
1. The PHY component on the Ethernet port restores clocks from the bit streams
of the Ethernet links, divides the frequency, and then transmits the clocks to
the system clock module.
2. The system clock module selects the clock with the highest priority according
to the clock source priority table and synchronizes the clock with the system
clock.
When the Ethernet port functions as the output clock of local NE to the
downstream device:
1. The system clock module transmits a high-precision system clock to the

Ethernet port.
2. The PHY component on the Ethernet port transmits the clock by means of the
bit streams on Ethernet links.

WDM OTN
Synchronous Ethernet Processing and Transparent Transmission

The support for synchronous Ethernet varies depending on the service
encapsulation types supported by OTN boards. Two implementation modes are
available: synchronous Ethernet processing and synchronous Ethernet transparent
transmission.
Figure 2-23 Synchronous Ethernet processing and transparent transmission
NOTE
The support for synchronous Ethernet of Ethernet ports on packet boards and EoS boards
do not depend on service encapsulation types. For these ports, only synchronous Ethernet
processing is supported, and synchronous Ethernet transparent transmission is not
supported.
When Ethernet services are received by tributary ports on an OTN board, the port
supporting synchronous Ethernet varies according to the encapsulation type. The
following table lists the details.
Table 2-7 Synchronous Ethernet supported by different port service mapping

paths
Service Port Mapping Encapsulati Synchronou Synchronou

Type on Mode s Ethernet s Ethernet
Processing Transparent
Transmissio
n
GE GE (GFP-T) GFP-T Supported Not

supported
GE (TTT-GMP) TTT+GMP Not Supported

supported
10GE LAN MAC transparent GFP-F Supported Not

mapping (10.7G) supported

WDM OTN

Transmissio
n
Bit transparent IMP+BMP Not Supported

100GE MAC transparent GFP-F Supported Not

mapping ODU4 supported
(100G)
Bit transparent GMP Not Supported

(100G)
MACB2B MACB2B Supported Not

supported
200GE MAC transparent Mac (IMP) Supported Not

mapping (inverse supported
multiplexing)
Bit transparent IMP Not Supported

multiplexing)
25GE/50GE MAC transparent GFP-F Supported Not

mapping (GFP-F) supported
Bit transparent BMP Not Supported

mapping (BMP) supported
400GE Bit transparent BMP Not Supported


supported
2.3 Dependencies and Limitations

This topic describes the limitations on and precautions for physical clocks.

WDM OTN
2.3.1 Feature Limitations

Table 2-8 Feature limitations
Item Dependency and Limitation
Clock Networks at the backbone and aggregation layers

should be configured with clock protection and be set
with the primary and secondary PRCs for active/
standby clock switching. For networks at the access
layer, only one PRC is set on the central NE in most
cases, and other NEs trace the clock of the central NE.
Service boards ● Before configuring the clock function, ensure that

the port status of service boards is normal and no
abnormal alarm is reported.
● When the ODUk cross-connect granularity of an
OTN line port is set to the maximum granularity
supported by the port, the physical-layer clock
synchronization is not supported. For OTN line
ports, physical-layer clocks can be used only when
lower-order ODUk cross-connections are
configured for the ports.
● For the tributary ports that receive Ethernet
services, physical-layer clocks can be used only
after services are configured for the ports.
Clock boards When the clock synchronization function is required

by UPS/OSN 6800/OSN 8800/OSN 9800 M/1800
V/OSN 1800 V Pro, two clock boards (either
independent clock boards or system boards integrated
with the clock function) must be configured to back
up each other.
Clock view When two sites use ST2/AST2+SFIU to configure

physical clocks, the physical clock view is supported if
no other optical-layer board exists between the two
sites. Otherwise, the physical clock view is not
supported.

WDM OTN
ST2/AST2 ● If the ST2/AST2 board uses the clock function, it

must be installed in a subrack housing clock
boards.
● The rules for configuring ST2/AST2 boards are as
follows:
– A maximum of four ST2/AST2 boards can be
configured on either side of a cross-connect
board in a cabinet.
– After a clock board is installed in an OSN 6800
subrack, no sufficient space is available for the
network cable of the ST2/AST2 board on the
right side of the clock board because fibers,
clock cables, and power cables occupy the fiber
routing space on the right of the cross-connect
board. Therefore, do not install the ST2/AST2
board on the right side of the clock board.
– Do not insert the ST2/AST2 board in the
rightmost slot of a universal platform subrack.
Otherwise, it is hard to connect or disconnect
the network cable.
● When an OLA is not configured with a clock board,
the ST2/AST2 board at the site can transparently
transmit physical clock signals.
● When an ST2/AST2 board is configured in an OSN
8800 subrack, only the pass-through of physical
clock signals and IEEE 1588v2 signals is supported.
The processing of physical clock signals and IEEE
1588v2 signals is not supported.
● When the ST2/AST2 board is used with the STG
board in a universal platform subrack, the board
can process physical clock signals and IEEE 1588v2
clock signals.
Output of the external ● When AST2/AST4 functions as the OSC and clock
clock transmission board, it cannot be used as the phase-
locked source output by the external clock port.
● For OSN 9800 earlier than V100R001C20SPC300,
only the second external clock port CLK2 on the EFI
board can correctly export line source clocks, and
the outputs of the CLK1 and CLK2 external clock
ports on the EFI board must be the same. To
correctly export different line source clocks using
the CLK1 and CLK2 external clock ports on the EFI
board, you must upgrade the EFI board software to
OSN 9800 V100R001C20SPC300 or later.

WDM OTN
AUX boards of the OSN When an OSN 1800 NE is configured with multiple
1800 AUX boards (F1AUX/B1AUX/B2AUX), you need to set
one AUX board as the main AUX board.
● In the master/slave subrack scenario, the main AUX
board must be configured on the master subrack.
● For the use restrictions on the external clock/time
ports of the TMB1AUX/TMB2AUX board, see Table
2-9.
Clock source ● The central node or the node with high reliability
provides the clock source.
● If there is a Building Integrated Timing Supply
(BITS) device or another external high-precision
clock device on the network, it is recommended
that NEs trace external clock sources. If there is no
BITS device or another external high-precision
clock device on the network, it is recommended
that NEs trace line clock sources. The internal clock
source usually has the lowest priority among all
the clock sources.
● Clock signals need to be compensated after a long
clock chain to avoid the drift of clock signals after
they are transmitted through multiple sites. ITU-T
G.781 stipulates that clock compensation is
required on a long chain consisting of 20 or more
NEs. Considering the transmission distance of
fibers, clock compensation is performed in practice
on a long chain consisting of more than 10 NEs.
● If a long clock chain contains more than 20 NEs,
clock signals need to be output to the BITS through
a 2M clock port (CLK port) for regeneration.
Moreover, the regenerated clock signals should be
sent back to the NEs and serve as the clock source
to be transmitted to the line side.

WDM OTN
Shortest path If NEs need to trace a line clock source, ensure that
the clock tracing path is the shortest. The details are
as follows:
● On a ring network consisting of fewer than six NEs,
the NEs can trace the reference clock source in one
direction.
● On a ring network consisting of six or more NEs,
ensure that the tracing path is the shortest. That is,
on a ring network consisting of N NEs, a half of
the NEs trace the reference clock source in one
direction and the other half of the NEs trace the
reference clock source in the other direction. (If N
is an odd number, the intermediate NE can trace
the reference clock source in either of the
directions.)

WDM OTN
SSM protocol ● If the SSM protocol is disabled, the clock network

can be configured to unidirectional only and
cannot be configured into rings.
● If the SSM protocol is enabled, the settings of the
SSM protocol information for all NEs in the
network should be consistent.
● The principles for enabling the SSM protocol when
the clock switching occurs are as follows:
– If you only want an NE to select a clock source
according to the preset priority without
consideration for the quality of the clock source,
the SSM protocol can be disabled.
– If you want an NE to automatically select a
clock source with the highest quality and
priority, the standard SSM protocol needs to be
enabled. If the clock network consists of Huawei
equipment and third-party equipment, you can
enable the standard SSM protocol only and the
extended SSM protocol cannot be enabled.
– If you want an NE to automatically select a
clock source with the highest quality and
priority and the clock network consists of
Huawei equipment only, you can enable the
extended SSM protocol. The clock source ID
provided by this protocol can avoid timing loops
in the clock network.
● The following principles must be applied if
different SSM protocols are enabled:
– If you enable the standard SSM protocol, you
can configure the clock network to bidirectional
but cannot configure the clock network into
rings.
– If you enable the extended SSM protocol, you
can configure the clock network to bidirectional
or configure the clock network into rings. In this
case, however, intersecting and tangent rings
are not permitted.
SDH clocks An SDH network is a synchronous system and has

high requirements on clock synchronization.
Therefore, ensure that SDH clocks have been
configured before configuring services and features.

WDM OTN
Configuring transport Changing the service type between GE(TTT-GMP)

clock attributes of and GE(GFP-T) for a board will interrupt services on
boards the board. After the operation, the services will be
automatically restored.
For the OSN 6800, changing the value of
Synchronous Clock Enabled for a board will cause a
transient service interruption on the board.
Clock synchronization For the current OSN 1800 version, slave subracks
of slave subracks support clock synchronization only when master and
slave subracks are cascaded.
In a slave subrack, only the following boards support
clock synchronization (that is, the ports on the
following boards are used as clock source ports):
● B1AUX/B2AUX: HPn port
● TMB1DFS/TMB1SFS/TMB1FS: HP port
● TMB1CMD4: TX1/RX1 port
Other types of ports, such as OSC clock sources, line
clock sources, and Ethernet service ports, do not
support clock synchronization.
Configuring clock ● The same subnet number must be assigned to NEs

source protection that trace the same clock source.
● If the extended SSM protocol is enabled, you are
not advised to change the ID of the clock source
being traced by the master NE when the clock
tracing performance is stable. This ensures proper
transmission of clock source IDs and prevents a
clock loop.
Switching a clock ● Performing clock source switching may cause

source service interruption.
● Before switching the clock source, ensure that a
new clock source that is not locked and that has
better quality is created in the priority table.

WDM OTN
Table 2-9 Use restrictions on the external clock/time ports of the TMB1AUX/
TMB2AUX board
Board External External Clock/Time Clock
Clock/Time Output (CLKn/TODn) Cascading
Input Between
(CLKn/ Master and
TODn) Slave
Subracks
(CLKn/TODn)
Main AUX board Not V100R021C00SPC300 and Supported

that works with supported earlier versions: not
the system supported
control board V100R021C10SPC300 and
supporting the later versions: supported
external time/
clock function
Non-main AUX Not V100R021C00SPC300 and Supported

board that works supported earlier versions: not
with the system supported
supporting the later versions: supported
external time/
clock function
Main AUX board Supported Supported Supported

that works with
the system
control board
without the
external time/
clock function
Non-main AUX Not V100R021C00SPC300 and Supported

board that works supported earlier versions: not
with the system supported
without the later versions: supported
external time/
clock function
NOTE
The system control boards of OSN 1800 II TP, OSN 1800 V Pro support the time/clock port
function, and the system control boards of other OSN 1800 devices do not support this
function. For the specifications of the external clock/time ports supported by the board, see
the Hardware Description.

WDM OTN
2.3.2 Affected Features

Table 2-10 Affected features
Loopback For a board port that is configured with physical

clocks, if the loopback test is to be configured on the
port or the interconnected port, the clock trace source
of the NE where the port is located must be switched
to the protection clock source, ensuring that the port
loopback has no impact on the clock function.
Optical line protection When optical line protection, intra-board 1+1

and intra-board 1+1 protection, and physical clock (SDH) are configured at
protection the same time, you are advised to retain the default
value 0 for Clock Source Hold-Off Time(100ms).
Otherwise, the SDH service interruption time may be
longer than 50 ms.
DLAG OSN 1800: If both DLAG and synchronous Ethernet

are to be configured on the TDM plane of the
equipment, configure DLAG first and then
synchronous Ethernet.
2.3.3 Mutually Exclusive Features

Table 2-11 Mutually exclusive features
Fiber Doctor system When the AST4 board works with the F5XCH/
F5UXCME/F5UXCM board, the line fiber quality
monitoring function and physical clocks or IEEE
1588v2 are mutually exclusive. If both are configured,
physical clocks and IEEE 1588v2 will become
abnormal.
When the AST2 board works with the 11STG/12STG/
K2STG/16SCC/16XCH/16UXCM board, the line fiber
quality monitoring function and physical clocks or
IEEE 1588v2 are mutually exclusive. If both are
configured, physical clocks and IEEE 1588v2 will
become abnormal.
2.4 Availability
This topic describes the board types and software versions that support physical
clocks.

WDM OTN
2.4.1 OSN 9800 Universal Platform Subrack Hardware and

Version Support
This section describes the board types and software versions that support physical
clocks in the OSN 9800 universal platform subrack.
Table 2-12 Boards and device versions that support physical clocks (OTN & Packet
& SDH) in the OSN 9800 universal platform subrack (optical-layer configuration)
Board Type Board Name Start Version
Clock board TN12STG V100R001C20
TN13STG V100R002C10
OSC board ST2 V100R001C20
AST2 V100R002C10
Optical SFIU V100R001C20

multiplexer and
demultiplexer DAPXF (XFIU unit) V100R005C10
board SRAPXF (XFIU unit) V100R006C00
NOTE
Clock synchronization can be implemented only when a clock board is configured for a
subrack.
2.4.2 OSN 9800 P Series Hardware and Version Support

This section describes the board types and software versions that support physical-
layer clocks in OSN 9800 P series subracks.
Table 2-13 Boards and device versions that support physical-layer clocks (OTN,
packet, and SDH) in OSN 9800 P series subracks (optical-layer configuration)
System control TMP1CTU V100R007C00

board
TMP2CTU V100R019C10
TMP3CTU V100R022C10
Clock interface TMP1EFI V100R007C00

board
Optical line ON32, ON32P V100R007C00

board
TMP3ON20, TMP3ON20P V100R019C10

WDM OTN
TMP2ON20H, TMP2ON20PH, V100R021C10

TMP2ON32H, TMP2ON32PH,
TMP3ON20H, TMP3ON20PH
TMP2ON32E, TMP2ON32PE, V100R022C00

TMP2ON32HE, TMP2ON32PHE
2.4.3 OSN 9800 U Series Hardware and Version Support

layer clocks in OSN 9800 U series subracks.
packet, and SDH) in OSN 9800 U series subracks (electrical-layer configuration)
Clock board TNU1CTU V100R001C20
TNS1CTU V100R001C30
TNU2CTU, TNS2CTU, TNU4CTU V100R007C00
TNU5CTU V100R019C10
Clock interface EFI V100R001C20

board
Tributary board T130, T216, T210, T220, G210, G220 V100R001C20
E124, E208, E212, E302, E401 V100R001C30
S216, T230, TNV3T404, S208 V100R002C10
G402, G404, T220E V100R003C10
TNV3T401, TNV3T402 V100R005C00
TNV5T404, TNV3S216, TNV5T401, V100R007C00

TNV5T402, TNV3G220, TNV2E224,
TNV2E402, TNV6T220, TNV7T402
TNV1T210U, TNV1T502, TNV8T404, V100R019C10

TNV4S216, TNV8T402, TNV7T220,
NV1T410, TNV3E402, TNV3E224
TNV1T402E, TNV3T220E, TNV3E404, V100R020C10

TNV6S216a, TNV6G216a
TNV6T216b, TNV6T230b, TNV6G230b V100R021C00

(OTN tributary), TNG2PD1
TNV1EMS12 V100R021C10

WDM OTN
TNV4E404, TNV4E224 V100R022C00
Line board TNU1NP400/TNU1NP400E V100R001C20
U401, U210 V100R001C30
TNU3N401, TNU3N402, TNU3SN402, V100R002C10

TNU5N402, TNU5N404, N402P
G402, G404 V100R003C10
U402 V100R005C00
TNU5N401, TNU4N501, TNU4N502 V100R006C00
TNU2N401P V100R006C10
TNU5N501P, TNV5T404 (line mode), V100R007C00

TNS2N504, TNS2N502, TNS2N404,
TNV5U220, TNV5U210, TNV5T401
(line mode), TNV5T402 (line mode),
TNS2N501, TNS2N401, TNS2N402,
TNU5U401, TNU5U501, TNU6N402,
TNU6N502, TNU6U402, TNU5NP200/
TNU5NP200E, TNU5NP400/
TNU5NP400E
TNU3N602, TNS2N220, TNS7N404, V100R019C10

TNS7N502, TNV6U210, TNV6U220,
TNV8T404 (line mode), TNV1EMS20,
TNV8T402 (line mode), TNS7N402,
TNS8N502, TNS4N402, TNU6U501,
TNS8N402, TNV1T502 (line mode),
TNU6U402C
TNS1N601a, TNU6U502, TNS6N216a, V100R020C10

TNS6N116, TNV6G216a
TNU7U402, TNSDN502b, TNU1N801c, V100R021C00

TNU6U316, TNV6G230b (line mode)
TNU7N502, TNSDN502, TNS1N502P, V100R021C10

TNS5NP400/TNS5NP400E
TNU8U402, TNU8U402C, TNV7U220, V100R022C00

TNS9N401
TNS5N401PE, TNS5N401P, TNS5N501 V100R022C10

PSE, TNS5N501PS, TNS5N402MP

WDM OTN
● T216/TNV1T210: Only ports 1 to 4 support synchronous Ethernet processing.

● When an electrical module is installed on a port, the port does not support
physical-layer clocks.
● In regeneration mode, boards support only transparent transmission of
physical-layer clocks, but not support physical-layer clock synchronization.
● When the ODUk cross-connect granularity of an OTN line port is set to the
maximum granularity supported by the port, the physical-layer clock
synchronization is not supported. For OTN line ports, physical-layer clocks
can be used only when lower-order ODUk cross-connections are configured
for the ports.
● For the tributary ports that receive Ethernet services, physical-layer clocks
can be used only after services are configured for the ports.
● For the boards working together with the TNU2CTU and TNS2CTU system
control boards, the physical-layer clock is supported since V100R007C00.
● a: The compatibility with the U1CTU/S1CTU boards in OSN 9800 U series
subracks is no longer applicable to OSN 9800 V100R020C10. The
compatibility with the U1CTU/S1CTU boards in OSN 9800 U series subracks
is continuously evolving in the SPCs of V100R019C10. Therefore, these boards
can work with the U1CTU or S1CTU board only in V100R019C10SPC800 and
later patch versions.
● b: The compatibility with the U1CTU/S1CTU boards in OSN 9800 U series
can work with the U1CTU/S1CTU board only in V100R019C10SPC900 and
● c: When the line ports on the TNU1N801 board work in OTUC8 mode,
physical-layer clock synchronization is not supported.

paths
Transmissio
n

supported

WDM OTN

Transmissio
n

supported



(100G)

(100G)

supported

multiplexing)

multiplexing)




supported
NOTE
When the port working mode is ODUflex non-convergence mode (Any->ODUflex),

synchronous Ethernet processing is supported, but synchronous Ethernet transparent
transmission is not supported.
NOTE
The packet service boards in Table 2-14 support synchronous Ethernet when receiving Ethernet
services.

WDM OTN
2.4.4 OSN 9800 M Series Hardware and Version Support

layer clocks in OSN 9800 M series subracks.
packet, and SDH) in OSN 9800 M series subracks
Clock board TNG1CXP V100R006C00
TMF1AUXa, TNG3CXP V100R007C00
TME1CTU, TME2CTU V100R019C10
TME3CTU V100R020C10
TNG4CXP V100R021C00
TMF2AUX01 V100R021C10

board
TMF1AUXa V100R007C00
TME3CTU, TMF3AUX V100R020C10
TMF2AUX V100R021C10
OSC board TNG2AST2 V100R019C10
TNG3OH20H (OSC unit) V100R020C10
TNG2AST4, TNG3OH20 (OSC unit) V100R021C00
TNG2AST4E, TNG2OH20 (OSC unit), V100R021C10

TNG2OH20H (OSC unit)
TNG2OH9 (OSC unit) V100R022C00
TNG3DAFS (OSC unit) V100R022C10
Optical TNG2DAPXF (XFIU unit), TNG3DAPXF V100R019C10

multiplexer and (XFIU unit), TNG2SRAPXF (XFIU unit),
demultiplexer TNG3SRAPXF (XFIU unit),
board TNG2WDAPXF (XFIU unit)
OTU board TNG1M402 V100R006C00
TNG1M402D, TNG1M402DM, V100R007C00

TNG1M502DM
TNG1M504DM, TNG1M520SM, V100R019C10

TNG1M404DM, TNG1M210D,
TNG2M604SM

WDM OTN
TNG2M504S, TNG1M804SM V100R020C10
TNG1M520S, TNG3M402D, V100R021C10

TNG3M504D
TNG2M504DM, TNG3M504SP V100R022C00
TNG1M411SMP, TNG1M828SM, V100R022C10

TNS5NP400Y
Tributary board A212, G402, T206, T212, T402, T401, V100R006C00

T210, T220, T230
TNV5T404, TNV3S216, TNV5T401, V100R007C00

TNV5T402, TNV3G220, TNV3T404,
TNV3T401, TNU1G404, TNV6T220,
TNV7T402, TNV2E224, TNV2E402
TNV1T210U, TNV1T502, TNV8T404, V100R019C10

TNV4S216, TNV8T402, TNV7T220,
TNV1T410, TNV3E402, TNV3E224,
TNV4T405
TNV1T402E, TNV3T220E, TNV3E404, V100R020C10

TNV6G216, TNG3SL16Q, TNG3SL64D,
TNG3SL41O, TNG1PD1, TNG1DMS
TNV6T216, TNV6T230, TNV6G230, V100R021C00

TNG3A204 (OTN tributary), TNG2PD1
TNG1EMS12, TNV1EMS12 V100R021C10
TNG3T212, TNG3A212 (tributary V100R022C00

mode), TNV4E404, TNV4E224
TNG1T210E V100R022C10
Line board A212, G402, N206, N210, TNU5N402, V100R006C00

TNU5N401, TNG1N401, U402,
TNU5NP200/TNU5NP200E,
TNU5NP400/TNU5NP400E
N501P V100R006C10
TNV5T404 (line mode), TNS2N504, V100R007C00

TNS2N502, TNS2N404, TNV5U220,
TNV5U210, TNU2N402P, TNU2N401P
(F51), TNV5T401 (line mode),
TNU5U501, TNU5N404, TNU1G404,
TNU6N502, TNU6N402, TNU6U402

WDM OTN
TNU3N602, TNS2N220, TNS7N404, V100R019C10

TNS7N502, TNV6U210, TNV6U220,
TNV8T404 (line mode), TNV1EMS20,
TNS8N402, TNV1T502 (line mode),
TNG2A212 (line mode), TNU6U402C
TNS1N601, TNU6U502, TNS6N216, V100R020C10

TNS6N116, TNV6G216
TNU7U402, TNSDN502, TNU1N801, V100R021C00

TNU6U316, TNV6G230 (line mode),
TNG3A204 (OTN line, SDH line)
TNU7N502, TNSDN502, TNS1N502P, V100R021C10

TNS5NP400/TNS5NP400E
TNU8U402, TNU8U402C, TNV7U220, V100R022C00

TNS9N401, TNG3N212, TNG3A212
(line mode)
TNS5N401PE, TNS5N401P, TNS5N501 V100R022C10

PSE, TNS5N501PS, TNS5N402MP
NOTE
● TNV1T210: Only ports 1 to 4 support synchronous Ethernet processing.
● When an electrical module is installed into a port, physical-layer clocks are not
supported.
● In regeneration mode, boards support only transparent transmission of physical-layer
clocks, but not support physical-layer clock synchronization.
● When the ODUk cross-connect granularity of an OTN line port is set to the maximum
granularity supported by the port, the physical-layer clock synchronization is not
supported. For OTN line ports, physical-layer clocks can be used only when lower-order
ODUk cross-connections are configured for the ports.
● For the tributary ports that receive Ethernet services, physical-layer clocks can be used
only after services are configured for the ports.
● The T210, T220, T230 boards are supported since V100R006C00SPC700 (excluding
V100R006C10).
● a: The AUX boards are system auxiliary communication boards that provide the clock
function.
● When the line ports on the TNU1N801 board work in OTUC8 mode, physical-layer clock
synchronization is not supported.
● TNG1M411SMP: When the TX11/RX11 port receives 4 x 10GE services, only the first
10GE channel of the 4 x 10GE services supports physical-layer clocks.

WDM OTN

paths
Transmissio
n

supported

supported



(100G)

(100G)

supported

multiplexing)

multiplexing)




supported

WDM OTN
NOTE
● When the port working mode is ODUflex non-convergence mode (Any->ODUflex),

synchronous Ethernet processing is supported, but synchronous Ethernet transparent
transmission is not supported.
● When the service type is 10GE LAN (IMP+BMP), the TNG1M411SMP board does not
support synchronous Ethernet transparent transmission.
2.4.5 OSN 8800 Hardware and Version Support

layer clocks in OSN 8800 subracks.
Table 2-18 Boards and device versions that support physical-layer clocks (OTN
and packet) in OSN 8800 subracks
Clock board TN52STGa, TNK2STGa V100R002C00
TN16XCH V100R006C00
TN16SCC V100R006C01
TN16UXCM V100R007C00
TN12STGa V100R008C10
TN54STG V100R009C10
TN13STG, TNK3STG V100R010C10
Clock interface TN52STI V100R002C00

board
TN16ATE V100R006C00
AST2 V100R011C00

multiplexer and
board
Tributary board TOG V100R002C00
LEM24, LEX4 V100R005C00
THA, TOA, TN55TQX, TN53TDX V100R006C01
TEM28 V100R006C03
TOX, THX, EG16, EX2 V100R007C00
TN55TTX V100R009C00
EX8 V100R008C10

WDM OTN
TN55TSC V100R011C10
LQCP V100R013C00
Line board TN54NQ2, TN52ND2 V100R002C00
TN54NS3 V100R005C00
NPO2, NPO2E, TN57NQ2, TN57ND2, V100R006C01

TN53NS2, TN53NQ2, TN53ND2
PND2 V100R007C00
NPS4, NPS4E, HUNS3, HUNQ2 V100R009C10

NOTE
● a: The clock pulse width supported by TN52STG, TNK2STG, TN12STG, and TN11STG
boards ranges from 10 ms to 500 ms.
● Clock synchronization can be implemented only when a clock board is configured for a
subrack.
● The TN16XCH/TN16SCC/TN16UXCM board integrates the functions of a clock board.
● The TN52ND2T04 board does not support physical-layer clocks.
Table 2-19 Boards and device versions that support physical-layer clocks (SDH) in
OSN 8800 subracks
Clock board TN16XCH, TN16UXCM, TN16ATE, V100R007C00

TN52STG
TN54STG V100R009C10
TNK3STG V100R010C10
Clock interface TN52STI, TNL1STI V100R007C00

board
Tributary board N1EGSH, N3EAS2 V100R007C00
Line board N4SLO16, N4SLQ64, N3SLH41, V100R007C00

N4SFD64, N4SF64, N1SF64A,
N4SLD64, N4SL64, N4SLQ16
HUNS3, HUNQ2 V100R008C00

WDM OTN
TN54HSNS4 V100R011C10
NOTE
The TX2/RX2 and TX4/RX4 optical ports of the N1EGSH board can process synchronous
Ethernet clock signals.

paths

Transmissio
n

supported

supported



(100G)

(100G)

supported

multiplexing)

multiplexing)


WDM OTN

Transmissio
n



supported

This section describes the board types and software versions of OSN 6800
subracks that support physical clocks.
Table 2-21 Boards and device versions that support physical-layer clocks (OTN) in
OSN 6800 subracks
Cross-connect TN12XCS V100R005C00

board
TN12STG V100R008C10
TN13STG V100R010C10
AST2 V100R011C00

multiplexer and
board
Tributary board LEM24, LEX4, TN52TOG, TN52TDX V100R005C00
TN53TDX, TN55TQX V100R006C01
Line board TN12ND2, TN52ND2 V100R005C00
TN53NQ2, TN53ND2, TN53NS2 V100R006C01

WDM OTN

NOTE
● Clock synchronization can be implemented only when a clock board is configured for a
subrack.
● If the OSN 6800 is configured with clock boards, cross-connect boards must also be
configured.
● The TN52ND2T04 board does not support physical-layer clocks.

paths
Transmissio
n

supported

supported



(100G)

(100G)

supported

WDM OTN

Transmissio
n

multiplexing)

multiplexing)




supported
2.4.7 OSN 1800 V Hardware and Version Support

layer clocks in OSN 1800 V subracks.
packet, and SDH) in OSN 1800 V subracks
Clock board TNF5UXCM (F5STG) V100R003C05
TNF5XCH (F5STG) V100R005C00
TNF5UXCME (F5STG) V100R005C20
TNZ5UXCMS (Z5STG) V100R006C10
TNZ8XCH (Z8STG) V100R009C00
Clock interface F1AUX V100R003C05

board
TMB1AUX V100R020C10
TMB2AUX V100R021C10

WDM OTN
AST4 V100R006C20
TMB1AST2 V100R009C00
TMB1MD40AFS (OSC unit) V100R020C10
TMB1MR4AFS/TMB1MR4FS (OSC unit) V100R021C00
TMB2MR4AFS/TMB2MR4FS (OSC V100R021C10

unit), TMB1MD48AFS (OSC unit)
TMB1DFS/TMB1SFS/TMB1FS (OSC V100R022C00

unit)
Optical DSFIU V100R005C00

multiplexer and
demultiplexer WSMD9XF (XFIU unit) V100R008C10
board TMB1MD40AFS (XFIU unit) V100R020C10
TMB1MR4AFS/TMB1MR4FS (XFIU V100R021C00

unit), TMB1WSMD9XF (XFIU unit)

unit), TMB1MD48AFS (XFIU unit)
TMB1DFS/TMB1SFS/TMB1FS (XFIU V100R022C00

unit)
OTN tributary TOA V100R003C05

board
TQX V100R005C00
TDX V100R005C10
TTA V100R006C20
TSC V100R007C10
OTU board TNF2LDX, F2ELOM (STND) V100R006C00

(client side)
F1LDCA V100R008C10
B1ELOM, B1LDX, B1LTX, B1LDCA, V100R019C10

B1LDCD, B1LDC
TNF3ELOM, TNF3LDX V100R020C10
B2LTX, B2LDCA V100R021C00
TMB2LDC, TMB2LDCD V100R021C10
TMB1LQCB V100R022C00
B2ELOM, B2LDX V100R022C10

WDM OTN
OTN line board HUNQ2, ND2 V100R003C05
HSNQ2 V100R005C10
Z5UNQ2 V100R006C10
UNS4, HSNS4, NP200, NP200E V100R006C20
UNQ1, NQ2, Z8NS4 V100R009C00
Z8UNQ2, Z8UTX2 V100R019C10
TNZ8UNS4/TNZ9UNS4 V100R021C00
OTU board F2ELOM (STND) V100R007C10

(WDM side)
F1LDCA V100R008C10

B1LDCD, B1LDC
TNF3ELOM V100R020C10
Packet board EM20 V100R003C05
EX4, EG10 V100R006C10
TMB1EG10 V100R021C10
PDH board PL3T, SP3D V100R003C05
CQ1, MD1a V100R006C10
TSP V100R006C20
PD1, DMS, PL4D V100R008C00
TMB1PL1D V100R020C10
TMB2PD1 V100R021C00
EoS board EGS4 V100R005C00
EMS10 V100R019C10
TMB2EGS4 V100R021C00
TMB3EMS10, TMB3EGS4 V100R021C10
SDH line board SL4D, SL1Q, HUNQ2 V100R003C05

WDM OTN
SLNO, SL64D V100R005C00
HSNQ2 V100R005C10
F5NS4 V100R006C00
UNQ2 V100R006C10
NP200, NP200E, UNS4, HSNS4, TSP V100R006C20
W1SL16Q, W1SL64S, UNQ1 V100R009C00
F8SLNO, F8SL16Q, F8SL64D, F8SL64S, V100R019C10

B1SL41O, B1SL41Q, B1SL16S,
Z8UNQ2, UTX2
TNZ8UNS4/TNZ9UNS4, TNF9SLNO, V100R021C00

TNF9SL16Q, TMB2SL41Q
TNFASL64S, TNFASL64D, TNFASL16Q, V100R021C10

TNFASLNO, TMB3SL16S, TMB3SL41Q,
TMB3SL41O
TMB3SL41S V100R022C00
NOTE
● In ODU1_ODU0 mode (OTU1->ODU1->ODU0), the TOA/TTA board receives OTU1
services from the client side and supports physical-layer clock processing, but does not
support transparent transmission of physical-layer clock signals.
supported.
● The AUX board is an auxiliary board that provides the clock function.
a: The MD1 board supports physical-layer clocks (SDH) only when the SSM protocol is not
used.

WDM OTN

paths

Transmissio
n
GE GE(GFP-T) GFP-T Supported Not

supported

supported



(100G)

(100G)


NOTE
● When receiving GE/10GE LAN/CPRI/OBSAI services, the OSN 810 (C15XnR) and OSN
810 (C15Xn) boards support transparent transmission of physical-layer clocks but do not
support processing of physical-layer clocks.
2.4.8 OSN 1800 II Enhanced Hardware and Version Support

layer clocks in OSN 1800 II Enhanced subracks.
packet, and SDH) in OSN 1800 II Enhanced subracks
Clock board TNZ1UXCL (Z1STG) V100R007C10
TNZ2UXCL (Z1STG) V100R008C00

WDM OTN

board
TMB1AUX V100R020C10
TMB2AUX V100R021C10
OSC board ST2, AST4 V100R007C10


unit)

multiplexer and
board TMB1MR4AFS/TMB1MR4FS (XFIU V100R021C00


unit)
OTN tributary TTA, TOA V100R007C10

board

(client side)
F1LDCA V100R008C10

B1LDC
TMB2LDC V100R021C10
OTN line board UNQ2, HSNQ2 V100R007C10
UNQ1, NQ2 V100R009C00

WDM OTN

(WDM side)
F1LDCA V100R008C10

B1LDC
TMB2LDC V100R021C10
Packet board EX4, EG10, EG4C, UXCL (EX1) V100R007C10
PDH board SP3D, PL3T, CQ1, MD1a, TSP V100R007C10
PD1, DMS V100R019C10
TMB2PD1 V100R021C00
EMS10 V100R019C10
SDH line board SL4D, SL1Q, SLNO, UNQ2, HSNQ2, V100R007C10

UXCL (SL64), UXCL (PSNS2), TSP
UXCL (SLN), UNQ1 V100R009C00
F8SLNO, Z8UNQ2, UTX2, B1SL41Q, V100R019C10

B1SL16S
TMB2SL41Q, TNF9SLNO V100R021C00
TNFASLNO, TMB3SL16S, TMB3SL41Q V100R021C10

WDM OTN

NOTE
● In ODU1_ODU0 mode (OTU1->ODU1->ODU0), the TTA/TOA board receives OTU1
services from the client side and supports physical-layer clock processing, but does not
support transparent transmission of physical-layer clock signals.
supported.
used.

paths

Transmissio
n

supported

supported



(100G)

(100G)

WDM OTN

Transmissio
n


2.4.9 OSN 1800 I Enhanced Hardware and Version Support

layer clocks in OSN 1800 I Enhanced subracks.
and packet) in OSN 1800 I Enhanced subracks
Clock board TMA1UXCL (A1STG) V100R008C10
OTN tributary UXCL (G12A) V100R009C00

board
OTN line board UXCL (PSND2) V100R008C10
UXCL (UND1), UXCL (UND2) V100R009C00
Packet board EG10, UXCL (EX2), UXCL (G12A) V100R008C10
PDH board SP3D, PL3T V100R008C10
UXCL (G12A), CQ1, MD1a V100R009C00
EMS10 V100R019C10
SDH line board SLNO, UXCL (PSND2), UXCL (SLND) V100R008C10
UXCL (UND1), UXCL (UND2) V100R009C00
TMB2SL41Q, TNF9SLNO V100R021C00

WDM OTN
TNFASLNO, TMB3SL41Q V100R021C10
NOTE
● The UXCL (G12A) board supports physical-layer clocks (packet) since 1800 I Enhanced
V100R008C10 and supports physical-layer clocks (OTN) since 1800 I Enhanced
V100R009C00.
used.
When Ethernet services are received on an OTN board, the port supporting
synchronous Ethernet varies according to the encapsulation type. The following
table lists the details.

paths
Service Type Port Mapping Synchronous Synchronous
Ethernet Ethernet
Transmission
GE GE (GFP-T) Supported Not supported
GE (TTT-GMP) Not supported Supported
10GE LAN MAC transparent Supported Not supported

mapping (10.7G)
Bit transparent Not supported Supported

mapping (11.1G)
2.4.10 OSN 1800 I&II Compact Hardware and Version Support

layer clocks in OSN 1800 I&II Compact subracks.

WDM OTN
Table 2-29 Boards and device versions that support physical-layer clocks (OTN) in
OSN 1800 I&II Compact subracks (TNF3SCC)
Clock board TNF3SCC (F3STG) V100R005C20
AST4 V100R006C20

multiplexer and

(client side)
TNF2LDX V100R006C00
F1LDCA V100R008C10

B1LDC

(WDM side)
B1LDC

NOTE
supported.

WDM OTN
Table 2-30 Boards and device versions that support physical-layer clocks (SDH) in
OSN 1800 I&II Compact subracks (TNF3SCC)
STM-N service TSP V100R006C20

board

paths
Transmissio
n

supported

supported



(100G)

(100G)


2.4.11 OSN 1800 V Pro Hardware and Version Support

layer clocks in OSN 1800 V Pro subracks.

WDM OTN
Table 2-32 Boards and device versions that support physical-layer clocks in OSN
1800 V Pro subracks
Clock board TMK5SXCH (K5STG) V100R019C10
TMK5XCH (K5STG), TMK5UXCME V100R021C00

(K5STG)
TMK5XCS (K5STG), TMK6UXCM V100R021C10

(K6STG), TMK5GSCC (K5STG)
TMK6XCH (K5STG) V100R022C10
Clock TMB1AUX V100R020C10

interface
board TMB2AUX V100R021C10
OSC board TMB1AST2, TNF1AST4, TNF1ST2, V100R019C10

TMB2AST2


unit)
TMB1CMD4 (OSC unit) V100R022C10
Optical TNF1DSFIU V100R019C10

multiplexer
and WSMD9XF (XFIU unit) V100R019C10
demultiplexer TMB1MD40AFS (XFIU unit) V100R020C10
board


unit)
OTN tributary TMK1TTA, TMK1TDC, TMK1GTA V100R019C10

board (tributary mode)
TMK1GDC (tributary mode) V100R020C10
TMB3EMS10 (B3TEM10) V100R021C10

WDM OTN
OTU board TNF2LDX, TNF2ELOM, TMB1ELOM, V100R019C10

(client side) TMB1LDX, TMB1LDCD, TMB1LDC,
TMB1LDCA, TMB1LTX, TMK1MDCA,
TNF1TSP(B)
TMB2LTX, TMB2LDCA, TMK2MDCA V100R021C00
TMB2ELOM, TMB2LDX, TMB1LTXMP V100R022C10
OTN line TMK1UNS5, TMK1UNQ2, TMK1GTA V100R019C10

board (line mode)
TMK1GDC (line mode) V100R020C10
TMK1UTX2, TMK1UNS4, TMK1UND3 V100R021C00
TMK1UND2, TMK1UNQ2M, V100R021C10

TMK1UTO2
TMK1UNS4MP V100R022C10
OTU board TNF2ELOM, TMB1ELOM, TMB1LDX, V100R019C10

(WDM side) TMB1LDCD, TMB1LDC, TMB1LDCA,
TMB1LTX, TMK1MDCA, TNF1TSP(B)
Packet board TMK1EX10 V100R021C00
TMK2EX10, TMB1EG10 V100R021C10
TMK1EC1, TMB3EMS10D V100R022C10
SDH line TMK1SLNO, TMK1SL64S, TMK1SL16Q, V100R019C10

board TMB1SL41O, TMB1SL41Q, TMB1SL16S
TMK2SLNO, TMB2SL41Q V100R021C00
TMB3SL16S, TMB3SL41Q, TMB3SL41O, V100R021C10

TMK3SL64S, TMK3SL64D, TMK3SL16Q,
TMK3SLNO

WDM OTN
PDH board TMB1PD1, TMB1DMS, TNF1SP3D V100R019C10
TMB2PD1 V100R021C00
EoS board TMB1EMS10, TMB1EGS4 V100R019C10
TMB3EMS10D V100R022C10
NOTE
supported.

paths
Transmissio
n

supported

supported



WDM OTN

Transmissio
n

(100G)

(100G)


2.4.12 OSN 1800 II Pro Hardware and Version Support

layer clocks in OSN 1800 II Pro subracks.
Table 2-34 Boards and device versions that support physical-layer clocks in OSN
1800 II Pro subracks
Clock board TMK2UXCL (K2STG) V100R019C10
TMK2UXCLE (K2STG) V100R021C00
Clock TNF1AUX V100R019C10

interface
TMB2AUX V100R021C10

TMB2AST2


unit)

WDM OTN

multiplexer
board


unit)

OTU board TNF2LDX, TNF2ELOM, TMB1ELOM, V100R019C10

(client side) TMB1LDX, TMB1LDCD, TMB1LDC,
TMB1LDCA, TMB1LTX, TMK1MDCA,
TNF1TSP(B)
TMB2LDC, TMB2LDCD, TMK1NP400M/ V100R021C10

TMK1NP400ME
OTN line TMK1UNS5, TMK1UNQ2, TMK1GTA V100R019C10

board (line mode)
TMK1UND2, TMK1UNQ2M, V100R021C10

TMK1UTO2
OTU board TNF2ELOM, TMB1ELOM, TMB1LDX, V100R019C10

(WDM side) TMB1LDCD, TMB1LDC, TMB1LDCA,
TMB1LTX, TMK1MDCA, TNF1TSP(B)

WDM OTN

TMK1NP400ME
TMK1EC1, TMB3EMS10D V100R022C10
SDH line TMK1SLNO, TMK1SL64S, TMK1SL16Q, V100R019C10

board TMB1SL41O, TMB1SL41Q, TMB1SL16S
TMK2SLNO, TMB2SL41Q V100R021C00
TMB3SL16S, TMB3SL41Q, TMB3SL41O, V100R021C10

TMK3SL64S, TMK3SL64D, TMK3SL16Q,
TMK3SLNO
PDH board TMB1PD1, TMB1DMS, TNF1SP3D V100R019C10
TMB2PD1 V100R021C00
EoS board TMB1EMS10, TMB1EGS4 V100R019C10
NOTE
supported.

WDM OTN

paths
Transmissio
n

supported

supported



(100G)

(100G)


2.4.13 OSN 1800 II TP Hardware and Version Support

layer clocks in OSN 1800 II TP subracks.
Table 2-36 Boards and device versions that support physical-layer clocks
Clock board TMB1SCC (B1STG) V100R009C00
TMT1SCC (T1STG) V100R021C00
Clock TMB1AUX V100R020C10

interface
OSC board TMB1AST2, TNF1AST4, TNF1ST2 V100R009C00

WDM OTN


unit)

multiplexer
board


unit)
OTU board TNF2ELOM, TNF2LDX V100R009C00

(client side)
TMB1ELOM, TMB1LDX, TMB1LTX, V100R019C10
TMB1LDCA, TMB1LDCD, TMB1LDC,
TMK1MDCA, TNF1TSP(B)
OTU board TNF2ELOM V100R009C00

(WDM side)
TMB1ELOM, TMB1LDX, TMB1LTX, V100R019C10
TMB1LDCA, TMB1LDCD, TMB1LDC,
TMK1MDCA, TNF1TSP(B)

WDM OTN

NOTE
supported.

paths
Transmissio
n

supported

supported



(100G)

(100G)


WDM OTN

Transmissio
n

2.4.14 OSN 1800 I Compact Hardware and Version Support

layer clocks in OSN 1800 I Compact subracks.
and packet) in OSN 1800 I Compact subracks
Clock board TMC1SCC (C1STG) V100R022C10
OTU board TMB2ELOM, TMB2LDX, TMB2LTX, V100R022C10

(client side) TNF3ELOM, TNF3LDX

(WDM side) TNF3ELOM
NOTE
When Ethernet services are received by an OTU board, the port supporting
synchronous Ethernet varies according to the encapsulation type. The following

paths
Transmissio
n

supported

WDM OTN

Transmissio
n

supported



(100G)

(100G)


2.5 Specifications
This section describes the physical-layer clock specifications supported by the
equipment.
Table 2-40 Physical-layer clock specifications

Item Specifications
Clock working mode ● Locked mode

● Holdover mode
● Free-run mode
Clock source ● Synchronous Ethernet clock

● External clock
● E1 tributary clock source
● Line clock source
● Internal clock source

WDM OTN
Item Specifications
Synchronous Ethernet ● FE optical port

● GE port
● 10GE optical port
NOTE
SFP electrical modules do not support synchronous Ethernet.
Only FlexE ports (100G/200G) on the TNG1M804SM/
TNV1T502 board support the physical-layer clock since
V100R020C10.
Only 40GE optical ports on packet boards support synchronous
Ethernet.
External clock port ITU-T G.703-compliant 2.048 MHz or 2.048 Mbit/s

signals can be used as inputs or outputs of external
clock ports. For details, see 2.2.3 Clock Source Port.
Clock synchronization 50 ppb

precision
Maximum number of 20
NEs on a clock chain
SSM protocol and Supported

extended SSM
protocol
Clock sources An NE supports a maximum of 32 clock sources.

WDM OTN
Item Specifications
Clock cascading ● OSN 9800:

between master and – Universal platform subrack: The universal
slave subracks platform subracks on the same NE implement
frequency/phase synchronization through clock
cascading between master and slave subracks.
– U series subrack:
In versions earlier than V100R007C00, electrical
subracks on the same NE do not support clock
Therefore, only one electrical subrack on each NE
supports frequency/phase synchronization. You
are advised to configure all boards requiring
frequency and phase synchronization in the same
subrack.
In V100R007C00 and later versions, when the
system control board is TNU2CTU or TNS2CTU,
electrical subracks on the same NE support clock
When the system control board is TNU4CTU or
TNU5CTU, electrical subracks on the same NE
support clock cascading between master and
slave subracks.
– M series subracks: Clock cascading between
master and slave subracks is supported.
– P series subracks: Clock cascading between
– Clock cascading between master and slave
subracks cannot be implemented between
universal platform subracks and U/M series
subracks.
● OSN 1800:
– Subracks that use the TMB1AUX board support
clock cascading between master and slave
subracks since V100R020C10. The ports supported
by the TMB1AUX board are external clock/time
ports and clock synchronization GE optical ports.
– Subracks that use the TMB2AUX/MD48AFS board
slave subracks since V100R021C10. The ports
supported by the TMB2AUX board are external
clock/time ports and clock synchronization GE
optical ports. The ports supported by the
MD48AFS board are clock synchronization GE
optical ports.
– Subracks that use the TMK5SXCH/TMK5UXCME/
TMK5XCH/TMK5GSCC board support clock

WDM OTN
Item Specifications
cascading between master and slave subracks

since V100R022C00. The ports supported by the
board are clock synchronization GE optical ports.
– Subracks that use the TMK6XCH board support
subracks since V100R022C10. The ports supported
by the board are clock synchronization GE optical
ports.
● OSN 8800/6800: Clock cascading between master
and slave subracks is supported.
NOTE
Clock cascading between master and slave subracks is
supported only when subracks are configured in master/slave
mode. For details about the specifications and capabilities of
the master and slave subracks, see
● For carriers: WDM OTN Master-Slave Subrack
Management Guide
● For enterprises: WDM OTN Master-Slave Subrack
Management Guide
When the OSN 9800/OSN 8800/OSN 6800 subracks that
support master-slave subrack clock cascading implement the
clock cascading function, two clock boards need to be
configured for each subrack. The master clock subrack can be
configured in the slave service subrack. Master and slave
service subracks can be separated from master and slave clock
subracks.
2.6 Feature Updates

This topic describes the feature updates of physical-layer clocks (OTN, packet, and
SDH) in the product versions, the reasons for the updates, and the corresponding
information updates. Any product versions that are not listed in the document
means that they have no feature updates.
NOTE
This topic records feature updates of boards. However, new board hardware is not recorded
as feature updates. For details, see the "Availability" section.
2.6.1 OSN 9800 Feature Updates

The physical-layer clock (OTN) feature is available since the OSN 9800 of
V100R001C20. The physical-layer clock (SDH and packet) feature is available since
the OSN 9800 of V100R001C30.

WDM OTN
Updates in V100R021C10SPC300 Compared with V100R021C00SPC300

Feature Update Reason for the Change Information Update
The clock The product function is 2.2.3 Clock Source Port

synchronization GE enhanced.
optical port supports the
cascading mode.


synchronization GE enhanced. 2.5 Specifications
optical port is newly
supported.

Feature Reason for Information Update
Update the Change
The OptiX Added a new 2.4.4 OSN 9800 M Series Hardware and
OSN 9800 subrack to Version Support
M05 subrack support basic
configured functions.
with the
TME1CTU/
TME2CTU
board is
added to
support
physical-layer
clocks.
The TNU5CTU The product 2.4.3 OSN 9800 U Series Hardware and
board of the function is Version Support
OSN 9800 U enhanced.
series subrack
is added to
support
physical-layer
clocks.

WDM OTN

Update the Change
The TNG4CXP The product 2.4.4 OSN 9800 M Series Hardware and
OSN 9800 enhanced.
M24 subrack
is added to
support
physical-layer
clocks.

Update the Change
The OSN Added a new 2.4.4 OSN 9800 M Series Hardware and
9800 M12 subrack to Version Support:
subrack is support basic Added OSN 9800 M12 subrack-related
added to functions. information.
support
physical-layer
clocks.
The TNU4CTU The product ● 2.4.3 OSN 9800 U Series Hardware and
board of the function is Version Support: Added the TNU4CTU
OSN 9800 U enhanced. board.
series subrack ● 2.8.1 Configuring Physical-Layer Clocks
is added to (OSN 1800/8800/9800Universal Platform
support Subrack/M Series/P Series/(U Series:
physical-layer U2CTU/S2CTU/U4CTU/U5CTU)): Added
clocks. the TNU4CTU board.
OSN 9800 enhanced.
M24 subrack
is added to
support
physical-layer
clocks.

WDM OTN
Updates in V100R007C00 Compared with V100R006C10

Update the Change
The OSN The product 2.4.2 OSN 9800 P Series Hardware and
9800 P series function is Version Support:
subrack is enhanced. Added the description of the OSN 9800 P
added to series subrack.
support
physical-layer
clocks.
and TNS2CTU function is Version Support: Added TNU2CTU and
boards of the enhanced. TNS2CTU.
OSN 9800 U ● 2.8.1 Configuring Physical-Layer Clocks
series subrack (OSN 1800/8800/9800Universal Platform
are added to Subrack/M Series/P Series/(U Series:
support U2CTU/S2CTU/U4CTU/U5CTU)): Added
physical-layer TNU2CTU and TNS2CTU.
clocks.
When The product 2.5 Specifications:

equipped with function is Added the description that the OSN 9800 U
the TNU2CTU enhanced. series subrack supports clock cascading
or TNS2CTU between master and slave subracks.
board, the
OSN 9800 U
series
subracks
support clock
cascading
between
master and
slave
subracks.
Updates in V100R006C00 Compared with V100R005C10SPC200

The OSN 9800 M24 Added a new subrack to 2.4.4 OSN 9800 M
subrack is added to support basic functions. Series Hardware and
support physical-layer Version Support:
clocks. Added OSN 9800 M24
subrack-related
information.

WDM OTN
Updates in V100R001C30SPC100 Compared with V100R001C30

The OSN 9800 U16 Added a new subrack to 2.4.3 OSN 9800 U Series
subrack is added to support basic functions. Hardware and Version
support physical-layer Support:
clocks. The OSN 9800 U16
subrack is added.
The NMS GUI for The NMS GUI is 2.8.2 Configuring

physical-layer clocks of optimized. Physical Clocks(OSN
OSN 9800 U64/U32/U16 9800 U Series: U1CTU/
subracks is modified. S1CTU):
The entire section is
added.
Updates in V100R001C20
The feature is available Physical-layer clock The entire chapter is

since this version. synchronization is a added.
method of recovering
clock frequencies from
physical signals. Physical-
layer clock
synchronization is used
to implement frequency
synchronization among
upstream and
downstream devices so
that services are
transmitted correctly.
2.6.2 OSN 8800&6800 Feature Updates

The physical clock (OTN) is available since the OSN 8800 of V100R002C00 version
and the OSN 6800 of V100R005C00 version. The physical clock (SDH & Packet) is
available since the OSN 8800 of V100R007C00 version.

WDM OTN
Updates of V100R009C10SPC300 Compared with V100R009C10SPC200

Feature Update Reason for the Update Information Update
The TN54TOG, The timeout duration for ● 2.8.1.3 Configuring

TN54TOA, TN57TOA, SSM packets is now the Synchronization
and TN54THA boards flexibly configured (it is Attributes of a Board:
are added to support fixed at 5s in the past). In The procedure for
the setting of SSM this way, the receive rate setting SSM Timeout
Timeout Period of SSM packets is Period (500ms) is
(500ms). increased, improving the added.
SSM quality. ● 2.8.1.15.2
Parameters: Clock
Attribute
Configuration: SSM
Timeout Period
(500ms) is added.
Updates of V100R008C10 Compared with V100R008C00SPC200

The OSN 8800 universal The clock functions are 2.3 Dependencies and
platform subrack newly enhanced. Limitations:
supports physical clocks. Descriptions of the OSN
8800 universal platform
subrack are added.
The TN12STG board is The product function is 2.4.5 OSN 8800

added, and it supports enhanced. Hardware and Version
clock source acquisition. Support:
Descriptions of the
TN12STG board are
added.

The 10GE LAN port NMS GUI element None.

mapping mode of the modification.
TN55TQX, TN53TDX,
and TOX boards are
changed from MAC
transparent mapping
(10.7G) support 1588
to MAC transparent
mapping (10.7G).

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Updates of V100R007C00 Compared with V100R006C03

The physical clock (SDH The product function is Descriptions of physical

& Packet) is available. enhanced. clock (SDH & Packet) are
added.
The EX2 and EG16 To enhance the clock 2.4.5 OSN 8800
boards are added, and functions of packet Hardware and Version
they support physical service boards. Support:
clocks. A description is added to
explain that packet
service boards support
physical clocks.
The TOA board supports This feature update is to None.

physical clock extend the range of
synchronization when clocks at the physical
OTU1 signals are layer.
provisioned on the client
side.
The service types for the NMS GUI element None.

TOG, TOA, and THA modification.
boards are changed
from GE (TTT-AGMP) to
GE (TTT-GMP).
Clock Source Hold-Off The Clock Source Hold- ● 2.8.1.8 Configuring

Time newly added for Off Time parameter is Clock Attributes: The
the clock feature. added for the clock Clock Source Hold-
feature. This parameter Off Time
specifies the time period configuration process
from the point when a is described.
clock source switching ● 2.8.1.15.12
condition is generated to Parameters: Clock
the point when a clock Source Reversion
source switchover occurs. Parameter: A
description of Clock
Source Hold-Off Time
is added.

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SSM Input Quality The SSM Input Quality ● 2.8.1.8 Configuring

Threshold newly added Threshold parameter Clock Attributes: The
for the clock feature. specifies the quality SSM Input Quality
thresholds of external Threshold
clocks to facilitate clock configuration process
source selection. When is described.
selecting a clock source, ● 2.8.1.15.8
the SSM algorithm Parameters: Clock
compares the quality of Source Quality: A
a clock source with the description of SSM
SSM input quality Input Quality
threshold specified for Threshold is added.
the clock source.
● If the quality of the
clock source is worse
than the specified
SSM Input Quality
Threshold, an
SSM_QL_FAILED
alarm is reported and
the clock source is
identified as invalid.
● If the quality of the
clock is better than or
the same as the
specified SSM Input
Quality Threshold,
the clock quality is
transparently
transmitted for the
clock to participate in
clock source selection.

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SSM Output Quality The SSM Output ● 2.8.1.10 Querying

Threshold newly added Quality Threshold Clock
for the clock feature. parameter specifies the Synchronization
quality threshold of a Status: The SSM
clock that an NE outputs. Output Quality
● When the SSM output Threshold
quality of the NE is configuration process
better than or the is described.
same as the specified ● 2.8.1.15.14
SSM Output Quality Parameters: Clock
Threshold, the Synchronization
specified threshold is Status: A description
considered as the SSM of SSM Output
output quality and Quality Threshold is
transmitted added.
downstream.
● If the SSM output
quality of the NE is
poorer than the
specified SSM Output
Quality Threshold,
the actual SSM output
quality is transmitted
downstream.

N/A Information optimization 2.8.1.14 Configuring the

ST2/AST4/AST2 Board to
Transparently Transmit
Clock Signals:
An example is provided
showing how to
configure the ST2 board
to transparently transmit
clock signals.

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N/A Information optimization 2.4.5 OSN 8800

Hardware and Version
Support:
Information is added to
show whether a tributary
board processes
synchronous Ethernet
packets under a specific
client service
configuration.

This section describes the start versions and change history of the physical-layer
clock (OTN, SDH, and packet) feature.
Table 2-41 Start versions supporting this feature
Feature Start Version
Physical-layer clock ● 1800 V V100R003C05

● 1800 II Enhanced V100R007C10
● 1800 I&II Compact V100R005C20
● 1800 II TP V100R009C00
● 1800 V Pro V100R019C10
● 1800 II Pro V100R019C10


supported. 2.8.1.1 Configuration
Process
2.8.1.5 Configuring a
Main AUX Board
2.8.1.7 Configuring the
Cascading Status of a
Clock GE Optical Port

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The new 1800 V Pro This subrack is new to Added 2.4.11 OSN 1800
chassis supports the product and should V Pro Hardware and
physical-layer clocks. support basic device Version Support.
functions.
The new 1800 II Pro This subrack is new to Added 2.4.12 OSN 1800
chassis supports the product and should II Pro Hardware and
functions.

The new 1800 II TP This subrack is new to Added 2.4.13 OSN 1800
chassis supports the product and should II TP Hardware and
functions.

Feature Reason for the Change Information
Update Update
The new 1800 This subrack is new to the product and should Added 2.4.9
I Enhanced support basic device functions. OSN 1800 I
chassis Enhanced
supports Hardware
physical-layer and Version
clocks (SDH Support.
and packet).

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Update Update
The new 1800 This subrack is new to the product and should Added 2.4.8
II Enhanced support basic device functions. OSN 1800 II
chassis Enhanced
supports Hardware
physical-layer and Version
clocks (OTN, Support.
SDH, and
packet).
2.7 Standard and Protocol Compliance

This section describes the standards and protocols specific to clocks.
The standards specific to clock synchronization are listed below:
● ITU-T G.810: Definitions and terminology for synchronization networks
● ITU-T G.811: Timing characteristics of primary reference clocks
● ITU-T G.812: Timing requirements of slave clocks suitable for use as node
clocks in synchronization networks
● ITU-T G.813: Timing characteristics of SDH equipment slave clocks (SEC)
● ITU-T G.823: The control of jitter and wander within digital networks which
are based on the 2048 kbit/s hierarchy
● ITU-T G.825: The control of jitter and wander within digital networks which
are based on the synchronous digital hierarchy (SDH)
● ITU-T G.8261/Y.1361: Timing and Synchronization aspects in Packet Networks
● ITU-T G.8262: Timing characteristics of synchronous Ethernet equipment slave
clock
● ITU-T G.781: Synchronization layer functions
2.8 Configuration Guide (NCE)
2.8.1 Configuring Physical-Layer Clocks (OSN

1800/8800/9800Universal Platform Subrack/M Series/P
Series/(U Series: U2CTU/S2CTU/U4CTU/U5CTU))
2.8.1.1 Configuration Process

This section describes the physical-layer clock configuration process.
Configure physical-layer clocks to implement frequency synchronization and query
the clock synchronization status. For details, see Figure 2-24 and Table 2-42.

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Figure 2-24 Physical-layer clock configuration process
Table 2-42 Clock configuration process

Operation Description
2.8.1.2 Configuring the Frequency Mandatory.

Source Mode Before configuring clocks, you need to
set the frequency source mode as
required.
● If physical-layer clock frequency
synchronization is used, select
Physical Synchronization.
● If IEEE 1588v2 frequency
synchronization is used, select PTP
Synchronization.
2.8.1.3 Configuring the Optional.

Synchronization Attributes of a When the boards are used to provide
Board clock synchronization, Synchronous
Clock Enabled, Service Type, and Port
Mapping must be set.
2.8.1.4 Configuring the Clock Center Optional.

Subrack When an NE is equipped with master
and slave subracks, you need to
specify a subrack with a clock board as
the clock center subrack. If other
subracks receive clock signals from the
upstream or output clock signals to
the downstream, you need to set the
clock cascading relationship between
these subracks and the clock center
subrack and correctly connect the
subracks.
When the OSN 1800 NE is equipped
with master and slave subracks, only
the master subrack can function as the
clock center subrack.

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2.8.1.5 Configuring a Main AUX Optional.

Board When an OSN 1800 NE is configured
with multiple AUX boards (F1AUX/
B1AUX/B2AUX), you need to set one
AUX board as the main AUX board.
The AUX board of the OSN 1800 has
use restrictions. For details, see use
restrictions in 2.3.1 Feature
Limitations.
NOTE
Only the OSN 1800 supports this function.
2.8.1.6 Configuring External Clock Optional.

Ports When an NE needs to receive or
transmit external clock signals, you
must set Port Cascading. The external
port of a clock board can be used to
receive external clock signals. In
addition, the external port can be used
for cascading the clock boards within a
multi-subrack NE.
To prevent clock signal deterioration,
you must add a BITS clock source for
clock compensation when more than
10 NEs are configured. In this case,
you must set Phase-Locked Source
Output of External Clocks.
2.8.1.7 Configuring the Cascading Optional.

Status of a Clock GE Optical Port When clock cascading between the
master and slave subracks needs to be
implemented through the clock GE
optical port, the cascading status of
the corresponding port needs to be set
to Enabled.
NOTE
Before using a clock synchronization GE
optical port, you need to add the port on
the NE Panel so that the port can be used
as a clock cascading port or synchronous
Ethernet port.

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2.8.1.8 Configuring Clock Attributes Mandatory.

This operation specifies the priority of
each required clock source. This
provides a criterion for selecting clock
sources in case of a clock switching
event. To provide a clock source
selection basis for each clock source
during clock switching, you must set
parameters System Clock Source
Priority Table, 2M External Clock
Source Priority Table, Clock Quality,
and Higher-Priority Clock Source
Reversion.
2.8.1.9 Configuring Clock Source Mandatory.

Protection Physical-layer clock synchronization
supports selecting and switching a
clock source under three SSM protocol
modes:
● Non-SSM protocol: Clock source
protection is not required.
● Standard SSM protocol: The
standard SSM protocol and SSM
output must be configured.
● Extended SSM protocol: The
extended SSM protocol, clock
subnet, and SSM output must be
configured.
2.8.1.10 Querying Clock Mandatory.

Synchronization Status After all the clock configuration
operations are completed, query all
ports and ensure that the port
synchronization status is the same as
that in the networking diagram.
2.8.1.11 Querying the Clock View Mandatory.

Correct clock tracing relationships are
critical to ensure network-wide clock
synchronization. Using NCE, you can
monitor the clock tracing status of
each NE.

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2.8.1.12 Configuring Clock Source Optional.

Switching When the clock source quality
deteriorates, you need to manually
switch clock sources, including setting
clock source switching conditions,
enabling clock source switching, and
starting clock source switching.
2.8.1.2 Configuring the Frequency Source Mode

In practical application, the frequency source mode of an NE must be configured
before configuring a clock.
Prerequisites
You are an NMS user with "Operator Group" privilege or higher.
Procedure
Step 1 Configure the frequency source mode.
NOTE
Before configuring clocks, you need to set the frequency source mode as required.
● If physical-layer clock frequency synchronization is used, select Physical
Synchronization.
● If IEEE 1588v2 frequency synchronization is used, select PTP Synchronization.
----End

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2.8.1.3 Configuring the Synchronization Attributes of a Board

To achieve time synchronization, the Service Type, Port Mapping, Synchronous
Clock Enabled, and SSM Timeout Period (500ms) parameters must be correctly
set for relevant boards.
Prerequisites
Context
NOTICE
Changing the service type between GE(TTT-GMP) and GE(GFP-T) for a board will
interrupt services on the board. After the operation, the services will be
NOTICE
For the OSN 6800, changing the value of Synchronous Clock Enabled for a board
will cause a transient service interruption on the board.
Procedure
Step 1 Set Service Type and Port Mapping for OTN boards.
For details about how to configure synchronous Ethernet on each board, see 2.4
Availability.
Step 2 Optional: Configure Synchronous Clock Enabled. For details about the
parameters, see 2.8.1.15.2 Parameters: Clock Attribute Configuration.

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Step 3 Optional: When the following boards are interconnected with third-party devices,
you must set parameter SSM Timeout Period (500ms) for these boards to
guarantee SSM quality. You do not need to configure other boards. For details
about the parameters, see 2.8.1.15.2 Parameters: Clock Attribute Configuration.
NOTE
Only the following boards support this parameter:

● OSN 8800: TN54TOG, TN54TOA, TN57TOA, and TN54THA
● OSN 1800: TNF5TOA, TNF6TOA, TNF2ELOM (STND), TNF3ELOM
----End
2.8.1.4 Configuring the Clock Center Subrack

In the case of an NE that is equipped with master and slave subracks, you need to
specify a subrack with a clock board as the clock center subrack.

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Prerequisites
Procedure
Step 1 Configure the clock center subrack.
----End
2.8.1.5 Configuring a Main AUX Board

When an OSN 1800 NE is configured with multiple AUX boards (F1AUX/B1AUX/
B2AUX), you need to set one AUX board as the main AUX board.
Prerequisites
Context
● In the master/slave subrack scenario, the main AUX board must be configured
on the master subrack.
● For the use restrictions on the external clock/time ports of the TMB1AUX/
TMB2AUX board, see Table 2-9.
Procedure
Step 1 Configure the main AUX board.

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----End
2.8.1.6 Configuring External Clock Ports

This section describes how to configure attributes of external clocks for a device so
that the device can properly extract external clock signals. These attributes include
the cascading mode of external clock ports on clock boards and PLL output.
Prerequisites
● You are an NMS user with "Operator Group" privilege or higher.
● A clock board and a clock interface board have been created.
NOTICE
For the OSN 1800, if the TNF1AUX board is required, you must create the STG
logical board and then the AUX logical board. Otherwise, the external clock/
time port of the TNF1AUX board cannot work properly. In this case, you need
to delete and re-create the logical AUX board.
● For the OSN 6800, when concatenation of the external ports of a clock board
is configured, the 120-ohm external clock port cable should be used as the
network cable for concatenation.
NOTE
When an NE is equipped with master and slave subracks, you need to specify a subrack
with a clock board as the clock center subrack. If other subracks receive clock signals from
the upstream or output time signals to the downstream, you need to set the clock
cascading relationship between these subracks and the clock center subrack and correctly
connect the subracks. For details, see 2.8.1.4 Configuring the Clock Center Subrack under
2.8.1.1 Configuration Process.
When an OSN 1800 NE is configured with multiple AUX boards (F1AUX/B1AUX/B2AUX),
you need to set one AUX board as the main AUX board. For details, see 2.8.1.5 Configuring
a Main AUX Board under 2.8.1.1 Configuration Process.

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Configuring the External Port Cascading Mode for Clock Boards

The external port of a clock board can be used to receive external clock signals. In
addition, the external port can be used for cascading the clock boards within a
multi-subrack NE.
● Each subrack has two clock ports and two time ports. These ports are used to
concatenate and transmit the clock or time signals among multiple subracks,
or are used to input or output external clock and time signals. By default,
Enabled Status of all ports is Unused. If any ports need to be used for the
input or output of external clock and time signals, Enabled Status of the
corresponding ports should be set to Disabled. One NE supports a maximum
of two ports for the input or output of external clock and time signals.
● After PTP Synchronization is enabled for an NE, the NE automatically
switches the frequency source mode to Physical Synchronization when
Enabled Status of the external clock port on the NE's clock board changes
from Enabled to Disabled or changes from Unused to Disabled. When this
occurs, manually set the frequency source mode of the NE to PTP
Synchronization.
NOTE
For details about the ports that support the cascading mode, see "Clock cascading between
master and slave subracks" in 2.5 Specifications.
Step 1 Configure Enabled Status. For details about the parameters, see 2.8.1.15.3
Parameters: Clock Port Link.
----End
Configuring Phase-Locked Source Output of External Clocks

When a clock signal passes through 10 or more NEs, frequency offset and drift
may occur. As a result, the clock signal transmitted to the downstream NE is
degraded. To prevent this from happening, you must add a BITS clock source for
clock compensation when more than 10 NEs are configured and configure the 2M
phase-locked source for links to optimize clock signals.
Step 1 Configure Phase-Locked Source Output by External Clock. For details about the
parameters, see 2.8.1.15.16 Parameters: Phase-Locked Source Output by

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External Clock.
NOTE
In the case of forced shutdown of the output of external clocks, the 2 Mbit/s and 2 MHz
two external clocks are shut down and there is no output signal from the two clocks. This
operation has a higher shutdown priority than all other automatic shutdown functions
provided by software. By default, the forced shutdown of the external clock output is
disabled.
----End
2.8.1.7 Configuring the Cascading Status of a Clock GE Optical Port

When clock cascading between the master and slave subracks needs to be
implemented through the clock GE optical port, the cascading status of the
corresponding port needs to be set to Enabled.
Prerequisites
● A clock synchronization GE optical port has been created on the NE Panel.
● Synchronous Clock Enabled of the clock synchronization GE optical port has

been correctly set.

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NOTE
Clock Cascading Status can be set to Enabled only when Synchronous Clock
Enabled of the clock synchronization GE optical port is set to Disabled. Clock
Cascading Status can be set to Disabled only when Synchronous Clock Enabled is
set to Enabled. For details, see Step 2 in 2.8.1.3 Configuring the Synchronization
Attributes of a Board.
Context
Clock cascading (frequency synchronization) and PTP cascading (time
synchronization) of clock synchronization GE optical ports can be configured
separately.
Enabled: The port works in cascading mode and is used for clock cascading
between master and slave subracks. The cascading port runs the internal protocol
of the NE.
● When Clock Cascading Port is set to Enabled, the cascading port does not
need to be added to the clock source priority list of the physical clock.
● When PTP Cascading Port is set to Enabled, you do not need to create a PTP
port.
Disabled: When the port works in the common synchronous Ethernet or PTP
mode, it supports interconnection with other NEs or devices.
● When Clock Cascading Port is set to Disabled, you need to add this
cascading port to the clock source priority list of the physical clock.
● When PTP Cascading Port is set to Disabled, you need to create a PTP port
as planned.
Procedure
Step 1 Configure the cascading mode of the clock GE optical port.
----End
2.8.1.8 Configuring Clock Attributes

Clock attributes include system clock source priority table, 2M external clock
source priority table, clock quality, and clock source reversion mode.

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Prerequisites
● The required boards have been created.
Precautions
NOTICE

Configuring the System Clock Source Priority Table

Configuring the system clock source priority table specifies the priority of each
required clock source. This provides a criterion for selecting clock sources in the
event of clock switching.
Step 1 Configure System Clock Source Priority List.
NOTE
● The internal clock source has the lowest priority.

● The clock sources are arranged in a descending order according to their priorities.
● An NE supports a maximum of 32 clock sources.
● Before you configure physical clock synchronization at sites A and B, configure the clock
source priority table for sites A and B. If site A needs to trace clocks from site B, set the
clock source priority of site B to 1. If site B needs to trace clocks from site A, set the
clock source priority of site A to 1. If there are sites A, B, and C, site A needs to trace
clocks from site B, and site B needs to trace clocks from site C, set the clock source
priority of the most upstream site (site C) to 1.
Step 2 Select a clock source and click or to adjust the clock source
priority.

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Step 3 Optional: Select a clock source and then click Delete to delete the clock source.
For details about the parameters, see 2.8.1.15.4 Parameters: System Clock
Source Priority List.
----End
Configuring the 2M External Clock Source Priority Table

required external clock source. This provides a criterion for selecting clock sources
in the event of clock switching.
Step 1 Check the 2M PLL clock source of the external clock port.
NOTE
● The relationship between the 2M PLL clock source and the external clock port depends
on the sequence of setting the cascaded external ports on the clock board.
● When the optical supervisory channel and clock transmission unit is AST2/AST4, the 2M
priority table cannot be configured.
Step 2 Configure Priority for PLL Clock Sources of 1st External Output or Priority for
PLL Clock Sources of 2nd External Output.
priority.
NOTE
External 2M output clock sources can be independently configured in a priority table.

Specifically, you can configure the line clock sources of the equipment as phase-locked
sources or the external clock sources as independent phase-locked sources.
Step 4 Click Apply to deliver the configuration data.
For details about the parameters, see 2.8.1.15.5 Parameters: Priority for PLL
Clock Sources of 1st External Output and 2.8.1.15.6 Parameters: Priority for
----End

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Configuring the Quality of Clock Sources

In a complex clock network, there may be some unknown clock sources, which are
defined as unavailable clocks to prevent NEs from tracing incorrect clock sources.
The NEs automatically obtain the quality information of the clock sources that
have been allocated to them. You need to define the quality level of clock sources
only during testing and maintenance.
Step 1 Configure Clock Quality. For details about the parameters, see 2.8.1.15.8
Parameters: Clock Source Quality.
NOTE
The default value Automatic Extraction is recommended for most situations.
NOTE
The SSM source selection algorithm of an NE first compares the quality level of a clock
source with the SSM Input Quality Threshold.
● SSM Input Quality Threshold: indicates the lowest input clock quality level. By
default, the value is Not Inferior to G.813 SETS Clock Signal.
● If the quality level is lower than the value of SSM Input Quality Threshold, the NE
reports an SSM_QL_FAILED alarm, and specifies the clock source as unavailable.
● If the quality level is higher than or the same as SSM Input Quality Threshold, the
NE transparently transmits the quality level of the clock source so that the source
selection flow selects the clock as its clock source.

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Step 2 Configure Manual Setting of 0 Quality Level. For details about the parameters,
see 2.8.1.15.9 Parameters: Manual Setting of Quality Level 0.
----End
Configuring the Clock Source Reversion Mode

If multiple clock sources are configured for an NE, set the clock sources to
automatic reversion mode, so that the deteriorated clock source automatically
becomes the traceable clock reference after it recovers.
Step 1 Configure Higher-Priority Clock Source Reversion, Clock Source WTR

Time(min), and Clock Source Hold-Off Time(100ms) accordingly. For details
about the parameters, see 2.8.1.15.12 Parameters: Clock Source Reversion
Parameter.

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NOTE
● To prevent repeated switching when the clock is unstable, do not set Clock Source WTR
Time(min) to 0.
● Clock Source Hold-Off Time(100ms): The default value is 0, indicating that the hold-
off timer is disabled. The Clock Source Hold-Off Time(100ms) can be set within the
range of 300 ms to 1800 ms with the step length of 100 ms.
● When a clock source for an NE fails, the clock failure status is sent to the source
selection flow only after the time specified by Clock Source Hold-Off Time(100ms)
elapses. This ensures that a short-term clock signal failure is not sent to the source
selection flow for clock source switching.
----End
2.8.1.9 Configuring Clock Source Protection

In a complex clock network, clock protection needs to be configured for all NEs.
The standard SSM protocol or extended SSM protocol can be enabled to prevent
NEs from tracing incorrect clock sources and to implement clock protection.
Prerequisites
● The relevant board has been created.
Configuring the SSM Protocol

Step 1 Configure Start Standard SSM Protocol or Start Extended SSM Protocol. If you
select Start Extended SSM protocol, you also need to set Clock Source ID of
Clock Source. For details about the parameters, see 2.8.1.15.7 Parameters: Clock
Subnet.

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NOTICE
If the extended SSM protocol is enabled, you are not advised to change the ID of
the clock source being traced by the master NE when the clock tracing
performance is stable. This ensures proper transmission of clock IDs and prevents
a clock loop.
NOTE
● The same SSM protection protocol must be used within the same clock protection subnet.
● Allocate the same subnet number to NEs tracing the same clock source.
Step 2 Optional: If the Clock Source ID is specified for the line clock of an NE, click the
Clock ID Output tab, and set the Output Clock ID to Enabled. Click Apply. For
details about the parameters, see 2.8.1.15.11 Parameters: Clock ID Status.
----End
Configuring SSM Output

If the standard SSM or extended SSM protocol is enabled, the output clock signals
carry SSM messages automatically. You can prevent clock sources from sending
SSM messages to other clock subnets. This ensures that the equipment of different
clock subnets does not affect each other at the edge of clock networks.

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Step 1 Set SSM Output. For details about the parameters, see 2.8.1.15.10 Parameters:
SSM Output Control.
----End
2.8.1.10 Querying Clock Synchronization Status

If the clocks between NEs in the network are not synchronized, pointer
justification errors, bit errors, and even service interruption may occur on the NE.
Using the NCE, you can ascertain and monitor the synchronization status of the
NE clocks.
Prerequisites
You are an NMS user with "Guests" privilege or higher.
Procedure
Step 1 Query the clock synchronization status.

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NOTE
● SSM Output Quality Threshold: indicates the highest output clock quality level. By
default the value is G.811 Clock Signal.
● If the SSM quality level of an NE is equal to or higher than SSM Output Quality
Threshold, the specified SSM Output Quality Threshold is sent to the downstream NE.
● If the SSM quality level is lower than the specified SSM Output Quality Threshold, the
actual clock quality level is sent to the downstream NE.
----End
2.8.1.11 Querying the Clock View

Correct clock tracing relationships are critical to ensure network-wide clock
synchronization. In the clock view, you can monitor the clock tracing status of
each NE.
Prerequisites
Context
When the clock tracing relationship changes, NCE automatically updates the
tracing relationship in the clock view.
Procedure
Step 1 In the Main Topology, select Clock View from the Current View drop-down list.
Then, select an NE whose clocks are to be queried or set from the Object Tree.
Step 2 In the Clock View, right-click and choose Search Clock Link from the shortcut
menu.
Step 3 In the Search Clock Link window, set Clock Type and Search Mode, select the NE
to be queried, and click OK.
Step 4 In the Result dialog box, click Close.
Step 5 View the clock tracing relationships of NEs.
----End

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2.8.1.12 Configuring Clock Source Switching

When the clock source quality deteriorates, you need to manually switch clock
sources, including setting clock source switching conditions, enabling clock source
switching, and starting clock source switching.
Prerequisites
● The clock source has been created.
Configuring Clock Source Switching Conditions

Users can specify conditions for switching a line clock source of an NE so that the
NE switches to other clocks when the clock source fails, minimizing the impact on
services.
Step 1 Double-click the parameter column and set the alarms and performance events
that are to be used as the clock source switching conditions to Yes. For details
about the parameters, see 2.8.1.15.15 Parameters: Clock Source Switching
Conditions.
----End
Enabling Clock Source Switching

Enabling or disabling the clock source switching function for a configured clock
source is actually a process of unlocking or locking the clock source.

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Step 1 Enable clock source switching. For details about the parameters, see 2.8.1.15.13
Parameters: Clock Source Switching.
----End
Performing Clock Source Switching

When the traceable clock source in a network deteriorates, clock switching may
not occur on downstream NEs. At this time, you must manually switch the clock
source to prevent clock deterioration from affecting services.
NOTICE
The clock source switching may cause service interruption.
Step 1 Perform clock source switching, including the operation of selecting Forced
Switching or Manual Switching.
NOTE
Before switching the clock source, ensure that a new clock source that is not locked and
that has better quality is created in the priority table.

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Step 2 Optional: To restore the automatic clock source selection mode, right-click the
switched clock source and choose Clear Switching.
----End
2.8.1.13 Configuring Clock Attributes of Boards to Implement Synchronous

Ethernet Transparent Transmission
OTUs or tributary boards provide the synchronous Ethernet transparent
transmission function to transparently transmit frequency signals only but not
extract or synchronize the frequency signals. To implement synchronous Ethernet
transparent transmission, ensure that the Service Type and Port Mapping values
of boards are correctly specified on NCE.
Prerequisites
Context
NOTE
When a board supports synchronous Ethernet transparent transmission, before changing

the value of Port Mapping for a port on the board from bit transparent mapping to MAC
transparent mapping, you must delete the port from the clock priority table.
NOTICE
Procedure
Step 1 Set Service Type and Port Mapping.
Availability.

WDM OTN
----End
2.8.1.14 Configuring the ST2/AST4/AST2 Board to Transparently Transmit

Clock Signals
When no clock board is configured for an OLA site, you are advised to configure
the ST2/AST4/AST2 board at the site to transparently transmit physical-layer
clocks and IEEE 1588v2 clocks. In other words, use the board to transparently
transmit frequency/phase signals to the downstream site but not extract or
process the frequency/phase signals.
Prerequisites
● Required boards have been created.
Context
Figure 2-25 Configuring the board to transparently transmit clock signals
Procedure
Step 1 Configure clock pass-through. For details about the parameters, see 2.8.1.15.17
Parameters: Clock Signal Pass-through.

WDM OTN
Step 2 Optional: You can delete clock pass-through on the NMS as required. Select the
existing clock pass-through record and click Delete. In the Are you sure to
delete? dialog box that is displayed, click OK.
----End
2.8.1.15 Parameters: Physical Clock (OSN 1800/8800/9800Universal Platform

Subrack/M Series/P Series/(U Series: U2CTU/S2CTU/U4CTU/U5CTU))
This chapter describes the parameters in process of configurations.
2.8.1.15.1 Parameters: Frequency Source Mode

In this user interface, you can specify the mode of the frequency source that the
NE traces according to the network planning.
Navigation Path
In the NE Explorer, select an NE and then choose Configuration > Clock >
Frequency Source Mode from Function Tree.
Parameters
Field Value Description
NE Name For example: NE7183 Displays the NE name.

WDM OTN
Frequency Source Mode Physical Synchronization, Indicates the mode of

PTP Synchronization the frequency source
that the NE traces.
NOTE
Before configuring clocks,
you need to set the
frequency source mode as
required.
● If physical-layer clock
frequency
synchronization is used,
select Physical
Synchronization.
● If IEEE 1588v2
frequency
select PTP
Synchronization.
2.8.1.15.2 Parameters: Clock Attribute Configuration

In this window, you can set and query Synchronous Clock Enabled, Synchronous/
Asynchronous Mode, and SSM Timeout Period (500ms) for clocks.
Navigation Path
In the NE Explorer, click the NE and choose Configuration > Clock > Clock
Attribute Configuration.
Parameters
Clock Board Example: Shelf8(Slave Chooses a clock board.

shelf8)-5-53TDX(STND)
Port Example: Shelf8(Slave Displays the clock port.

-4(RX2/TX2)
Synchronous Clock Valid values include ● Enabled: Synchronous

Enabled Disabled and Enabled. Ethernet is supported.
Default value: Disabled ● Disabled:
Synchronous Ethernet
is not supported.

WDM OTN
Synchronous/ - Sets the clock port to

Asynchronous Mode work in synchronous
mode or asynchronous
mode. The equipment
does not support this
parameter.

WDM OTN
SSM Timeout Period 0 to 120 When the following

(500ms) Default: 10 boards are
interconnected with
third-party devices, you
must set parameter SSM
Timeout Period
(500ms) for these
boards to guarantee SSM
quality. You do not need
to configure other
boards. For details about
the parameters, see
2.8.1.15.2 Parameters:
Clock Attribute
Configuration.
When the reference
source port configured in
the priority table cannot
extract valid SSM
information within the
consecutive time
specified by SSM
Timeout Period
(500ms), the port
reports an SSM_LOS
alarm to perform clock
source switching.
NOTE
Only the following boards
support this parameter:
● OSN 8800: TN54TOG,
TN54TOA, TN57TOA,
and TN54THA
● OSN 1800: TNF5TOA,
TNF6TOA, TNF2ELOM
(STND), TNF3ELOM
NOTE
● This parameter is valid
only when
Synchronous Clock
Enabled is set to
Enabled.
● The unit is 500 ms.
Therefore, the actual
timeout period is 500
times of the specified
value. For example, if
the value is 10, the
actual timeout period
will be 5s (10 x 500
ms).

WDM OTN
2.8.1.15.3 Parameters: Clock Port Link

In this user interface, you can set whether the external ports on clock boards are
used for concatenating the clock signals among the clock boards in the multiple
subracks on an NE.
Navigation Path
In the NE Explorer, select an NE and then choose Configuration > Clock > Port
Cascading from Function Tree.
Parameters
Port shelf ID (shelf name)- Displays the port name.

slot number-board
name-external clock
interface, shelf ID (shelf
name)-slot number-
board name-external
time interface

WDM OTN
Enabled Status Enabled, Disabled, The Enable Status

Unused parameter provides an
Default: Unused option to enable or
disable the external port
on the clock board as a
cascading port.
In the case of the maser-
slave subracks, clock
synchronization are
based on the cascading
ports. If this parameter is
set improperly, the
master and slave
subracks fail to maintain
clock synchronization or
time synchronization.
● Enabled: Indicates
that the external port
is used as a cascading
port.
● Disabled: Indicates
inputs/outputs the
external clock/time.
● Unused: Indicates that
the external port is
unused.
2.8.1.15.4 Parameters: System Clock Source Priority List

In this window, you can query, modify and set the priority list of clock sources,
select the external clock source mode, and select the tributary board for tributary
clock source.
Navigation Path
In the NE Explorer, select an NE and choose Configuration > Clock > Physical
Layer Clock > Clock Source Priority from the Function Tree. Click the System
Clock Source Priority List tab.

WDM OTN
Parameters
Parameter Value Description
Clock source Internal Clock Source, The clock sources in the

External Clock Source, list used by the current
Subrack ID (subrack NE have different
name)-slot number- priorities according to
board name-port their sequences, with the
number (port name) uppermost clock source
having the highest
priority.
An NE supports a
maximum of 32 clock
sources.
NOTICE
It is recommended that
two clock sources in
different directions be
configured for a single site
to implement protection. If
a site is configured with
three or more clock
sources, strictly check the
clock tracing relationship
during clock source
switching to prevent clock
loops.
Other Fiber End Example: NE2- Indicates the port

Shelf18(subrack)-18-11 connected to the clock
ST2-2(RM2/TM2) source by a fiber.
External Clock Source 2Mbit/s, 2MHz Indicates the input signal

Mode Default value: 2Mbit/s format of the external
clock source.
● 2Mbit/s: 2 Mbit/s
signals
● 2MHz: 2 MHz signals
The clock frequency can
be extracted from the
input external clock
signals only when the
parameter value is the
same as the format of
the input clock signals
from the external clock
source.

WDM OTN
Synchronous Status Byte SA4, SA5, SA6, SA7, SA8 Specifies the timeslots
Default value: SA4 for the SSM quality
information in the input
external clock signals.
● SA4: sa4 timeslot
This parameter is valid
only when External
Clock Source Mode is
set to 2Mbit.
Clock Source Priority An integer greater than Displays the priority

Sequence (Highest: 1) or equal to 1 sequence of this clock
source.
2.8.1.15.5 Parameters: Priority for PLL Clock Sources of 1st External Output
When you need to use the line clock source of the equipment as the phase-locked
source, you must configure the priority table for phase-locked sources in this user
interface. In this user interface, you can also query and set priority table for phase-
locked sources of first external output clocks and adjust the priority of each clock
source.
The available clock source with the highest priority can be used as the phase-
locked source to lock the phase of first external output clock. An internal source
can be assigned with the lowest priority level only.
NOTE
When two 2M phase-locked loops (PLLs) are required to track line sources, it is
recommended that the 2M PLLs of OSN 9800 universal platform subracks be used. The 2M
PLLs of OSN 9800 electrical subrack is used to track system clock sources by default.
Navigation Path
In the NE Explorer, select the NE and choose Configuration > Clock > Physical
Layer Clock > Clock Source Priority from the Function Tree. Click the Priority for
PLL Clock Sources of 1st External Output tab.
Parameters
Clock Source For example: Internal Displays the name of the

Clock Source clock source.

WDM OTN
Other Fiber End For example: NE2- Indicates the port

Shelf18(subrack)-18-11S connected to the clock
T2-2(RM2/TM2) source by a fiber.
Current Status Valid, Invalid Displays the active state

of the clock source. If the
clock source exists, its
active state is displayed
as Valid.
S1 Byte For example: The S1 Byte Received

Synchronous Source parameter indicates the
Unavailable value of the S1 byte of
the current traced source
in the system clock
priority table.
This field displays no
information until the S1
byte (clock protection
function) is activated.
● SDH equipment
timing source (SETS)
signal: Indicates that
the clock quality of
the current traced
source is 0x0b.
● G.812 Local Clock:
Indicates that the
clock quality of the
current traced source
is 0x08.
● G.812 Transit Clock:
Indicates that the
is 0x04.
● G.811 Reference
Clock: Indicates that
the current traced
source is 0x02.
● Synchronous Source
Unavailable: Indicates
that the clock quality
of the current traced
source is 0x0f.

WDM OTN
Lock Status Lock, Unlock Sets the locking state of

Default: Unlock the clock source, which is
usually set to Unlock.
● Lock: Indicates that a
certain channel of
clock source in the
priority table is in the
lock status where the
switching of clock
sources is not
allowed.
● Unlock: Indicates that
a certain channel of
clock source in the
unlock status where
the switching of clock
sources is allowed.
Switching Source For example: 18- Displays the switched

ST2-2(RM2/TM2) clock source that the NE
For example: Internal is tracing.
Clock Source
Current Trace Source For example: 18- Displays the clock source
ST2-2(RM2/TM2) that the NE is currently
For example: Internal tracing.
Clock Source
Switching Status Forced Switching, Displays the switching

Manual Switching, status of clock source.
Normal
2.8.1.15.6 Parameters: Priority for PLL Clock Sources of 2nd External Output
interface. You can also query and set priority table for phase-locked sources of
second external output clocks and adjust the priority of each clock source.
locked source to lock the phase of second external output clock. An internal
source can be assigned with the lowest priority level only.
NOTE

WDM OTN
Navigation Path
In the NE Explorer, click the NE and choose Configuration > Clock > Physical
Layer Clock > Clock Source Priority from the Function Tree. On the page that is
displayed, click the Priority for PLL Clock Sources of 2nd External Output tab.
Parameters



as Valid.

WDM OTN

in the system clock
priority table.
● SDH equipment
the current traced
source is 0x0b.
Indicates that the
is 0x08.
Indicates that the
is 0x04.
● G.811 Reference
the current traced
source is 0x02.
source is 0x0f.

WDM OTN

certain channel of
clock source in the
switching of clock
sources is not
allowed.
clock source in the
unlock status where
sources is allowed.

Clock Source
Clock Source

Normal
2.8.1.15.7 Parameters: Clock Subnet

In this interface, you can query, set or activate clock subnets, clock source IDs, the
SSM protocol and the S1 byte of an NE.
Navigation Path
Physical Clock > Clock Subnet Configuration > Physical Clock Subnet
Configuration from the Function Tree. Click the Clock Subnet tab.

WDM OTN
Parameters
Affiliated Subnet 0 to 255 This field enables you to

Default: 0 set the clock subnet
number of the NE.

WDM OTN
Protection Status Start Extended SSM The Protection Status

Protocol, Start Standard parameter indicates the
SSM Protocol, Stop SSM working mode of the
Protocol clock protocol for a clock
Default: Stop SSM subnet.
Protocol The protection status of
the entire clock subnet
should be consistent. To
avoid a clock tracing
loop on a ring or mesh
network, it is
recommended that you
set this parameter to
Start Extended SSM
Protocol.
● Non-SSM protocol
– When the SSM
protocol is
disabled, clock
signals do not
contain clock
quality
information. Clocks
are selected based
on the specified
clock source
priorities. In this
mode, clock loops
may occur.
– This mode is used
on a non-ring
network with
multiple clock
sources. The clock
source is selected
according to the
clock source
priority list.
● Standard SSM
protocol
– When the standard
SSM protocol is
enabled, clock
quality levels are
used to prevent
clock loops.
on a non-ring

WDM OTN
network with
multiple clock
sources. The clock
signal carries
quality
information. It is
used when the
WDM/OTN device
interconnects with
a third-party
device.
● Extended SSM
protocol
– When the
extended SSM
protocol is
enabled, clock
source IDs are
introduced to
prevent clock
loops.
– This protocol is
applicable only to
a ring network. It
is a Huawei
proprietary
protocol and
cannot be used
when the
WDM/OTN device
interconnects with
a third-party
device. If the
extended SSM
protocol is enabled
on an NE, the
standard SSM
protocol can be
configured on the
downstream NEs;
however, if the
standard SSM
protocol is enabled
on an NE, the
extended SSM
protocol cannot be
configured on the
downstream NEs.
It is recommended

WDM OTN
that the extended

SSM protocol be
enabled on ring
networks.
Clock Source Internal Clock Source, This field displays the

External Clock Source, configured clock source
Shelf ID (shelf name)- of the NE. You can either
slot number-board add or delete a clock
name-port number (port source in the clock
name) source priority list.
Clock Source ID 1 to 15 The Clock Source ID

Default: None parameter provides an
option to set an ID for a
clock source. ITU-T
defines only the lower
four bits of the S1 byte
and Huawei defines the
higher four bits of the S1
byte as the clock source
ID. In the case of a
network fault, an NE
may trace its own clock
and the clock cross-
tracing problem may
occur. The clock source
ID helps avoid such a
problem.
When the system traces
an external clock source
or a clock source of
another clock subnet,
this parameter should be
set. For the line clock
sources of other subnets,
however, this parameter
does not need to be set.
2.8.1.15.8 Parameters: Clock Source Quality

In this user interface, you can query the clock source quality and set the clock
source parameters, such as configuration quality and clock quality.
Navigation Path
Configuration from the Function Tree. Click the Clock Quality tab. Click the
Clock Source Quality tab.

WDM OTN
Parameters

External Clock Source, name of the configured
Shelf ID (shelf name)- clock source. You can
slot number-board either add or delete a
name-port number (port clock source in the clock
Configured Quality Unknown The Configured Quality

Synchronization Quality, parameter provides an
G.811 Clock Signal, G. option to set the
812 Transit Clock Signal, configuration quality
G.812 Local Clock Signal, level of a clock source.
G.813 SDH Equipment This parameter is
Timing source (SETS) applicable to certain
Signal, Do Not Use For special scenarios or tests
Synchronization, and therefore does not
Automatic Extraction need to be set in most
Default: Automatic cases.
Extraction When the parameter
value changes, the clock
source selecting protocol
re-selects a clock source.
As a result, a clock
source switching may
occur.
Set this parameter only
when a clock source
does not contain the
clock quality information
or the clock quality
information contained in
a clock source is not
required. For example, in
the case of an external
clock in 2MHz mode,
this parameter needs to
be set.

WDM OTN
Received Quality - The Received Quality

parameter indicates the
quality information
about the clock source
received by an NE. When
receiving a clock source,
the NE extracts the clock
quality information from
the S1 byte in the clock
source.
In most cases, the clock
source of the highest
quality is most likely to
be selected as the
current clock source.

WDM OTN
SSM Input Quality Not Inferior to G.811 Indicates the threshold

Threshold Clock Signal, Not Inferior of input clock sources
to G.812 Transit Clock quality for an NE. The
Signal, Not Inferior to G. clock sources are
812 Local Clock Signal, specified for the NE
Not Inferior to G.813 according to this
SETS Clock Signal threshold.
Default: Not Inferior to The SSM source selection
G.813 SETS Clock Signal algorithm of an NE first
compares the quality
G.811 Clock Signal, G. level of a clock source
812 Transit Clock Signal, with the SSM Input
G.812 Local Clock Signal, Quality Threshold.
G.813 SETS Clock Signal
● If the quality level is
Default: G.813 SETS lower than the SSM
Clock Signal Input Quality
Threshold, the NE
reports an
SSM_QL_FAILED
alarm, and specifies
the clock source as
invalid.
higher than or the
same as the SSM
Input Quality
Threshold, the NE
transparently
transmits the quality
level of the clock
source to the normal
select flow so that the
normal select flow
selects the clock as its
clock source.
2.8.1.15.9 Parameters: Manual Setting of Quality Level 0

In this user interface, you can query and set the quality level of a clock.
Navigation Path
Manual Setting of Quality Level tab.

WDM OTN
Parameters
Quality Level 0 Do Not Use For The Quality Level 0

Synchronization, G.811 parameter provides an
Reference Clock, option to set the quality
Between G.811 level when the quality
Reference Clock and G. information of a clock
812 Transit Clock, G.812 source is unknown.
Transit Clock, Between G. According to the SSM
812 Transit Clock and G. protocol, when the
812 Local Clock, G.812 quality level of a clock
Local Clock, Between G. source is 0, it indicates
812 Local Clock and that the clock
synchronous equipment information of the clock
timing source (SETS), source is unknown.
SETS Clock, Between Hence, the SSM protocol
synchronous equipment enables compatibility
timing source (SETS) and with the signal source
quality unavailable that does not support
Default: Do Not Use For the SSM protocol. To
Synchronization include a clock source
with unknown quality
information in the SSM
protocol, a quality level
should be defined for the
clock source.
All the clock sources with
unknown quality
information can be
included in the source
selecting protocol. This
parameter has an impact
on selection of the clock
source.
Set this parameter
according to the quality
of the unknown clock
sources in the system
and the specific
application scenarios of
the unknown clock
sources.
When the quality level of
a clock source is
manually set as
unknown, set the quality
level for the clock source
similarly.

WDM OTN
2.8.1.15.10 Parameters: SSM Output Control

In this user interface, you can decide whether the clock signal that the equipment
outputs through the external clock interface contains SSM messages.
Navigation Path
Configuration from the Function Tree. Click the SSM Output tab.
Parameters
Line Port External Clock Source, This field displays the

Shelf ID (shelf name)- line port and the
slot number-board external clock
name-port number interface name.
(port name)

Shelf18(subrack)-18-1 connected to the
1ST2-2(RM2/TM2) clock source by a
fiber.
Output S1 Byte Info Enabled, Disabled Output S1 Byte Info-

Default: Enabled Enables an NE in a
clock subnet to send
SSM messages to the
NEs in other clock
subnets if the
standard or extended
SSM protocol is
enabled. In normal
situation, however,
this parameter should
be disabled to
prevent mutual
interference of clock
subnets.
This parameter is
valid only for the line
clock source.
2.8.1.15.11 Parameters: Clock ID Status

When you create a clock subnet or handle a clock fault, you can distinguish
different clock sources by clock ID. In this user interface, you can query and set the
enabling status of clock IDs.

WDM OTN
Navigation Path
Configuration from the Function Tree. Click the Clock ID Output tab.
Parameters
Line Port Shelf ID (shelf name)- This field displays the

slot number-board name of the tributary
name-port number (port and line port.
name)

Output Clock ID Enabled, Disabled This field allows you to

Default: Enabled set whether the output
service through the port
carries any clock ID
signal or not.
2.8.1.15.12 Parameters: Clock Source Reversion Parameter

In this user interface, you can query and set the reversion mode and WTR time of
clock sources.
Navigation Path
Clock > Clock Source Switching from the Function Tree. Click the Clock Source
Reversion tab.
Parameters
NE Name For example: NE18 Displays the name of an

NE.

WDM OTN
Higher-Priority Clock Auto-Revertive, Non- If two clock sources have

Source Reversion Revertive the same quality level
Default: Auto-Revertive but different priorities,
the NE automatically
switches to the clock
source with a lower
priority when the clock
source with a higher
priority is degraded.
When the clock source
with a higher priority
recovers, you can set the
Higher-Priority Clock
Source Reversion
parameter to determine
whether to enable the
NE to automatically
switch to the clock
priority.

WDM OTN
Clock Source WTR 0 to 12 The Clock Source WTR

Time(min) Default: 5 Time(min) parameter
provides an option to set
the time from detection
of signal recovery to
triggered response of the
clock selector. The WTR
time is set to prevent the
clock selector from
responding to a transient
signal recovery. In this
manner, the clock signals
are re-selected as the
clock source only when
the synchronous clock
signals recover from a
failure and stay valid
within the WTR time.
Within the WTR time,
the recovered clock
signals are still
considered invalid for
the quality of the
recovered clock signals is
still QL_DNU according
to the SSM protocol.
That is, the clock signals
are unavailable.

WDM OTN
Clock Source Hold-Off 0, 3 to 18, step length is Indicates the hold-off

Time(100ms) 1. time of a clock source
Default: 0 switching event.
● By default the value is
0, which means that
the hold-off timer is
disabled.
● When a clock source
for an NE fails, the
status of the clock is
sent to the select flow
only after the
specified Clock
Source Hold-Off
Time(100ms) elapses
so that the NE can
determine whether to
select another clock
source. The Clock
Source Hold-Off
Time(100ms) ensures
that a short-term
clock signal failure is
not sent to the select
flow for clock source
switching.
2.8.1.15.13 Parameters: Clock Source Switching

In this user interface, you can query the clock source switching status and perform
clock source switching.
Navigation Path
Switching tab.
Parameters

External Clock Source, configured clock source.
Shelf ID (shelf name)-
slot number-board
name-port number (port
name)

WDM OTN
Current Status Valid, Invalid This field shows the

clock source is valid or
invalid. For query only.
Lock Status Lock, Unlock This field allows you to

enable or disable the
switching operation.
Switching Source Internal Clock Source, This field displays the

External Clock Source, switched clock source
Shelf ID (shelf name)- that the NE is tracing.
slot number-board
name)
Switching Status Forced Switching, This field displays the

Manual Switching, switching status of clock
Normal source.
2.8.1.15.14 Parameters: Clock Synchronization Status

In this user interface, you can query clock synchronization status of equipment,
and set NE clock working mode, synchronous source and data output method in
the holdover mode.
Navigation Path
Clock > Clock Synchronization Status from the Function Tree.
Parameters

NE.

WDM OTN
NE Clock Mode Tracing Mode, Holdover The NE Clock Mode

Mode, Free-Run Mode parameter indicates the
current working mode of
the clock board on the
NE. The NE selects the
best clock source by
running a protocol. If the
best clock source is not
the local clock, the clock
board is in the tracing
mode. In the tracing
mode, if all the clock
sources are lost, the
clock board switches to
the holdover mode. If
the priority table
contains only the local
clock source, the clock
board directly switches
to the free-run mode.
● Tracing Mode:
Indicates the normal
working mode. When
there are services on
the NE, the NE
maintains
synchronization with
the input reference
clock source.
● Holdover Mode:
Indicates that the
local clock considers
the stored frequency
information as the
timing reference
when all the reference
clock sources are lost.
● Free-Run Mode:
Indicates that the
local clock functions
on the basis of the
internal oscillator.

WDM OTN
S1 Byte Synchronous Synchronous Source Specifies the

Quality Info Unavailable, Quality synchronization quality
Unknown, G.811 information in the S1
Reference Clock, G.812 byte that is output by
Transit Clock, G.812 the currently traced
Local Clock, SDH synchronous source.
equipment timing source The S1 Byte
(SETS) signal Synchronous Quality
Info parameter indicates
the quality of the traced
clock source. As defined
in the SSM protocol,
each clock source
corresponds to a certain
quality level. The clock
of the highest priority
and quality is selected
according to the
protocol.
Unavailable: indicates
that the SSM protocol
is disabled and the S1
byte synchronization
quality information
output by the
synchronous source is
not available.
● Quality Unknown:
indicates that the
SSM protocol is
enabled but the S1
quality information
output by the
unknown.
● G.811 Reference
Clock: indicates that
the SSM protocol is
enabled and the S1
quality information
output by the
the G.811 reference
clock.
indicates that the

WDM OTN
SSM protocol is
enabled and the S1
quality information
output by the
the G.812 transit
clock.
indicates that the
SSM protocol is
enabled and the S1
quality information
output by the
the G.812 local clock.
● SDH equipment
signal: indicates that
the SSM protocol is
enabled and the S1
quality information
output by the
the synchronous
equipment timing
source (SETS) clock.
S1 Byte Clock Synchronous Source Specifies the

Synchronous Source Unavailable, Quality synchronization quality
equipment timing source The S1 Byte Clock
(SETS) signal Synchronous Source
best clock source. As
defined in the SSM
protocol, the entire NE
traces the best clock
source, that is, the clock
source with the highest
quality and priority.

WDM OTN
Synchronous Source External Clock Source, Displays the trace source

Shelf ID (shelf name)- of the current NE clock.
slot number-board For query only.
name-port number (port Normally, the
name) synchronous source
should be a clock source
with the highest priority
among the clock
stratums. If the
synchronous source
cannot be traced, try to
trace a clock source with
a lower priority level
according to the
sequence of the clock
stratums.
Data Output Method in Normal Data Output, The Data Output

Holdover Mode Keep the Latest Data Method in Holdover
Default: Normal Data Mode parameter
Output provides an option to set
the method of
outputting data in
holdover mode. When all
the clock sources of an
NE are lost, the NE
enters the holdover
mode. The NE may keep
the latest data forever or
maintain the holdover
state for 24 hours or a
specified period. If the
NE maintains the
holdover state, the NE
switches to the free-run
mode when the period
of 24 hours or a
specified period expires.

WDM OTN
SSM Output Quality G.811 Clock Signal, G. Indicates the threshold

Threshold 812 Transit Clock Signal, of output clock sources
G.812 Local Clock Signal, quality for an NE.
G.813 SETS Clock Signal ● If the clock quality
Default: G.811 Clock level of an NE is equal
Signal to or higher than SSM
Output Quality
Threshold, the
Quality Threshold is
sent to the
downstream NE.
● If the clock quality
level is lower than the
Quality Threshold,
the actual clock
quality level is sent to
the downstream NE.
SSM Input Quality G.811 Clock Signal, G. Indicates the threshold

Threshold 812 Transit Clock Signal, of input clock sources
G.812 Local Clock Signal, quality for an NE. The
G.813 SETS Clock Signal clock sources are
Default: G.811 Clock specified for the NE
Signal according to this
threshold.
lower than the SSM
Input Quality
Threshold, the NE
reports an
SSM_QL_FAILED
the clock source as
invalid.
higher than or the
same as the SSM
Input Quality
Threshold, the NE
transparently
level of the clock
normal select flow
clock source.

WDM OTN
2.8.1.15.15 Parameters: Clock Source Switching Conditions

In this user interface, you can query and set clock source switching conditions, and
the status of switching condition enabling.
Navigation Path
Switching Conditions tab.
Parameters
Clock Source Shelf ID (shelf name)- This field displays the

slot number-board name of the clock
name-port number (port source.
name)
OTU1_DEG Alarm Yes, No Specifies the switching

Default: No condition enabling
status.
When an OTU1_DEG
alarm occurs in the NE,
the NE regards that the
corresponding clock
source fails.
OTU2_DEG Alarm Yes, No This field allows you to

Default: No set the switching
condition enabling
status. When an
OTU2_DEG alarm occurs
in the NE, the NE
regards that the
corresponding clock
source fails.

condition enabling
status. When an
in the NE, the NE
regards that the
corresponding clock
source fails.

WDM OTN

condition enabling
status. When an
in the NE, the NE
regards that the
corresponding clock
source fails.
ODU2_PM_AIS Alarm Yes, No This parameter allows

Default: No you to set the switching
condition enabling
status.
When an ODU2_PM_AIS
corresponding clock
source fails.
ODU2_PM_DEG Alarm Yes, No This parameter allows

condition enabling
status.
When an
ODU2_PM_DEG alarm
occurs in the NE, the NE
regards that the
corresponding clock
source fails.
MS_AIS Alarm Yes, No Sets the switching

Default: No condition enable status.
When an MS_AIS alarm
regards that the
corresponding clock
source fails.
B2_EXC Alarm Yes, No This field allows you to

condition enabling
status. When an B2_EXC
corresponding clock
source fails.

WDM OTN
2.8.1.15.16 Parameters: Phase-Locked Source Output by External Clock

In this window, you can set the external clock source attributes of the 2M phase-
locked source. In the system clock phase-locked state, you can set the clock output
mode, output timeslot, output threshold, and 2 MHz phase-locked source
invalidation condition and action.
Navigation Path
Clock > Phase-Locked Source Output by External Clock from the Function Tree.
Parameters
2M Phase-Locked Source External Clock Source 1, Displays the IDs of

Number External Clock Source 2 outputs from external
clock sources.
External Clock Output 2Mbit/s, 2MHz Specifies the format of

Mode Default value: 2Mbit/s the 2M output clock
signals from the external
clock source.
The 2 MHz clock signals
cannot carry any other
information. If you set
2M Phase-Locked
Source Fail Action to
2M Output S1 Byte
Unavailable or Send
AIS, the failure
information cannot be
transmitted to the
equipment using the
external output clock
signals when the external
output fails.

WDM OTN
External Clock Output ALL, SA4, SA5, SA6, SA7, Specifies the timeslots
Timeslot SA8 used by the SSM quality
Default value: ALL information in the output
clock signals.
● ALL: All timeslots
only when External
Clock Output Mode is
set to 2Mbit/s.
External Source Output Threshold Disabled, Not The External Source

Threshold Inferior to G.813 SETS Output Threshold
Signal, Not Inferior to G. parameter specifies the
812 Local Clock Signal, extent to which the 2M
Not Inferior to G.812 external output clock
Transit Clock Signal, Not signals are degraded to
Inferior to G.811 Clock cause an output failure.
Signal If the SSM protocol is
Default value: Threshold running in the Stop SSM
Disabled Protocol mode, setting
this parameter is
ineffective, because the
current clock source does
not contain quality
information.
When the quality of the
traced clock source is
lower than the specified
threshold, the 2M clock
signals are output
according to the 2M
Phase-Locked Source
Fail Action value.

WDM OTN
2M Phase-Locked Source AIS, LOF, AIS OR LOF, No The 2M Phase-Locked

Failure Condition Failure Condition Source Failure
Default value: No Failure Condition parameter
Condition specifies the alarm in 2M
external input clock as a
condition of an input
failure.
The parameter value has
a direct impact on clock
source selection of the
system. For example,
when the AIS alarm is
not considered as a
failure, the system still
traces the 2M external
input clock and does not
switch the clock sources,
even when the system
detects an AIS alarm.
If the system needs to
trace the external clock
receives the AIS or LOF
alarm, do not enable the
AIS or LOF alarm as a
failure condition.
Otherwise, enable the
failure condition.
● AIS
– If the AIS alarm is
enabled as a failure
condition, the 2M
external input clock
is considered failed
when the system
detects an AIS
alarm.
not enabled as a
failure condition,
the 2M external
input clock is not
considered as a
failure even when
the system detects
an AIS alarm.
● LOF

WDM OTN
– If the LOF alarm is

condition, the 2M
is considered as a
failure when the
system detects a
LOF alarm.
not enabled as a
failure condition,
the 2M external
input clock is not
considered as a
failure even when
the system detects
a LOF alarm.
The AIS or LOF alarm can
be detected only when
the mode of the external
clock source is set to
2Mbit/s. When the mode
of the external clock
source is set to 2MHz,
this parameter is invalid.

WDM OTN
2M Phase-Locked Failure 2M Output S1 Byte The 2M Phase-Locked

Handing Unavailable, Send AIS, Failure Handing
Shut Down Output parameter specifies the
Default value: Shut type of the signals
Down Output output by the external
clock port when the 2M
phase-locked source fails.
Set this parameter
according to the
the external output and
the processing capability
of the equipment that
uses the external output
clock.
● 2M Output S1 Byte
Unavailable:
The external clock
signals are output
normally but the
quality information in
the S1 byte is
unavailable.
● Send AIS:
The external output is
still available and the
AIS signals are output.
● Shut Down Output:
The 2M external
output is disabled
when the phase-
locked source fails.
If the ongoing working
mode of the SSM
protocol is Stop SSM
Protocol, the S1 byte of
the external output clock
is unavailable. In this
case, if you set this
parameter to 2M Output
S1 Byte Unavailable,
this parameter is
ineffective.
When External Clock
Source Mode is set to
2MHz, the S1 byte and
AIS signals cannot be
carried. In this case, if
you set this parameter to

WDM OTN
2M Output S1 Byte
Unavailable or Send
AIS, this parameter is
ineffective.
Force Output Shutdown Enabled, Disabled Allows you to enable or

Default value: Disabled disable the forced
shutdown of outputs.
2.8.1.15.17 Parameters: Clock Signal Pass-through

In this interface, you can query and set the parameters of the clock signal pass-
through.
Navigation Path
In the NE Explorer, click the NE and choose Configuration > Clock > Clock Signal
Pass-through.
Parameters
Source Slot For example: Indicates the source slot

Shelf1(subrack)-22-11ST name.
2
Source Port For example: 1(RM1/ Indicates the source port

TM1) name
Sink Slot For example: Indicates the sink slot

2
Sink Port For example: 2(RM2/ Indicates the sink port

TM2) name.
Pass-through Type PTP Clock Sets the pass-through

type of the clock.
2.8.2 Configuring Physical Clocks(OSN 9800 U Series: U1CTU/

S1CTU)

This topic describes the clock configuration process based on a flow chart.

WDM OTN
Figure 2-26 Configuration process for Physical Synchronization

the clock synchronization status. For details, see Table 2-43.

2.8.2.2 Configuring Transport Clock Optional.

Attributes of Boards When the line boards and tributary
boards are used to provide clock
synchronization, you need to set
Service Type and Port Mapping.

Ports To prevent clock signal deterioration,
you need to add a BITS clock source
for clock compensation when more
than 10 NEs are configured. In this
case, you need to set Phase-Locked
Source Output of External Clocks.
2.8.2.4 Configuring Clock Source Mandatory.

Attributes To provide a clock source selection
basis for each clock source during
clock switching, you need to set
System Clock Source Priority Table,
2M External Clock Source Priority
Table, Clock Quality, and Higher-
Priority Clock Source Reversion.
NOTE
If a port that supports synchronous
Ethernet needs to output synchronous
Ethernet clock signals that carry SSM
information, you need to add the port to
System Clock Source Priority List of the
NE and set Clock Source Priority to 0. For
details about the capabilities of ports
supporting synchronous Ethernet
processing, see 2.4.3 OSN 9800 U Series
Hardware and Version Support.

WDM OTN
2.8.2.5 Configuring the Clock Source Mandatory.

Protection Clock synchronization at the physical
layer supports clock source selection
and switching in the following
scenarios:
● When the SSM protocol is not
enabled, configuring the clock
source protection is not required.
● When the standard SSM protocol is
enabled, enabling standard SSM
protocol is required.
● To enable the extended SSM
protocol, you need to configure the
extended SSM protocol.
2.8.2.6 Querying Clock Mandatory.

ports for the clock synchronization
status to ensure that the port
defined in the networking diagram.
2.8.2.7 Querying Clock Tracing Mandatory.

Status Correct clock tracing relationships are
critical to ensure the clock
synchronization within the entire
network. Using NCE, you can monitor
the clock tracing status of each NE.

switch clock sources. To manually
switch clock sources, perform the
operations of setting clock source
switching conditions, enabling clock
source switching, and starting clock
source switching.
2.8.2.2 Configuring Transport Clock Attributes of Boards

To achieve frequency synchronization of a board, you need to set the Service Type
and Port Mapping of the board on the NCE.
Prerequisites

WDM OTN
Context
NOTE
Since OSN 9800 V100R001C20, you do not need to set Synchronous Clock Enabled for the
OSN 9800.
NOTICE
Procedure
Availability.
Step 2 Add a port to the clock source priority table and set the priority to 0. For details,
see Configuring the System Clock Source Priority Table.
----End

that the device can properly extract external clock signals.
Prerequisites
● The required CTU board has been created.

WDM OTN

multi-subrack NE.
or are used to input or output external clock and time signals. By default, all
these ports are not used. If any ports need to be used for the input or output
of external clock and time signals, the ports should be disabled. One NE
supports a maximum of two ports for the input or output of external clock
and time signals.
from Enabled to Disabled or changes from Unused to Disabled. Therefore,
you need to manually set the frequency source mode of the NE to PTP
Synchronization.
Step 1 Configure Enabled Status.
----End
Procedure
degraded. To prevent this from happening, a 2M phase-locked source must be
used to optimize the clock signal.
Step 1 Set the external clock attributes of the 2M phase-locked source, including the
external clock output switch, output mode, output timeslot, and output threshold.
2.8.2.10.9 Parameters: Phase-Locked Source Output by External ClockFor
details about these parameters, see 2.8.2.10.9 Parameters: Phase-Locked Source
Output by External Clock.
----End
2.8.2.4 Configuring Clock Source Attributes

Clock source attributes include the system clock source priority table, 2M external
clock source priority table, clock source quality, and clock source reversion mode.
Prerequisites

WDM OTN
Precautions
NOTICE


NOTE
If a port that supports synchronous Ethernet needs to output synchronous Ethernet clock
signals that carry SSM information, you need to add the port to System Clock Source
Priority List of the NE and set Clock Source Priority to 0. For details about the capabilities
of ports supporting synchronous Ethernet processing, see 2.4.3 OSN 9800 U Series
----End


WDM OTN
NOTE
The relationship between the 2M PLL clock source and the external clock port depends on
the sequence of setting the cascaded external ports on the clock board.
Step 2 Configure Priority for PLL Clock Sources of 1st External Output List or Priority
for PLL Clock Sources of 2nd External Output List.
NOTE
External 2M output clock sources can be independently configured in a priority table. In

addition, you can configure line clock sources as phase-locked sources, and configure the
priorities of line clock sources in the priority table for the output phase-locked source of the
first or second external clock.
----End

WDM OTN

The NEs automatically obtain quality information of clock sources that are
allocated to them. Therefore, the quality levels of clock sources are defined only
during testing and maintenance.
Step 1 Configure Clock Quality to the desired level. For details about the parameters, see
2.8.2.10.5 Parameters: Clock Source Quality.
NOTE
----End


Parameter.

WDM OTN
NOTE
Time(min) to 0.
● Clock Source HoldOff Time(100ms): The Clock Source HoldOff Time(100ms) can be
set within the range of 300 ms to 1800 ms with the step length of 100 ms.
----End
2.8.2.5 Configuring the Clock Source Protection

After the clock source is set and the clock priority level for the NEs is specified, the
standard SSM or extended SSM protocol can be enabled to prevent the NEs from
tracing an incorrect clock source.
Prerequisites

WDM OTN
Procedure
Step 1 Configure Enable Standard SSM Protocol Control or Enable Extend SSM
Protocol Control.
NOTE
The same SSM protection protocol must be used within the same clock protection subnet.
Step 2 Optional: If the Enable Extend SSM Protocol Control is selected, set the Clock
Source ID of the Clock Source. For details about these parameters, see 2.8.2.10.4
Parameters: Clock Subnet.
NOTICE
a clock loop.
----End

WDM OTN
2.8.2.6 Querying Clock Synchronization Status

If the clocks between NEs in the network are not synchronized, pointer
justification errors, bit errors, and even service interruption may occur on the NE.
Using the NCE, you can ascertain and monitor the synchronization status of the
NE clocks.
Prerequisites
Procedure
Step 1 Query clock synchronization status. For details about the parameters, see
2.8.2.10.8 Parameters: Clock Synchronization Status.
----End
2.8.2.7 Querying Clock Tracing Status

synchronization. Using NCE, you can monitor the clock tracing status of each NE.
Prerequisites
Context
Procedure
menu.

WDM OTN
----End

When a traced clock source degrades, clock switching needs to be performed
manually.
Prerequisites
Procedure
When the traceable clock source in a network deteriorates, NEs may not be able
to execute a switch on the clock source. Users need to manually switch the clock
source to prevent clock deterioration from affecting the normal running of NEs.
NOTICE
Performing clock source switching may cause service interruption.
Step 1 Perform clock source switching, including the operation of selecting Forcible
Source Selection or Manual Source Selection. For details about these

WDM OTN
parameters, see 2.8.2.10.7 Parameters: Clock Source Switching.
switched clock source and choose Clear Source Selection.
----End
2.8.2.9 Configuring Board Attributes to Implement Synchronous Ethernet

Transparent Transmission
of boards are correctly specified on NCE.
Prerequisites
Context
NOTE

NOTICE
Procedure

WDM OTN
Availability.
----End
2.8.2.10 Parameters: Physical Clock(OSN 9800 U Series: U1CTU/S1CTU)

This topic describes the parameters in process of configurations.

In this user interface, you can query, modify and set the priority list of clock
sources, select the external clock source mode, and select the tributary board.
Navigation Path
Layer Clock > Clock Source Priority. Click the System Clock Source Priority List
tab.
Parameters
Clock Source Type For example: Internal Displays the type of the
Clock Source For example: local Displays the name of the

clock source.
External Clock Source 2MBit/s, 2MHz The External Clock

Mode Default: 2MBit/s Source Mode parameter
the format of the input
clock signals from the
external clock source.

WDM OTN
Synchronous Status Sa4, Sa5, Sa6, Sa7, Sa8 The Synchronous Status
Byte Default: Sa4 Byte parameter provides
an option to set the
timeslots for the SSM
the input external clock
signals.
Clock Source Priority (1 0 to 255 Displays the priority

is the highest) Default: 1 sequence of this clock
source.
1 indicates the highest
priority. A larger value
indicates a lower priority.
0 indicates that the clock
source is not a candidate
clock source but is used
to output clock signals.
source.
Navigation Path
Layer Clock > Clock Source Priority. Click the Priority for PLL Clock Sources of
1st External Output List tab.
Parameters

Shelf ID /slot number/ clock source. You can
sub-board number/port either add or delete a
number clock source in the clock
source priority list.

WDM OTN

as Valid.
Clock Source Priority (1 0 to 255 Set the priority sequence

is the highest) Default: 1 of this clock source.
Navigation Path
2nd External Output List tab.
Parameters


as Valid.


WDM OTN

Navigation Path
Layer Clock > Clock Subnet Configuration from the Function Tree. Click the
Clock Subnet Configuration Attribute tab.
Parameters

number of the NE.

WDM OTN
Protection Status Enable Standard SSM The Protection Status

Protocol Control, Enable parameter indicates the
Extend SSM Protocol working mode of the
Control, Disable SSM clock protocol for a clock
Protocol Control subnet.
Default: Disable SSM ● Non-SSM protocol
Protocol Control
– When the SSM
protocol is
disabled, clock
signals do not
contain clock
quality
information. Clocks
are selected based
on the specified
clock source
priorities. In this
mode, clock loops
may occur.
on a non-ring
network with
multiple clock
sources. The clock
source is selected
according to the
clock source
priority list.
● Standard SSM
protocol
SSM protocol is
enabled, clock
quality levels are
used to prevent
clock loops.
on a non-ring
network with
multiple clock
sources. The clock
signal carries
quality
information. It is
used when the
WDM/OTN device
interconnects with
a third-party
device.

WDM OTN
● Extended SSM
protocol
– When the
extended SSM
protocol is
enabled, clock
source IDs are
introduced to
prevent clock
loops.
applicable only to
a ring network. It
is a Huawei
proprietary
protocol and
cannot be used
when the
WDM/OTN device
interconnects with
a third-party
device. If the
extended SSM
protocol is enabled
on an NE, the
standard SSM
protocol can be
configured on the
downstream NEs;
however, if the
standard SSM
protocol is enabled
on an NE, the
extended SSM
protocol cannot be
configured on the
downstream NEs.
It is recommended
that the extended
SSM protocol be
enabled on ring
networks.
Clock Source For example: local This field displays the

configured clock source
of the NE. You can either
add or delete a clock
source in the clock

WDM OTN

Default: 0 parameter provides an
clock source. ITU-T
tracing problem may
problem.

Navigation Path
Clock Quality tab.
Parameters

WDM OTN

name of the configured
clock source. You can
either add or delete a
clock source in the clock
Configured Quality Auto, G.811 Clock, G.812 The Configured Quality

TNC, G.812 LNC, SDH, parameter provides an
Unavailable Clock option to set the
Source, Unknown SSM configuration quality
Level level of a clock source.
Default: Auto This parameter is
applicable to certain
special scenarios or tests
and therefore does not
need to be set in most
cases.
When the parameter
occur.
when a clock source
clock in 2MHz mode,
be set.

WDM OTN

quality information
source.
be selected as the

clock sources.
Navigation Path
Layer Clock > Clock Source Switching. Click the Clock Source Reversion tab.

WDM OTN
Parameters
Field Value Range Description

source with a lower
recovers, the NE may
automatically switch to
the clock source or not.
Whether the NE
automatically switches
to the clock source
depends on the
parameter setting.

WDM OTN
Clock Source WTR 0-12 The Clock Source WTR

clock selector from
the recovered clock
signals are still
the quality of the
are unavailable.

WDM OTN
Clock Source HoldOff 3 to 18. The step is 1. Specifies the time period
Time(100ms) Default: 10 from the point when a
clock source switching
condition is generated to
the point when a clock
source switchover occurs.
When a clock source for
an NE fails, the status of
the clock is sent to the
select flow only after the
specified Clock Source
Hold-Off Time(100ms)
elapses so that the NE
can determine whether
to select another clock
source. This parameter
ensures that a short-
term clock signal failure
is not sent to the select
switching.

Navigation Path
Layer Clock > Clock Source Switching. Click the Clock Source Switching tab.
Parameters

configured clock source.

Switching Status Forcible Source Selection, This field displays the

Manual Source Selection, switching status of clock
Normal source.

WDM OTN
Switching Source Type For example: Internal This field displays the
Clock Source switched clock source
type that the NE is
tracing.
Switching Source For example: local This field displays the

switched clock source
that the NE is tracing.

the holdover mode.
Navigation Path
Layer Clock > Clock Synchronization Status from the Function Tree.
Parameters
NE Clock Mode Free-Run, Fast Lock, The NE Clock Mode

Trace, Hold parameter indicates the
best clock source is the
local clock, the clock
the priority table

WDM OTN
S1 Byte Synchronous - The S1 Byte

Quality Info Synchronous Quality
each clock source
according to the
protocol.
S1 Byte Synchronous - The S1 Byte Clock

Source Synchronous Source
defined in the SSM
Synchronous Source For example: local Displays the trace source

of the current NE clock.
For query only.
Normally, the
synchronous source
among the clock
stratums. If the
synchronous source
according to the
stratums.

WDM OTN
Data Output Method in 24th Keep, Long Term The Data Output
Holdover Mode Keep Method in Holdover
Default: 24th Keep Mode parameter
the method of
outputting data in
NE are lost, the NE
enters the holdover
NE maintains the
of 24 hours or a
Unknown SSM Level G.811 Clock, G.812 TNC, The Unknown SSM
Map G.812 LNC, SDH, Level Map parameter
Unavailable Clock Source provides an option to set
the quality level when
the quality information
of a clock source is
unknown.

In this user interface, you can set the external clock source attributes of the 2M
phase-locked source. You can set the output mode, output timeslot, and output
threshold.
Navigation Path
Physical Layer Clock > Phase-Locked Source Output by External Clock from the
Function Tree.

WDM OTN
Parameters
2M Phase-Locked bits0, bits1 This field displays the

Source Number numbering IDs of the
outputs from external
clock sources.
External Clock Output false, true This field allows you to

Shutdown Default: false enable or disable the
forced shutdown of
outputs.
External Clock Output 2 MBit/s, 2 MHz The External Clock

Mode Default: 2 MBit/s Output Mode parameter
the format of the 2M
output clock signals from
the external clock source.
2M Phase-Locked
2M Output S1 Byte
Unavailable or Send
AIS, the failure
transmitted to the
equipment using the
signals when the
external output fails.

WDM OTN
External Clock Output ALL, Sa4, Sa5, Sa6, Sa7, The External Clock
Timeslot Sa8 Output Timeslot
Default: ALL parameter provides an
option to set the
timeslots used by the
SSM quality information
in the output clock
signals.
only when External
set to 2M Bit/s.
External Source Output Unavailable Clock The External Source

Threshold Source, SDH, G.812 LNC, Output Threshold
G.812 TNC, G.811 Clock parameter provides an
Default: Unavailable option to specify the
Clock Source extent to which the 2M
signals are degraded to
cause an output failure.
If the SSM protocol is
running in the Stop SSM
Protocol mode, setting
this parameter is
not contain quality
information.
signals are output
according to the 2M
Phase-Locked Source
Fail Action value.

WDM OTN
External Source Invalid No Condition, AIS Alarm, The External Source

Condition LOF Alarm, AIS or LOF Invalid Condition
Alarm parameter provides an
Default: No Condition option to specify the
alarm in 2M external
input clock as a
failure.
2MPLL Los External Shutdown External Clock The 2MPLL Los External
Clock Output Action Output, External Clock Clock Output Action
Tx AIS Alarm, External parameter provides an
Clock Tx DNU Level option to specify the
Default: Shutdown type of the signals
External Clock Output output by the external
phase-locked source
fails.
2.9 Configuration Guide (U2000)
2.9.1 Configuring Physical Clocks (OSN 1800/8800/9800

Universal Platform Subrack/M Series Subrack/P Series
Subrack/(U Series Subrack: U2CTU/S2CTU/U4CTU))

This section describes the physical clock configuration process.
Figure 2-27 Physical clock configuration process
Configure physical clocks to implement frequency synchronization and query clock

synchronization status. For details, see Table 2-44.

WDM OTN

2.9.1.2 Mandatory.
Configuring the Before configuring clocks, you need to set the frequency
Frequency source mode as required.
Source Mode
● If physical clock frequency synchronization is used, select
● If IEEE 1588v2 frequency synchronization is used, select
PTP Synchronization.
2.9.1.3 Optional.
Configuring When the boards are used to provide clock synchronization,
Transport Clock Synchronous Clock Enabled, Service Type, and Port
Attributes of Mapping must be set.
Boards
2.9.1.4 Optional.
Configuring the When an NE is equipped with master and slave subracks,
Clock Center you need to specify a subrack with a clock board as the
Subrack clock center subrack. If other subracks receive clock signals
from the upstream or output clock signals to the
downstream, you need to set the clock cascading
relationship between these subracks and the clock center
subrack and correctly connect the subracks.
2.9.1.5 Optional.
Configuring When an NE needs to receive or transmit external clock
External Clock signals, you must set Port Cascading. The external port of a
Ports clock board can be used to receive external clock signals. In
addition, the external port can be used for cascading the
clock boards within a multi-subrack NE.
To prevent clock signal deterioration, you must add a BITS
clock source for clock compensation when more than 10
NEs are configured. In this case, you must set Phase-Locked
2.9.1.6 Mandatory.
Configuring This operation specifies the priority of each required clock
Clock Source source. This provides a criterion for selecting clock sources in
Attributes case of a clock switching event. To provide a clock source
selection basis for each clock source during clock switching,
you must set parameters System Clock Source Priority
Table, 2M External Clock Source Priority Table, Clock
Quality, and Higher-Priority Clock Source Reversion.

WDM OTN
2.9.1.7 Mandatory.
Configuring the Physical clock synchronization supports selecting and
Clock Source switching a clock source under three SSM protocol modes:
Protection
● Non-SSM protocol: Clock source protection is not
required.
● Standard SSM protocol: The standard SSM protocol and
SSM output must be configured.
● Extended SSM protocol: The extended SSM protocol,
clock subnet, and SSM output must be configured.
2.9.1.8 Viewing Mandatory.

Clock After all the clock configuration operations are completed,
Synchronization query all ports and ensure that the port synchronization
Status status is the same as that in the networking diagram.
2.9.1.9 Viewing Mandatory.

the Clock Correct clock tracing relationships are critical to ensure
Tracing Status network-wide clock synchronization. Using U2000, you can
monitor the clock tracing status of each NE.
2.9.1.10 Optional.
Configuring When the clock source quality deteriorates, you need to
Clock Source manually switch clock sources, including setting clock source
Switching switching conditions, enabling clock source switching, and
starting clock source switching.
2.9.1.2 Configuring the Frequency Source Mode

In practical application, the frequency source mode of an NE must be configured
before configuring a clock.
Prerequisites
Procedure

WDM OTN
NOTE
● If physical clock frequency synchronization is used, select Physical Synchronization.
----End

To achieve frequency synchronization, the Service Type, Port Mapping,
Synchronous Clock Enabled, and SSM Timeout Period (500ms) parameters
must be correctly set for relevant boards on the U2000.
Prerequisites
You are an NMS user with Operation Level rights or higher.
Context
NOTICE

WDM OTN
NOTICE
For OSN 6800, changing the value of Synchronous Clock Enabled for a board will
cause a transient service interruption on the board.
Procedure
Step 1 Configure Service Type and Port Mapping in the following way:
Availability.
Step 2 Optional: Configure Synchronous Clock Enabled. For details about the
parameters, see 2.9.1.13.2 Parameters: Clock Attribute Configuration.
Step 3 Optional: When the following boards are interconnected with third-party devices,
you must set parameter SSM Timeout Period (500ms) of the boards to
guarantee SSM quality. You do not need to configure the other boards. For details
about the parameters, see 2.9.1.13.2 Parameters: Clock Attribute Configuration.

WDM OTN
NOTE
This parameter can be set only for the following boards:

● OSN 1800 V: TNF5TOA, TNF6TOA, and TNF2ELOM (STND)
● OSN 1800 I&II compact: TNF2ELOM (STND)
● OSN 1800 II enhanced: TNF2ELOM (STND)
----End
2.9.1.4 Configuring the Clock Center Subrack

In the case of an NE that is equipped with master and slave subracks, you need to
specify a subrack with a clock board as the clock center subrack.
Prerequisites
Procedure
Step 1 Configure the clock center subrack.

WDM OTN
----End

that the device can properly extract external clock signals. These attributes include
the cascading mode of external clock ports on clock boards and PLL output.
Prerequisites
● You are an NMS user with "Operator Group" authority or higher.
● The clock board has been created.
is configured, the 120-ohm external clock port cable should be used as the
network cable for concatenation.

multi-subrack NE.
and time signals.
Synchronization.

WDM OTN
----End
Configuring Phase-Locked Source Output of External Clocks

Step 1 Configure Phase-Locked Source Output by External Clock. For details about the
parameters, see 2.9.1.13.16 Parameters: Phase-Locked Source Output by
External Clock.

WDM OTN
NOTE
In the case of forced shutdown of the output of the external clock, the 2 Mbit/s and 2 MHz
two external clocks are shut down and there is no output signal from the two clocks. This
operation has a higher shutdown priority than all other automatic shutdown functions
provided by software. By default, the forced shutdown of the external clock output is
disabled.
----End
2.9.1.6 Configuring Clock Source Attributes

Clock source attributes include the system clock source priority table, 2M external
clock source priority table, clock source quality, and clock source reversion mode.
Prerequisites
Precautions
NOTICE



WDM OTN
NOTE
● The internal clock source has the lowest priority.

● The clock sources are arranged in a descending order according to their priorities.
● An NE supports a maximum of 32 clock sources.
● Before you configure physical clock synchronization at sites A and B, configure the clock
source priority table for sites A and B. If site A needs to trace clocks from site B, set the
clock source priority of site B to 1. If site B needs to trace clocks from site A, set the
clock source priority of site A to 1. If there are sites A, B, and C, site A needs to trace
clocks from site B, and site B needs to trace clocks from site C, set the clock source
priority of the most upstream site (site C) to 1.
priority.
----End


WDM OTN
NOTE
● The relationship between the 2M PLL clock source and the external clock port depends
on the sequence of setting the cascaded external ports on the clock board.
● When the optical supervisory channel and clock transmission unit is AST2/AST4, the 2M
priority table cannot be configured.
priority.
NOTE
External 2M output clock sources can be independently configured in a priority table.

Specifically, you can configure the line clock sources of the equipment as phase-locked
sources or the external clock sources as independent phase-locked sources.
Step 4 Click Apply to deliver the configuration data.

WDM OTN
----End

allocated to them. You should define the quality level of clock sources only during
testing and maintenance.
Step 1 Configure Clock Quality. For details about the parameters, see 2.9.1.13.8
Parameters: Clock Source Quality.
NOTE
NOTE
The SSM source selection algorithm of an NE first compares the quality level of a clock
source with the SSM Input Quality Threshold.
● SSM Input Quality Threshold: indicates the lowest input clock quality level. By
default, the value is Not Inferior to G.813 SETS Clock Signal.
● If the quality level is lower than the value of SSM Input Quality Threshold, the NE
reports an SSM_QL_FAILED alarm, and specifies the clock source as unavailable.
● If the quality level is higher than or the same as SSM Input Quality Threshold, the
NE transparently transmits the quality level of the clock source so that the source
selection flow selects the clock as its clock source.
Step 2 Configure Manual Setting of Quality Level. For details about the parameters, see
2.9.1.13.9 Parameters: Manual Setting of Quality Level 0.

WDM OTN
----End


Parameter.

WDM OTN
NOTE
Time(min) to 0.
● Clock Source Hold-Off Time(100ms): The default value is 0, indicating that the hold-
off timer is disabled. The Clock Source Hold-Off Time(100ms) can be set within the
range of 300 ms to 1800 ms with the step length of 100 ms.
----End

The standard SSM protocol or extended SSM protocol can be enabled to prevent
NEs from tracing incorrect clock sources and to implement clock protection.
Prerequisites
Configuring the SSM Protocol

Step 1 Configure Start Standard SSM Protocol or Start Extended SSM Protocol. If the
Start Extended SSM protocol is selected, set the Clock Source ID of the Clock
Source. For details about these parameters, see 2.9.1.13.7 Parameters: Clock
Subnet.

WDM OTN
NOTICE
a clock loop.
NOTE
● The same SSM protection protocol must be used within the same clock protection subnet.
● Allocate the same subnet number to NEs tracing the same clock source.
Step 2 Optional: If the Clock Source ID is specified for the line clock of an NE, click the
Clock ID Output tab, and set the Output Clock ID to Enabled. Click Apply. For
details about these parameters, see 2.9.1.13.11 Parameters: Clock ID Status.
----End
Configuring the SSM Output

If the standard SSM or extended SSM protocol is enabled, the clock signals carry
SSM messages automatically. You can prevent clock sources from sending SSM
messages to other clock subnets. This ensures that the equipment of different
clock subnets does not affect each other at the edge of clock networks.
Step 1 Configure SSM Output. For details about these parameters, see 2.9.1.13.10
Parameters: SSM Output Control.

WDM OTN
----End
2.9.1.8 Viewing Clock Synchronization Status

If the clocks between NEs in the network are not synchronous, pointer justification
errors, bit errors, and even service interruption may occur on the NE. Using the
U2000, you can ascertain and monitor the synchronization status of the NE clocks.
Prerequisites
Procedure
Step 1 View clock synchronization status.

WDM OTN
NOTE
● SSM Output Quality Threshold: indicates the highest output clock quality level. By
default the value is G.811 Clock Signal.
● If the clock quality level of an NE is equal to or higher than SSM Output Quality
Threshold, the specified SSM Output Quality Threshold is sent to the downstream NE.
● If the clock quality level is lower than the specified SSM Output Quality Threshold, the
actual clock quality level is sent to the downstream NE.
----End
2.9.1.9 Viewing the Clock Tracing Status

Correct clock tracing relationships are critical to ensure the clock synchronization
within the entire network. Using the U2000, you can monitor the clock trace
status of each NE.
Prerequisites
Context
When the clock tracing relationships are changed, the U2000 automatically
refreshes the tracing status in Clock View.
Procedure
menu.
----End

manually. To manually perform clock source switching, users first need to
configure clock source switching conditions and enable clock source switching.
Prerequisites
Configuring Switching Conditions for Clock Sources

For OSN 8800/OSN 6800/OSN 1800, if the traceable clock source of an NE is a
line clock, you can customize switching conditions for the clock source so that the

WDM OTN
NE switches to other clocks when the clock source fails. Taking this measure will
minimize the impact that a clock failure has on services.
Step 1 Double-click the parameter column and set the alarms and performance events
that are to be used as the clock source switching conditions to Yes. For details
about these parameters, see 2.9.1.13.15 Parameters: Clock Source Switching
Conditions.
----End
Enabling Clock Source Switching

Enabling or disabling the clock source switching function for a configured clock
source is actually a process of unlocking or locking the clock source.
Step 1 Enable clock source switching. For details about these parameters, see 2.9.1.13.13
Parameters: Clock Source Switching.
----End
Switching a Clock Source


WDM OTN
NOTICE
Step 1 Perform clock source switching, including the operation of selecting Forced
Switching or Manual Switching.
NOTE
Before switching the clock source, ensure that a new clock source that is not locked and
that has better quality is created in the priority table.
switched clock source and choose Clear Switching.
----End
2.9.1.11 Configuring Board Attributes to Implement Synchronous Ethernet

Transparent Transmission
of boards are correctly specified on the U2000.
Prerequisites
You are an NMS user with "Operator Group" authority or higher.

WDM OTN
Context
NOTE

NOTICE
Procedure
Availability.
----End
2.9.1.12 Configuring the ST2/AST2/AST4 Board to Transparently Transmit

Clock Signals
When no clock board is configured for an OLA site, you are advised to configure
the ST2/AST2/AST4 board at the site to transparently transmit physical-layer
clocks and IEEE 1588v2 clocks. In other words, use the board to transparently
transmit frequency/phase signals to the downstream site but not extract or
process the frequency/phase signals.
Prerequisites
● You are an NMS user with "Monitor Group" authority or higher.

WDM OTN
● The required boards have been configured at the OLA site.
Context
Figure 2-28 Configuring the board to transparently transmit clock signals
Procedure
Step 1 Configure clock pass-through. For details about the parameters, see 2.9.1.13.17
Parameters: Clock Signal Pass-through.
Step 2 Optional: You can delete clock pass-through on the NMS as required. Select the
existing clock pass-through record and click Delete. In the Are you sure to
delete? dialog box that is displayed, click OK.
----End

WDM OTN
2.9.1.13 Parameters: Physical Clock (OSN 1800/8800/9800 Universal

Platform Subrack/M Series Subrack/P Series Subrack/U Series Subrack:
U2CTU/S2CTU/U4CTU)

Navigation Path
Parameters

that the NE traces.
NOTE
you need to set the
required.
● If physical clock
frequency
select Physical
Synchronization.
● If IEEE 1588v2
frequency
select PTP
Synchronization.
2.9.1.13.2 Parameters: Clock Attribute Configuration

In this window, you can set and query Synchronous Clock Enabled, Synchronous/
Asynchronous Mode, and SSM Timeout Period (500ms) for clocks.
Navigation Path
In the NE Explorer, click the NE and choose Configuration > Clock > Clock
Attribute Configuration.

WDM OTN
Parameters
Clock Board Example: Shelf8(Slave Chooses a clock board.

Port Example: Shelf8(Slave Displays the clock port.

-4(RX2/TX2)
Synchronous Clock Valid values include ● Enabled: Synchronous

Enabled Disabled and Enabled. Ethernet is supported.
Default value: Disabled ● Disabled:
Synchronous Ethernet
is not supported.
Synchronous/ - Sets the clock port to

Asynchronous Mode work in synchronous
mode or asynchronous
mode. The equipment
does not support this
parameter.

WDM OTN
SSM Timeout Period 0 to 120 When the following

(500ms) Default value: 10 boards are
interconnected with
third-party devices, you
must set SSM Timeout
Period (500ms) for
these boards to
guarantee SSM quality.
You do not need to set
this parameter for other
boards. For details about
the parameter, see
2.9.1.13.2 Parameters:
Clock Attribute
Configuration.
When the reference
source port configured in
the priority table cannot
extract valid SSM
information within the
consecutive time
specified by SSM
Timeout Period
(500ms), the port
reports an SSM_LOS
alarm to perform clock
source switching.
NOTE
This parameter can be set
only for the following
boards:
TN54TOA, TN57TOA,
and TN54THA
● OSN 1800 V: TNF5TOA,
TNF6TOA, TNF2ELOM
(STND)
● OSN 1800 I&II
compact: TNF2ELOM
(STND)
● OSN 1800 II enhanced:
TNF2ELOM (STND)

WDM OTN

NOTE
● This parameter is valid
only when
Synchronous Clock
Enabled is set to
Enabled.
● The unit is 500 ms.
Therefore, the actual
timeout period is 500
times of the specified
value. For example, if
the value is 10, the
actual timeout period
will be 5s (10 x 500
ms).

subracks on an NE.
Navigation Path
Parameters

slot number-board
name-external clock
name)-slot number-
board name-external
time interface

WDM OTN

cascading port.
synchronization are
set improperly, the
master and slave
port.
inputs/outputs the
unused.

In this window, you can query, modify and set the priority list of clock sources,
select the external clock source mode, and select the tributary board for tributary
clock source.
Navigation Path
Layer Clock > Clock Source Priority from the Function Tree. Click the System
Clock Source Priority List tab.

WDM OTN
Parameters
Clock Source Internal Clock Source, Displays the clock source

External Clock Source, type. The clock sources
Subrack ID (subrack in the list used by the
name)-slot number- current NE have different
board name-port priorities according to
number (port name) their sequences, with the
uppermost clock source
having the highest
priority.
An NE supports a
maximum of 32 clock
sources.
NOTICE
It is recommended that
two clock sources in
different directions be
configured for a single site
to implement protection. If
a site is configured with
three or more clock
sources, strictly check the
clock tracing relationship
during clock source
switching to prevent clock
loops.
Other Fiber End Example: NE2- Indicates the port

Shelf18(subrack)-18-11 connected to the clock
ST2-2(RM2/TM2) source by a fiber.
External Clock Source 2Mbit/s, 2MHz Indicates the input signal

Mode Default value: 2Mbit/s format of the external
clock source.
● 2Mbit/s: 2 Mbit/s
signals
● 2MHz: 2 MHz signals
If the external input port
is connected to an
external output port of
the local system, the
input mode of the input
port must be consistent
with the output mode of
the output port.

WDM OTN
Synchronous Status Byte SA4, SA5, SA6, SA7, SA8 Specifies the timeslots
Default value: SA4 for the SSM quality
information in the input
external clock signals.
only when External
Clock Source Mode is
set to 2Mbit.
Clock Source Priority An integer greater than Displays the priority

Sequence (Highest: 1) or equal to 1 sequence of this clock
source.
source.
NOTE
Navigation Path
In the NE Explorer, select the NE and choose Configuration > Clock > Physical
PLL Clock Sources of 1st External Output tab.
Parameters


WDM OTN


as Valid.

in the system clock
priority table.
● SDH equipment
the current traced
source is 0x0b.
Indicates that the
is 0x08.
Indicates that the
is 0x04.
● G.811 Reference
the current traced
source is 0x02.
source is 0x0f.

WDM OTN

certain channel of
clock source in the
switching of clock
sources is not
allowed.
clock source in the
unlock status where
sources is allowed.

Clock Source
Clock Source

Normal
NOTE

WDM OTN
Navigation Path
In the NE Explorer, click the NE and select Configuration > Clock > Physical
PLL Clock Sources of 2nd External Output tab.
Parameters



as Valid.

WDM OTN

in the system clock
priority table.
● SDH equipment
the current traced
source is 0x0b.
Indicates that the
is 0x08.
Indicates that the
is 0x04.
● G.811 Reference
the current traced
source is 0x02.
source is 0x0f.

WDM OTN

certain channel of
clock source in the
switching of clock
sources is not
allowed.
clock source in the
unlock status where
sources is allowed.

Clock Source
Clock Source

Normal

Navigation Path
Configuration from the Function Tree. Click the Clock Subnet tab.

WDM OTN
Parameters

number of the NE.

WDM OTN
Protection Status Start Extended SSM The Protection Status

Protocol, Start Standard parameter indicates the
SSM Protocol, Stop SSM working mode of the
Protocol clock protocol for a clock
Default: Stop SSM subnet.
Protocol The protection status of
the entire clock subnet
should be consistent. To
avoid a clock tracing
loop on a ring or mesh
network, it is
recommended that you
set this parameter to
Start Extended SSM
Protocol.
● Stop SSM Protocol:
– When the SSM
protocol is
disabled, clock
signals do not
contain clock
quality
information. Clocks
are selected based
on the specified
clock source
priorities. In this
mode, clock loops
may occur.
on a non-ring
network with
multiple clock
sources. The clock
source is selected
according to the
clock source
priority list.
● Start Standard SSM
Protocol:
SSM protocol is
enabled, clock
quality levels are
used to prevent
clock loops.
on a non-ring

WDM OTN
network with
multiple clock
sources. The clock
signal carries
quality
information. It is
used when the
WDM/OTN device
interconnects with
a third-party
device.
● Start Extended SSM
Protocol:
– When the
extended SSM
protocol is
enabled, clock
source IDs are used
to prevent clock
loops.
applicable only to
a ring network. It
is a Huawei
proprietary
protocol and
cannot be used
when the
WDM/OTN device
interconnects with
a third-party
device. If the
extended SSM
protocol is enabled
on an NE, the
standard SSM
protocol can be
configured on the
downstream NEs;
however, it cannot
be configured on
the NE if the
standard SSM
protocol is enabled
on the upstream
NEs.

WDM OTN

External Clock Source, configured clock source
Shelf ID (shelf name)- of the NE. You can either
slot number-board add or delete a clock
name-port number (port source in the clock

Default: None parameter provides an
clock source. ITU-T
tracing problem may
problem.

Navigation Path
Clock Source Quality tab.

WDM OTN
Parameters

Shelf ID (shelf name)- clock source. You can
slot number-board either add or delete a
name-port number (port clock source in the clock
Configured Quality Unknown The Configured Quality

Synchronization Quality, parameter provides an
G.811 Clock Signal, G. option to set the
812 Transit Clock Signal, configuration quality
G.812 Local Clock Signal, level of a clock source.
G.813 SDH Equipment This parameter is
Timing source (SETS) applicable to certain
Signal, Do Not Use For special scenarios or tests
Synchronization, and therefore does not
Automatic Extraction need to be set in most
Default: Automatic cases.
Extraction When the parameter
occur.
when a clock source
clock in 2MHz mode,
be set.

WDM OTN

quality information
source.
be selected as the

WDM OTN
SSM Input Quality Not Inferior to G.811 Indicates the threshold

Threshold Clock Signal, Not Inferior of input clock sources
to G.812 Transit Clock quality for an NE. The
Signal, Not Inferior to G. clock sources are
812 Local Clock Signal, specified for the NE
Not Inferior to G.813 according to this
SETS Clock Signal threshold.
Default: Not Inferior to The SSM source selection
G.813 SETS Clock Signal algorithm of an NE first
compares the quality
G.811 Clock Signal, G. level of a clock source
812 Transit Clock Signal, with the SSM Input
G.812 Local Clock Signal, Quality Threshold.
G.813 SETS Clock Signal
Default: G.813 SETS lower than the SSM
Clock Signal Input Quality
Threshold, the NE
reports an
SSM_QL_FAILED
the clock source as
invalid.
higher than or the
same as the SSM
Input Quality
Threshold, the NE
transparently
level of the clock
normal select flow
clock source.
2.9.1.13.9 Parameters: Manual Setting of Quality Level 0

In this user interface, you can query and set the quality level of a clock.
Navigation Path
Manual Setting of Quality Level tab.

WDM OTN
Parameters
Quality Level 0 Do Not Use For The Quality Level 0

Synchronization, G.811 parameter provides an
Reference Clock, option to set the quality
Between G.811 level when the quality
Reference Clock and G. information of a clock
812 Transit Clock, G.812 source is unknown.
Transit Clock, Between G. According to the SSM
812 Transit Clock and G. protocol, when the
812 Local Clock, G.812 quality level of a clock
Local Clock, Between G. source is 0, it indicates
812 Local Clock and that the clock
synchronous equipment information of the clock
timing source (SETS), source is unknown.
SETS Clock, Between Hence, the SSM protocol
synchronous equipment enables compatibility
timing source (SETS) and with the signal source
quality unavailable that does not support
Default: Do Not Use For the SSM protocol. To
Synchronization include a clock source
with unknown quality
information in the SSM
protocol, a quality level
should be defined for the
clock source.
All the clock sources with
unknown quality
information can be
included in the source
selecting protocol. This
parameter has an impact
on selection of the clock
source.
Set this parameter
according to the quality
of the unknown clock
sources in the system
and the specific
the unknown clock
sources.
When the quality level of
a clock source is
manually set as
unknown, set the quality
level for the clock source
similarly.

WDM OTN
2.9.1.13.10 Parameters: SSM Output Control

In this user interface, you can decide whether the clock signal that the equipment
outputs through the external clock interface contains SSM messages.
Navigation Path
Configuration from the Function Tree. Click the SSM Output tab.
Parameters
Line Port External Clock Source, This field displays the

Shelf ID (shelf name)- line port and the
slot number-board external clock
name-port number interface name.
(port name)

Shelf18(subrack)-18-1 connected to the
1ST2-2(RM2/TM2) clock source by a
fiber.
Output S1 Byte Info Enabled, Disabled Output S1 Byte Info-

Default: Enabled Enables an NE in a
clock subnet to send
SSM messages to the
NEs in other clock
subnets if the
standard or extended
SSM protocol is
enabled. In normal
situation, however,
this parameter should
be disabled to
prevent mutual
interference of clock
subnets.
This parameter is
valid only for the line
clock source.
2.9.1.13.11 Parameters: Clock ID Status

When you create a clock subnet or handle a clock fault, you can distinguish
different clock sources by clock ID. In this user interface, you can query and set the
enabling status of clock IDs.

WDM OTN
Navigation Path
Configuration from the Function Tree. Click the Clock ID Output tab.
Parameters
Line Port Shelf ID (shelf name)- This field displays the

slot number-board name of the tributary
name-port number (port and line port.
name)

Output Clock ID Enabled, Disabled This field allows you to

Default: Enabled set whether the output
service through the port
carries any clock ID
signal or not.

clock sources.
Navigation Path
Reversion tab.
Parameters

NE.

WDM OTN

source with a lower
recovers, you can set the
Higher-Priority Clock
Source Reversion
parameter to determine
whether to enable the
NE to automatically
switch to the clock
priority.

WDM OTN
Clock Source WTR 0 to 12 The Clock Source WTR

clock selector from
the recovered clock
signals are still
the quality of the
are unavailable.

WDM OTN
Clock Source Hold-Off 0, 3 to 18, step length is Indicates the hold-off

Time(100ms) 1. time of a clock source
Default: 0 switching event.
● By default the value is
0, which means that
the hold-off timer is
disabled.
● When a clock source
for an NE fails, the
status of the clock is
sent to the select flow
only after the
specified Clock
Source Hold-Off
Time(100ms) elapses
so that the NE can
determine whether to
select another clock
source. The Clock
Source Hold-Off
Time(100ms) ensures
that a short-term
clock signal failure is
not sent to the select
switching.

Navigation Path
Switching tab.
Parameters

External Clock Source, configured clock source.
Shelf ID (shelf name)-
slot number-board
name)

WDM OTN

Lock Status Lock, Unlock This field allows you to

enable or disable the
switching operation.
Switching Source Internal Clock Source, This field displays the

External Clock Source, switched clock source
Shelf ID (shelf name)- that the NE is tracing.
slot number-board
name)
Switching Status Forced Switching, This field displays the

Manual Switching, switching status of clock
Normal source.

the holdover mode.
Navigation Path
Clock > Clock Synchronization Status from the Function Tree.
Parameters

NE.

WDM OTN
NE Clock Mode Tracing Mode, Holdover The NE Clock Mode

Mode, Free-Run Mode parameter indicates the
best clock source is not
the local clock, the clock
the priority table
● Tracing Mode:
Indicates the normal
working mode. When
there are services on
the NE, the NE
maintains
synchronization with
the input reference
clock source.
● Holdover Mode:
Indicates that the
local clock considers
the stored frequency
information as the
timing reference
when all the reference
clock sources are lost.
● Free-Run Mode:
Indicates that the
local clock functions
on the basis of the
internal oscillator.

WDM OTN
S1 Byte Synchronous Synchronous Source Specifies the

Quality Info Unavailable, Quality synchronization quality
equipment timing source The S1 Byte
(SETS) signal Synchronous Quality
each clock source
according to the
protocol.
Unavailable: indicates
that the SSM protocol
is disabled and the S1
quality information
output by the
not available.
● Quality Unknown:
indicates that the
SSM protocol is
enabled but the S1
quality information
output by the
unknown.
● G.811 Reference
Clock: indicates that
the SSM protocol is
enabled and the S1
quality information
output by the
the G.811 reference
clock.
indicates that the

WDM OTN
SSM protocol is
enabled and the S1
quality information
output by the
the G.812 transit
clock.
indicates that the
SSM protocol is
enabled and the S1
quality information
output by the
the G.812 local clock.
● SDH equipment
signal: indicates that
the SSM protocol is
enabled and the S1
quality information
output by the
the synchronous
equipment timing
source (SETS) clock.
S1 Byte Clock Synchronous Source Specifies the

Synchronous Source Unavailable, Quality synchronization quality
equipment timing source The S1 Byte Clock
(SETS) signal Synchronous Source
defined in the SSM

WDM OTN
Synchronous Source External Clock Source, Displays the trace source

Shelf ID (shelf name)- of the current NE clock.
slot number-board For query only.
name-port number (port Normally, the
name) synchronous source
among the clock
stratums. If the
synchronous source
according to the
stratums.
Data Output Method in Normal Data Output, The Data Output

Holdover Mode Keep the Latest Data Method in Holdover
Default: Normal Data Mode parameter
Output provides an option to set
the method of
outputting data in
NE are lost, the NE
enters the holdover
NE maintains the
of 24 hours or a

WDM OTN
SSM Output Quality G.811 Clock Signal, G. Indicates the threshold

Threshold 812 Transit Clock Signal, of output clock sources
G.812 Local Clock Signal, quality for an NE.
G.813 SETS Clock Signal ● If the clock quality
Default: G.811 Clock level of an NE is equal
Signal to or higher than SSM
Output Quality
Threshold, the
Quality Threshold is
sent to the
downstream NE.
● If the clock quality
level is lower than the
Quality Threshold,
the actual clock
quality level is sent to
the downstream NE.
SSM Input Quality G.811 Clock Signal, G. Indicates the threshold

Threshold 812 Transit Clock Signal, of input clock sources
G.812 Local Clock Signal, quality for an NE. The
G.813 SETS Clock Signal clock sources are
Default: G.811 Clock specified for the NE
Signal according to this
threshold.
lower than the SSM
Input Quality
Threshold, the NE
reports an
SSM_QL_FAILED
the clock source as
invalid.
higher than or the
same as the SSM
Input Quality
Threshold, the NE
transparently
level of the clock
normal select flow
clock source.

WDM OTN
2.9.1.13.15 Parameters: Clock Source Switching Conditions

In this user interface, you can query and set clock source switching conditions, and
the status of switching condition enabling.
Navigation Path
Switching Conditions tab.
Parameters
Clock Source Shelf ID (shelf name)- This field displays the

slot number-board name of the clock
name-port number (port source.
name)
OTU1_DEG Alarm Yes, No Specifies the switching

Default: No condition enabling
status.
When an OTU1_DEG
corresponding clock
source fails.

condition enabling
status. When an
in the NE, the NE
regards that the
corresponding clock
source fails.

condition enabling
status. When an
in the NE, the NE
regards that the
corresponding clock
source fails.

WDM OTN

condition enabling
status. When an
in the NE, the NE
regards that the
corresponding clock
source fails.
ODU2_PM_AIS Alarm Yes, No This parameter allows

condition enabling
status.
When an ODU2_PM_AIS
corresponding clock
source fails.
ODU2_PM_DEG Alarm Yes, No This parameter allows

condition enabling
status.
When an
ODU2_PM_DEG alarm
regards that the
corresponding clock
source fails.
MS_AIS Alarm Yes, No Sets the switching

Default: No condition enable status.
When an MS_AIS alarm
regards that the
corresponding clock
source fails.
B2_EXC Alarm Yes, No This field allows you to

condition enabling
status. When an B2_EXC
corresponding clock
source fails.

WDM OTN

In this window, you can set the external clock source attributes of the 2M phase-
locked source. In the system clock phase-locked state, you can set the clock output
mode, output timeslot, output threshold, and 2 MHz phase-locked source
invalidation condition and action.
Navigation Path
Clock > Phase-Locked Source Output by External Clock from the Function Tree.
Parameters
2M Phase-Locked Source External Clock Source 1, Displays the IDs of

Number External Clock Source 2 outputs from external
clock sources.
External Clock Output 2Mbit/s, 2MHz The External Clock

Mode Default value: 2Mbit/s Output Mode parameter
specifies the format of
the 2M output clock
signals from the external
clock source.
2M Phase-Locked
2M Output S1 Byte
Unavailable or Send
AIS, the failure
transmitted to the
equipment using the
signals when the external
output fails.

WDM OTN
External Clock Output ALL, SA4, SA5, SA6, SA7, Specifies the timeslots
Timeslot SA8 used by the SSM quality
Default value: ALL information in the output
clock signals.
only when External
set to 2Mbit/s.
External Source Output Threshold Disabled, Not The External Source

Threshold Inferior to G.813 SETS Output Threshold
Signal, Not Inferior to G. parameter specifies the
812 Local Clock Signal, extent to which the 2M
Not Inferior to G.812 external output clock
Transit Clock Signal, Not signals are degraded to
Inferior to G.811 Clock cause an output failure.
Signal If the SSM protocol is
Default value: Threshold running in the Stop SSM
Disabled Protocol mode, setting
this parameter is
not contain quality
information.
signals are output
according to the 2M
Phase-Locked Source
Fail Action value.

WDM OTN
2M Phase-Locked Source AIS, LOF, AIS OR LOF, No The 2M Phase-Locked

Failure Condition Failure Condition Source Failure
Default value: No Failure Condition parameter
Condition specifies the alarm in 2M
external input clock as a
failure.
The parameter value has
a direct impact on clock
source selection of the
system. For example,
when the AIS alarm is
not considered as a
failure, the system still
traces the 2M external
input clock and does not
switch the clock sources,
detects an AIS alarm.
If the system needs to
trace the external clock
receives the AIS or LOF
alarm, do not enable the
failure condition.
Otherwise, enable the
failure condition.
● AIS
condition, the 2M
is considered failed
when the system
detects an AIS
alarm.
not enabled as a
failure condition,
the 2M external
input clock is not
considered as a
failure even when
the system detects
an AIS alarm.
● LOF

WDM OTN

condition, the 2M
is considered as a
failure when the
system detects a
LOF alarm.
not enabled as a
failure condition,
the 2M external
input clock is not
considered as a
failure even when
the system detects
a LOF alarm.
The AIS or LOF alarm can
be detected only when
the mode of the external
clock source is set to
2Mbit/s. When the mode
source is set to 2MHz,
this parameter is invalid.

WDM OTN
2M Phase-Locked Failure 2M Output S1 Byte The 2M Phase-Locked

Handing Unavailable, Send AIS, Failure Handing
Shut Down Output parameter specifies the
Default value: Shut type of the signals
Down Output output by the external
phase-locked source fails.
Set this parameter
according to the
the external output and
the processing capability
of the equipment that
uses the external output
clock.
● 2M Output S1 Byte
Unavailable:
The external clock
signals are output
normally but the
the S1 byte is
unavailable.
● Send AIS:
The external output is
still available and the
AIS signals are output.
● Shut Down Output:
The 2M external
output port is disabled
when the phase-
locked source fails.
If the ongoing working
mode of the SSM
protocol is Stop SSM
Protocol, the S1 byte of
the external output clock
is unavailable. In this
case, if you set this
parameter to 2M Output
S1 Byte Unavailable,
this parameter is
ineffective.
When External Clock
Source Mode is set to
2MHz, the S1 byte and
AIS signals cannot be
carried. In this case, if
you set this parameter to

WDM OTN
2M Output S1 Byte
Unavailable or Send
AIS, this parameter is
ineffective.
Force Output Shutdown Enabled, Disabled Allows you to enable or

Default value: Disabled disable the forced
shutdown of outputs.
2.9.1.13.17 Parameters: Clock Signal Pass-through

In this interface, you can query and set the parameters of the clock signal pass-
through.
Navigation Path
In the NE Explorer, click the NE and choose Configuration > Clock > Clock Signal
Pass-through.
Parameters
Source Slot For example: Indicates the source slot

2
Source Port For example: 1(RM1/ Indicates the source port

TM1) name
Sink Slot For example: Indicates the sink slot

2
Sink Port For example: 2(RM2/ Indicates the sink port

TM2) name.
Pass-through Type PTP Clock Sets the pass-through

type of the clock.
2.9.2 Configuring Physical Clocks(OSN 9800 U Series: U1CTU/

S1CTU)


WDM OTN
Figure 2-29 Configuration process for Physical Synchronization

the clock synchronization status. For details, see Table 2-45.

2.9.2.2 Configuring Transport Clock Optional.

Attributes of Boards When the line boards and tributary
boards are used to provide clock
synchronization, you need to set
Service Type and Port Mapping.

Ports To prevent clock signal deterioration,
you need to add a BITS clock source
for clock compensation when more
than 10 NEs are configured. In this
case, you need to set Phase-Locked
2.9.2.4 Configuring Clock Attributes Mandatory.

To provide a clock source selection
basis for each clock source during
clock switching, you need to set
System Clock Source Priority Table,
2M External Clock Source Priority
Table, Clock Quality, and Higher-
Priority Clock Source Reversion.
NOTE
If a port that supports synchronous
Ethernet needs to output synchronous
Ethernet clock signals that carry SSM
information, you need to add the port to
System Clock Source Priority List of the
NE and set Clock Source Priority to 0. For
details about the capabilities of ports
supporting synchronous Ethernet
processing, see 2.4.3 OSN 9800 U Series

WDM OTN
2.9.2.5 Configuring the Clock Source Mandatory.

Protection Clock synchronization at the physical
layer supports clock source selection
and switching in the following
scenarios:
● When the SSM protocol is not
enabled, configuring the clock
source protection is not required.
● When the standard SSM protocol is
enabled, configuring the standard
SSM protocol is required.
● When the extended SSM protocol is
enabled, configuring the extended
SSM protocol is required.
2.9.2.6 Viewing Clock Mandatory.

ports for the clock synchronization
status to ensure that the port
defined in the networking diagram.
2.9.2.7 Viewing the Clock Tracing Mandatory.

network. Using the U2000, you can
each NE.

switch clock sources. To manually
switch clock sources, perform the
operations of setting clock source
switching conditions, enabling clock
source switching, and starting clock
source switching.

To achieve frequency synchronization of a board, you need to set the Service Type
and Port Mapping of the board on the U2000.

WDM OTN
Prerequisites
Context
NOTE
Since OSN 9800 V100R001C20, you do not need to set Synchronous Clock Enabled for the
OSN 9800.
NOTICE
Procedure
Availability.
Step 2 Add a port to the clock source priority table and set the priority to 0. For details,
see 2.9.2.4 Configuring Clock Attributes.
----End

This topic describes how to configure attributes of external clocks for a device so
that the device can properly extract external clock signals.

WDM OTN
Prerequisites
● The CTU board has been created.

The external port of a clock board can be used to connect the external time. In
multi-subrack NE.
● Each subrack has two clock ports and two timing ports. These ports are used
to concatenate and transmit the clock or timing signals among multiple
subracks, or are used to input or output external clock and timing signals. By
default, the Enabled Status is unused. If any ports need to be used for the
input or output of external clock and timing signals, the ports should be set
to the disabled state. One NE supports a maximum of two ports for the input
or output of external clock and timing signals.
switches the frequency source mode to Physical Synchronization when the
Synchronization.
Step 1 Configure Enabled Status.
----End
Procedure
Step 1 Set the external clock attributes of the 2M phase-locked source. Set the
parameters manually, such as External Clock Output Shutdown, External Clock
Output Mode, External Clock Output Timeslot, and External Source Output

WDM OTN
Threshold. For details about these parameters, see2.9.2.10.9 Parameters: Phase-

Locked Source Output by External Clock.
----End
2.9.2.4 Configuring Clock Attributes

Clock attributes include system clock source priority table, 2M external clock
source priority table, clock quality, and clock source reversion mode.
Prerequisites
Precautions
NOTICE



WDM OTN
NOTE
If a port that supports synchronous Ethernet needs to output synchronous Ethernet clock
signals that carry SSM information, you need to add the port to System Clock Source
Priority List of the NE and set Clock Source Priority to 0. For details about the capabilities
of ports supporting synchronous Ethernet processing, see 2.4.3 OSN 9800 U Series
----End


WDM OTN
NOTE
The relationship between the 2M PLL clock source and the external clock port depends on
the sequence of setting the cascaded external ports on the clock board.
NOTE
External 2M output clock sources can be independently configured in a priority table. In

addition, you can configure line clock sources as phase-locked sources, and configure the
priorities of line clock sources in the priority table for the output phase-locked source of the
first or second external clock.
----End

allocated to them. Therefore, the quality levels of clock sources are defined only
during testing and maintenance.
Step 1 Configure Clock Quality to the desired level. For details about the parameters, see
2.9.2.10.5 Parameters: Clock Source Quality.

WDM OTN
NOTE
----End


Parameter.

WDM OTN
NOTE
Time(min) to 0.
● Clock Source HoldOff Time(100ms): The Clock Source HoldOff Time(100ms) can be
set within the range of 300 ms to 1800 ms with the step length of 100 ms.
----End

After the clock source is set and the clock priority level for the NEs is specified, the
standard SSM or extended SSM protocol can be enabled to prevent the NEs from
tracing an incorrect clock source.
Prerequisites
Procedure
Step 1 Configure Enable Standard SSM Protocol Control or Enable Extend SSM
Protocol Control.
NOTE
The same SSM protection protocol must be used within the same clock protection subnet.
Step 2 Optional: If the Enable Extend SSM Protocol Control is selected, set the Clock
Source ID of the Clock Source. For details about these parameters, see 2.9.2.10.4

WDM OTN
NOTICE
a clock loop.
----End
2.9.2.6 Viewing Clock Synchronization Status

If the clocks between NEs in the network are not synchronous, pointer justification
errors, bit errors, and even service interruption may occur on the NE. Using the
U2000, you can ascertain and monitor the synchronization status of the NE clocks.
Prerequisites
Procedure
Step 1 View clock synchronization status. For details about these parameters, see
2.9.2.10.8 Parameters: Clock Synchronization Status.

WDM OTN
----End

status of each NE.
Prerequisites
Context
Procedure
menu.
----End

manually.

WDM OTN
Prerequisites
Procedure
NOTICE
Step 1 Perform clock source switching, including the operation of selecting Forcible
Source Selection or Manual Source Selection. For details about these
parameters, see 2.9.2.10.7 Parameters: Clock Source Switching.
switched clock source and choose Clear Source Selection.
----End
2.9.2.9 Configuring OTUs or Tributary Boards to Implement Synchronous

Ethernet Transparent Transmission
of boards are correctly specified on the U2000.
Prerequisites

WDM OTN
Context
NOTE
When a board supports transparent transmission of synchronous Ethernet services, before

changing the value of Port Mapping for a port on the board from bit transparent mapping
to MAC transparent mapping, you must delete the port from the clock priority table.
NOTICE
Procedure
Availability.
----End
2.9.2.10 Parameters: Physical Clock (OSN 9800 U Series: U1CTU/S1CTU)


In this user interface, you can query, modify and set the priority list of clock
sources, select the external clock source mode, and select the tributary board.

WDM OTN
Navigation Path
Layer Clock > Clock Source Priority. Click the System Clock Source Priority List
tab.
Parameters
Clock Source For example: local Displays the name of the

clock source.
External Clock Source 2MBit/s, 2MHz The External Clock

Mode Default: 2MBit/s Source Mode parameter
the format of the input
clock signals from the
Synchronous Status Sa4, Sa5, Sa6, Sa7, Sa8 The Synchronous Status
Byte Default: Sa4 Byte parameter provides
timeslots for the SSM
the input external clock
signals.
Clock Source Priority (1 0 to 255 Displays the priority

is the highest) Default: 1 sequence of this clock
source.
1 indicates the highest
priority. A larger value
indicates a lower priority.
0 indicates that the clock
source is not a candidate
clock source but is used
to output clock signals.
source.

WDM OTN
Navigation Path
1st External Output List tab.
Parameters


as Valid.

Navigation Path
2nd External Output List tab.
Parameters

WDM OTN


as Valid.


Navigation Path
Clock Subnet Configuration Attribute tab.
Parameters

number of the NE.

WDM OTN
Protection Status Enable Standard SSM The Protection Status

Protocol Control, Enable parameter indicates the
Extend SSM Protocol working mode of the
Control, Disable SSM clock protocol for a clock
Protocol Control subnet.
Default: Disable SSM ● Stop SSM Protocol:
Protocol Control
– When the SSM
protocol is
disabled, clock
signals do not
contain clock
quality
information. Clocks
are selected based
on the specified
clock source
priorities. In this
mode, clock loops
may occur.
on a non-ring
network with
multiple clock
sources. The clock
source is selected
according to the
clock source
priority list.
● Start Standard SSM
Protocol:
SSM protocol is
enabled, clock
quality levels are
used to prevent
clock loops.
on a non-ring
network with
multiple clock
sources. The clock
signal carries
quality
information. It is
used when the
WDM/OTN device
interconnects with
a third-party
device.

WDM OTN
● Start Extended SSM

Protocol:
– When the
extended SSM
protocol is
enabled, clock
source IDs are used
to prevent clock
loops.
applicable only to
a ring network. It
is a Huawei
proprietary
protocol and
cannot be used
when the
WDM/OTN device
interconnects with
a third-party
device. If the
extended SSM
protocol is enabled
on an NE, the
standard SSM
protocol can be
configured on the
downstream NEs;
however, it cannot
be configured on
the NE if the
standard SSM
protocol is enabled
on the upstream
NEs.

configured clock source
of the NE. You can either
add or delete a clock
source in the clock

WDM OTN

clock source. ITU-T
tracing problem may
problem.

Navigation Path
Clock Quality tab.
Parameters

WDM OTN

name of the configured
clock source. You can
either add or delete a
clock source in the clock
Configured Quality Auto, G.811 Clock, G.812 The Configured Quality

TNC, G.812 LNC, SDH, parameter provides an
Unavailable Clock option to set the
Source, Unknown SSM configuration quality
Level level of a clock source.
Default: Auto This parameter is
applicable to certain
special scenarios or tests
and therefore does not
need to be set in most
cases.
When the parameter
occur.
when a clock source
clock in 2MHz mode,
be set.

WDM OTN

quality information
source.
be selected as the

clock sources.
Navigation Path
Layer Clock > Clock Source Switching. Click the Clock Source Reversion tab.

WDM OTN
Parameters

source with a lower
recovers, the NE may
automatically switch to
the clock source or not.
Whether the NE
automatically switches
to the clock source
depends on the
parameter setting.

WDM OTN
Clock Source WTR 0-12 The Clock Source WTR

clock selector from
the recovered clock
signals are still
the quality of the
are unavailable.

WDM OTN
Clock Source HoldOff 3 to 18. The step is 1. Specifies the time period
Time(100ms) Default: 10 from the point when a
clock source switching
condition is generated to
the point when a clock
source switchover occurs.
When a clock source for
an NE fails, the status of
the clock is sent to the
select flow only after the
specified Clock Source
Hold-Off Time(100ms)
elapses so that the NE
can determine whether
to select another clock
source. This parameter
ensures that a short-
term clock signal failure
is not sent to the select
switching.

Navigation Path
Layer Clock > Clock Source Switching. Click the Clock Source Switching tab.
Parameters

configured clock source.

Switching Status Forcible Source Selection, This field displays the

Manual Source Selection, switching status of clock
Normal source.

WDM OTN
Switching Source Type For example: Internal This field displays the
Clock Source switched clock source
type that the NE is
tracing.
Switching Source For example: local This field displays the

switched clock source
that the NE is tracing.

the holdover mode.
Navigation Path
Layer Clock > Clock Synchronization Status from the Function Tree.
Parameters
NE Clock Mode Free-Run, Fast Lock, The NE Clock Mode

Trace, Hold parameter indicates the
best clock source is the
local clock, the clock
the priority table

WDM OTN
S1 Byte Synchronous - The S1 Byte

Quality Info Synchronous Quality
each clock source
according to the
protocol.
S1 Byte Synchronous - The S1 Byte Clock

Source Synchronous Source
defined in the SSM
Synchronous Source For example: local Displays the trace source

of the current NE clock.
For query only.
Normally, the
synchronous source
among the clock
stratums. If the
synchronous source
according to the
stratums.

WDM OTN
Data Output Method in 24th Keep, Long Term The Data Output
Holdover Mode Keep Method in Holdover
Default: 24th Keep Mode parameter
the method of
outputting data in
NE are lost, the NE
enters the holdover
NE maintains the
of 24 hours or a
Unknown SSM Level G.811 Clock, G.812 TNC, The Unknown SSM
Map G.812 LNC, SDH, Level Map parameter
Unavailable Clock Source provides an option to set
the quality level when
the quality information
of a clock source is
unknown.

In this user interface, you can set the external clock source attributes of the 2M
phase-locked source. You can set the output mode, output timeslot, and output
threshold.
Navigation Path
Physical Layer Clock > Phase-Locked Source Output by External Clock from the
Function Tree.

WDM OTN
Parameters
2M Phase-Locked bits0, bits1 This field displays the

Source Number numbering IDs of the
outputs from external
clock sources.
External Clock Output false, true This field allows you to

Shutdown Default: false enable or disable the
forced shutdown of
outputs.
External Clock Output 2 MBit/s, 2 MHz The External Clock

Mode Default: 2 MBit/s Output Mode parameter
the format of the 2M
output clock signals from
2M Phase-Locked
2M Output S1 Byte
Unavailable or Send
AIS, the failure
transmitted to the
equipment using the
signals when the
external output fails.

WDM OTN
External Clock Output ALL, Sa4, Sa5, Sa6, Sa7, The External Clock
Timeslot Sa8 Output Timeslot
Default: ALL parameter provides an
option to set the
timeslots used by the
SSM quality information
in the output clock
signals.
only when External
set to 2M Bit/s.
External Source Output Unavailable Clock The External Source

Threshold Source, SDH, G.812 LNC, Output Threshold
G.812 TNC, G.811 Clock parameter provides an
Default: Unavailable option to specify the
Clock Source extent to which the 2M
signals are degraded to
cause an output failure.
If the SSM protocol is
running in the Stop SSM
Protocol mode, setting
this parameter is
not contain quality
information.
signals are output
according to the 2M
Phase-Locked Source
Fail Action value.

WDM OTN
External Source Invalid No Condition, AIS Alarm, The External Source

Condition LOF Alarm, AIS or LOF Invalid Condition
Alarm parameter provides an
Default: No Condition option to specify the
alarm in 2M external
input clock as a
failure.
2MPLL Los External Shutdown External Clock The 2MPLL Los External
Clock Output Action Output, External Clock Clock Output Action
Tx AIS Alarm, External parameter provides an
Clock Tx DNU Level option to specify the
Default: Shutdown type of the signals
External Clock Output output by the external
phase-locked source
fails.

WDM OTN
Clock Synchronization Feature Guide 3 IEEE 1588v2 (OTN & Packet)
3 IEEE 1588v2 (OTN & Packet)
3.1 Introduction of IEEE 1588v2 (OTN & Packet)

WDM/OTN equipment supports IEEE 1588v2 to implement frequency and phase
synchronization.
Overview
The IEEE 1588v2 standard specifies Precision Time Protocol (PTP) in a
measurement and control system. The PTP protocol enables precise clock
synchronization between distributed and standalone devices in the measurement
and control systems and ensures clock synchronization precision to
submicroseconds.
Traditional GPS signals can satisfy time synchronization requirements but feature
high installation and maintenance costs. In addition, GPS signals depend on
satellites, which may bring communication security risks. IEEE 1588v2 can function
as an alternative to the GPS or other complex timing systems, providing high-
precision time for NodeBs or eNodeBs.
Application Scenario
Different from physical clocks that recover clock information from service bit
streams, IEEE 1588v2 implements frequency and phase synchronization through
PTP packet exchanges, as shown in the following figure. The synchronization is
implemented hop by hop, which requires that all devices in the synchronization
network must support IEEE 1588v2.

WDM OTN
Figure 3-1 IEEE 1588v2 application scenario
NOTE
3.2 Principles
An IEEE 1588v2 clock transfers the reference time to each control point accurately
by building the master-slave relationship between network nodes, and by using
the time synchronization mechanism.

An IEEE 1588v2 clock system uses the master-slave hierarchy. The grandmaster
clock (GMC) that is the clock at the highest level transmits clock information to
the terminal equipment through an ordinary clock (OC), a boundary clock (BC),
and a transparent clock (TC).
The best clock in the entire system is the GMC due to its stability, accuracy, and
certainty. According to the precision and level of clocks on each node and the
traceability of UTC, the BMC algorithm selects the master clock in each subnet
automatically (see 3.2.5 BMC Algorithm). In the system where there is only one
subnet, GMC is the master clock. Each system has only one GMC, and each subnet
has only one master clock. Slave clocks are kept synchronized with the master
clock.
In a PTP clock subnet, the master-slave hierarchy can be established between the
OC and BC, between OCs, or between BCs.
Figure 3-2 shows the process of building the master-slave hierarchy between the
OC and BC in a PTP clock subnet.

WDM OTN
Figure 3-2 Master-slave clock hierarchy
In Figure 3-2, Ordinary clock-1 is at the bottom of the hierarchy and is referred to
as grandmaster. Port-1 of Boundary clock-1 is a SLAVE (S for short) compared
with the grandmaster. The other ports of Boundary clock-1 are all MASTER (M for
short) compared with the clock equipment that is connected to the ports. Hence,
port-1 of Boundary clock-2 is a SLAVE compared with Boundary clock-1.
The master-slave hierarchy of a PTP clock system is built depending on the
Announce packets received by the port from other clock ports, port data sets, BMC
algorithms, and port state machines. The process of building the master-slave
hierarchy is as follows:
1. Receives and authenticates the Announce packets from other clock ports.
2. Uses the BMC algorithm to determine the recommended state of a port.
3. Updates the port data set based on the decision point specified by the port
status decision algorithm for entering the recommended state.
4. The port state machine determines the actual state of the port based on the
recommended state and status decision event, and builds the master-slave
hierarchy.
NOTE
The master-slave clock hierarchy exists only between the OC and BC, and only the BC can
have the branch nodes in the master-slave hierarchy. For example, trails 1, 2, 3, 4, and 5
may contain TCs, but the TC equipment is not involved in the master-slave hierarchy and
does not maintain the relationship.
3.2.2 IEEE 1588v2 Clock Architecture

The clock architecture specified in the IEEE 1588v2 standard classifies NE clocks
into three models: ordinary clock (OC), boundary clock (BC), and transparent clock
(TC).
Clock Port Status

Every port of the OC and BC maintains an independent PTP state machine that
defines the status allowed by ports and the port status conversion rules. A port
may be in one of the following states:
● MASTER: The port provides a timing source for the downstream equipment on
the trail.
● SLAVE: The port is kept synchronized with the port in MASTER state on the
upstream equipment on the trail.

WDM OTN
● PASSIVE: The port on the path is not in the MASTER status and does not
maintain synchronization with the port in the MASTER status. That is, the
upstream port and downstream port are isolated.
● FAULTY: The state of a port changes from master, slave, or passive to faulty
when a LOS, AIS, LinkDown, or other alarm is reported for the port.
Clock Models
The following concepts are essential for the IEEE 1588v2 clock models:
● PTP device: A clock device that supports the IEEE 1588v2 protocol is defined
as a PTP device.
● PTP port: A port that supports the IEEE 1588v2 protocol on a PTP device is
defined as a PTP port.
Figure 3-3 Clock Models
TCs are classified into P2P TCs and E2E TCs according to different mechanisms of
processing packets.
● P2P TC: The device measures the residence time of an IEEE 1588v2 packet to
be forwarded and the transmission delay of the link connected to the port
that receives this IEEE 1588v2 packet. It also records the residence time and
link transmission delay in the IEEE 1588v2 packet for further processing at a
slave clock device.
● E2E TC: The device measures the residence time of an IEEE 1588v2 packet to
be forwarded and records the residence time in the IEEE 1588v2 packet for
future processing at a slave clock device.
3.2.3 Clock Subnet and Clock Source ID in IEEE 1588v2

A clock synchronous network can be divided into independent clock subnets. In
each clock subnet, a clock participating in IEEE 1588v2 clock source selection
needs to be assigned a unique identifier, which is called a clock source ID.
Clock Subnet
An IEEE 1588v2 clock subnet is a logical set in which clocks are synchronized with
each other using the IEEE 1588v2 protocol. A physical packet switched network

WDM OTN
can be divided into multiple logical clock subnets. The clocks within a subnet are
synchronized with each other. Each clock subnet uses its own synchronization
source.
● An ordinary clock (OC) or boundary clock (BC) can be configured in a clock

subnet. It processes the IEEE 1588v2 packets of this clock subnet and discards
the IEEE 1588v2 packets from other clock subnets.
● A transparent clock (TC) does not need to be configured in a clock subnet. It
transparently transmits IEEE 1588v2 packets or correct transmission delays in
the IEEE 1588v2 packets.
In an IEEE 1588v2 packet, a clock subnet ID occupies one byte.
Clock Source ID
A clock source ID identifies a clock in an IEEE 1588v2 clock subnet. In an IEEE
1588v2 packet, a clock source ID occupies eight bytes. It consists of two parts:
● Organizational Unique Identifier (OUI): an organization identifier uniformly

assigned by the IEEE standard.
● Extended ID: an identifier uniformly assigned by the organization represented
by the OUI to ensure that the Clock Source ID in each IEEE 1588v2 packet is
unique.
3.2.4 Time Source Port

Time source information can be received through external time ports and service
time ports.
Table 3-1 Port types
Time Port Supported Port Mode Function

Type Format
External 1PPS+TOD RJ45 ● Receives time signals

time port from the BITS or other
devices that have the
same port.
● Cascades with other
devices of the same
type at the same site.
● Connects to the lower-
layer PTN/SDH
network.
Service time Ethernet Inband port that Connects to the lower-

port services, runs with services. layer PTN/SDH network
including GE, without equipment room
10GE, and or site sharing
40GE restrictions.

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Type Format
OSC clock OSC OSC optical port Supports time

devices.
Clock Ethernet port GE optical port Used for time

synchroniza synchronization between
tion GE NEs or time cascading
synchronization are
supported. Ethernet
services cannot be
transmitted.
A synchronous network using the IEEE 1588v2 protocol obtains time signals from
the reference time source grandmaster clock using external time ports.
1PPS+TOD Time Signals

1PPS+TOD time signals consist of 1PPS signals and TOD time information.
● 1PPS
1PPS is short for one pulse per second. 1PPS signals are used for time scaling
and work at the RS-422 levels. The pulse frequency of 1PPS is 1 Hz. That is,
one pulse is transmitted per second. The 1PPS signal pulse width ranges from
20 ms to 200 ms. The rising edge of the pulse is strictly coincident with the
UTC time.
● TOD
TOD is short for time of day. TOD messages provide time in ASCII format.
TOD signals also work at the RS-422 levels and provide a baud rate of 9600
bit/s. A TOD message contains information such as current date/time, time
standard ID, 1PPS status flag, date/time adjusted based on UTC leap seconds,
leap second adjustment directive, and GPS time.
The clock board supports mutual conversion between 1PPS+TOD quality

information and IEEE 1588v2 time quality levels.
● If the manually specified Time Quality Level is not the default value 187, the
manually specified IEEE 1588v2 time quality level applies.
● If the manually specified Time Quality Level is the default value 187, the
clock board automatically converts the quality information carried in the TOD
into the IEEE 1588v2 time quality level based on the predefined conversion
table.
Table 3-2 provides the mapping between TOD status information and PTP time
quality levels.

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Table 3-2 Mapping between TOD status information and PTP levels
TOD Status Information PTP Time Quality Level
0x00: normal 6
0x01: holdover on the time synchronous 7

device (atomic clock)
0x02: unavailable 255

device (high stability crystal oscillator)
0x04: holdover on the transmission 187

equipment
0x05: holdover on the local rubidium clock 8
Others: reserved. 255
External Time Ports

Port Port

universal platform
subrack
OSN 8800
universal platform
subrack
OSN 6800

series/M24/P32/
P32C

T32/T64

CLK3/TOD3 CLK3/TOD3

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Port Port

Enhanced
CLK3/TOD3 CLK3/TOD3

Enhanced

Compact
(TNF3SCC)

TMT1SCC

CLK3/TOD3 CLK3/TOD3

TMK5XCH,
TMK6XCH,
TMK5UXCME,
TMK6UXCM,
TMK5XCSb

CLK3/TOD3 CLK3/TOD3

CLK3/TOD3 CLK3/TOD3
NOTE
NOTE

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External Time Connection Mode

External time mode: The external time port is used to interconnect with the BITS
or other devices. The output time can be synchronized with the system time of an
NE or the line source specified by the NMS. When a port works in external time
mode, it transmits time signals unidirectionally. Therefore, you need to specify
whether the port is used for signal input or output.
Cascading mode: The external time port is used only for interconnection between
multiple subracks of WDM/OTN products and is always synchronized with the
system time. When a port works in the cascading mode, it transmits time signals
bidirectionally. The system automatically determines the time tracing relationship.
NOTE
is set to Enabled, the cascading mode is used. When this parameter is set to Disabled, the
external time mode is used.

Time Port Supported Applicable Scenario Networking Diagram
Type Format

time mode work in the where WDM/OTN
external time equipment is
mode. interconnected with
external time source
devices or
WDM/OTN NEs are
interconnected.
Cascading All subracks This mode is Figure 3-5

time mode work in this recommended when
1 cascading master and slave
time mode to subracks are
form ring configured and the
protection. subracks support the
clock cascading
Cascading All subracks mode. Figure 3-6
time mode work in this
NOTE
2 cascading For details about
mode with which products
protection support clock
paths. cascading between
master and slave
subracks, see 2.5
Specifications.

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NOTE
the TOD port.
similar.
Figure 3-4 Connection diagram of the external time mode

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Figure 3-5 Connection diagram of cascading time mode 1

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Figure 3-6 Connection diagram of cascading mode 2


OSN 1800 II Pro
OSN 1800 II TP
OSN 1800 V

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OSN 1800 II Enhanced TMB1MD48AFS HP1 (HP2)

TMK6XCH, TMK5UXCME,
TMK6UXCM, TMK5GSCC

OSN 9800 M05

OSN 9800 M12
OSN 9800 M05

NOTE

NOTE
V100R021C10SPC100.

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separately.
NOTE
protection.


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3.2.5 BMC Algorithm

The best master clock (BMC) algorithm can determine the GMC in any network
structure and build the master-slave hierarchy. In addition, the BMC algorithm
transfers the master clock and reference time to each node level by level for the
best possible clock precision.

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Overview
The BMC algorithm compares the description data of two clocks to determine
which data better describes the clock. In other words, the algorithm is used to
determine which of the multiple Announce messages received by the local clock
port describes the best clock. The algorithm is also used to determine whether a
new clock source (that is, the external MASTER) has better quality than the local
clock. The data that describes the external MASTER information is contained in
the Grandmaster field of an Announce message. The data that describes the local
clock is contained in the data set of the clock.
The BMC algorithm runs on each clock in a domain independently. That is, each
clock does not need to negotiate with the other clocks, but calculates the status of
its own ports. The algorithm prevents situations where multiple master clocks exist
in the PTP clock system at the same time, there is no master clock, or the PTP
clock system is in the free-run mode.
BMC Algorithm Introduction

The BMC algorithm consists of two parts, which are:
● Data group comparison algorithm
The algorithm compares the advantages and disadvantages of the two groups
of data of two clock ports. One group of data represents the default features
of the local clock, and the other group of data represents the information
contained in the synchronous packets received from the external port.
● Status decision algorithm
The algorithm calculates the recommended status of each port based on the
comparison result of data groups. The states include primary site, secondary
site, standby, listen only, and inhibited.
The BMC algorithm is dynamic. That is, when the BMC algorithm runs in a clock
synchronization system, the BMC algorithm continuously calculates the port status
based on the real-time data and then adjusts the status of each node and port
dynamically while also adjusting the route of transmitting the time signals. Hence,
when the active master clock is faulty or its performance deteriorates, the system
may select another suitable node to serve as the master clock.
The BMC algorithm runs on each port of each clock locally. The BMC algorithm
specifies the order in which data is compared and the comparison rules, namely,
clock level, clock identifier, clock variable, trail length, and so on. The current
status of each port of each clock can be obtained after the data is compared.

WDM OTN
NOTE
● Static BMC can be set to either Enabled or Disabled to enable or disable the IEEE
1588v2 protocol. When it is set to Enabled, users can manually configure the port
status as master or slave.
● For OSN 9800 service boards (with OTN tributary and line functions), when multiple
clock ports are configured, the BMC algorithm determines which port is used as the
clock source based on the port number. The system algorithm complies with the
following rules:
● For the boards that support IEEE 1588v2/ITU-T G.8275.1/ITU-T G.8273.2 only on
ports 1 to 15, the system preferentially selects the port with a smaller port number
as the clock source.
● For the boards that support IEEE 1588v2/ITU-T G.8275.1/ITU-T G.8273.2 in all ports,
ports 1 to 15 and the ports with a number greater than 15 form two groups. The
system preferentially selects the latter group and then the former group. In each
group, the system preferentially selects the port with a smaller number as the clock
source. For example, if ports 3, 7, 16, and 20 are configured as clock ports, the
priority is port 16 > port 20 > port 3 > port 7.
Figure 3-12 shows a typical application of the BMC algorithm for clock C0 that
has N ports.
Figure 3-12 BMC clock algorithm model
1. For each port, the BMC module compares the data groups of the qualified
announce packets received by other clock ports that are connected to the port
on the communication trail, and the data group comparison algorithm
determines the best packets Erbest for the port.
2. In the case of N ports of clock C0, the BMC module compares Erbest of each
port and determines the best packets Ebest of N ports.
3. In the case of each port of N ports of clock C0, the BMC module uses the
status decision algorithm and the state machine of the port to determine the
port status based on Ebest, Erbest, and the default data group D0.

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3.2.6 Delay Compensation

When the product connects to a clock device through its external time port,
transmission delay of the cable connecting to the external time port and PTP link
asymmetry can be corrected.
Compensation for the Transmission Delay of the Cable Connecting to the

External Time Port
Time information is required for transmitting electrical signals. Therefore, 1PPS
+TOD time signals need to be sent to a slave clock device through a cable. There
is a difference between the time when the slave clock device receives the
timescale pulse and the time that the pulse actually represents. Accurate time
synchronization can be achieved by correcting the delay introduced by the cable
connecting to the external time port.
NOTE
The external time port on the product is not a PTP port and does not support the IEEE
1588v2 protocol. The transmission delay cannot be measured automatically. Therefore, the
transmission delay of the cable connecting to the external time port must be measured
using a test instrument or computed based on the cable length.
Correction for PTP Link Asymmetry

The PTP link asymmetry means that the cables for receiving and transmitting PTP
messages between two devices have different lengths. This causes a variation
between the cable transmission delays in the receive and transmit directions.
The IEEE 1588v2 packet delay measurement algorithm is based on the assumption
that the PTP link transmission delays in the receive and transmit directions are the
same. If the receive and transmit cables on the PTP link are asymmetric, the
computed delay will differ from the actual transmission delay.
The PTP asymmetry correction mechanism uses the asymmetric delay variation
compensation value to correct the computed value, thereby achieving accurate
The delay compensation value for the transmission asymmetry can be obtained
according to the length difference between the cables in the signal receive and
signal transmit directions. Alternatively, the value can be obtained according to
the transmission time of a signal on the cables in the receive and transmit
directions using a test instrument. The compensation value takes effect only after
it is manually set for the PTP ports.
NOTE
The IEEE 1588v2 protocol can detect the mean transmission delay of two connected PTP
ports but cannot detect the transmission delay caused by the PTP link asymmetry.
Asymmetric delay must be measured with a test instrument or computed based on the
cable lengths.
Automatic Calculation and Compensation of Ring Network Delay Offset

Automatic calculation and compensation of ring network delay offset are
applicable to two-fiber bidirectional ring networks.

WDM OTN
NOTE
Only the following boards on the following products support automatic compensation of
ring network delay offset. For details about the restrictions, see 3.3.1 Feature Limitations.
● OSN 1800 V (Z-series system control boards) V100R009C00 and later versions: UNS4,
EX4, EG10, and UNQ2
● OSN 1800 V Pro (K5UXCME system control board):
● V100R021C10 and later versions: UNS5, UNS4, GTA, UNQ2, UND3 and EX10
● V100R022C10 and later versions: K1GDC
● OSN 1800 II Pro (K2UXCLE system control board):
After a PTP time synchronization network is commissioned, the length difference

between the transmit and receive fibers on the line may change greatly and the
asymmetric delay may change due to fiber maintenance (such as fiber cut repair
and fiber route change) in the O&M phase of the network. If the compensation
value cannot be set correctly, the time synchronization function will be affected.
The automatic ring network delay calculation function can be used to
automatically calculate the fiber asymmetry compensation value on time nodes
with protection trails, such as on a ring network, and provide a recommended
compensation value. In addition, automatic compensation within the
compensation range is supported, requiring no manual measurement operations.
The basic principle is as follows:
1. The following takes a west fiber as an example. When a fiber cut occurs, the
clock node switches to the PTP port on the east fiber to implement time
synchronization.
2. After the west fiber is repaired, the clock node re-obtains the PTP packets
from the west port and calculates the offset between the time when the west
PTP port is selected as the time source for time synchronization and the
current node's synchronization time through simulation. In this way, a new
compensation value is obtained.
3. When Ring Network Automatic Compensation is set to Enabled:
– If the offset value is less than 50 ns, automatic compensation is not
performed on the ring network and the FIB_LEN_CHANGE alarm is not
reported. Only logs are recorded.
– If the offset value is within the automatic compensation range (50 ns to
500 ns), automatic compensation is performed on the ring network and
an event is reported.
– If the offset value is greater than 500 ns, the FIB_LEN_CHANGE and
FIBER_ASYMMETRIC_CHANGED alarms are reported. You need to
manually set the compensation value according to the recommended
value. After the configuration is complete, the alarms will be cleared.
4. When Ring Network Automatic Compensation is set to Disabled, no
automatic compensation is performed but the FIB_LEN_CHANGE and
FIBER_ASYMMETRIC_CHANGED alarms are reported. The alarms will be
cleared after the compensation value is manually configured.
The offset compensation value needs to be transmitted to the peer NE through
DCN channels and encrypted using the HMAC_SHA256 algorithm.

WDM OTN
Single-Fiber Bidirectional Asymmetric Compensation

In a single-fiber bidirectional system consisting of single-fiber bidirectional optical
modules, dispersion occurs during transmission because receive and transmit
wavelengths are different, causing delay asymmetry. In this case, automatic delay
compensation is required to ensure that offset is within the allowed range and
clock precision is not affected.
NOTE
Only the following boards on the following products support single-fiber bidirectional
asymmetric compensation. For details about the restrictions, see 3.3.1 Feature Limitations.
● OSN 1800 V (Z-series system control boards) V100R009C00 and later versions: EX4 and
EG10
● OSN 1800 V Pro (K5UXCME system control board): EX10
● OSN 1800 II Pro (K2UXCLE system control board): EX10
3.2.7 IEEE 1588v2-Compliant Phase Synchronization

The IEEE 1588v2 clock system ensures that slave clocks remain synchronized with
the master clock through PTP packets according to the PTP synchronization
mechanism.
IEEE 1588v2 Packet

The packets in PTP telecommunication defined in the IEEE 1588v2 protocol include
the following types:
● Announce packets are used to build the master-slave synchronization
hierarchy.
● Sync packets are used by the master clock to initiate a synchronization
request.
● Follow_Up packets are used by two-step clocks to carry timestamps.
● Delay request packets are used by a slave clock to initiate a delay
measurement request. Delay_Req is used in the E2E mode, while Pdelay_Req
is used in the P2P mode.
● Delay response packets that are used to respond to the delay measurement
request from a slave clock. Delay_Resp is used in the E2E mode, while
Pdelay_Resp is used in the P2P mode.
● Management packets are used to query and update the PTP data set that a
clock maintains, and are also used to customize a PTP system, initialization,
and fault management. The management packets are used between the
administration node and the clock equipment.
IEEE 1588v2 Clock Phase Synchronization Mechanism

The IEEE 1588v2 protocol is based on the most accurate match time at which
synchronous data packets are propagated and received. Each slave clock is
synchronized with the master clock by exchanging the synchronous packets with
the master clock.
Figure 3-13 shows the IEEE 1588v2 clock phase synchronization process.

WDM OTN
Figure 3-13 IEEE 1588v2 clock phase synchronization process
1. At the time of t1, the master clock sends a Sync message. If the master clock
is a one-step clock, the t1 timestamp is contained in the Sync message and
sent to the slave clock. If the master clock is a two-step clock, then the t1
timestamp is contained in the subsequent Follow_Up message and sent to the
slave clock.
2. At the time of t2, the slave clock receives the Sync message (one-step mode)
and obtains the t1 timestamp from the Sync message or from the subsequent
Follow_Up message (two-step mode).
3. At the time of t3, the slave clocks send delay request messages.
4. At the time of t4, the master clocks receive delay request messages.
5. At the time of t5, the master clock sends delay response messages that carry
the information of the time of t4.
The method of calculating the time difference between slave clocks and the
master clock and the link delay is as follows:
Because
t2-t1=Delay+Offset
t4-t3=Delay-Offset
Hence,
Offset=[(t2-t1)-(t4-t3)]/2
Delay=[(t2-t1)+(t4-t3)]/2
NOTE
● Offset: Time difference of a slave clock from the master clock.

● Delay: The delay time caused by network transmission.

WDM OTN
3.2.8 IEEE 1588v2-Compliant Frequency Synchronization

Frequency synchronization is implemented based on the received and transmitted
timestamps in Sync messages defined by the IEEE 1588v2 protocol.
NOTE
● IEEE 1588v2-compliant frequency synchronization involves two actions: frequency

gauging and frequency correction. The synchronization precision of this method is lower
than that of frequency synchronization based on physical clocks.
● Synchronous Ethernet is preferred for the Ethernet ports that support both synchronous
Ethernet and IEEE 1588v2-compliant frequency synchronization.
Figure 3-14 shows the time of receiving and transmitting Sync messages between
clock A (slave) and clock B (master) when clock A synchronizes to clock B. Clock A
can correct its clock frequency after comparing the interval between two message
transmitting timestamps with the interval between two message receiving
timestamps. In this manner, clock A synchronizes to clock B. If the changes in the
link delay and residence time are negligible, the clock frequency of clock A can be
corrected using the following formula:
(t1[N] - t1[0])/(t2[N] - t2[0])
● If the value of the "t2[N] - t2[0]" is equal to the value of "t1[N] - t1[0]": This
means that clock A and clock B run at the same rate.
● If the value of the "t2[N] - t2[0]" is greater than the value of "t1[N] - t1[0]":
This means that clock A runs faster than clock B and needs to slow down its
frequency.
● If the value of the "t2[N] - t2[0]" is less than the value of "t1[N] - t1[0]": This
means that clock A runs slower than clock B and needs to accelerate its
frequency.
NOTE
● t2[N] - t2[0]: Indicates the number of clock cycles within the interval between two Sync
messages received by clock A.
messages transmitted by clock B.
● In one-step mode, t1[n] is contained in the Sync message. In two-step mode, t1[n] is
contained in the Follow_Up message.
In practical application, transmission delays and the residence times on a TC clock

must be considered and corrected.

WDM OTN
Figure 3-14 Intervals of transmitting Sync messages

This topic describes the limitations on and precautions for IEEE 1588v2 clocks.

WDM OTN

Automatic ● Only the following boards on the following

compensation upon a products support automatic compensation upon a
fiber cut on a ring fiber cut on a ring network:
network – OSN 1800 V (Z-series system control boards)
V100R009C00 and later versions: UNS4, EX4,
EG10, and UNQ2
– OSN 1800 V Pro (K5UXCME system control
board):
– V100R021C10 and later versions: UNS5,
UNS4, GTA, UNQ2, UND3 and EX10
– V100R022C10 and later versions: K1GDC
– OSN 1800 II Pro (K2UXCLE system control
board):
● This feature is supported only when the working
mode of the NE is BC. After automatic
compensation upon a fiber cut on a ring network is
enabled, the working mode of the NE cannot be
set to other modes.
● Ring network compensation can be enabled only
after an NE achieves time synchronization (traces
the grandmaster clock). Otherwise, the calculated
compensation value may be inaccurate.
● Ring networks do not support TC pass-through.
● If the working mode of the NE before the upgrade
is BC, automatic compensation upon a fiber cut on
a ring network is automatically enabled after the
upgrade.
● Optical modules delivered by Huawei must be
used.
● During fiber restoration, ensure that at least one
channel of clock signal and one channel of time
signal have been traced. Otherwise, the calculated
● During automatic compensation, do not perform a
cold reset on the system control board, cross-
connect board, or clock board, or power off the NE.
Otherwise, automatic compensation cannot work
properly.

WDM OTN
Single-fiber ● Only the following boards on the following

bidirectional products support single-fiber bidirectional
asymmetric asymmetric compensation:
compensation – OSN 1800 V (Z-series system control boards)
V100R009C00 and later versions: EX4 and EG10
board): EX10
board): EX10
● The equipment supports only the single-span
single-wavelength scenarios.
Function dependencies ● In scenarios where automatic compensation upon

a fiber cut and single-fiber bidirectional
asymmetrical compensation are enabled
concurrently on the same port:
– For single-fiber bidirectional optical modules,
only single-fiber bidirectional asymmetric
compensation takes effect.
– For two-fiber bidirectional optical modules,
automatic compensation takes effect only upon
a fiber cut on the ring network.
● Static BMC source selection and automatic
compensation upon a fiber cut on a ring network
are mutually exclusive and therefore cannot be
enabled concurrently.
Primary reference clock ● Networks at the aggregation layer should be

(PRC) configured with clock protection and be set with
the primary and secondary PRCs for active/standby
switching of clocks.
● For networks at the access layer, only one PRC is
set on the central NE in most cases, and other NEs
trace the clock of the central NE.
● If the BITS or other external clock equipment with
high precision exists, use the external timing mode
for the NE. Otherwise, use the line timing mode
instead. You are advised to use the internal timing
as a clock source of the lowest level.

WDM OTN
Methods for obtaining If there are multiple NEs at a core site of a WDM/OTN
frequency and phase network, the frequency/phase information can be
information obtained in either of the following ways:
● If physical OSC or ESC connections are established
between the NEs, the OSC or ESC channels can be
used to transmit IEEE 1588v2 frequency and phase
information between the NEs.
● ESC two-fiber bidirectional phase synchronization is
easily affected by factors such as protection
switching and board delay difference. If the east-
west delay offset is too large, phase indicators
change and deteriorate. As a result, frequent
network switching occurs and maintenance cannot
be performed.
● If the NEs are deployed in the same
telecommunication room and the intervals
between them are less than 200 m, the external
2M clock ports or 1PPS+TOD time ports on the NEs
can be used to transmit the frequency and phase
information between them.
● When IEEE 1588v2 signals are transmitted between
OTN devices, line boards or OSC boards are
recommended. When OTN equipment is
interconnected with third-party equipment to
transmit IEEE 1588v2 signals, tributary boards are
recommended.
TNV2E224/TNV2E402/ The VLAN ID of IEEE 1588v2 packets must be

TNV3E224/TNV3E402 different from the VLAN ID of the inband DCN. If they
are the same, IEEE 1588v2 packets cannot be received
normally and IEEE 1588v2 clocks cannot be
synchronized.
TN55TTX/TN56TOX When the mapping path of the TN55TTX/TN56TOX

board is 10GE LAN->ODUflex, the board does not
support IEEE 1588v2.
TN54EX2/TN54EG16 When TN54EX2 or TN54EG16 boards are used to

deploy IEEE 1588v2 clocks, due to the limited
processing capabilities of the boards, the OC/BC ports
may receive packets from multiple clock sources when
physical loops are present on a network. As a result,
IEEE 1588v2 clocks cannot be synchronized. Therefore,
you are not advised to configure the TC mode
(including pure TC, TC+OC, and TC+BC) for an NE on
which E-LAN services are configured. When physical
loops are present on a network, the OC/BC mode is
recommended networkwide.

WDM OTN
TN16AUX For the OSN 8800 T16, two TN16AUX boards must be
configured when the IEEE 1588v2 function is required.
TMB1LDCD/TMB1LDC When the port on the TMB1LDCD/TMB1LDC board

functions as a slave port, its interconnected port
(master port) cannot be configured with a VLAN ID.
Otherwise, PTP clocks cannot be traced and the
downstream PTP clocks may be affected. As a result,
PTP clock tracing is abnormal.
Service board ● Before configuring the clock function, ensure that

● For OTN line ports, IEEE 1588v2 can be used only
when lower-order ODUk cross-connections are
configured for the ports.
services, IEEE 1588v2 can be used only after
services are configured for the ports.
● When a tributary board is used to configure the
IEEE 1588v2 feature, IEEE 1588v2 packets occupy
the port bandwidth. When the port is fully loaded
with traffic, packets may be lost.
Clock board When the clock synchronization function is required

up each other.

WDM OTN
ST2/AST2 ● The ST2/AST2 board must be installed in a subrack

with a clock board if the clock function is required.
follows:
board in a cabinet.
the network cable.
● When no clock board is available, the ST2/AST2
board supports IEEE 1588v2 pass-through at OLA
sites.
● When configured in a universal platform subrack
and used with the STG board, the ST2/AST2 board
supports physical-layer clock processing and IEEE
1588v2 clock processing.
10GE LAN tributary When the 10GE LAN tributary board is used on OSN
board 9800 V100R001C00 or V100R001C01 and Port
Mapping is set to MAC Transparent Mapping
(10.7G), if the OSN 9800 is upgraded to
V100R001C20, configuring the port as a PTP port to
support IEEE 1588v2 interrupts traffic on the port. The
traffic is restored automatically after the configuration
is completed.
2-9.

WDM OTN
ANNOUNCE Packet When the TN52TOG/TN54TOG/TN54TOA/TN57TOA/

Period(s) TN54THA/ELOM/TNF5TOA board is interconnected
with a PTN device to transmit IEEE 1588v2 clock
signals, ANNOUNCE Packet Period(s) must be set to
64/1028. Otherwise, the interconnected PTN device
may fail to trace the clock source once the link is
faulty.
Packet service board ● When the EX2/TN54EG16 board is used to

implement IEEE 1588v2, the VLAN ID of the DCN
on the local equipment must be different from the
VLAN ID carried in the IEEE 1588v2 packets sent by
the interconnected equipment due to the limitation
of the chip capability of the board. Otherwise, IEEE
1588v2 packets cannot be received normally and
the IEEE 1588v2 clock cannot be synchronized.
● When the packet service board is used to
implement IEEE 1588v2 and the TC port of device
A and OC/BC port of device B are interconnected to
transparently transmit third-party clocks, Direction
at both ends must be set to UNI-UNI rather than
UNI-NNI, and Encapsulation Type cannot be set
to QinQ.
● For packet boards EX2 and TN54EG16, TC clock
services need to be created on TC ports. The
configuration method is the same as that for
common UNI ports. In addition, the TC clock
service must be assigned a TC tag.
Interface protocol type ● When an NE works in 1PPS+Time mode, a warm

reset on the NE's active clock board will generate
alarms indicating clock source switching and loss
of clock source on the downstream NE. To prevent
the problem, perform an active/standby clock
board switchover and then perform a warm reset
on the standby clock board.
● When an NE works in 1PPS+Time mode, a cold
board switchover and then perform a cold reset on
the standby clock board.
NOTE
The active/standby clock board switchover is not required
before a warm reset on the TN13STG, TN54STG, or TNK3STG
board.

WDM OTN
Frequency source mode ● After PTP Synchronization is enabled for an NE,

the NE automatically switches the frequency
source mode to Physical Synchronization when
Enabled Status of the external clock port on the
NE's clock board changes from Enabled to
Disabled or changes from Unused to Disabled.
Therefore, you need to manually set the frequency
source mode of the NE to PTP Synchronization.
● When the frequency source mode of an NE is set to
PTP Synchronization, you can change the priority
of physical-layer synchronization or SSM
information, but the setting does not take effect.
The settings take effect only when the frequency
source mode of the NE is set to Physical
Synchronization.
● When the external time port of an NE is set to
1PPS+Time input, the frequency source mode of
the NE cannot be set to PTP Synchronization.
Configuring PTP packet ● If the PTP frequency synchronization scheme is

attributes used, to ensure clock synchronization performance,
it is recommended that 128 or more SYNC packets
be sent per second, that is, the SYNC packet period
be lower than or equal to (8/1024)s.
● If the physical-layer synchronization solution is
used, the SYNC packet period can be kept at
(64/1024)s.
Static BMC When NE Clock Type is TC or TC+OC for a port,

Static BMC cannot be set to Disabled.
SLAVE_ONLY For the OSN 1800, the port of the clock equipment in
the SLAVE_ONLY state cannot enter into the MASTER
state. That is, this clock equipment cannot function as
the clock source for the downstream equipment on
the trail. Only the port of the clock equipment in the
NON_SLAVE_ONLY state can enter into the MASTER
state. That is, this clock equipment can function as the
clock source for the downstream equipment on the
trail. Therefore, the PTP system must contain at least
one clock equipment that is in the NON_SLAVE_ONLY
state.

WDM OTN
NE Clock Type The working mode supported by a PTP port depends

on the NE working mode and port type.
● When the NE working mode is OC, the port
working mode can only be OC.
● When the NE working mode is BC, the port
working mode can only be BC.
● When the NE working mode is TC, the port
working mode can only be TC.
● When the NE working mode is TC+OC, the port
working mode can be TC or TC+OC.
● When the NE working mode is TC+BC, the port
working mode can be TC or BC.
NOTE
● OTN tributary ports (Ethernet services) support the OC,
BC, TC, and TC+OC modes.
● OTN line ports, OSC ports, and clock synchronization GE
optical ports support the OC and BC modes.
● Ports on packet boards:
● OSN 9800/OSN 8800: supports the OC, BC, TC, and TC
+OC modes.
● OSN 1800: When working with F5UXCM/F5UXCME,
the F5EM20 board of the 1800 V supports the OC, BC,
TC, and TC+OC modes. In other scenarios, ports on
packet boards support only the BC mode.
For the OSN 1800:
● The device that is in the BC or OC working mode
can belong to only one clock subnet, and its clock
source can be selected only within the same clock
subnet.
● When the working mode of a port is set to TC, it is
recommended that IEEE 1588v2 packets be
forwarded in a QoS queue with a higher priority.
● After NE Clock Type is modified, you need to re-
create all PTP clock ports on the NE
● When NE Clock Type is set to TC+BC and you
modify the value of PTP Mode for a port, you need
to re-create the port.

WDM OTN
IEEE 1588v2 frequency ● The IEEE 1588v2 frequency synchronization

synchronization function is available only when the active and
standby boards (system control board and cross-
connect board) are upgraded and both support this
function.
● When the system control board of the WDM
equipment undergoes a cold or warm reset, the
WDM equipment cannot output external time
signals (1PPS+TOD). The system control board can
output external time signals only after it resumes.
If other equipment uses the external time output
signals of the WDM equipment, the WDM
equipment may fail to work properly when the
system control board undergoes a reset.
● After IEEE 1588v2 frequency synchronization is
enabled, physical-layer clock synchronization is not
supported. Therefore, the original SDH clock
synchronization function becomes invalid.
Attributes of the PTP For the OSN 1800:

clock port (Packet) ● If clock synchronization is implemented between
two interconnected NEs using the IEEE 1588v2
protocol, the ports at both ends must be enabled.
In addition, PTP Packet VLAN, PTP Packet
Encapsulation Format, Step Mode, and P/E Mode
must be set to the same values for the two NEs
● For NEs that use IEEE 1588v2 for frequency
synchronization, set SYNC Packet Period(s) to
4/1024 or 8/1024.
● If the TC port of equipment A is interconnected
with the OC or BC port of equipment B to
transparently transmit third-party clocks, the
interconnected ports cannot be NNI logical ports
and cannot be set to S-TAG encapsulation mode.

WDM OTN
CFP optical module For the boards that use CFP optical modules,
compensation for the asymmetrical transmission
delay is required after the boards are powered on or
undergo cold resets, the optical modules are replaced,
or the line code pattern is switched; otherwise, a time
deviation of about 100 ns may be generated.
FlexE port When FlexE ports are used to implement clock

synchronization (frequency synchronization) or time
synchronization, the clock synchronization or time
synchronization function of the corresponding ports
must be enabled on OTN devices to meet the
requirements of the PTP protocol. Otherwise, the
synchronization performance of downstream devices
cannot be ensured.
Fiber parameters When the OSC board is used for high-precision clock
synchronization, you need to correctly set the fiber
type, fiber length, and fiber dispersion coefficient on
the WDM Interface > Advanced Attributes page of
the NMS.

Intra-board 1+1 If both IEEE 1588v2 and intra-board 1+1 protection or

protection or optical optical line protection are configured, single-fiber
line protection bidirectional (OSC) must be used to implement IEEE
1588v2 time synchronization. If IEEE 1588v2 time
synchronization is implemented in two-fiber
bidirectional mode (ESC or OSC), fiber asymmetry will
occur after a switchover of boards such as OLP, DCP,
or OTU, affecting the time synchronization precision.
Packet LAG/APS/ERPS ● When the IEEE 1588v2 feature works with packet
LAG/APS/ERPS, it is recommended that the P2P TC
mode be used if NE Clock Type is set to TC.
Otherwise, set NE Clock Type to TC+BC.
● When the IEEE 1588v2 feature works with packet
LAG, it is recommended that Load Balancing be
set to Non-Sharing for LAG on the interconnection
points of BC/OC equipment if NE Clock Type is set
to TC+BC.

WDM OTN
Loopback For a board port that is configured with the IEEE

1588v2 function, if the loopback test is to be
configured on the port or the interconnected port, the
clock trace source of the NE where the port is located
must be switched to the protection clock source,
ensuring that the port loopback has no impact on the
clock function.
Fiber Doctor system When the IEEE 1588v2 feature works with the Fiber
Doctor system, service running and the IEEE 1588v2
clock synchronization may be affected. For details, see
the feature dependencies and limitations of the Fiber
Doctor system.
If the single-fiber bidirectional OSC board is used to
implement PTP time synchronization and intelligent
fiber management at the same time, pay attention to
the following points when using the Fiber Doctor
system:
● If the OSC_CLK_MISMATCH alarm is found on the
live network, online fiber detection using Default
Mode or Online mode in Advanced Mode is not
allowed.
● If no OSC_CLK_MISMATCH alarm is found on the
live network but more than four OLA sites are
deployed in an OMS, clock boards that meet
requirements need to be configured at the next
OLA site behind every four OLA sites. Otherwise,
online fiber detection using Default Mode or
Online mode in Advanced Mode is not allowed
because PTP time synchronization is affected in
this scenario.
● If online monitoring has been started for an OTS of
an OMS but the monitoring is not completed,
online monitoring cannot be started for other OTSs
on the OMS; otherwise, PTP time synchronization is
affected.
● If PTP time synchronization is also enabled, ensure
that online monitoring is started for no more than
14 OTSs on the entire network; otherwise, PTP
time synchronization is affected.

WDM OTN

Client 1+1 protection Client 1+1 protection and IEEE 1588v2 are mutually
exclusive. If both are configured, IEEE 1588v2 will
become abnormal.
Fiber Doctor system When the AST4 board works with the F5XCH/
F5UXCME/F5UXCM board, the line fiber quality
detection function cannot be configured together with
the physical-layer clock and IEEE 1588v2 functions.
Otherwise, the physical-layer clock and IEEE 1588v2
functions will be abnormal.
When the AST2 board works with the 11STG/12STG/
K2STG/16SCC/16XCH/16UXCM board, the line fiber
quality detection function cannot be configured
together with the physical-layer clock and IEEE
1588v2 functions. Otherwise, the physical-layer clock
and IEEE 1588v2 functions will be abnormal.
Optical-layer ASON When SFIU boards (including DAPXF boards that

function as SFIU boards) are used to configure or
reserve the IEEE 1588v2 function, optical-layer ASON
is not supported.
SDH ASON When the TNV2U210, TNU3U401 boards are used,

SDH ASON and IEEE 1588v2 are mutually exclusive as
follows:
● If SDH ASON has been enabled on the NMS, IEEE
1588v2 clock source ports cannot be configured.
● If IEEE 1588v2 clock source ports have been
configured, SDH ASON does not take effect.
Ring MSP When the TNV2U210, TNU3U401, NP200, and

NP200E boards are used, ring MSP and IEEE 1588v2
are mutually exclusive as follows:
● If ring MSP has been configured on a board port,
IEEE 1588v2 clock ports can be created on the
board.
● If an IEEE 1588v2 clock port has been created on a
board, ring MSP cannot be configured for the
board.

WDM OTN
Latency measurement When overhead bytes (2 rows, 3 columns) used for

(OTN) latency measurement are the same as the IEEE
1588v2 overhead bytes of the OTN interface (2 rows,
3 columns), and these overhead bytes transmit IEEE
1588v2 protocol packets concurrently, the IEEE 1588v2
transmission will be interrupted during the
measurement, adversely affecting services. Therefore,
IEEE 1588v2 and latency measurement cannot be
enabled at the same time.
NOTE
The UNS4 and UNQ2 boards of the OSN 1800 V support the
setting of the IEEE 1588v2 overhead bytes to a 1 x 13
structure (1 row, 13 columns). This avoids an overhead
conflict between IEEE 1588v2 and latency measurement.
Therefore, IEEE 1588v2 and latency measurement can be
enabled at the same time for the boards.
3.4 Availability
This section describes the board types and software versions that support IEEE
1588v2.
3.4.1 License Support

The IEEE 1588v2/ITU-T G.8275.1 feature can be used only when the corresponding
license is obtained on the NMS .
Table 3-9 License function and application description

Function Application
The IEEE 1588v2/ITU-T G.8275.1 Before configuring the IEEE 1588v2/

feature can be used only when the ITU-T G.8275.1 feature for an NE, you
corresponding license is obtained. must enable the feature. One license is
required for enabling this feature on
each NE.

Version Support
1588v2 in the OSN 9800 universal platform subrack.

WDM OTN
Table 3-10 Boards and device versions that support IEEE 1588v2 in the OSN 9800
universal platform subrack (optical-layer configuration)
Clock boards TN12STG V100R001C20
TN13STG V100R002C10
AST2 V100R002C10

multiplexer and
NOTE
Time synchronization can be implemented only when a clock board is configured for a
subrack.

1588v2 in OSN 9800 P series subracks.
NOTE
Only some boards support high-precision clock synchronization. For details, see 5 High-
Precision Clock Synchronization Solution.
Table 3-11 Boards and device versions that support IEEE 1588v2 in OSN 9800 P
series subracks (optical-layer configuration)

board
TMP2CTUHP V100R019C10

board
Optical line TMP1ON32, TMP1ON32P V100R007C00

board

WDM OTN
TMP2ON20HHP, TMP2ON20PHHP, V100R021C10

TMP2ON32HHP, TMP2ON32PHHP,
TMP3ON20HHP, TMP3ON20PHHP

TMP2ON32HEHP, TMP2ON32PHEHP
NOTE
HP: indicates that the board supports high-precision clock synchronization. Only products in
V100R021C10SPC300 (with NCE V100R021C10SPC200) and later versions support high-
precision clock synchronization.

1588v2 in OSN 9800 U series subracks.
NOTE
Only OSN 9800 U32E/U64E enhanced subracks support high-precision clock
synchronization. OSN 9800 U32/U64 standard subracks do not support high-precision clock
synchronization.
Table 3-12 Boards and device versions that support IEEE 1588v2 in OSN 9800 U
series subracks (electrical-layer configuration)
Clock board TNU1CTU V100R001C20
TNS1CTU V100R001C30
TNU2CTU, TNU4CTUHP V100R007C00
TNU5CTUHP V100R019C10

board
Tributary board T130, T216, T210, T220, G210, G220 V100R001C20
E124, E208, E212, E302, E401 V100R001C30
T230, TNV3T404 V100R002C10
G402, G404, T220E V100R003C10
TNV3T401, TNV3T402 V100R005C00
TNV5T404, TNV5T401, TNV5T402, V100R007C00

TNV3G220, TNV6T220, TNV7T402

WDM OTN
TNV1T210U, TNV1T502HP, TNV8T404, V100R019C10

TNV2E224, TNV2E402, TNV3E402HP,
TNV3E224HP, TNV8T402, TNV7T220,
TNV1T410
TNV1T402EHP, TNV3T220EHP, V100R020C10

TNV3E404HP, TNV6G216a, HP
TNV6T216b, HP, TNV6T230b, HP, V100R021C00

TNV6G230b, HP, TNV7S216b, HP (OTN
tributary)
TNV4E404HP, TNV4E224HP V100R022C00
Line board TNU1NP400/TNU1NP400E V100R001C20
U401, U210 V100R001C30
TNU3U401, TNV2U210 V100R002C10
U402 V100R005C00
TNV5U220, TNV5U210, TNU5U401, V100R007C00

TNU5U501, TNU6U402, TNU5NP200/
TNU5NP400E

TNU6U402C
TNU6U502 V100R020C10
TNU7U402, TNU6U316 V100R021C00
TNS5NP400/TNS5NP400E V100R021C10
TNU8U402, TNU8U402C, TNV7U220 V100R022C00
TNS5N401PE, TNS5N401P, V100R022C10

TNS5N501PSE, TNS5N501PS

WDM OTN
● HP: indicates that the board supports high-precision clock synchronization.

Only products in V100R021C10SPC300 (with NCE V100R021C10SPC200) and
later versions support high-precision clock synchronization. XFIU units do not
affect synchronization precision.
● You are advised to use OSC boards to implement PTP time synchronization
between sites. The single-fiber bidirectional OSC mode supports
commissioning-free and delay compensation-free functions. However, when
line boards are used to configure PTP time synchronization, compensation for
asymmetric delay is required, the construction cost is high, and the
maintainability is poor. Therefore, this mode is not recommended.
● For OTN line ports, IEEE 1588v2 can be used only when lower-order ODUk
cross-connections are configured for the ports.
● For the tributary ports that receive Ethernet services, IEEE 1588v2 can be
used only after services are configured for the ports.
● T130: Only ports 1 to 7 and ports 9 to 15 support IEEE 1588v2.
● T216/TNV1T210: Only ports 1 to 4 support IEEE 1588v2.
● TNV2T220/TNV2G220/TNV3T230/TNV3T220/TNV2T220E/TNV6T220/
TNV7T220/TNV6T216/TNV6T230/TNV6G230/TNU6U316/TNV7U220: Only
ports 1 to 15 support IEEE 1588v2.
● : When an electrical module is installed in a port, the port does not support
IEEE 1588v2.
● Boards do not support IEEE 1588v2 when working in relay mode.
● The boards that work with TNU2CTU support IEEE 1588v2 since
V100R007C00.
● When TNS5NP400/TNS5NP400E is interconnected with TNU5NP400/
TNU5NP400E or TNU1NP400/TNU1NP400E, IEEE 1588v2, ITU-T G.8273.2,
and ITU-T G.8275.1 are not supported.
● When TNS5N401P/TNS5N401PE is interconnected with TNU5NP400/

WDM OTN
When OTN tributary ports receive Ethernet services, the working modes of the
ports that support IEEE 1588v2 vary according to the encapsulation type. The
Table 3-13 Port working modes supported by different port service mapping paths
Service Port Mapping Encapsulati Port PTP ETH
Type on Mode Working Encapsulati
Mode (TC, on
TC+OC, BC,
or OC)
GE GE(GFP-T) GFP-T Supported Supported
GE (TTT-GMP) TTT+GMP Not Not

supported supported
10GE LAN MAC transparent GFP-F Supported Supported

mapping (10.7G)
Bit transparent IMP+BMP Not Not

mapping (11.1G) supported supported
100GE MAC transparent GFP-F Supported Supported

mapping ODU4
(100G)
Bit transparent GMP Not Not

mapping ODU4 supported supported
(100G)
MACB2B MACB2B Supported Supported
200GE MAC transparent Mac (IMP) Supported Supported

mapping (inverse
multiplexing)
Bit transparent IMP Not Not

mapping (inverse supported supported
multiplexing)
25GE/50GE MAC transparent GFP-F Supported Supported

mapping (GFP-F)
Bit transparent BMP Not Not

mapping (BMP) supported supported

mapping (GFP-F)

WDM OTN
NOTE
● When the port working mode is ODUflex non-convergence mode (Any->ODUflex), the
TC, TC+OC, BC, and OC modes and PTP ETH encapsulation are supported.
● All packet service boards listed in Table 3-12 support the TC, TC+OC, BC, and OC
working modes and the PTP ETH and PTP IP encapsulation modes.

1588v2 in OSN 9800 M series subracks.
NOTE
Table 3-14 Boards, devices, and product versions that support IEEE 1588v2
TMF1AUXa, HP, TNG3CXPHP V100R007C00
TME1CTUHP, TME2CTUHP V100R019C10
TME3CTUHP, TMF3AUX01HP V100R020C10
TNG4CXPHP V100R021C00
TMF2AUX01HP V100R021C10

board
TMF1AUXa, HP V100R007C00
TNG3OH20HHP (OSC unit) V100R020C10
TNG2AST4HP, TNG3OH20 (OSC unit) V100R021C00
TNG2AST4EHP, TNG2OH20 (OSC unit), V100R021C10

TNG2OH20HHP (OSC unit)
TNG2OH9HP, b (OSC unit) V100R022C00
TNG3DAFS (OSC unit)HP V100R022C10

WDM OTN

OTU board TNG1M402 V100R006C00

TNG1M502DM
TNG1M504DM, TNG1M520SMHP, V100R019C10

TNG1M404DM, TNG1M210D,
TNG2M604SM
TNG1M520SHP, TNG3M402D, V100R021C10

TNG3M504D
TNG1M411SMPHP, TNG1M828SMHP, V100R022C10

TNS5NP400YHP

T210, T220, T230

TNV3G220, TNV3T404, TNV3T401,
TNU1G404, TNV6T220, TNV7T402

TNV2E224, TNV2E402, TNV3E402HP,
TNV3E224HP, TNV8T402, TNV7T220,
TNV1T410, TNG2A212 (tributary
mode)

TNV3E404HP, TNV6G216HP
TNV6T216HP, TNV6T230HP, V100R021C00

TNV6G230HP, TNV7S216HP (OTN
tributary), TNG3A204HP (OTN
tributary)

mode), TNV4E404HP, TNV4E224HP
TNG1T210EHP V100R022C10
Line board TNU5NP200/TNU5NP200E, V100R006C00

TNU5NP400/TNU5NP400E, U402

WDM OTN

TNU5U501, TNU6U402

TNU6U402C
TNU6U502 V100R020C10
TNU7U402, TNU6U316 V100R021C00

NOTE
● HP: indicates that the board supports high-precision clock synchronization. Only
products in V100R021C10SPC300 (with NCE V100R021C10SPC200) and later versions
support high-precision clock synchronization. XFIU units do not affect synchronization
precision.
● You are advised to use OSC boards to implement PTP time synchronization between
sites. The single-fiber bidirectional OSC mode supports commissioning-free and delay
compensation-free functions. However, when line boards are used to configure PTP time
synchronization, compensation for asymmetric delay is required, the construction cost is
high, and the maintainability is poor. Therefore, this mode is not recommended.
● For OTN line ports, IEEE 1588v2 can be used only when lower-order ODUk cross-
connections are configured for the ports.
● For the tributary ports that receive Ethernet services, IEEE 1588v2 can be used only after
● TNV1T210: Only ports 1 to 4 support IEEE 1588v2.
● TNV3T230/TNV3T220/TNV6T220/TNV7T220/TNV6T216/TNV6T230/TNV6G230/
TNU6U316/TNV7U220: Only ports 1 to 15 support IEEE 1588v2.
● The port equipped with an electrical module does not support IEEE 1588v2.
V100R006C10).
function.
● b: The TNG2OH9 board supports high-precision clock only when it uses the BIDI OSC
module.
● TNG1T210E: IEEE 1588v2 is not supported when its port type is VP.
10GE channel of the 4 x 10GE services supports IEEE 1588v2.
● When TNS5NP400/TNS5NP400E is interconnected with TNU5NP400/TNU5NP400E or
TNU1NP400/TNU1NP400E, IEEE 1588v2, ITU-T G.8273.2, and ITU-T G.8275.1 are not
supported.
● When TNS5N401P/TNS5N401PE is interconnected with TNU5NP400/TNU5NP400E or
supported.

WDM OTN
Mode (TC, on
TC+OC, BC,
or OC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (inverse
multiplexing)

multiplexing)

mapping (GFP-F)


mapping (GFP-F)

WDM OTN

1588v2 in OSN 8800 subracks.
Table 3-16 Boards and device versions that support IEEE 1588v2 in OSN 8800
subracks
Clock board TN52STG, TNK2STG V100R002C00
TN16XCH V100R006C00
TN16SCC V100R006C01
TN16UXCM V100R007C00
TN12STG V100R008C10
TN54STG V100R009C10
TN13STG, TNK3STG V100R010C10
Clock interface TN52STI V100R002C00

board
TN16ATE V100R006C00
AST2 V100R011C00

multiplexer and
board
Tributary board TOG V100R002C00
LEM24, LEX4 V100R005C00
THA, TOA, TN55TQX, TN53TDX V100R006C01
TOX, THX V100R007C00
EG16, EX2 V100R008C10
EX8, TN55TTX V100R009C00
TN55TSC V100R012C00
LQCP V100R013C00
Line board TN54NQ2, TN52ND2 V100R002C00
TN54NS3 V100R005C00
NPO2, NPO2E, TN53NQ2, TN53ND2, V100R006C01

TN53NS2, TN57NQ2, TN57ND2

WDM OTN
NPS4, NPS4E, HUNQ2, HUNS3 V100R009C10

NOTE
● Time synchronization can be implemented only when a clock board is configured for a
subrack.
● The TN52ND2T04 board does not support IEEE 1588v2.
● The line board TN52ND2 does not support frequency synchronization using IEEE 1588v2
packets. Other line boards support frequency synchronization using IEEE 1588v2 packets
in the same way as they support frequency synchronization using physical-layer clocks.
For details, see 2.4.5 OSN 8800 Hardware and Version Support.
Mode (TC, on
TC+OC, BC,
or OC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

WDM OTN

Mode (TC, on
TC+OC, BC,
or OC)

(100G)

mapping (inverse
multiplexing)

multiplexing)

mapping (GFP-F)


mapping (GFP-F)

1588v2 in OSN 6800 subracks.
Table 3-18 Boards and device versions that support IEEE 1588v2 in OSN 6800
subracks

board
TN12STG V100R008C10
TN13STG V100R010C10
AST2 V100R011C00

WDM OTN

multiplexer and
board
Tributary board LEM24, LEX4, TN52TOG, TN55TQX V100R005C00
TN53TDX V100R006C01
Line board TN12ND2, TN52ND2 V100R005C00
TN53NQ2, TN53ND2, TN53NS2 V100R006C01

NOTE
subrack.
configured.
● The TN52ND2T04 board does not support IEEE 1588v2.
● For the TN12XCS board, only VER.C supports IEEE 1588v2.
Mode (TC, on
TC+OC, BC,
or OC)

supported supported

mapping (10.7G)

WDM OTN

Mode (TC, on
TC+OC, BC,
or OC)


mapping ODU4
(100G)

(100G)

mapping (inverse
multiplexing)

multiplexing)

mapping (GFP-F)


mapping (GFP-F)

1588v2 in OSN 1800 V subracks.
Table 3-20 Boards and device versions that support IEEE 1588v2 in OSN 1800 V
subracks
Clock board TNF5UXCM (F5STG) V100R005C00
TNF5XCH (F5STG) V100R005C00
TNF5UXCME (F5STG) V100R005C20

WDM OTN

board
TMB1AUX V100R020C10
TMB2AUX V100R021C10
AST4 V100R006C20


unit)

multiplexer and



unit)
OTN tributary TOA, TQX V100R005C00

board
TTA V100R006C20

(client side)
F1LDCA V100R008C10

B1LDCD, B1LDC

WDM OTN
TMB2ELOM, TMB2LDX V100R022C10
Line board UNS4, Z5UNQ2 V100R009C00
TNZ8UNS4, TNZ9UNS4 V100R021C00
OTU board B1ELOM, B1LDX, B1LTX, B1LDCA V100R019C10

(line side)
Packet board EM20 V100R005C10
EX4, EG10 V100R008C00
NOTE
● When an electrical module is inserted into a port of the board, IEEE 1588v2 is not
supported.
● When the EM20 board works with the Z5UXCMS system control board, IEEE 1588v2 is
supported since V100R020C10.
● The TQX board does not support IEEE 1588v2 with ODUflex non-aggregation mode
(Any->ODUflex).
● When the service cross-connections on the line board are switched, IEEE 1588v2 clock
tracing is affected. As a result, the clock source may be switched temporarily.
When the OTN board receives Ethernet services, the working modes of the ports
that support IEEE 1588v2 vary according to the encapsulation types. The following

WDM OTN

Mode (TC, on
TC+OC, BC,
or OC)
GE GE (GFP-T) GFP-T Supported Supported

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (GFP-F)

NOTE
● For line boards, Clock Type can only be set to BC or OC, and P/E Mode can only be set to
E2E.
● When receiving Ethernet services, OTN tributary ports only support the BC or TC mode of
Clock Type, and only support the PTP ETH encapsulation mode.
● When receiving OTN services, OTN tributary ports only support the BC or OC mode of Clock
Type, and only support E2E of P/E Mode.
● The OSC boards support only BC and OC modes.
● When receiving GE or 10GE LAN services, the EM20 board (working with the F5UXCM/
F5UXCME board) supports the TC, TC+OC, BC, and OC modes and both PTP ETH
encapsulation and PTP IP encapsulation. When working with the Z5UXCMS board, the EM20
board supports only the BC mode and both PTP ETH encapsulation and PTP IP
encapsulation.
● When receiving GE or 10GE LAN services, the EX4 and EG10 boards support only the BC
mode but support both PTP ETH encapsulation and PTP IP encapsulation.

1588v2 in OSN 1800 II Enhanced subracks.

WDM OTN
Table 3-22 Boards and device versions that support IEEE 1588v2 in OSN 1800 II
Enhanced subracks

board
TMB1AUX V100R020C10
TMB2AUX V100R021C10


unit)

multiplexer and


unit)

board

(client side)
LDCA V100R008C10

B1LDC
TMB2LDC V100R021C10

WDM OTN
Line board Z8UNQ2, Z8UTX2 V100R019C10

(line side)
Packet board UXCL (EX1) V100R007C10
EX4, EG10 V100R008C00
NOTE
supported.

Mode (TC, on
TC+OC, BC,
or OC)

supported supported

mapping (10.7G)

WDM OTN

Mode (TC, on
TC+OC, BC,
or OC)


mapping ODU4
(100G)

(100G)

mapping (GFP-F)

NOTE
● The ST2, AST4, and LDCA boards support only BC and OC modes.
● When receiving GE or 10GE LAN services, the UXCL (EX1) board supports only the BC mode
and supports both PTP ETH encapsulation and PTP IP encapsulation.
● When receiving GE or 10GE LAN services, the EX4 and EG10 boards support only the BC
mode but support both PTP ETH encapsulation and PTP IP encapsulation.

1588v2 in OSN 1800 I&II Compact subracks.
Table 3-24 Boards and device versions that support IEEE 1588v2 in OSN 1800 I&II
Compact subracks (TNF3SCC)
AST4 V100R006C20

WDM OTN

multiplexer and
OTU board F2ELOM (STND), TNF2LDX V100R006C00

(client side)
F1LDCA V100R008C10

B1LDC

(line side)
NOTE
supported.
Mode (TC, on
TC+OC, BC,
or OC)

supported supported

mapping (10.7G)


WDM OTN

Mode (TC, on
TC+OC, BC,
or OC)

mapping ODU4
(100G)

(100G)

mapping (inverse
multiplexing)

multiplexing)

mapping (GFP-F)


mapping (GFP-F)

1588v2 in OSN 1800 V Pro subracks.
NOTE
Table 3-26 Boards and device versions that support IEEE 1588v2
Clock board TMK5SXCH (K5STG)HP V100R019C10
TMK5XCH (K5STG)HP, TMK5UXCME V100R021C00

(K5STG)HP

WDM OTN
TMK6UXCM (K6STG)HP, TMK5GSCC V100R021C10

(K5STG)HP
TMK6XCH (K5STG)HP V100R022C10
Clock TMB1AUXHP V100R020C10

interface
board TMB2AUXHP V100R021C10

TMB2AST2
TMB1MR4AFSHP/TMB1MR4FSHP (OSC V100R021C00

unit)

unit), TMB1MD48AFSHP (OSC unit)
TMB1DFSHP/TMB1SFSHP/TMB1FSHP V100R022C00
(OSC unit)
TMB1CMD4HP (OSC unit) V100R022C10

multiplexer
board


unit)
OTN tributary TMK1TTAHP, TMK1TDCHP, TMK1GTAHP V100R019C10

TMB3EMS10 (B3TEM10) V100R021C10
OTU board TNF2LDX, TNF2ELOM, TMB1ELOMHP, V100R019C10

(client side) TMB1LDXHP, TMB1LDCD, TMB1LDC,
TMB1LDCAHP, TMB1LTXHP,
TMK1MDCAHP

WDM OTN
TMB2LTXHP, TMB2LDCAHP, V100R021C00

TMK2MDCAHP
TMB2ELOMHP, TMB2LDXHP, V100R022C10

TMB1LTXMPHP
Line board TMK1UNS5, TMK1UNQ2, TMK1GTA V100R019C10

(line mode)
OTU board TMB1ELOM, TMB1LDX, TMB1LDCA, V100R019C10

(WDM side) TMB1LTX, TMK1MDCA
TMB2ELOM, TMB2LDX, TMB1LTXMPHP V100R022C10
NOTE
precision.
supported.

WDM OTN
Mode (TC, on
TC+OC, BC,
or OC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (GFP-F)

NOTE
E2E.

1588v2 in OSN 1800 II Pro subracks.
NOTE

WDM OTN
Clock board TMK2UXCL (K2STG)HP V100R019C10
TMK2UXCLE (K2STG)HP V100R021C00
Clock F1AUX V100R019C10

interface
TMB2AUXHP V100R021C10

TMB2AST2

unit)

(OSC unit)

multiplexer
board


unit)


TMK1MDCAHP

WDM OTN

TMK2MDCAHP

TMK1NP400ME

TMB1LTXMPHP

(line mode)

TMK1NP400M/TMK1NP400ME V100R021C10
NOTE
precision.
supported.

WDM OTN
Mode (TC, on
TC+OC, BC,
or OC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (GFP-F)

NOTE
E2E.

1588v2 in OSN 1800 II TP subracks.
NOTE

WDM OTN
Table 3-30 Boards and device versions that support IEEE 1588v2 (optical-layer
configuration)
Clock board TMB1SCC (B1STG)HP V100R009C00
TMT1SCC (T1STG)HP V100R021C00
Clock interface TMB1AUXHP V100R020C10

board

unit)

(OSC unit)

multiplexer and



unit)

(client side)
TMB1LTXHP, TMB1LDCAHP, TMB1LDCD,
TMB1LDC, TMK1MDCAHP

WDM OTN

TMK2MDCAHP

TMB1LTXMPHP

(WDM side) TMB1LDCA, TMK1MDCA
NOTE
precision.
supported.

Mode (TC, on
TC+OC, BC,
or OC)

WDM OTN

Mode (TC, on
TC+OC, BC,
or OC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (GFP-F)


1588v2 in OSN 1800 I Compact subracks.
Table 3-33 Boards and device versions that support IEEE 1588v2 in OSN 1800 I
Compact subracks
Clock board TMC1SCC (C1STG)HP V100R022C10
OTU board TMB2ELOMHP, TMB2LDXHP, V100R022C10

(client side) TMB2LTXHP, TNF3ELOM, TNF3LDX
OTU board TMB2ELOMHP, TMB2LDXHP, V100R022C10

(line side) TMB2LTXHP
NOTE
supported.

WDM OTN
Mode (TC, on
TC+OC, BC,
or OC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (inverse
multiplexing)

multiplexing)

mapping (GFP-F)


mapping (GFP-F)

WDM OTN
3.5 Specifications
This section describes the specifications for IEEE 1588v2.
Table 3-35 lists the specifications for IEEE 1588v2.
Table 3-35 IEEE 1588v2 specifications

Item Specifications
Clock The equipment supports the following clock modes:

model ● OC
● BC
● TC
● TC+OC
● TC+BC
A port supports the following clock modes:

● OC
● BC
● TC
● TC+OC
NOTE
For the relationships between NE working modes, port working modes, and
port types, see 3.3.1 Feature Limitations.
Clock BMC algorithm: supported

source
selection Static selection for time sources: supported
algorith
m
Packet ● PTP packet encapsulation format: Ethernet 802.3 (PTP ETH) and
encapsul UDP/IPv4 (PTP IP)
ation ● PTP packet VLAN: supported
format
NOTE
● For ports on packet boards, the encapsulation format of PTP packets can
be set to PTP ETH or PTP IP, and the VLAN IDs can be set.
● When receiving Ethernet services, OTN tributary ports only support the
PTP ETH encapsulation mode, and VLAN IDs can be set.
● Clock synchronization GE optical ports only support the PTP ETH
encapsulation mode, and VLAN IDs can be set.
● OTN line ports and OSC ports transmit PTP packets through overhead
bytes, and neither encapsulation format nor VLAN ID is involved.

WDM OTN
Item Specifications
Phase Delay measurement:

synchron ● End-to-end delay measurement (E2E mode): supports the one-
ization step or two-step mode.
● Peer-to-peer delay measurement (P2P mode): supports the one-
step or two-step mode.
NOTE
Only packet board ports and OTN tributary ports support the P2P and one-
step modes.
Supported Ethernet ports:

● GE optical ports
● 10GE optical ports
● 40GE optical portsa
● FlexE portsb
NOTE
● SFP electrical modules do not support IEEE 1588v2.
● a: Only 40GE optical ports on packet boards support IEEE 1588v2.
● b: Only FlexE ports (100G/200G) on the TNG1M804SM/TNV1T502 board
support IEEE 1588v2 since V100R020C10.
Time synchronization precision: The time synchronization precision

of a network containing 30 or less NEs is less than ±1 μs.
Frequenc Supported Ethernet ports:

y ● GE optical ports
synchron
ization ● 10GE optical ports
● 40GE optical portsa
● FlexE portsb
NOTE
● SFP electrical modules do not support IEEE 1588v2.
● a: Only 40GE optical ports on packet boards support IEEE 1588v2.
● b: Only FlexE ports (100G/200G) on the TNG1M804SM/TNV1T502 board
support IEEE 1588v2 since V100R020C10.

WDM OTN
Item Specifications
Frequency synchronization precision: The frequency recovery

precision of a network containing 20 NEs complies with the ITU-T G.
823 SEC template.
Delay ● Automatic compensation upon a fiber cut on a ring network

compens ● Single-fiber bidirectional asymmetric compensation
ation
NOTE
type Only the following boards on the following products support automatic
compensation of ring network delay offset. For details about the restrictions,
see 3.3.1 Feature Limitations.
● OSN 1800 V (Z-series system control boards) V100R009C00 and later
versions: UNS4, EX4, EG10, and UNQ2
● V100R021C10 and later versions: UNS5, UNS4, GTA, UNQ2, UND3 and
EX10
● V100R021C10 and later versions: UNS5, UNS4, GTA, UNQ2, UND3 and
EX10
External Supports 1PPS+ToD external time ports. For details, see 3.2.4 Time
time Source Port.
port

WDM OTN
Item Specifications
Clock ● OSN 9800:

cascadin – Universal platform subrack: The universal platform subracks on
g the same NE implement frequency/phase synchronization
between through clock cascading between master and slave subracks.
master
and – U series subrack:
slave In versions earlier than V100R007C00, electrical subracks on
subracks the same NE do not support clock cascading between master
and slave subracks. Therefore, only one electrical subrack on
each NE supports frequency/phase synchronization. You are
advised to configure all boards requiring frequency and phase
synchronization in the same subrack.
In V100R007C00 and later versions, when the system control
board is TNU2CTU or TNS2CTU, electrical subracks on the
same NE support clock cascading between master and slave
subracks. When the system control board is TNU4CTU or
TNU5CTU, electrical subracks on the same NE support clock
– M series subracks: Clock cascading between master and slave
subracks is supported.
– P series subracks: Clock cascading between master and slave
– Clock cascading between master and slave subracks cannot be
implemented between universal platform subracks and U/M
series subracks.
● OSN 1800:
– Subracks that use the TMB1AUX board support clock cascading
between master and slave subracks since V100R020C10. The
ports supported by the TMB1AUX board are external clock/
time ports and clock synchronization GE optical ports.
– Subracks that use the TMB2AUX/MD48AFS board support
clock cascading between master and slave subracks since
V100R021C10. The ports supported by the TMB2AUX board are
external clock/time ports and clock synchronization GE optical
ports. The ports supported by the MD48AFS board are clock
– Subracks that use the TMK5SXCH/TMK5UXCME/TMK5XCH/
TMK5GSCC board support clock cascading between master
and slave subracks since V100R022C00. The ports supported by
the board are clock synchronization GE optical ports.
– Subracks that use the TMK6XCH board support clock cascading
between master and slave subracks since V100R022C10. The
ports supported by the board are clock synchronization GE
optical ports.
● OSN 8800/6800: Clock cascading between master and slave

WDM OTN
Item Specifications
NOTE
Clock cascading between master and slave subracks is supported only when
subracks are configured in master/slave mode. For details about the
specifications and capabilities of the master and slave subracks, see
● For carriers: WDM OTN Master-Slave Subrack Management Guide
● For enterprises: WDM OTN Master-Slave Subrack Management Guide
When the OSN 9800/OSN 8800/OSN 6800 subracks that support master-slave
subrack clock cascading implement the clock cascading function, two clock
boards need to be configured for each subrack. The master clock subrack can
be configured in the slave service subrack. Master and slave service subracks
can be separated from master and slave clock subracks.
3.6 Feature Updates

This topic describes the IEEE 1588v2 feature updates in the product versions, the
reasons for the updates, and the corresponding information updates. Any product
versions that are not listed in the document means that they have no feature
updates.
NOTE

The IEEE 1588v2 feature is available since OSN 9800 V100R001C20.

OSN 9800 U/M/P series The product function is 3.4.3 OSN 9800 P Series
subracks (with NCE enhanced. Hardware and Version
V100R021C10SPC200 Support
and later versions) newly 3.4.4 OSN 9800 U Series
support high-precision Hardware and Version
clock synchronization. Support
3.4.5 OSN 9800 M
Series Hardware and
Version Support
5 High-Precision Clock
Synchronization
Solution
The clock The product function is 3.2.4 Time Source Port

cascading mode.

WDM OTN

The external time port The product function is 3.8.1.10.3 Parameters:

newly supports enhanced. Clock Synchronization
transmission of G.8271 Attribute
packets.


supported.

Update the Change
The new Added a new 3.4.5 OSN 9800 M Series Hardware and
OptiX OSN subrack to Version Support:
9800 M05 support basic Added OptiX OSN 9800 M05 subrack-related
subrack functions. information.
(system
control board:
TME1CTU/
TME2CTU)
supports IEEE
1588v2.
series subrack
is added to
support IEEE
1588v2.

WDM OTN

Update the Change
OSN 9800 enhanced.
M24 subrack
is added to
support IEEE
1588v2.

Update the Change
support IEEE
1588v2.
series subrack ● 3.8.1 Configuring IEEE 1588v2 (OSN
is added to 1800/8800/9800Universal Platform
support IEEE Subrack/M Series/P Series/(U Series:
1588v2. U2CTU/S2CTU/U4CTU/U5CTU)): Added
the TNU4CTU board.
OSN 9800 enhanced.
M24 subrack
is added to
support
physical-layer
clocks.

WDM OTN

Update the Change
The OSN The product 3.4.3 OSN 9800 P Series Hardware and
9800 P series function is Version Support:
subrack is enhanced. Added the description of the OSN 9800 P
added to series subrack.
support IEEE
1588v2.
OSN 9800 U ● 3.8.1 Configuring IEEE 1588v2 (OSN
series subrack 1800/8800/9800Universal Platform
are added to Subrack/M Series/P Series/(U Series:
support IEEE U2CTU/S2CTU/U4CTU/U5CTU)): Added
1588v2. TNU2CTU and TNS2CTU.
When The product 3.5 Specifications:

equipped with function is Added the description that the OSN 9800 U
the TNU2CTU enhanced. series subrack supports clock cascading
or TNS2CTU between master and slave subracks.
board, the
OSN 9800 U
series
subracks
support clock
cascading
between
master and
slave
subracks.
Updates in V100R006C00 Compared with V100R005C10SPC200

The OSN 9800 M24 Added a new subrack to 3.4.5 OSN 9800 M
subrack is added to support basic functions. Series Hardware and
support IEEE 1588v2. Version Support:
Added OSN 9800 M24
subrack-related
information.

WDM OTN
Updates in V100R001C30SPC100 Compared with V100R001C30

The OSN 9800 U16 Added a new subrack to 3.4.4 OSN 9800 U Series
subrack is added to support basic functions. Hardware and Version
support IEEE 1588v2. Support:
Added the OSN 9800
U16 subrack.
The NMS GUI for IEEE The NMS GUI is 3.8.2 Configuring IEEE
1588v2 of OSN 9800 optimized. 1588v2 (OSN 9800 U
U64/U32/U16 subrack is Series: U1CTU/S1CTU):
changed. Added the entire chapter.
The feature is available IEEE 1588v2 is a standard The entire chapter is

since this version. defining the precision added.
clock synchronization
protocol for
measurement and
control systems. This
standard defines the PTP,
which enables accurate
clock synchronization
between distributed and
standalone devices in
measurement and
control systems. The
standard permits phase
synchronization accuracy
better than 1
nanosecond.

The IEEE 1588v2 synchronization is available since the OSN 8800 of V100R002C00
and OSN 6800 of V100R005C00.

WDM OTN

The TN54TOG/ This function can be used ● The 3.8.1.10.11

TN54TOA/TN57TOA/ to configure the physical Parameters: MAC
TN54THA boards newly addresses for sending Address
support MAC address PTP and SSM packets so Configuration is
configuration. that fields can be filled in added.
to the sent packets based ● 3.8.1.5 Configuring
on the requirements of PTP Port Parameters:
the downstream The procedure for
equipment, improving configuring the MAC
the configuration addresses is added.
flexibility for
interconnection with
third-party equipment.
The maximum value of The range for the 3.8.1.10.3 Parameters:

ANNOUNCE Packet timeout duration of Clock Synchronization
Timeout Coefficient ANNOUNCE packets on a Attribute:
for the TN54TOG/ board is increased, The ANNOUNCE Packet
TN54TOA/TN57TOA/ enhancing the error Timeout Coefficient
TN54THA boards is tolerance capability for parameter value range is
extended from 10 to interconnection with extended.
255. third-party equipment.
The limitations of When the TN52TOG/ 3.3 Dependencies and

ANNOUNCE Packet TN54TOG/TN54TOA/ Limitations:
Period(s) for the TN57TOA/TN54THA Limitations of
TN52TOG/TN54TOG/ board is interconnected ANNOUNCE Packet
TN54TOA/TN57TOA/ with a PTN device to Period(s) are added.
TN54THA board are transmit IEEE 1588v2
added. clock signals,
ANNOUNCE Packet
Period(s) must be set to
64/1028; otherwise, the
interconnected PTN
device may fail to
properly trace clock
sources after the link is
broken.

WDM OTN

The EX2 and EG16 The boards are new to ● 3.4.6 OSN 8800
boards are added and the product and should Hardware and
they support IEEE support the basic board Version Support: A
1588v2. functions. description is added to
explain that packet
IEEE 1588v2.
● 3.3 Dependencies
and Limitations: A
description is added to
explain that packet
IEEE 1588v2.
● 3.8.1.4 Configuring
PTP NEs: A description
is added to explain
that the packet service
boards support
Configuring the PTP
Clock Domain.
The OSN 8800 universal The clock function is 3.3 Dependencies and
platform subrack newly enhanced. Limitations:
supports IEEE 1588v2. A description is added to
explain that the OSN
8800 universal platform
subrack supports IEEE
1588v2.
The TN12STG board is The product function is 3.4.6 OSN 8800

added, and it supports enhanced. Hardware and Version
time source acquisition. Support and 3.4.7 OSN
6800 Hardware and
Version Support:
Descriptions of the
TN12STG board are
added.

WDM OTN

The STG clock board The product function is 3.2.4 Time Source Port:
newly supports mutual optimized to meet the The STG clock board's
conversion between requirements of function of mutual
1PPS+TOD quality industrial standards. conversion between 1PPS
information and IEEE +TOD quality information
1588v2 time quality and IEEE 1588v2 time
levels. quality levels is described
in detail.
PTP Clock Domain is The PTP clock domain ID ● 3.8.1.4 Configuring

added and the can differ from the clock PTP NEs: Operations
parameter is subnet ID of NEs during are added for setting
configurable. the exchange of Pdelay PTP Clock Domain.
messages only when ● 3.8.1.10.3
Work Mode is set to TC Parameters: Clock
or TC+OC and P/E Mode Synchronization
is set to P2P for PTP Attribute: The
ports. To interconnect Domain ID is
with the peer device, you described.
need to set the domain
ID of the port to be the
same as that of the peer
device.

The 10GE LAN port The NMS GUI is None.

mapping mode of the optimized.
TN55TQX, TN53TDX,
TOX boards are changed
from MAC transparent
mapping (10.7G)
support 1588 to MAC
transparent mapping
(10.7G).

WDM OTN

The service types for the The NMS GUI is None.

TOG, TOA, and THA optimized.
boards are changed
from GE (TTT-AGMP) to
GE (TTT-GMP).

N/A Information optimization 3.4.6 OSN 8800

Support and 3.4.7 OSN
6800 Hardware and
Version Support:
Information is added to
show whether a tributary
board supports TC, TC
+OC, BC, or OC under a
specific client service
configuration.

This section describes the start version and change history of the IEEE 1588v2
feature.

IEEE 1588v2 ● 1800 V V100R005C00

● 1800 I&II Compact (F3SCC) V100R006C00
● 1800 II TP V100R009C00
● 1800 V Pro V100R019C10
● 1800 II Pro V100R019C10

WDM OTN

The 1800 V Pro, 1800 II The product function is 3.4.11 OSN 1800 V Pro
Pro, and 1800 II TP (with enhanced. Hardware and Version
NCE Support
V100R021C10SPC200 3.4.12 OSN 1800 II Pro
and later versions) newly Hardware and Version
support high-precision Support
3.4.13 OSN 1800 II TP
Support
Synchronization
Solution

The 1800 V Pro and 1800 The product function is 3.3.1 Feature
II Pro chassis (with NCE enhanced. Limitations
V100R021C10SPC200 3.8.1.1 Configuration
and later versions) newly Process
support automatic
compensation for ring 3.8.1.9 Configuring Ring
network delay offset and Network Automatic
automatic single-fiber Compensation
bidirectional
compensation.


supported.

packets.

WDM OTN

Feature Update Reason for the Information Update
Change
The new 1800 V Pro This subrack is new Added 3.4.11 OSN 1800 V Pro
chassis supports to the product and Hardware and Version Support.
IEEE 1588v2. should support basic
device functions.
The new 1800 II Pro This subrack is new Added 3.4.12 OSN 1800 II Pro
device functions.

Change
The new 1800 II TP This subrack is new Added 3.4.13 OSN 1800 II TP
device functions.

Update Update
The line The product function is enhanced. 3.4.8 OSN

boards of 1800 V
OSN 1800 V Hardware
are added to and Version
support IEEE Support:
1588v2. Added the
descriptions
of line boards.

WDM OTN

Update Update
The OSN The product function is enhanced. 3.8.1.5

1800 V Configuring
supports the PTP Port
configuration Parameters:
of the Added the
position and operation
frame format tasks and
of PTP clock restrictions on
packets. the position
and frame
format of PTP
clock packets.

WDM OTN

Update Update
The OSN The product function is enhanced. ● 3.2.6

1800 V Delay
supports Compensa
automatic tion, 3.5
compensation Specificati
upon a fiber ons, and
cut on a ring 3.3.1
network and Feature
single-fiber Limitation
bidirectional s: Added
asymmetric the
compensation description
when the s of
system automatic
control board compensat
is UXCMS. ion upon a
fiber cut
on a ring
network
and single-
fiber
bidirection
al
asymmetri
c
compensat
ion.
● 3.8.1.1
Configurat
ion
Process:
Added the
description
of
configuring
the IEEE
1588v2
compensat
ion value
backhaul
security
key, single-
fiber
bidirection
al
asymmetri
c
compensat
ion, Ring

WDM OTN

Update Update
Network
Compensa
tion
Calculatio
n, and
Ring
Network
Automatic
Compensa
tion.
● 3.8.1.4
Configurin
g PTP NEs:
Added the
procedure
for
configuring
a key for
securely
returning
an IEEE
1588v2
compensat
ion value.
● 3.8.1.5
Configurin
g PTP Port
Parameter
s: Added
the
procedure
for
configuring
single-fiber
bidirection
al
asymmetri
c
compensat
ion.
● 3.8.1.10.3
Parameter
s: Clock
Synchroni
zation
Attribute:
Added the
description

WDM OTN

Update Update
of
parameters
related to
ring
compensat
ion value
calculation,
ring
network
automatic
compensat
ion, and
single-fiber
bidirection
al
asymmetri
cal
compensat
ion.
● Added
3.8.1.10.10
Parameter
s: 1588
Compensa
tion Back
Safe
Password.

Update Update
The new OSN This subrack is new to the product and should Added 3.4.9
1800 II support basic device functions. OSN 1800 II
Enhanced Enhanced
chassis Hardware
supports IEEE and Version
1588v2. Support.

WDM OTN

Update Update
The OSN The product function is enhanced. Added 3.4.10

1800 I&II OSN 1800
Compact I&II Compact
(F3SCC) Hardware
chassis newly and Version
supports IEEE Support.
1588v2.

Update Update
The OSN The product function is enhanced. 3.4.8 OSN

1800 V 1800 V
chassis newly Hardware
1588v2 Support:
(packet). Added the
descriptions
of IEEE
1588v2
(packet) for
the OSN 1800
V.
Update Update
The OSN The product function is enhanced. Added 3.4.8

1800 V OSN 1800 V
chassis newly Hardware
1588v2 Support.
(OTN).

This topic provides the standards and protocols for the IEEE 1588v2.
The IEEE 1588v2 feature complies with the following standards and protocols:

WDM OTN
● IEEE 1588v2: IEEE Standard for a Precision Clock Synchronization Protocol for
Networked Measurement and Control Systems
● ITU-T G.781: Synchronization layer functions
clock
3.8.1 Configuring IEEE 1588v2 (OSN 1800/8800/9800Universal

Platform Subrack/M Series/P Series/(U Series: U2CTU/S2CTU/
U4CTU/U5CTU))

This section describes the IEEE 1588v2 clock configuration process.
Figure 3-15 and Table 3-37 describe the process of implementing time
synchronization using IEEE 1588v2 packets.
NOTICE
To deploy high-precision clock synchronization, specific products and boards are

required. In addition, NEs and boards must be configured to work in high-precision
mode. For details, see 5 High-Precision Clock Synchronization Solution and
5.9.1 Setting the High-Precision Clock Mode.

WDM OTN
Figure 3-15 Process of configuring IEEE 1588v2-compliant frequency and phase

synchronization
NOTE
The procedure provided in Table 3-37 is only used to configure IEEE 1588v2-compliant
frequency and phase synchronization. To provide physical clock frequency synchronization
and IEEE 1588v2-compliant phase synchronization, configure the physical-layer clocks by
referring to 2.8.1.1 Configuration Process and then perform the procedure provided in
Table 3-37 to configure IEEE 1588v2 packets.
Table 3-37 Procedure for configuring IEEE 1588v2-compliant frequency and phase
synchronization
Procedure Remarks
3.8.1.2 Enabling IEEE 1588v2 Mandatory.

You must enable IEEE 1588v2 before
configuring it for a subrack. One
license is consumed by each subrack
for which the IEEE 1588v2 function is
enabled.
NOTE
Since OSN 1800 V100R007C00, before IEEE
1588v2 is enabled, Protection Status of
SSM must be set to Start Extended SSM
Protocol or Start Standard SSM Protocol.

WDM OTN
Procedure Remarks
3.8.1.3 Setting the High-Precision Optional.

Clock Mode To deploy high-precision clock
synchronization, allocate high-
precision clock licenses and configure
boards to work in high-precision mode.
Specific subracks and boards of the
OSN 9800 and OSN 1800 support
high-precision clock synchronization.
For details, see 5 High-Precision Clock
Synchronization Solution.
NOTE
When the OSC board is used for high-
precision clock synchronization, you need
to correctly set the fiber type, fiber length,
and fiber dispersion coefficient on the
WDM Interface > Advanced Attributes
page of the NMS.

WDM OTN
Procedure Remarks
3.8.1.4 Configuring PTP NEs Mandatory.

● Set Frequency Source Mode:
– When physical-layer clock
frequency synchronization and
IEEE 1588v2-compliant phase
synchronization are required, set
Frequency Source Mode to
– When IEEE 1588v2-compliant
frequency and phase
synchronization is required, set
Frequency Source Mode to PTP
Synchronization.
● Set clock synchronization attributes.
According to the practical
networking, you need to set the
clock synchronization attributes of
each NE on the NCE, including the
PTP working mode, system time,
and system time calibration
parameters.
● Configure the BMC static source
selection. The status of the master,
slave, and passive ports is manually
set to achieve time synchronization.
The dynamic BMC automatic source
selection algorithm is not enabled,
ensuring that automatic switching
does not occur when a port is
faulty.
● Configure clock subnets. This
operation is mandatory when a
physical OTN needs to be divided
into multiple clock domains.
Otherwise, retain the default value.
● Set local clock attributes. According
to the practical networking, you
must set the local clock parameters
received by the local NE, so that the
clock selection module can
calculate the best master clock.

WDM OTN
Procedure Remarks
3.8.1.5 Configuring PTP Port Mandatory.

Parameters NOTE
as a PTP port or clock cascading port.
● Set PTP Clock Message Location
and Frame Format. To ensure
successful board interconnection,
the values of PTP Clock Message
Location and Frame Format set for
two interconnected boards must be
the same.
● Create a clock port and set port
packet attributes. The ports that
transmit or receive IEEE 1588v2
packets must be configured as PTP
ports to trace PTP clock sources.
● Configure single-fiber bidirectional
asymmetric compensation. In a
single-fiber bidirectional system
consisting of single-fiber
bidirectional optical modules,
dispersion occurs during
transmission because receive and
transmit wavelengths are different,
causing delay asymmetry. In this
case, automatic delay
compensation is required to ensure
that offset is within the allowed
range and clock precision is not
affected.
NOTE
Only the following boards on the
following products support single-fiber
bidirectional asymmetric compensation.
For details about the restrictions, see
● OSN 1800 V (Z-series system
control boards) V100R009C00 and
later versions: EX4 and EG10
● OSN 1800 V Pro (K5UXCME system
control board): EX10
● OSN 1800 II Pro (K2UXCLE system
● Set the Cable Transmission Warp
parameter of the clock port. Set the
parameters related to cable
transmission deviation according to
the actual situation to compensate

WDM OTN
Procedure Remarks
for the delay generated by external

time cables.
● Set MAC addresses. The physical
addresses for sending PTP and SSM
packets can be configured so that
fields can be filled in to the sent
packets based on the requirements
of the downstream equipment,
improving the configuration
flexibility for interconnection with
3.8.1.6 Configuring External Time Optional.

Ports When an NE needs to input or output
external time signals, you must enable
the port cascading function and set
external time port attributes and the
Cable Transmission Warp parameter.
NOTE
When an NE is equipped with master and
slave subracks, you need to specify a
subrack with a clock board as the clock
center subrack. If other subracks receive
clock signals from the upstream or output
time signals to the downstream, you need
to set the clock cascading relationship
between these subracks and the clock
center subrack and correctly connect the
subracks. For details, see 2.8.1.4
Configuring the Clock Center Subrack
under 2.8.1.1 Configuration Process.
When an OSN 1800 NE is configured with
multiple AUX boards (F1AUX/B1AUX/
B2AUX), you need to set one AUX board as
the main AUX board. For details, see

to Enabled.
3.8.1.7 Querying Port Status Mandatory.

After all the clock configuration
ports and ensure that the port status is
the same as that in the networking
diagram.

WDM OTN
Procedure Remarks

each NE.
3.8.1.9 Configuring Ring Network Optional.

Automatic Compensation When the OSN 1800 is used to form a
ring network, it is recommended that
you set Ring Network Compensation
Calculation and Ring Network
Automatic Compensation to
Enabled.
NOTE
Only the following boards on the following
products support automatic compensation
of ring network delay offset. For details
about the restrictions, see 3.3.1 Feature
Limitations.
● OSN 1800 V (Z-series system control
boards) V100R009C00 and later
control board):
● V100R021C10 and later versions:
UNS5, UNS4, GTA, UNQ2, UND3
and EX10
K1GDC
control board):
and EX10
K1GDC
3.8.1.2 Enabling IEEE 1588v2

You must enable IEEE 1588v2 before configuring it for a subrack. The number of
available licenses is deducted by 1 each time IEEE 1588v2 is enabled for a subrack.
Prerequisites
● IEEE 1588v2 license resources are available.

WDM OTN
Context
In the case of an NE that is equipped with master and slave subracks, an IEEE
1588v2 license needs to be allocated to each subrack that requires PTP clock
synchronization, and clock cascading needs to be correctly configured for the
master and slave subracks.
Procedure
Step 1 Enable IEEE 1588v2 for a new subrack.

WDM OTN
NOTE
ITU-T G.8275.1 and IEEE 1588v2 share license resources. After IEEE 1588v2 is enabled on
the NMS, ITU-T G.8275.1 is also enabled.
Step 2 Enable IEEE 1588v2 for existing subracks.
----End
3.8.1.3 Setting the High-Precision Clock Mode

To implement high-precision clock synchronization, you must load the high-
precision clock license and set the clock precision mode of the board to high.
Prerequisites
● The high-precision clock license has been loaded. For details, see License
Guide.
Precautions
The high-precision clock synchronization can be implemented for NEs and boards
only after the high-precision clock mode is set. The high-precision clock mode
controls the time synchronization performance of NEs and boards. Other
operations such as configuring the functions and parameters of PTP NEs and PTP
ports are the same as those for the common-precision clock mode. Configure the
clock mode based on the protocol type.
● If IEEE 1588v2 is used, see 3.8 Configuration Guide (NCE).

● If ITU G.8275.1 is used, see 4.8 Configuration Guide (NCE).
Procedure
Step 1 Configure the number of high-precision clock function licenses.

WDM OTN
Step 2 Set the Clock Precision Mode of the board to High.
NOTICE
To make the high-precision clock mode take effect, you must set the clock
precision mode of the corresponding board to high before creating a PTP port. If a
PTP port is created before you set the high-precision clock mode for a board, you
must delete the PTP port and then create a new one.
----End
Follow-up Procedure
When the OSC board is used for high-precision clock synchronization, you need to
correctly set the fiber type, fiber length, and fiber dispersion coefficient on the
WDM Interface > Advanced Attributes page of the NMS.

WDM OTN
3.8.1.4 Configuring PTP NEs

To ensure normal operation of the PTP clock for each NE in a network, you need
to configure the frequency source mode, clock synchronization attributes, static
BMC, PTP clock subnet, and local clock attributes for the NE, and configure a
password for securely returning an IEEE 1588v2 compensation value.
Prerequisites
● IEEE 1588v2 has been enabled.
Configuring the Frequency Source Mode

Based on the practical networking, you need to configure the frequency source
mode of an NE before configuring a clock.

WDM OTN
NOTE
● If physical-layer clock frequency synchronization is used, select Physical
Synchronization.
----End
Configuring Clock Synchronization Attributes

Based on the practical networking, you need to configure the clock
synchronization attributes of each NE on NCE, including the PTP working mode,
system time, and system time calibration.
Step 1 Optional: Change PTP System Time.
NOTE
● The PTP System Time field can be set only when the NE traces local clock sources.
● The time range is 2000-01-01 00:00:00 to 2069-12-31 23:59:59.

WDM OTN
Step 2 Configure NE Clock Type, Slave Only, PTP Time Adjustment. For details about
the parameters, see 3.8.1.10.3 Parameters: Clock Synchronization Attribute.
NOTE
● The Slave Only parameter is available only when NE Clock Type is set to OC.
● If an NE requires only frequency synchronization, set PTP Time Adjustment to
Disabled; if an NE requires both frequency and time synchronization, set PTP Time
Adjustment to Enabled.
● When NE Clock Type of an NE is set to OC, Clock Type of PTP ports on the NE must be
set to OC and only one PTP port on the NE can be enabled.
● When NE Clock Type of an NE is set to BC, Clock Type of PTP ports on the NE must be
set to BC.
● When NE Clock Type of an NE is set to TC, Clock Type of PTP ports on the NE must be
set to TC.
● When NE Clock Type of an NE is set to TC+OC, Clock Type of PTP ports on the NE can
be set to either TC+OC or TC.
● When NE Clock Type of an NE is set to TC+BC, Clock Type of PTP ports on the NE can
be set to either TC or BC.
● When NE Clock Type of an NE is set to TC+BC, and Static BMC is set to Enabled, do
not change the Clock Type of PTP ports on the NE to TC.
● The device that is in the BC or OC working mode can belong to only one clock subnet,
and its clock source can be selected only within the same clock subnet.
NOTICE
Exercise caution when performing this operation. If Time Adjusting is set to

Disabled, the time synchronization function will be unavailable. When only PTP
frequency synchronization is required and time synchronization is not, Time
Adjusting can be set to Disabled. By default, it is set to Enabled and the default
setting does not need to be changed in most cases.
----End

WDM OTN
Configuring Static BMC

Unlike the dynamic clock source selection function that uses the dynamic BMC
algorithm, the static clock source selection function uses the static BMC algorithm
to achieve time synchronization after you manually set the port status (master,
slave, or passive). Automatic switching is not triggered when a port becomes
abnormal.
Step 1 Configure Static BMC.
----End
Configuring a PTP Clock Subnet

According to the actual networking situation, the network planning personnel
need to divide the entire network into different clock subnets in planning the clock
network. Within each subnet, time synchronization can be implemented for all
clocks to meet customer requirements.
PTP clock source computing is specific to clock subnets. In other words, clock
subnets separately compute their current clock sources. An NE can belong to only
one clock subnet at a time. Each BC or OC device can be configured only with one
clock subnet. The clock source should be selected from within the same clock
subnet. The packets sent from different clock subnets are discarded by the NE.

WDM OTN
Step 1 Configure PTP Clock Subnet. For details about the parameters, see 3.8.1.10.5
Parameters: PTP Clock Subnet.
NOTE
● The NEs that have the same subnet number belong to the same clock subnet.
● Equipment that is in the BC or OC working mode can belong to only one clock subnet,
and its clock source can be selected only from within the same clock subnet.
----End
Configuring Local Clock Attributes

Configure the attributes of the local clock of an NE as required. Based on the
configured local clock attributes, the clock selection module can compute the best
master clock.
Step 1 Configure Time Quality Level, Time Precision, Clock Source Type, and so on. For
details about the parameters, see 3.8.1.10.6 Parameters: BMC (Clock Subnet).
----End

WDM OTN
3.8.1.5 Configuring PTP Port Parameters

To ensure that PTP ports of each NE on a network work properly, you need to
create clock ports, configure PTP clock packet positions and frame formats, PTP
packet attributes, cable transmission deviation of PTP clock ports, single-fiber
bidirectional asymmetric compensation, and MAC addresses.
Prerequisites
Configuring the Position and Frame Format of PTP Clock Packets

To ensure successful OTN port interconnection, the values of PTP Clock Message
Location and Frame Format set for two interconnected ports must be the same.
● PTP Clock Message Location:
– 2 rows, 3 columns: The PTP clock packet overhead uses a 2 x 3 structure.
This structure conflicts with that used for latency measurement.
Therefore, IEEE 1588v2 and latency measurement cannot be enabled
concurrently.
– 1 row, 13 columns: The PTP clock packet overhead uses a 1 x 13
structure. This structure does not conflict with that for latency
measurement. IEEE 1588v2 and delay measurement can be enabled
concurrently.
● Frame Format:
– GFP: uses the GFP protocol to encapsulate the data of the VCTRUNK port.
– HDLC: uses the HDLC protocol to encapsulate the data of the VCTRUNK
port.

WDM OTN
NOTE
● For OSN 1800, Frame Format can be set for the following boards:
● New OTU boards and OTN line boards (including universal line boards) in
V100R019C10 and later versions.
● UNS4 board of the OSN 1800 V.
● For the OSN 9800, Frame Format can be set for the following boards: new OTU boards
and OTN line boards (including universal line boards) in V100R007C00SPC700 and later
versions.
● After the Frame Format of the UNS4 board on the OSN 1800 V is set to HDLC, the PTP
Clock Message Location parameter can be set.
● PTP Clock Message Location can be set for the Z5UNQ2 board on OSN 1800. When
the overhead in row 1 and column 13 is used, the Frame Format is GFP. When the
overhead in row 2 and column 3 is used, the Frame Format is HDLC.
● For boards on other products, when the Frame Format is set to GFP, the overhead
bytes in row 1 and column 13 are used. When the Frame Format is set to HDLC, the
overhead bytes in row 2 and column 3 are used.
NOTICE
● When the same type of boards are interconnected, PTP Clock Message
Location and Frame Format can retain the default values.
● When different boards are interconnected, you must query and set PTP Clock
Message Location and Frame Format to ensure that they are consistent on
the interconnected ports.
For example, when a Z5UNS4 board on the OSN 1800 interconnects with a
K1UNS4/K1UNS5 board, PTP Clock Message Location and Frame Format
need to be modified.
● If the ODUk trail delay measurement function is required in the O&M
phase, set the PTP packet frame format to GFP for the Z5UNS4 and
K1UNS4/K1UNS5 boards.
● If the ODUk trail delay measurement function is not required, set PTP
Clock Message Location of the Z5UNS4 board to row 2 and column 3,
and set Frame Format to HDLC at both ends.
● When Frame Format of a local board changes between GFP and HDLC and is
different from that of the interconnected board, clock source tracing will be
affected.
Step 1 Configure PTP Clock Message Location.

WDM OTN
Step 2 Configure Frame Format.
----End
Creating a Clock Port

● A clock port can be used to trace PTP clock sources. Creating a clock port is to
enable a PTP clock port so that PTP packets can be received.
● A clock port is used for time synchronization between a clock node and other
clock nodes. According to the actual networking situation, several clock ports
can be created for a board to connect with other clock nodes.
Step 1 Create a clock port.

WDM OTN
NOTICE
Creating or deleting a PTP clock port on a TN52TOG board transiently interrupts

services on the port.
When the 10GE LAN tributary board is used on OSN 9800 V100R001C00 or
V100R001C01 and Port Mapping is set to MAC Transparent Mapping (10.7G), if
the OSN 9800 is upgraded to V100R001C20, configuring the port as a PTP port to
support IEEE 1588v2 interrupts traffic on the port. The traffic is restored
automatically after the configuration is completed.
NOTE
In the OC working mode, only one clock port can be created.
Step 2 Set parameters related to the port status.
NOTE
● After enabling static BMC, you must manually set the status of ports where IEEE 1588v2
is enabled. The default port state is LISTENING.
● If you want to modify a selected port, select the corresponding port in the Selected
Port field, and then click to add the port to Available Port.
----End
Configuring a PTP Clock Domain

When a tributary board or a packet service board exchanges PDELAY packets, the
domain ID of the PTP port can be different from the clock subnet ID of the NE if
the following conditions are met:
● The working mode of the PTP port is TC or TC+OC.
● P/E Mode is set to P2P.
To interconnect with the peer device, you need to set the domain ID of the port to
be the same as the domain ID of the peer device. When the working mode of the

WDM OTN
port is BC or OC, the domain ID of the port is the same as the clock subnet ID of
the NE.
Step 1 Configure Domain ID. For details, see 3.8.1.10.3 Parameters: Clock
Synchronization Attribute.
----End
Configuring PTP Packet Attributes

To ensure the normal operation of the PTP clock of each NE in the network, you
need to set the corresponding PTP packet attributes based on the working mode
of each NE.
Step 1 Select a port and set P/E Mode, SYNC Packet Period(s), DELAY Packet
Period(s), PDELAY Packet Period(s), ANNOUNCE Packet Period(s), and
ANNOUNCE Packet Timeout Coefficient. For details about the parameters, see
3.8.1.10.3 Parameters: Clock Synchronization Attribute.
NOTE
DELAY Packet Period(s) is available only when P/E Mode is set to E2E. PDELAY Packet
Period(s) is available only when P/E Mode is set to P2P.
----End
Setting the Cable Transmission Deviation for the Clock Port

When the transmission time and length of a cable in the receive and transmit
directions are not consistent, the cable transmission deviation must be to be set to
rectify the PTP clock synchronization process and ensure clock synchronization
precision.
The cable transmission deviation means the time difference of transmitting clock
signals in the receive and transmit directions between two NEs. The cable
transmission deviation can be represented by time or by length.
After the fiber recovers in scenarios where the fiber length and offset value have
changed:

WDM OTN
● When Ring Network Automatic Compensation is set to Enabled:

– If the offset value is less than 50 ns, the ring network automatic
compensation is not performed and the FIB_LEN_CHANGE alarm is not
an event is reported to the system control board.
– If the offset value is greater than 500 ns, the FIB_LEN_CHANG and
● When Ring Network Automatic Compensation is set to Disabled, no
automatic compensation is performed but an alarm is reported. The alarm is
Step 1 Select a port, and set Warp Direction, Warp Mode, Warp Length(m), and Warp
Time(ns). For details about the parameters, see 3.8.1.10.3 Parameters: Clock
NOTE
● The value Positive of the Warp Direction parameter specifies that transmission
distance in the receive direction is longer than the distance in the transmit direction, or
the transmission time in the receive direction is longer than the time in the transmit
direction; the value Negative specifies just the opposite.
● Warp Length(m) is available only when Warp Mode is set to Length; Warp Time(ns)
is available only when Warp Mode is set to Time.
● The values of Warp Length(m) and Warp Time(ns) are set depending on the
networking scheme for the site.
----End
Configuring Single-Fiber Bidirectional Asymmetric Compensation

wavelengths are different, causing latency asymmetry. In this case, automatic

WDM OTN
latency compensation is required to ensure that deviation is within the allowed

range and clock precision is not affected.
NOTE
EG10
Step 1 Configure single-fiber bidirectional asymmetric compensation.
----End
Configuring MAC Addresses

This function can be used to configure the physical addresses for sending PTP and
SSM packets so that fields can be filled in to the sent packets based on the
requirements of the downstream equipment, improving the configuration
flexibility for interconnection with third-party equipment.
NOTE
MAC Address Configuration is supported only by the following boards:

● For OSN 8800, this parameter is available only for the TN54TOG, TN54TOA, TN57TOA,
and TN54THA boards.
● For OSN 1800, this parameter is available only for the following boards:
● TNF5TOA, TNF6TOA, and TNF2ELOM (STND)
● New OTU boards and OTN tributary boards in V100R019C10 and later versions

WDM OTN
Step 1 Select a port and set its MAC address. For details about the parameters, see
3.8.1.10.11 Parameters: MAC Address Configuration.
----End
3.8.1.6 Configuring External Time Ports

When there are external clock sources for an NE, you need to configure attributes
of the external clock sources so that the equipment can correctly extract external
clock information, including configuring the external port cascading mode for
clock boards, configuring attributes of external time ports, and configuring the
cable transmission distance permitted by an external time port.
Prerequisites
● A clock board and a clock interface board have been created.
NOTICE
For the OSN 1800, if the TNF1AUX board is required, you must create the STG
logical board and then the AUX logical board. Otherwise, the external clock/
time port of the TNF1AUX board cannot work properly. In this case, you need
to delete and re-create the logical AUX board.
● For the OSN 6800, you have prepared a 120-ohm external clock port cable as
the network cable for external port cascading of clock boards.
NOTE
When an NE is equipped with master and slave subracks, you need to specify a subrack
with a clock board as the clock center subrack. If other subracks receive clock signals from
the upstream or output time signals to the downstream, you need to set the clock
cascading relationship between these subracks and the clock center subrack and correctly
connect the subracks. For details, see 2.8.1.4 Configuring the Clock Center Subrack under
2.8.1.1 Configuration Process.
When an OSN 1800 NE is configured with multiple AUX boards (F1AUX/B1AUX/B2AUX),
you need to set one AUX board as the main AUX board. For details, see 2.8.1.5 Configuring
a Main AUX Board under 2.8.1.1 Configuration Process.

WDM OTN

multi-subrack NE.
or are used to input or output external clock and time signals. By default,
Enabled Status of all ports is Unused. If any ports need to be used for the
input or output of external clock and time signals, Enabled Status of the
corresponding ports should be set to Disabled. One NE supports a maximum
of two ports for the input or output of external clock and time signals.
Synchronization.
NOTE
For details about the ports that support the cascading mode, see "Clock cascading between
master and slave subracks" in 2.5 Specifications.
----End
Configuring Attributes of External Time Ports

When there are external clock sources for an NE, you need to set the attributes of
the external time ports so that the clock selection module of the NE can compute
which clock is the best to be used as the master clock.
Enabled Status of an external time port must be set to Disabled.
Step 1 Select an external time port and set Direction, Interface Protocol Type, and
Interface Level. For details about the parameters, see 3.8.1.10.7 Parameters:

WDM OTN
Basic Attribute.
NOTE
For the Interface Level parameter, the OSN 6800 supports only the value RS422.
Step 2 Set Time Quality Level, Time Precision, Clock Source Type, Clock Source
Priority 1, Clock Source Priority 2, and Clock Source Deviation. For details about
the parameters, see 3.8.1.10.8 Parameters: BMC (External Time Interface).
The STG clock board supports mutual conversion between 1PPS+TOD quality
● If the manually specified Time Quality Level is the default value 187, the STG
table.
Table 3-38 provides the mapping between the TOD status information and IEEE
1588v2 time quality level.

WDM OTN
Table 3-38 Mapping between the TOD status information and IEEE 1588v2 time
quality level
TOD Status Information IEEE 1588v2 Time Quality Level
0x00: normal 6


0x04: holdover on the transmission device 187
Other (remain) 255
----End
Configuring the Cable Transmission Distance Permitted by an External Time

Port
You need to set the cable transmission distance based on the actual length of an
external time cable to facilitate the recovery and transmission of time signals.
Step 1 Select an external time port and set Transmitting Direction, Transmitting
Distance Mode, Transmitting Length(m), and Transmitting Time(ns). For
details about the parameters, see 3.8.1.10.9 Parameters: Cable Transmitting
Distance.

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NOTE
● Transmitting Length(m) is available only when Transmitting Distance Mode is set to

Length; Transmitting Time(ns) is available only when Transmitting Distance Mode is
set to Time.
● The values of Transmitting Length(m) and Transmitting Time(ns) are set depending
on the networking scheme for the site.
----End
3.8.1.7 Querying Port Status

The NCE supports the function of querying the clock source received at a port.
This function enables you to query the time tracing status of an NE.
Prerequisites
● A clock port has been created.
Querying Port Status

Step 1 Query the port status.
----End

Prerequisites

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Context
Procedure
menu.
----End
3.8.1.9 Configuring Ring Network Automatic Compensation

When the OSN 1800 is deployed on a ring network, you are advised to configure
the ring network automatic compensation function.
Prerequisites
● Time synchronization has been implemented between NEs on the ring
network.
● The DCN communication between NEs on the ring network is normal.

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Context
NOTE
EX4, EG10, and UNQ2
● Ring network automatic compensation can be enabled only after an NE
achieves time synchronization (traces the grandmaster clock). Otherwise, the
calculated compensation value may be inaccurate.
● The ring network compensation value is returned through DCN channels.
Ensure that the DCN links between sites are normal.
Procedure
Step 1 Set Ring Network Compensation Calculation and Ring Network Automatic
Compensation. For details about the parameters, see 3.8.1.10.3 Parameters:
Clock Synchronization Attribute.

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Step 2 Set 1588 Compensation Back Safe Password. The values of 1588 Compensation
Back Safe Password must be consistent between the NEs at both ends. For details
about the parameters, see 3.8.1.10.10 Parameters: 1588 Compensation Back
Safe Password.
----End
Follow-up Operations
If Ring Network Automatic Compensation is set to Disabled, the system
provides the recommended compensation value in the alarm after the
asymmetrical offset value of the ring link changes. You need to set the
compensation value manually.
3.8.1.10 Parameters: IEEE 1588v2 (OSN 1800/8800/9800Universal Platform

This section describes the parameters involved in the process of configuration.


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Navigation Path
Parameters

that the NE traces.
NOTE
you need to set the
required.
● If physical-layer clock
frequency
select Physical
Synchronization.
● If IEEE 1588v2
frequency
select PTP
Synchronization.

subracks on an NE.
Navigation Path
Parameters

slot number-board
name-external clock
name)-slot number-
board name-external
time interface

WDM OTN

cascading port.
synchronization are
set improperly, the
master and slave
port.
inputs/outputs the
unused.
3.8.1.10.3 Parameters: Clock Synchronization Attribute

In this window, you can configure and query NE and port attributes, such as the
PTP system time, working mode, packet transmission period on a port, and
transmission deviation of the cable, in the PTP clock system.
Navigation Path
In the NE Explorer, select an NE and then choose Configuration > Clock > PTP
Clock > Clock Synchronization Attribute from the Function Tree.

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Parameters
Table 3-39 Clock Synchronization Attribute

PTP System Time For example: Displays the PTP system time.
2009-02-01 01:01:01 You can manually modify this
parameter.

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NE Clock Type OC, TC, BC, TC+BC, TC The NE Clock Type parameter
+OC provides an option to set the
Default: BC working mode (OC, TC, BC, TC
+BC, TC+OC) of the node that
adopts the IEEE 1588v2 clock.
According to the network
planning, an NE on the network
must work in the OC, TC, BC, TC
+BC, or TC+OC mode. The
specific working mode of the NE
must be determined in the
network planning phase.
During network planning, first
determine the position and
function of the NE and each port
on the NE. Then, set the working
mode of the NE according to the
features of each working mode.
● OC: As a clock device with
only one PTP port in the clock
domain, OC maintains the
time stamp used in the clock
domain. The clock device can
function as a master clock
device to provide a clock
source or as a slave clock
device to keep synchronous
with other clock devices.
● TC: TC forwards certain PTP
event messages and records
the residence time of the PTP
event messages on it. In
addition, TC provides the
recorded information to the
clock that receives the PTP
event messages. Then, the
recorded information is used
for transparent transmission
of packets and adjustment of
the residence time of the
packets on the equipment.
● BC: As a clock device with
multiple PTP ports in the clock
domain, BC maintains the
device to provide a reference
clock source or as a slave

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clock device to keep

synchronous with other clock
devices.
● TC+BC: TC+BC has the same
features as BC, except for that
the former only processes
delay but excludes itself from
● TC+OC: TC+OC is a mode for
transparently transmitting
time signals. An NE working in
this mode does not recover
the time, but it recovers the
clock. For an NE to
transparently transmit time
signals, Frequency Source
Mode must be set to PTP
Synchronization, and NE
Clock Type must be set to TC
+OC.
Static BMC Enabled, Disabled Static BMC can be set to either

Default: Disabled Enabled or Disabled to enable
or disable the IEEE 1588v2
protocol. When it is set to
Enabled, you can manually
configure the port status as
master or slave.
Slave Only Yes, No The Slave Only parameter

Default: Yes provides an option to set the
Slave_Only attribute for an OC
port. This attribute determines
whether the OC port works only
as a slave clock port.
NOTE
This parameter is available only
when NE Clock Type is set to OC.
● Yes: The port works only as a
slave clock port.
● No: The port works as a slave
clock port or a master clock
port.

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PTP Time Enabled, Disabled During network planning, set this

Adjustment Default: Enabled parameter according to the
networking. If the NE requires
only frequency synchronization,
set this parameter to Disabled. If
the NE requires both frequency
synchronization, set this
parameter to Enabled.
Protocol Packet NMEA, UBX, G.8271 Configures and queries the

Format Default: UBX protocol packet format of
external time.
The Protocol Packet Format
parameter is valid only when
Interface Protocol Type of the
external time interface is set to
1PPS+Time.
NOTE
The TMB1AUX board does not
support NMEA packets.
In the OSN 1800 series, only the
following devices running
V100R020C10 and later versions
support G.8271 packets.
● 1800 II Compact (F3SCC)
● 1800 II Enhanced (Z2UXCL)
● 1800 V (Z series)
● 1800 II Pro
● 1800 V Pro
OSN 9800 series devices running
WTR Time(min) 0 to 12 Specifies the time from detection

Default: 5 of signal recovery to triggered
response of the time selector. The
WTR time is set to prevent the
time selector from responding to
a transient signal recovery. In this
manner, the clock signals are re-
selected as the clock source only
when the synchronous clock
signals recover from a failure and
stay valid within the WTR time.
Local Clock For example: Displays the clock number of the

Source No. Company Code: 00259E local clock source of the NE.
Supplying Code: 30
NE ID: 007E028B

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Current Master For example: The Current Master Clock No.

Clock No. Company Code: 00259E parameter indicates the number
of the clock source traced by the
Supplying Code: 30 NE, which is the number of the
NE ID: 007E028B master clock traced by the NE
after the NE selects the clock
source.
Ingress of Shelf ID (shelf name)- Displays the local clock input

Current Master slot number-board interface of the master clock that
Clock name-port number the NE traces after you specify
(port name) the clock source for the NE.
Ring Network Enabled, Disabled Specifies the ring network

Compensation Default: Disabled compensation calculation.
Calculation NOTE
following products support
automatic compensation of ring
network delay offset. For details
about the restrictions, see 3.3.1
Feature Limitations.
control boards) V100R009C00
and later versions: UNS4, EX4,
EG10, and UNQ2
● OSN 1800 V Pro (K5UXCME
system control board):
● V100R021C10 and later
versions: UNS5, UNS4, GTA,
UNQ2, UND3 and EX10
versions: K1GDC
● OSN 1800 II Pro (K2UXCLE
UNQ2, UND3 and EX10
versions: K1GDC

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Ring Network Enabled, Disabled Specifies the automatic ring

Automatic Default: Disabled network compensation.
Compensation After this function is enabled, an
NE can automatically calculate
and compensate for fiber
asymmetry after a fiber cutover
or adjustment on a ring network.
This function eliminates the need
of manual measurement and
helps the NE time to keep
synchronized with the GPS.
NOTE
EG10, and UNQ2
UNQ2, UND3 and EX10
versions: K1GDC
UNQ2, UND3 and EX10
versions: K1GDC
Table 3-40 Port Status

Port Shelf ID (shelf name)- Displays the name of the ports

slot number-board where the PTP clocks are
name-port number synchronized.
(port name)

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Clock Type OC, BC, TC, TC+OC The Clock Type parameter
Default: BC provides an option to set the
working mode (OC, BC, TC, or
Each board supports TC+OC) of the node that adopts
the clock type, refer to the IEEE 1588v2 clock. According
the availability of IEEE to the network planning, an NE
1588v2. on the network must work in
the OC, BC, TC, or TC+OC mode.
The specific working mode of
the NE must be determined in
the network planning phase.
● OC: When ports on an NE are
set to OC mode, the NE can
work only in master or slave
status. A port in OC mode
can be used only for time
input or output.
● BC: When ports on an NE are
set to BC mode, the master or
slave status of the NE is
determined by using the BMC
algorithm.
● TC: If ports on an NE are set
to TC mode, the NE only
transparently transmits time
messages and does not
restore clock or time
information. In addition, the
NE does not have the master
or slave status.
● TC+OC: When ports on an NE
are set to TC+OC mode the
NE restores clock information
but does not restore time
information, achieving TC
performance transmission.
● When NE Clock Type of an
NE is set to OC, Clock Type
of PTP ports on the NE must
be set to OC and only one
PTP port on the NE can be
enabled.
NE is set to BC, Clock Type of
PTP ports on the NE must be
set to BC.
NE is set to TC, Clock Type of

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set to TC.
NE is set to TC+OC, Clock
Type of PTP ports on the NE
can be set to either TC+OC or
TC.
NE is set to TC+BC, Clock
can be set to either TC or BC.
NE is set to TC+BC, and
Static BMC is set to Enabled,
do not change the Clock
to TC.
Step Mode One step, Two step Specifies whether an IEEE 1588
Default: One step port works in the one-step or
two-step mode. Only tributary
boards support the settings of
one-step and two-step modes.
● In one-step mode, the actual
Tx time stamp is sent through
the Sync packet to be
transmitted. The one-step
mode requires the equipment
of high precision and
accuracy.
● In two-step mode, the actual
Tx time stamp is not added to
transmitted. Instead, the time
stamp is sent through the
subsequent Follow-Up
message.

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PTP Packet VLAN 1 to 4094, or 0xFFFF The PTP Packet VLAN

Default: 0xFFFF parameter provides an option to
set the VLAN IDs with the PTP
packets at a port. In the scenario
of interconnection with other
client-side equipment, the
transmitted PTP packets must
contain VLAN IDs.
● 1 to 4094: Indicates that the
specified VLAN ID is equal to
the VLAN ID of the packets.
● 0xFFFF: Indicates that the
VLAN ID is invalid.
PTP Packet PTP ETH, PTP IP Sets the encapsulation format of

Encapsulation Default: PTP ETH the PTP packet.
Format Based on the actual networking,
when local client-side equipment
is interconnected with other
client-side equipment, you need
to set the encapsulation format
of the PTP packet of the local
equipment accordingly because
the other client-side equipment
may use L2 or L3 forwarding
mode.

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Current Port MASTER, SLAVE, The Current Port Status

Status PASSIVE, LISTENING, parameter indicates the status of
FAULTY the clock source port on the
service board. The BMC
algorithm computes the port
status based on the quality and
priority of the clock source.
● MASTER: Indicates that the
port can provide a clock
source for the downstream
equipment on the path.
● SLAVE: Indicates that the port
maintains synchronization
with the upstream equipment
with the port in the MASTER
status on the path.
● PASSIVE: Indicates that the
port on the path is not in the
MASTER status and does not
maintain synchronization
status. That is, the upstream
port and downstream port
are isolated.
● LISTENING: Indicates that the
port is expecting the
Announce packets from the
MASTER port. This status
ensures that the clocks are
added to the domain in an
order.
● FAULTY: The state of a port
changes from MASTER,
SLAVE, or PASSIVE to FAULTY
when a LOS, AIS, or
LinkDown alarm is reported
for the port.
Reference Clock NE clock ID-port ID This parameter is used to set the

Source No. number of the clock that is set
as the clock source for the port
to trace.
Domain ID 0–255 Queries and sets the domain ID

Default: 0 of a port.

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Table 3-41 Port Message

Port Shelf ID (shelf name)-slot Displays the name of

number-board name-port the ports where the
number (port name) PTP clocks are
synchronized.

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P/E Mode Cancel, P2P, E2E The P/E Mode

Default: E2E parameter provides an
option to set and
query the P/E mode of
a PTP port.
● P2P: Indicates the
P2P port mode.
● E2E: Indicates the
E2E port mode.
● Cancel: Indicates no
port mode.
TCs are classified into
P2P TCs and E2E TCs
according to different
mechanisms of
processing packets.
● P2P TC: The device
measures the
residence time of
an IEEE 1588v2
packet to be
forwarded and the
transmission delay
of the link
connected to the
port that receives
this IEEE 1588v2
packet. It also
records the
residence time and
link transmission
delay in the IEEE
1588v2 packet for
further processing
at a slave clock
device.
● E2E TC: The device
measures the
residence time of
an IEEE 1588v2
packet to be
forwarded and
records the
residence time in
the IEEE 1588v2
packet for future
processing at a
slave clock device.

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SYNC Packet 4/1024, 8/1024, 16/1024, The SYNC Packet

Period(s) 32/1024, 64/1024, 128/1024, Period(s) parameter
256/1024, 512/1024, 1, 2 provides an option to
Default: 8/1024 set the period at
which the PTP port
transmits the Sync
packets. The delay-to-
respond mechanism
uses the Sync,
Delay_Req, Follow_Up,
and Delay_Resp
packets to achieve
synchronization
between OC and BC.
DELAY Packet 64/1024, 128/1024, 256/1024, The DELAY Packet

Period(s) 512/1024, 1, 2, 4, 8, 16 Period(s) parameter
Default: 1 provides an option to
set the period at
which the PTP port
transmits the Delay
respond mechanism
uses the Sync,
and Delay_Resp
packets to achieve
synchronization
between OC and BC.
This parameter can be
set only when P/E
Mode is set to E2E.

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PDELAY Packet 64/1024, 128/1024, 256/1024, The PDELAY Packet

Period(s) 512/1024, 1, 2, 4, 8, 16 Period(s) parameter
Default: 1 provides an option to
set the period at
which the PTP port
transmits the Pdelay
packets. The
Pdelay_Req,
Pdelay_Resp, and
Pdelay_Resp_Follow_U
p packets are used to
measure the link delay
between two clock
ports where the
Pdelay mechanism
functions.
set only when Work
Mode is set to TC and
P/E Mode to P2P for
the port.
ANNOUNCE 64/1024, 128/1024, 256/1024, The ANNOUNCE

Packet Period(s) 512/1024, 1, 2, 4, 8, 16 Packet Period(s)
Default: 128/1024 parameter provides an
option to set the
period at which the
PTP port transmits the
ANNOUNCE packets.
The ANNOUNCE
packets contain the
clock attributes of an
NE and are used to set
up a synchronous
system.
NOTE
When the TN52TOG/
TN54TOG/TN54TOA/
TN57TOA/TN54THA/
ELOM/TNF5TOA board
is interconnected with a
PTN device to transmit
IEEE 1588v2 clock
signals, ANNOUNCE
Packet Period(s) must
be set to 64/1028.
Otherwise, the
interconnected PTN
device may fail to trace
the clock source once
the link is faulty.

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ANNOUNCE For TN54TOG, TN54TOA, The ANNOUNCE

Packet Timeout TN57TOA, and TN54THA and Packet Timeout
Coefficient 1800, the value range is 3 to 255. Coefficient parameter
For other boards, the value range provides an option to
is 3 to 10. set the timeout
For OSN 3800 and OSN 9800, coefficient of receiving
Default: 4 the ANNOUNCE
packets. By default, if
For OSN 6800, the ANNOUNCE
● TN12ND2 packets are not
8 received for four
● TN52ND2, TN11ST2, consecutive periods,
TN52TOG, TN55TQX, the packet receiving
TN53TDX times out and the link
4 fails.
For OSN 1800, Default: 3
Table 3-42 Cable Transmitting Warp

Port Shelf ID (shelf name)-slot Displays the name of

number-board name-port the ports where the
number (port name) PTP clocks are
synchronized.

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Warp Direction Positive, Negative The Warp Direction

Default: Positive parameter provides an
option to set how the
time of transmission
over the cables
between two NEs
warps in the transmit
and receive directions.
● Positive: Indicates
that the
transmission
distance or
transmission time
in the receive
direction is longer
than that in the
transmit direction.
● Negative: Indicates
that the
transmission
distance or
transmission time
in the transmit
direction is longer
than that in the
receive direction.

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Warp Mode Length, Time The Warp Mode

Default: Time parameter provides an
option to set the
mode of warp in
transmission over the
cables in the transmit
and receive directions
between two NEs.
● Length Indicates
that there is a warp
of transmission
distance in the
transmit and
receive directions
on the line
between two NEs.
● Time Indicates that
there is a warp of
transmission time
in the transmit and
receive directions
on the line
between two NEs.
Warp Length(m) - The Warp Length(m)

option to set the warp
of transmission
distance over the
cables in the transmit
and receive directions
between two NEs.
Then, adjust the time
synchronization
according to the
actual warp of
transmission distance.
NOTE
This parameter is
available only when the
Warp Mode parameter
is set to Length.

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Warp Time(ns) - The Warp Time(ns)

option to set the warp
of transmission time
over the cables in the
transmit and receive
directions between
two NEs. Then, adjust
the time
synchronization
according to the
actual warp in
transmission time.
NOTE
This parameter is
Warp Mode parameter
is set to Time.

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Suggest Positive, Negative Specifies the

Compensate Default: - suggested
Direction compensation
direction.
NOTE
Only the following
boards on the following
products support
automatic
compensation of ring
network delay offset.
For details about the
restrictions, see 3.3.1
● OSN 1800 V (Z-
series system control
boards)
V100R009C00 and
later versions: UNS4,
EX4, EG10, and
UNQ2
● OSN 1800 V Pro
(K5UXCME system
control board):
● V100R021C10
and later
versions: UNS5,
UNS4, GTA,
UNQ2, UND3
and EX10
● V100R022C10
and later
versions: K1GDC
● OSN 1800 II Pro
(K2UXCLE system
control board):
● V100R021C10
and later
versions: UNS5,
UNS4, GTA,
UNQ2, UND3
and EX10
● V100R022C10
and later
versions: K1GDC

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Suggest - Specifies the

Length(m) suggested
compensation length.
NOTE
Only the following
products support
automatic
● OSN 1800 V (Z-
boards)
V100R009C00 and
EX4, EG10, and
UNQ2
● OSN 1800 V Pro
(K5UXCME system
control board):
● V100R021C10
and later
versions: UNS5,
UNS4, GTA,
UNQ2, UND3
and EX10
● V100R022C10
and later
versions: K1GDC
● OSN 1800 II Pro
(K2UXCLE system
control board):
● V100R021C10
and later
versions: UNS5,
UNS4, GTA,
UNQ2, UND3
and EX10
● V100R022C10
and later
versions: K1GDC

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Time(nm) suggested
compensation time.
NOTE
Only the following
products support
automatic
● OSN 1800 V (Z-
boards)
V100R009C00 and
EX4, EG10, and
UNQ2
● OSN 1800 V Pro
(K5UXCME system
control board):
● V100R021C10
and later
versions: UNS5,
UNS4, GTA,
UNQ2, UND3
and EX10
● V100R022C10
and later
versions: K1GDC
● OSN 1800 II Pro
(K2UXCLE system
control board):
● V100R021C10
and later
versions: UNS5,
UNS4, GTA,
UNQ2, UND3
and EX10
● V100R022C10
and later
versions: K1GDC

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Table 3-43 Parameters for single-fiber bidirectional asymmetric compensation

Port Slot ID-Board Displays the

name-Port port name of
number(Port an NE.
name)
Single-Fiber Two-Way Dispensation Enabled, Specifies

Compensation Disabled whether to
Default: enable single-
Disabled fiber
bidirectional
dispersion
compensation
Remote Transmit Wavelength (nm) Example: Specifies and

1310 displays the
remote
transmit
wavelength.
Setting rule:
This
parameter is
available only
when Single-
Fiber Two-
Way
Dispensation
Compensatio
n is set to
Enabled.
Fiber Type Example: 255 Specifies and

displays the
fiber type.
Dispersion Slope Value Type Egress, Specifies and

Ingress displays the
type of the
fiber
dispersion
slope value
(value K).
Dispersion Slope Value Example: 93 Specifies and

displays the
fiber
dispersion
slope value
(value K).

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Dispersion Compensation Value Type Egress, Specifies and

type of the
fiber
dispersion
inherent
compensation
(value b).
Dispersion Compensation Value Example: Specifies and

124150 displays the
fiber
dispersion
inherent
compensation
(value b).
NOTE
EG10
3.8.1.10.4 Parameters: Clock Source at Port

This topic describes how to query the clock source that the port receives and the
link status.
Navigation Path
In the NE Explorer, select the NE and choose Configuration > Clock > PTP Clock
> Clock Source at Port from Function Tree.
Parameters
Board shelf ID (shelf name)- Selects the board to be

slot number-board queried.
name-optical port
number(optical port
name)

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Port shelf ID (shelf name)- Displays the port to be

name)-optical port
number(optical port
name)
PTP Clock Source No. For example: Displays the clock

Company Code: 00259E number of the clock
source that the port
Supplying Code: 30 receives.
NE ID: 007E028B
Tracing Direction upstream, downstream When the specified port

can receive ANNOUNCE
messages from the
connected port and has
no abnormal alarm,
Tracing Direction is
upstream; otherwise, the
status is downstream.
3.8.1.10.5 Parameters: PTP Clock Subnet

In this window, you can set the clock subnet to ensure that the clocks in the same
clock subnet are synchronized according to the network planning.
Navigation Path
> PTP Clock Subnet Configuration from the Function Tree. Then, click the PTP
Clock Subnet tab.
Parameters
PTP Clock Subnet No. 0 to 255 Specifies the clock

Default: 0 subnet number to which
the NE belongs.
The NEs with the same
clock subnet number
belong to the same clock
subnet.

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3.8.1.10.6 Parameters: BMC (Clock Subnet)

In this user interface, you can set the BMC algorithm that the local clock source
uses, so that the system can calculate and select the best clock source according
to the set attributes, such as precision and priority.
Navigation Path
> PTP Clock Subnet Configuration from the Function Tree. Then, click the BMC
tab.
Parameters
Time Quality Level 6, 7, 13, 14, 52, 58, 68 to The Time Quality Level
122, 133 to 170, 216 to parameter provides an
232, 187, 193, 248, 255 option to set the quality
Default: 187 level of the time or
frequency allocated by
the master clock device.
A smaller parameter
value indicates a higher
quality level.
This parameter has an
impact on selection of
the external clock source
for tracing. If the PTP
Clock Source Priority 1
values of the clock
candidates are the same,
Time Quality Level
determines which clock
is preferred. That is, the
clock with a smaller
Time Quality Level
value is of a higher
quality level and is
preferred as the time
source for tracing.

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Time Precision For OSN 9800 M/U/P The Time Precision

subracks and OSN 1800 parameter provides an
subracks, the value option to set the time
ranges from 0 to 255. precision of the master
For other subracks, the clock or expected time
value ranges from 0 to precision of the
255 in new versions and candidate master clock.
from 32 to 49 in old A smaller parameter
versions. value indicates a higher
Default: for OSN 9800 quality level.
M/U/P subracks and This parameter has an
OSN 1800 subracks: 254; impact on selection of
for other subracks in the external clock source
new versions: 254; for for tracing. If the PTP
other subracks in old Clock Source Priority 1
versions: 49 and Time Quality Level
values of the clock
Time Precision
Time Precision value is
of higher time precision
and is preferred as the
clock source for tracing.

WDM OTN
PTP Clock Source Type ATOMIC_CLOCK, GPS, The PTP Clock Source
TERRESTRIAL_RADIO, Type parameter provides
PTP, NTP, HAND_SET, an option to set the type
OTHER, of the clock source.
INTERNAL_OSCILLATOR ● ATOMIC_CLOCK:
Default: Indicates an atomic
INTERNAL_OSCILLATOR clock.
● GPS: Indicates a GPS
time source.
● TERRESTRIAL_RADIO:
Indicates the clock
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
● PTP: Indicates a clock
source compliant with
the PTP protocol.
● NTP: Indicates a clock
the network time
protocol (NTP).
● HAND_SET: Indicates
a clock source
manually set.
● OTHER: Indicates
other clock sources.
● INTERNAL_OSCILLAT
OR: Indicates an
internal clock source.

WDM OTN
PTP Clock Source 0 to 255 The PTP Clock Source

Priority 1 Default: 128 Priority 1 parameter
the primary priority of
the clock source. A
smaller parameter value
indicates a higher
priority.
for tracing. This
parameter is the primary
factor that determines
the quality of a clock
source. That is, the clock
source with a smaller
PTP Clock Source
Priority 1 value is of a
higher quality level and
is preferred as the clock
source for tracing.

the auxiliary priority of
the clock source. A
indicates a higher
priority.
for tracing. When the
PTP Clock Source
Priority 1, Time Quality
Level, Time Precision,
and PTP Clock Source
Drift Rate values of the
clock candidates are the
same, this parameter
determines the clock
quality. That is, the clock
PTP Clock Source
Priority 2 value is of
higher quality and is
preferred as the clock
source for tracing.

WDM OTN

Deviation Default: 65535 Deviation parameter
the deviation of the
master clock from the
standard time. A smaller
parameter value
indicates a lower clock
deviation rate and better
clock signals.
Clock Source Priority 1,
Time Quality Level, and
Time Precision values of
the clock candidates are
the same, PTP Clock
Source Deviation
clock with a smaller PTP
Clock Source Deviation
value is of higher time
precision and is preferred
as the clock source for
tracing.
3.8.1.10.7 Parameters: Basic Attribute

In this window, when an NE is connected to an external clock source, you can set
the interface attributes of the external clock source, so that the NE can extract the
external clock properly.
Navigation Path
Clock > External Time Interface from the Function Tree. Click the Basic Attribute
tab.

WDM OTN
Parameters
External Time Interface shelf ID (shelf name)- Displays the name of the
slot number-board input interface of the
name-external clock external clock source on
interface the NE.
Direction Ingress, Egress Specifies the direction of

Default: Egress the external clock source.
Interface Protocol Type 1PPS+Time The Interface Protocol

Default: 1PPS+Time Type parameter provides
protocol type for the
interface with the
external clock source on
an NE.
set only when Enabled
Status is set to Disabled
for the port.
Interface Level RS422 Specifies the interface

Default: RS422 level according the
interface type when the
NE is connected to an
RS422 indicates that the
interface type is RJ45.
3.8.1.10.8 Parameters: BMC (External Time Interface)

In this user interface, when the NE is connected to an external clock source, you
can set the BMC algorithm that the external clock source uses through the
external interface, so that the system can calculate and select the best clock
source according to the set attributes, such as precision and priority.
Navigation Path
Clock > External Time Interface from the Function Tree. Click the BMC tab.

WDM OTN
Parameters
interface the NE.
A smaller parameter
quality level.
values of the clock
Time Quality Level
Time Quality Level
source for tracing.

WDM OTN

255 in new versions and candidate master clock.
from 32 to 49 in old A smaller parameter
M/U/P subracks: 33; for This parameter has an
for other subracks in the external clock source
new versions: 33; for for tracing. If the PTP
other subracks in old Clock Source Priority 1
versions: 49 and Time Quality Level
values of the clock
Time Precision

WDM OTN
time source.
Indicates the clock
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the network time
protocol (NTP).
a clock source
manually set.
OR: Indicates an

WDM OTN
PTP Clock Source Priority 0 to 255 The PTP Clock Source

1 Default: 128 Priority 1 parameter
the clock source. A
indicates a higher
priority.
for tracing. This
PTP Clock Source
source for tracing.
PTP Clock Source Priority 0 to 255 The PTP Clock Source

2 Default: 128 Priority 2 parameter
the clock source. A
indicates a higher
priority.
PTP Clock Source
PTP Clock Source
source for tracing.

WDM OTN

Deviation Default: 65535 Deviation parameter
the deviation of the
master clock from the
standard time. A smaller
parameter value
clock signals.
the same, PTP Clock
Source Deviation
tracing.
Local Priority 1 to 255 Indicates the clock

Default: 128 source priority of the
port.
The smaller the value,
the higher the priority.
3.8.1.10.9 Parameters: Cable Transmitting Distance

In this window, when the NE is connected to an external clock source, you can set
the cable transmission distance to modify the clock synchronization.
Navigation Path
Clock > External Time Interface from the Function Tree. Click the Cable
Transmitting Distance tab.

WDM OTN
Parameters
interface the NE.
Transmitting Direction Ingress, Egress Sets the transmission

direction of the cable of
NOTE
● When Enabled Status
of a port is set to
Enabled, Transmitting
Direction can be set to
only Ingress.
of a port is set to
Disabled, Transmitting
Ingress and Egress.
Transmitting Distance Length, Time The Transmitting

Mode Default: Length Distance Mode
parameter provides an
option to set the
transmission distance
mode for the clock
interface. This parameter
can be set to Length or
Time.
If the delay can be
measured, set this
parameter to Time;
otherwise, set this
parameter to Length.
● Length: Indicates that
the transmission
distance is expressed
in terms of length.
● Time: Indicates that
the transmission
in terms of time.

WDM OTN
Transmitting 0 to 300 The Transmitting

Length(m) Default: 0 Length(m) parameter
the transmission distance
source over cables. Set
this parameter according
to the actual
transmission length to
adjust the delay in
transmitting the clock
signals.
Set this parameter
according to the
measured length of the
transmission cable. If
Enable Status is set to
Enabled for the port, the
delay can be
compensated only at the
receive end and the
compensation should be
the same as the actual
distance. If Enable
for the port, the delay
can be compensated at
both the transmit and
receive ends. The sum of
compensation at the
ends should be equal to
the actual distance.
set only when
Transmitting Distance
Mode is set to Length.
In the case of the
transmit direction, the
delay at the transmit end
is compensated. In the
case of the receive
direction, the delay at
the receive end is
compensated.

WDM OTN
Transmitting Delay(ns) 0 to 1350 The Transmitting

Default: 0 Delay(ns) parameter
the delay in transmitting
the clock source over the
cable. Set this parameter
properly to adjust time
synchronization.
In the case of the
case of the receive
the receive end is
compensated.
set only when
Mode is set to Time.
3.8.1.10.10 Parameters: 1588 Compensation Back Safe Password

In this user interface, you can configure a password for securely returning an IEEE
1588v2 compensation value.
Navigation Path
In the NE Explorer, select an NE and choose Configuration > Clock > PTP Clock >
Safety Password from the Function Tree.

WDM OTN
Parameters
Table 3-44 Parameter for displaying a password

1588 Example: Test_1234 Displays the

Compensatio key for
n Back Safe securely
Password returning an
IEEE 1588v2
compensation
value.
NOTE
The value is
displayed as
"********" and
the query is
not
supported.

WDM OTN
Table 3-45 Parameters for adding a password

New Example: Test_1234 Sets the

Password password for
securely
returning an
IEEE 1588v2
compensation
value.
Value
description:
The value
contains 8 to
128
characters. It
is
recommended
that the value
contain at
least three
types of the
following
characters:
● Lower-case
letters
● Upper-case
letters
● Digits
● Space or
special
characters
Setting rule:
The values of
New
Password and
Confirm
Password
must be the
same.

WDM OTN

NOTE
The default
key for
securely
returning an
IEEE 1588v2
compensation
value on the
upstream and
downstream
devices is
HW@_77wa.
You are
advised to
change the
default key
when using
the device for
the first time.
Confirm Example: Test_1234 Sets the

Password confirm
password for
securely
returning an
IEEE 1588v2
compensation
value.
Setting rule:
The values of
New
Password and
Confirm
Password
must be the
same.
3.8.1.10.11 Parameters: MAC Address Configuration

In this user interface, you can query or set the physical address of boards. This
address will be carried in PTP and SSM packets.
Navigation Path
In the NE Explorer, click the NE and choose Configuration > Clock > PTP Clock >
MAC Address Configuration.

WDM OTN
Parameters
Board Example: Shelf5(Slave Indicates the clock

shelf5)-5-54TOA(STND) board.
MAC Address For example: This function can be

88-00-88-00-88-00 used to configure the
physical addresses for
sending PTP and SSM
packets so that fields can
be filled in to the sent
packets based on the
requirements of the
downstream equipment,
improving the
configuration flexibility
for interconnection with
NOTE
Value range for each octet:
00-FF (Special characters
are not supported.)
NOTE
MAC Address
Configuration is
supported only by the
following boards:
● For OSN 8800, this
parameter is available
only for the TN54TOG,
TN54TOA, TN57TOA,
and TN54THA boards.
boards:
● TNF5TOA,
TNF6TOA, and
TNF2ELOM (STND)
● New OTU boards
and OTN tributary
boards in
V100R019C10 and
later versions
3.8.2 Configuring IEEE 1588v2 (OSN 9800 U Series: U1CTU/

S1CTU)

WDM OTN

Figure 3-16 shows the process of implementing time synchronization using IEEE
1588v2 packets.
Figure 3-16 Process of configuring frequency and phase synchronization using

IEEE 1588v2 packets
Table 3-46 provides the detailed procedure for configuring IEEE 1588v2-compliant
frequency and phase synchronization.
NOTE
synchronization
Operation Remarks

configuring it for a subrack. The
number of available licenses is
deducted by 1 each time IEEE 1588v2
is enabled for a subrack.
NOTE

WDM OTN
Operation Remarks

parameters.
● Configure static BMC source
faulty.
3.8.2.4 Configuring PTP Ports Mandatory.

time cables.


WDM OTN
Operation Remarks

diagram.

each NE.

You must enable IEEE 1588v2 before configuring it for a subrack. The number of
Prerequisites
● The required subracks have been created.
Procedure
Step 1 Change the 1588V2 attribute to Enabled.

WDM OTN
NOTE
----End

to configure PTP clock global parameters, PTP clock subnets, and local clock
attributes for the NE.
Prerequisites

WDM OTN
Configuring PTP Clock Global Parameters

Based on the practical networking situation, you need to set the clock
synchronization attributes of each NE on the NCE. The attributes include PTP work
mode, PTP system time, and static BMC.
Step 1 Configure PTP Profile.
NOTE
The PTP System Time field can be set only when the NE traces local clock sources.
Step 3 Set Ne Clock Type, Static BMC, Slave Only, Packet Multicast Mode, Protocol
Packet Format, Correct UTC Time. For details about the parameters, see 3.8.2.8.1

WDM OTN
Parameters: Clock Synchronization Attribute.
NOTE
The Slave Only parameter is available only when NE Clock Type is set to OC.
----End

The calculation of the PTP clock source is based on the clock subnet. Each clock
subnet calculates its own current clock source separately. For an NE, only one time
domain is supported at a time. Each BC or OC equipment can only be configured
with one clock subnet. The clock source should be selected from within the same
clock subnet. The packets sent from different clock subnets are discarded by the
NE.

WDM OTN
Step 1 Configure Clock Subnet No.. For details about the parameter, see 3.8.2.8.3
NOTE
----End

configured local clock attributes, the clock selection module of the NE can
compute which clock is the best to be used as the master clock.
Step 1 Set Time Quality Level, Time Precision, Clock Source Type, Clock Source
Priority 1, and Clock Source Priority 2. For details about the parameters, see
3.8.2.8.4 Parameters: BMC (Clock Subnet).
----End

WDM OTN
3.8.2.4 Configuring PTP Ports

To ensure that PTP ports of each NE on a network work correctly, you need to
create PTP ports, configure attributes of PTP packets, and specify the cable
transmission deviation of PTP clock ports.
Prerequisites
Configuring a Clock Port

Step 1 Configure a clock port. For details about the parameters, see 3.8.2.8.1
NOTICE
NOTE
----End

WDM OTN
Configuring the Clock Source Priority Table

Step 1 Set Clock Source WTR Time(min).
NOTE
The value of Clock Source WTR Time(min) ranges from 0 to 12 with a step of 1 minute.
The default value is 5.
Step 2 Set Port, Clock Source No, and Clock Source PortNo.
----End

WDM OTN

of each NE.
Step 1 Set P/E Mode, SYNC Packet Period(s), DELAY Packet Period(s), PDELAY Packet
Period(s), ANNOUNCE Packet Period(s), and ANNOUNCE Packet Timeout
Coefficient. For details about the parameters, see 3.8.2.8.1 Parameters: Clock
NOTE
----End

precision.
The transmission deviation of a cable means the time difference of the clock
signals in the cable transmission in the receive and transmit directions between
two NEs. Generally, the actual time difference of cable transmission for the two
directions is calculated by GPS in the deployment. The cable transmission
deviation can be represented by time or by length.
Step 1 Set Warp Direction, Warp Mode, Warp Length(m), and Warp Time(ns). For
details about the parameters, see 3.8.2.8.1 Parameters: Clock Synchronization

WDM OTN
Attribute.
NOTE
----End

clock information, including configuring attributes of external time ports and the
cable transmission distance permitted by external time ports.
Prerequisites
● The required CTU board has been created.

external time ports so that the NE can use the correct external clock.
Step 1 Select an external time port and set External Time Interface Direction and
Interface Protocol Type. For details about the parameters, see 3.8.2.8.5

WDM OTN
Parameters: Basic Attribute.
Step 2 Set Bits Type, Bits Clock Class Level, Bits Precision, Bits Time Source, Bits
Priority 1, Bits Priority 2. For details about the parameters, see 3.8.2.8.6
Parameters: BMC (External Time Interface).
----End

Port
Step 1 Select an external time port and set Input Warp Mode, Input Warp Length(m),
Input Warp Time(ns), Output Warp Mode, Output Warp Length(m), and
Output Warp Time(ns). For details about the parameters, see 3.8.2.8.7

WDM OTN
Parameters: Cable Transmitting Distance.
NOTE
● Input Warp Length(m) is available only when Input Warp Mode is set to Length;
Input Warp Time(ns) is available only when Input Warp Mode is set to Time.
● Output Warp Length(m) is available only when Output Warp Mode is set to Length;
Output Warp Time(ns) is available only when Output Warp Mode is set to Time.
● The values of Input Warp Length(m), Output Warp Length(m), Input Warp
Time(ns), and Output Warp Time(ns) are set depending on the networking scheme
for the site.
----End

Prerequisites

WDM OTN
Procedure
Step 1 Query the information about the clock source received at the port.
----End

Prerequisites
Context
Procedure
menu.

WDM OTN
----End
3.8.2.8 Parameters: IEEE 1588v2 (OSN 9800 U Series: U1CTU/S1CTU)

This section describes the parameters in process of configurations.

Navigation Path
Clock > Clock Synchronization Attribute from the Function Tree.
Parameters
parameter.
+BC, or TC+OC) of the node that
+BC, or TC+OC mode. The
specific mode of the NE must be
determined in the network
planning phase.

WDM OTN
Static BMC Enabled, Disabled NOTE

Static BMC can be set to either
Default: Disabled Enabled or Disabled to enable or
disable the IEEE 1588v2 protocol.
When it is set to Enabled, you can
manually configure the port status
as master or slave.

Default: No provides an option to set the
NOTE
Enable Automatic Enable, Disable On a ring network, if a fiber is

Compensation Default: Disable cut over or adjusted, the NE
Measurement automatically computes fiber
length variation. In this course,
users do not need to manually
measure the fiber length
variation, but only need to set
compensation parameters. In
this manner, the NE can
maintain time synchronization
with GPS.
NOTE
The WDM/OTN equipment does not
support setting Enable Automatic
Compensation Measurement.
Packet Multicast Multicast, Partly- In multicast mode, SYNC,

Mode Multicast ANNOUNCE, and DELAY packets
Default: Multicast are multicasted. In part
multicast mode, SYNC and
ANNOUNCE packets are
multicasted, whereas DELAY
packets are unicasted.
Inpartly-multicast mode,
Delay_Req and Delay_Resp
packets are unicasted. In E2E TC
scenarios, this avoids
transmission of delay Req
packets between slave
equipment.
Protocol Packet NMEA, UBX Sets and queries the IEEE 1588
Format Default: UBX clock protocol packet format.

WDM OTN

Source No. 00259e30007d0050 local clock source of the NE.
Current Master For example: Displays the master clock

Clock No. 00259e30007d0050 number that the NE traces.
Ingress of Current For example: PTP Displays the local clock input
Master Clock interface of the master clock
that the NE traces after you
specify the clock source for the
NE.
Hops of Current For example: 2 Indicates the number of hops for

Master Clock transmitting clock signals from
the master clock to the current
NE.
For example, the signal route is
NE A (master clock)->NE B->NE
C->NE D. For NE D, Hops of
Current Master Clock is 3.
Correct UTC Time 0 to 255 Correct the UTC time.

Default: 35
PTP Profile IEEE 1588v2, G.8275.1 Indicates the PTP protocol type
Default: IEEE 1588v2 used by the NE.

Port For example: Displays the name of the ports

Otn0/12/255/1 where the PTP clocks are
synchronized.
PTP Packet VLAN 0 to 4094 The PTP Packet VLAN

Default: 0 parameter provides an option to
contain VLAN IDs.
PTP Packet VLAN 0 to 7 Sets the VLAN priority of a port

Priority Default: 7 PTP packet.
PTP Packet DSCP 0 to 63 Sets the DSCP priority of a port


WDM OTN

mode.
PTP Packet - -
Destination MAC
Address
PTP Packet Source - -

IP Address
PTP Packet - -
Destination IP
Address
Port Prefigure MASTER+SLAVE, Sets the prefigure status of a

Status MASTER, SLAVE port.
Default: MASTER
+SLAVE
Current Port Master, Slave, Passive, Displays the current status of a

Status Listening port.
Port Manual Master, Slave, Passive, The Current Port Status

Status Listening parameter indicates the status of
Default: Listening the clock source port on the
status according to the quality
and priority of the clock source.
Port Domain 0 to 255 Queries and sets the domain ID

Default: 0 of a port.

WDM OTN
Step Module One step, Two step Specifies whether an IEEE 1588
Default: One step port works in the one-step or
two-step mode.
accuracy.
message.
PTP port type none, BC, TC Specifies PTP port type.

Default: none
PTP Status Enabled, Disabled Specifies whether a port

Default: Enabled supports PTP packets.


synchronized.

WDM OTN
P/E Mode P2P, E2E The P/E Mode parameter

Default: E2E provides an option to set and
query the P/E mode of a PTP
port.
● P2P: Indicates the P2P port
mode.
● E2E: Indicates the E2E port
mode.
● Cancel: Indicates no port
mode.
TCs are classified into P2P TCs
and E2E TCs according to
different mechanisms of
processing packets.
● P2P TC: The device measures
the residence time of an IEEE
1588v2 packet to be
forwarded and the
transmission delay of the link
connected to the port that
receives this IEEE 1588v2
packet. It also records the
residence time and link
transmission delay in the IEEE
1588v2 packet for further
processing at a slave clock
device.
● E2E TC: The device measures
1588v2 packet to be
forwarded and records the
residence time in the IEEE
1588v2 packet for future
device.
SYNC Packet 4/1024, 8/1024, 16/1024, The SYNC Packet Period(s)

Period(s) 32/1024, 64/1024, parameter provides an option to
128/1024, 256/1024, set the period at which the PTP
512/1024, 1, 2 port transmits the Sync packets.
Default: 64/1024 The delay-to-respond
mechanism uses the Sync,
Delay_Req, Follow_Up, and
Delay_Resp packets to achieve
synchronization between OC
and BC.

WDM OTN
DELAY Packet 64/1024, 128/1024, The DELAY Packet Period(s)

Period(s) 256/1024, 512/1024, 1, parameter provides an option to
2, 4, 8, 16 set the period at which the PTP
Default: 1 port transmits the Delay
packets. The delay-to-respond
and BC.
This parameter can be set only
when P/E Mode is set to E2E.
PDELAY Packet 64/1024, 128/1024, The PDELAY Packet Period(s)

Default: 1 port transmits the Pdelay
packets. The Pdelay_Req,
Pdelay_Resp, and
Pdelay_Resp_Follow_Up packets
are used to measure the link
delay between two clock ports
where the Pdelay mechanism
functions.
when Work Mode is set to TC
and P/E Mode to P2P for the
port.
ANNOUNCE 64/1024, 128/1024, The ANNOUNCE Packet

Packet Period(s) 256/1024, 512/1024, 1, Period(s) parameter provides
2, 4, 8, 16 an option to set the period at
Default: 128/1024 which the PTP port transmits
the ANNOUNCE packets. The
ANNOUNCE packets contain the
clock attributes of an NE and
are used to set up a
synchronous system.
ANNOUNCE 3 to 10 Specifies the times of the

Packet Timeout Default: 4 ANNOUNCE message period.
Coefficient The value of this parameter
multiplied by the ANNOUNCE
message period is equal to the
timeout interval of receiving
ANNOUNCE packets. When the
port does not receive
ANNOUNCE packets within the
set timeout interval, it is
considered that the packets
cannot arrive and the link fails.

WDM OTN


synchronized.
Warp Direction Positive, Negative The Warp Direction parameter

Default: Positive provides an option to set how
the time of transmission over
the cables between two NEs
warps in the transmit and
receive directions.
● Positive: Indicates that the
transmission distance or
transmission time in the
receive direction is longer
than that in the transmit
direction.
● Negative: Indicates that the
transmit direction is longer
than that in the receive
direction.
Warp Mode Length, Time The Warp Mode parameter

Default: Time provides an option to set the
mode of warp in transmission
over the cables in the transmit
and receive directions between
two NEs.
● Length: Indicates that there
is a warp of transmission
distance in the transmit and
receive directions on the line
between two NEs.
● Time: Indicates that there is a
warp of transmission time in
the transmit and receive
directions on the line
between two NEs.

WDM OTN
Warp Length(m) 0 to 3555555 The Warp Length(m)

set the warp of transmission
distance over the cables in the
transmit and receive directions
between two NEs. Then, adjust
the time synchronization
according to the actual warp of
NOTE
when the Warp Mode parameter is
set to Length.
Warp Time(ns) 0 to 8000000 The Warp Time(ns) parameter

Default: 0 provides an option to set the
warp of transmission time over
the cables in the transmit and
receive directions between two
NEs. Then, adjust the time
synchronization according to the
actual warp in transmission
time.
NOTE
set to Time.
Actual Positive, Negative In the positive direction, the

Measurement length or time in the receive
Warp Direction direction is longer than the
length or time in the transmit
direction. In the negative
direction, the length or time in
the transmit direction is longer
than the length or time in the
receive direction.
Actual Example: 10 The value relies on the deviation

Measurement mode (length or time).
Warp (ns) If a fiber/cable between two NEs
does not have transmission
deviation between the sending
and receiving directions, Actual
Measurement Warp (ns) and
Accept Actual Measurement
Warp are grayed out.
Accept Actual Example: 10 No compensation is required if

Measurement the deviation is within the
Warp accepted range.

WDM OTN

link status.
Navigation Path
> Clock Source Priority Table from Function Tree. Click the Clock Source at Port
tab.
Parameters
Port For example: Displays the port to be

Otn0/12/255/1 queried.
Clock Source No. For example: Displays the clock

001e100009006910 number of the clock
receives.
Link Status Up, Down When the specified port

messages from the
no abnormal alarm, Link
Status is Up; otherwise,
the status is Down.

Navigation Path
> Clock Subnet Configuration from the Function Tree. Then, click the Clock
Subnet tab.

WDM OTN
Parameters
Clock Subnet No. 0 to 255 Specifies the clock

the NE belongs.
clock subnet number
subnet.

Navigation Path
> Clock Subnet Configuration from the Function Tree. Then, click the BMC tab.

WDM OTN
Parameters
Time Quality Level 0 to 255 The Time Quality Level

option to set the quality
level of the time or
A smaller parameter
quality level.
values of the clock
Time Quality Level
Time Quality Level
source for tracing.

WDM OTN
Time Precision 0 to 255 The Time Precision

option to set the time
precision of the master
clock or expected time
precision of the
candidate master clock.
A smaller parameter
quality level.
and Time Quality Level
values of the clock
Time Precision

WDM OTN
time source.
Indicates the clock
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the Network Time
Protocol (NTP).
a clock source that is
manually set.
OR: Indicates an

WDM OTN

the clock source. A
indicates a higher
priority.
for tracing. This
PTP Clock Source
source for tracing.
Clock Source Priority 2 0 to 255 The PTP Clock Source

Default: 128 Priority 2 parameter
the clock source. A
indicates a higher
priority.
PTP Clock Source
PTP Clock Source
source for tracing.

WDM OTN

Navigation Path
Clock > External Time Interface from the Function Tree. Click the External Time
Interface Attribute tab.
Parameters
External Time Interface Example: bits2 Displays the name of the

input interface of the
the NE.

WDM OTN
Interface Mode External Clock Interface, The features of an

External Time Interface external clock interface
are as follows:
● Configuration
management of 2
Mbit/s clock sources
in the input and
output directions.
● Configuration
management of 2
Mbit/s output clock
sources.
● 2 Mbit/s clock sources
can function as the
reference clock
sources for system
frequency
synchronization.
The features of an
external time interface
are as follows:
● You can configure the
input/output
direction, protocol
type, and interface
level of an external
time interface.
● An external time
interface can function
as the reference clock
source for restoring
time, and can also
function as the
reference clock source
for restoring the
system clock
frequency.
External Time Interface Input, Output Specifies the direction of

Direction Default: Output the external clock source.

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interface with the
an NE.
for the port.

Navigation Path
Parameters

the NE.

WDM OTN
Bits Type Manual, Auto Indicates the mode for

Default: Manual setting the time quality
levels of external time
interfaces.
● Manual: You can
manually set the time
quality levels of
external time
interfaces. Quality
Level indicates the
time quality level.
● Auto: NEs obtain the
time quality levels of
external time
interfaces
automatically after
converting 1PPS
status values
according to the
conversion table.
Bits 1PPS Status Available, Atomic Clock 1PPS status values can
Hold, Unavailable, be converted into time
Oscillator Hold, quality levels according
Transport Device Hold, to the conversion table.
Rubidiumc Clock Hold ● Available corresponds
to level 6.
● Atomic Clock Hold,
Unavailable
corresponds to level 7.
● Unavailable
corresponds to level
255.
● Oscillator Hold
52.
● Transport Device Hold
187.
● Rubidiumc Clock Hold
Bits Quality Level 0 to 255 Indicates the actual time

quality levels of external
time interfaces.

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Bits Clock Class Level 0 to 255 The Bits Clock Class

Default: 6 Level parameter provides
quality level of the time
or frequency allocated by
A smaller parameter
quality level.
Bits Precision 0 to 255 The Bits Precision

precision of the
A smaller parameter
quality level.
Bits Time Source ATOMIC_CLOCK, GPS, The Bits Time Source

TERRESTRIAL_RADIO, parameter provides an
PTP, NTP, HAND_SET, option to set the type of
OTHER, the clock source.
INTERNAL_OSCILLATOR
Default: GPS
Bits Priority 1 0 to 255 The Bits Priority 1

option to set the primary
priority of the clock
source. A smaller
parameter value
indicates a higher
priority.

option to set the
auxiliary priority of the
clock source. A smaller
parameter value
indicates a higher
priority.


WDM OTN
Navigation Path
Clock > External Time Interface from the Function Tree. Click the Bits
Transmitting Warp tab.
Parameters

the NE.
Input Warp Mode Length, Time The Input Warp Mode

option to set the
mode for the clock
interface of input
direction. This parameter
Time.
Input Warp Length(m) 0 to 300 The Input Warp

Default: 0 Length(m) parameter
source over cables of
input direction. Set this
parameter according to
the actual transmission
length to adjust the
delay in transmitting the
clock signals.
Input Warp Time(ns) 0 to 1350 The Input Warp

Default: 0 Time(ns) parameter
cable of input direction.
Set this parameter
synchronization.

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Output Warp Mode Length, Time The Output Warp Mode

option to set the
mode for the clock
interface of output
Time.
Output Warp 0 to 300 The Output Warp

output direction. Set this
clock signals.
Output Warp Time(ns) 0 to 1350 The Output Warp

cable of output direction.
Set this parameter
synchronization.
3.9.1 Configuring IEEE 1588v2 (OSN 1800/8800/9800 Universal

Platform Subrack/M Series/P Series/ (U Series: U2CTU/S2CTU/
U4CTU))

Figure 3-17 shows the process of implementing time synchronization using IEEE
1588v2 packets.

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Figure 3-17 Process of configuring frequency and phase synchronization using

IEEE 1588v2 packets
Table 3-51 provides the detailed procedure for configuring IEEE 1588v2-compliant
NOTE
synchronization
Operation Remarks

configuring it for a subrack. The
number of available licenses is
NOTE

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Operation Remarks

● Set Frequency Source Mode:
– When physical-layer clock
frequency synchronization and
IEEE 1588v2-compliant phase
synchronization are required, set
Frequency Source Mode to
– When IEEE 1588v2-compliant
frequency and phase
synchronization is required, set
Frequency Source Mode to PTP
Synchronization.
● Configure a password for securely
returning an IEEE 1588v2
compensation value. This operation
is mandatory when ring-network
compensation needs to be
configured for an NE. The values of
1588 Compensation Back Safe
Password must be consistent
between the NEs at both ends.
NOTE
This function is supported only when
the system control board of the OSN
1800 V is UXCMS and the product
version is V100R009C00 or later. For
details about the restrictions, see 3.3.1
each NE on the U2000, including
the PTP working mode, system
time, and system time calibration
parameters.
● Configure static BMC source
faulty.

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Operation Remarks

● Set Ring Network Compensation
Enabled according to the network
plan.
NOTE

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Operation Remarks

Parameters ● Set PTP Clock Message Location
the same.
causing latency asymmetry. In this
case, automatic latency
that deviation is within the allowed
affected.
NOTE
time cables.

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Operation Remarks

NOTE
For details, see 2.9.1.4 Configuring the
Clock Center Subrack under 2.9.1.1
Configuration Process.
3.9.1.6 Viewing Port Status Mandatory.

diagram.

synchronization. Using U2000, you can
each NE.

You must enable IEEE 1588v2 before configuring it for an NE. The number of
Prerequisites
● You are an NMS user with Operator Group rights or higher.
Procedure

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NOTE

WDM OTN
NOTE
● OSN 9800:
– Universal platform subrack: The universal platform subracks on the same NE
implement frequency/phase synchronization through clock cascading between
In versions earlier than V100R007C00, electrical subracks on the same NE do not
support clock cascading between master and slave subracks. Therefore, only one
electrical subrack on each NE supports frequency/phase synchronization. You are
advised to configure all boards requiring frequency and phase synchronization in
the same subrack.
In V100R007C00 and later versions, when the system control board is TNU2CTU or
TNS2CTU, electrical subracks on the same NE support clock cascading between
master and slave subracks. When the system control board is TNU4CTU or
TNU5CTU, electrical subracks on the same NE support clock cascading between
– M series subracks: Clock cascading between master and slave subracks is
supported.
– P series subracks: Clock cascading between master and slave subracks is supported.
– Clock cascading between master and slave subracks cannot be implemented
between universal platform subracks and U/M series subracks.
● OSN 1800:
– Subracks that use the TMB1AUX board support clock cascading between master
and slave subracks since V100R020C10. The ports supported by the TMB1AUX
board are external clock/time ports and clock synchronization GE optical ports.
– Subracks that use the TMB2AUX/MD48AFS board support clock cascading between
master and slave subracks since V100R021C10. The ports supported by the
TMB2AUX board are external clock/time ports and clock synchronization GE optical
ports. The ports supported by the MD48AFS board are clock synchronization GE
optical ports.
– Subracks that use the TMK5SXCH/TMK5UXCME/TMK5XCH/TMK5GSCC board
support clock cascading between master and slave subracks since V100R022C00.
The ports supported by the board are clock synchronization GE optical ports.
– Subracks that use the TMK6XCH board support clock cascading between master
and slave subracks since V100R022C10. The ports supported by the board are clock
● OSN 8800/6800: Clock cascading between master and slave subracks is supported.
Step 2 Enable IEEE 1588v2 for the created subrack.

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----End

Prerequisites
Configuring the Frequency Source Mode

Based on the practical networking, you need to configure the frequency source
mode of an NE before configuring a clock.

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NOTE
Based on the practical networking, you need to configure the frequency source mode of an
NE before configuring a clock.
● If physical-layer clocks are used to achieve frequency synchronization, select Physical
Synchronization.
● If IEEE 1588v2 packets are used for frequency synchronization, select PTP
Synchronization.
----End
Configuring Clock Synchronization Attributes

Based on the practical networking situation, you need to set the clock
synchronization attributes of each NE on the U2000. The attributes include PTP
work mode, PTP system time, and time adjustment.

WDM OTN
NOTE
● The PTP System Time field can be set only when the NE traces local clock sources.
● The time range is 2000-01-01 00:00:00 to 2069-12-31 23:59:59.
Step 2 Configure NE Clock Type, Slave Only, PTP Time Adjustment, Ring Network
Compensation Calculation, Ring Network Automatic Compensation. For details
about the parameters, see 3.9.1.8.3 Parameters: Clock Synchronization
Attribute.

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NOTE
● The Slave Only parameter is available only when NE Clock Type is set to OC.
● If an NE requires only frequency synchronization, set PTP Time Adjustment to
Disabled; if an NE requires both frequency and time synchronization, set PTP Time
Adjustment to Enabled.
● When NE Clock Type of an NE is set to OC, Clock Type of PTP ports on the NE must be
set to OC and only one PTP port on the NE can be enabled.
● When NE Clock Type of an NE is set to BC, Clock Type of PTP ports on the NE must be
set to BC.
● When NE Clock Type of an NE is set to TC, Clock Type of PTP ports on the NE must be
set to TC.
● When NE Clock Type of an NE is set to TC+OC, Clock Type of PTP ports on the NE can
be set to either TC+OC or TC.
● When NE Clock Type of an NE is set to TC+BC, Clock Type of PTP ports on the NE can
be set to either TC or BC.
● When NE Clock Type of an NE is set to TC+BC, and Static BMC is set to Enabled, do
not change the Clock Type of PTP ports on the NE to TC.
● The device that is in the BC or OC working mode can belong to only one clock subnet,
and its clock source can be selected only within the same clock subnet.
NOTICE

----End
Configuring Static BMC

Unlike the dynamic clock source selection function that uses the dynamic BMC
algorithm, the static clock source selection function uses the static BMC algorithm
to achieve time synchronization after you manually set the port status (master,
slave, or passive). Automatic switching is not triggered when a port becomes
abnormal.
Step 1 Configure Static BMC.

WDM OTN
----End

Network planning personnel need to divide the entire network into different clock
subnets in planning the clock network according to the scheme for the site. Within
each subnet, time synchronization can be implemented for all clocks.
NE.
Step 1 Set PTP Clock Subnet. For details about the parameter, see 3.9.1.8.5 Parameters:
PTP Clock Subnet.

WDM OTN
NOTE
----End

Step 1 Configure Time Quality Level, Time Precision, Clock Source Type, and so on. For
----End
Configuring a Key for Securely Returning an IEEE 1588v2 Compensation

Value
Configure a key for securely returning an IEEE 1588v2 compensation value when
ring-network compensation needs to be configured for an NE.
Step 1 Configure 1588 Compensation Back Safe Password.

WDM OTN
----End

Prerequisites

To ensure successful board interconnection, the values of PTP Clock Message
Location and Frame Format set for two interconnected boards must be the same.
This structure conflicts with that used for latency measurement.
Therefore, IEEE 1588v2 and latency measurement cannot be enabled
concurrently.
structure. This structure does not conflict with that for latency
measurement. IEEE 1588v2 and delay measurement can be enabled
concurrently.
● Frame Format:
port.

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NOTE
● Before configuring a port on a board as a PTP port, you need to configure the position
and frame format of PTP clock packets.
● PTP Clock Message Location is available only when Frame Format is set to HDLC.
● Only the UNS4 and UNQ2 boards of the OSN 1800 V support the setting of PTP Clock
Message Location.
● Only the UNS4 board of the OSN 1800 V supports the setting of Frame Format.
● When Frame Format of a local board changes between GFP and HDLC and is different
from that of the interconnected board, clock source tracing will be affected.

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----End


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NOTICE
Creating or deleting a PTP clock port on a TN52TOG board transiently interrupts

services on the port.
NOTE
NOTE
● After enabling static BMC, you must manually set the status of ports where IEEE 1588v2
is enabled. The default port state is LISTENING.
● If you want to modify a selected port, select the corresponding port in the Selected
Port field, and then click to add the port to Available Port.
----End

When a tributary board or a packet service board exchanges PDELAY packets, the
domain ID of the PTP port can be different from the clock subnet ID of the NE if
the following conditions are met:
● The working mode of the PTP port is TC or TC+OC.
● P/E Mode is set to P2P.
To interconnect with the peer device, you need to set the domain ID of the port to
be the same as the domain ID of the peer device. When the working mode of the
port is BC or OC, the domain ID of the port is the same as the clock subnet ID of
the NE.

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Step 1 Set the domain ID. For details, see 3.9.1.8.3 Parameters: Clock Synchronization
Attribute.
----End

of each NE.
Step 1 Select a port and set P/E Mode, SYNC Packet Period(s), DELAY Packet
Period(s), PDELAY Packet Period(s), ANNOUNCE Packet Period(s), and
ANNOUNCE Packet Timeout Coefficient. For details about the parameters, see
NOTE
----End

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precision.
changed:

WDM OTN
NOTE
----End

NOTE
This function is supported only when the system control board of the OSN 1800 V is
UXCMS and the product version is V100R009C00 or later. For details about the restrictions,
----End

The physical addresses for sending PTP and SSM packets can be configured so that
fields can be filled in to the sent packets based on the requirements of the
downstream equipment, improving the configuration flexibility for interconnection
with third-party equipment.

WDM OTN
NOTE

----End

When there are external clock sources for an NE, users need to configure the clock
attributes of the external clock sources, such as configuring the external port
cascading mode for clock boards, configuring attributes of external time ports, and
configuring the cable transmission distance permitted by an external time port.
Based on the configured clock attributes, the clock selection module can compute
which clock is best to use as the best master clock.
Prerequisites
● The IEEE 1588v2 has been enabled.
● The STG board has been created.
is configured, the 120-ohm external clock interface cable should be used as
the network cable for the concatenation.

WDM OTN

The external port of a clock board can be used to connect the external time. In
multi-subrack NE.
● Each subrack has two clock ports and two timing ports. These ports are used
to concatenate and transmit the clock or timing signals among multiple
to the disabled state. One NE supports a maximum of two ports for the input
or output of external clock and timing signals.
switches the frequency source mode to Physical Synchronization when the
Synchronization.
----End
Configuring External Time Interfaces

When there are external clock sources for an NE, users need to set the attributes
of the external time interfaces so that the NE can use the correct external clock.
The Enabled Status of the external time interface must be set to Disabled.
Step 1 Select an external time interface and configure the settings in the following fields:
Direction, Interface Protocol Type, and Interface Level. For parameter details,
see 3.9.1.8.7 Parameters: Basic Attribute.

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NOTE
For the Interface Level field, the OSN 6800 only supports the value RS422.
Step 2 Configuring Time Quality Level, Time Precision, Clock Source Type, Clock
Source Priority 1, Clock Source Priority 2, and Clock Source Deviation fields.
Then configure the settings for each parameter. For parameter details, see
3.9.1.8.8 Parameters: BMC (External Time Interface).
The STG clock board supports mutual conversion between 1PPS+TOD quality
● If the manually specified Time Quality Level is the default value 187, the STG
table.
Table 3-52 provides the mapping between the TOD status information and IEEE
1588v2 time quality level.

WDM OTN
Table 3-52 Mapping between the TOD status information and IEEE 1588v2 time
quality level
TOD Status Information IEEE 1588v2 Time Quality Level
0x00: normal 6


Other (remain) 255
----End
Configuring Cable Transmission Distance Permitted by an External Time Port

Users need to set the cable transmission distance based on the actual length of an
Step 1 Select an external time interface and configure settings in the following fields:
Transmitting Direction, Transmitting Distance Mode, Transmitting Length(m),
and Transmitting Time(ns). For parameter details, see 3.9.1.8.9 Parameters:
Cable Transmitting Distance.

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NOTE
● The Transmitting Length(m) field is available only when the Transmitting Distance
Mode is set to Length; the Transmitting Time(ns) field is available only when the
Transmitting Distance Mode is set to Time.
● The values of the Transmitting Length(m) and Transmitting Time(ns) are set
depending on the networking scheme for the site.
----End
3.9.1.6 Viewing Port Status

The U2000 supports the function of querying the clock source received at the port.
By using this function, you can query the tracing status of the NE time.
Prerequisites
● The clock port has been created.
Viewing Port Status

Step 1 Query port status. Ensure that slave ports carry the designated clock tracing paths.
----End
Viewing the Clock Source Received at a Port

Step 1 Query the clock source received at the port.

WDM OTN
----End

status of each NE.
Prerequisites
Context
Procedure
menu.
----End
3.9.1.8 Parameters: IEEE 1588v2 (OSN 1800/8800/9800 Universal Platform

Subrack/M Series Subrack/P Series Subrack/U Series Subrack: U2CTU/S2CTU/
U4CTU)

WDM OTN

Navigation Path
Parameters

that the NE traces.
NOTE
you need to set the
required.
● If physical clock
frequency
select Physical
Synchronization.
● If IEEE 1588v2
frequency
select PTP
Synchronization.

subracks on an NE.
Navigation Path

WDM OTN
Parameters

slot number-board
name-external clock
name)-slot number-
board name-external
time interface

cascading port.
synchronization are
set improperly, the
master and slave
port.
inputs/outputs the
unused.

Navigation Path
Clock Synchronization Attribute from the Function Tree.

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Parameters

parameter.
NE Name Example: NE7183 Displays the NE name.

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+OC specifies the working mode (OC,
Default value: BC TC, BC, TC+BC, or TC+OC) of the
node that adopts the IEEE
1588v2 clock. According to the
network planning, an NE on the
network must work in the OC,
TC, BC, TC+BC, TC+OC mode. The
specific working mode of the NE
must be determined in the
network planning phase.
During network planning, first
determine the position and
function of the NE and each port
on the NE. Then, set the working
mode of the NE according to the
features of each working mode.
● OC: As a clock device with
only one PTP port in the clock
domain, OC maintains the
device to provide a clock
source or as a slave clock
device to keep synchronous
with other clock devices.
● TC: TC forwards certain PTP
event messages and records
the residence time of the PTP
event messages on it. In
addition, TC provides the
recorded information to the
clock that receives the PTP
event messages. Then, the
recorded information is used
for transparent transmission
of packets and adjustment of
the residence time of the
packets on the device.
● BC: As a clock device with
domain, BC maintains the
device to provide a reference
clock source or as a slave
clock device to keep

WDM OTN

devices.
● TC+BC: TC+BC has the same
features as BC, except for that
the former only processes
delay but excludes itself from
● TC+OC: TC+OC is a mode for
transparently transmitting
time signals. An NE working in
this mode does not recover
the time, but it recovers the
clock. For an NE to
transparently transmit time
signals, Frequency Source
Mode must be set to PTP
Synchronization, and NE
Clock Type must be set to TC
+OC.

Default value: Disabled Enabled or Disabled to enable
or disable the IEEE 1588v2
protocol. When it is set to
Enabled, you can manually
configure the port status as
master or slave.

Default value: Yes specifies the Slave_Only attribute
for an OC port. This attribute
determines whether the OC port
works only as a slave clock port.
NOTE
● Yes: The port works only as a
slave clock port.
● No: The port works as a slave
clock port or a master clock
port.

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Adjustment Default value: Enabled parameter according to the
Protocol Packet NMEA, UBX Set and query the format of

Format Default value: UBX external clock protocol packets.
external time port is set to 1PPS
+Time.
WTR Time(min) 0–12 Specifies the time from detection

Default value: 5 of signal recovery to triggered

Supplying Code: 30
NE ID: 007E028B
Current Master For example: Indicates the number of the clock

Clock No. Company Code: 00259E source traced by the NE, which is
the number of the master clock
Supplying Code: 30 traced by the NE after the NE
NE ID: 007E028B selects the clock source.
Ingress of Subrack ID (subrack Specifies the local clock input

Current Master name)-slot ID-board port for the master clock that an
Clock name-port ID (port NE currently traces.
name)

WDM OTN

Compensation Default value: Disabled compensation calculation.
Calculation NOTE
details about the restrictions, see
Ring Network Enabled, Disabled Specifies whether to enable

Automatic Default value: Disabled automatic ring network
Compensation compensation.
After this function is enabled, an
NOTE

Port Subrack ID (subrack Specifies the name of the ports

name)-slot ID-board where the PTP clocks are
name-port ID (port synchronized.
name)

WDM OTN
Clock Type OC, BC, TC, TC+OC The Clock Type parameter
Default value: BC specifies the working mode (OC,
BC, TC, or TC+OC) of the node
For details about the that adopts the IEEE 1588v2
clock types supported clock. According to the network
by each board, see planning, an NE on the network
Availability in IEEE must work in the OC, BC, TC, or
1588v2. TC+OC mode. The specific
working mode of the NE must
be determined in the network
planning phase.
● OC: When ports on an NE are
set to OC mode, the NE can
work only in master or slave
status. A port in OC mode
can be used only for time
input or output.
● BC: When ports on an NE are
set to BC mode, the master or
slave status of the NE is
determined by using the BMC
algorithm.
● TC: If ports on an NE are set
to TC mode, the NE only
messages and does not
restore clock or time
information. In addition, the
NE does not have the master
or slave status.
● TC+OC: When ports on an NE
are set to TC+OC mode, the
NE restores clock information
but does not restore time
information, achieving TC
performance transmission.
NE is set to OC, Clock Type
of PTP ports on the NE must
be set to OC and only one
PTP port on the NE can be
enabled.
NE is set to BC, Clock Type of
set to BC.
NE is set to TC, Clock Type of

WDM OTN

set to TC.
NE is set to TC+OC, Clock
can be set to either TC+OC or
TC.
NE is set to TC+BC, Clock
can be set to either TC or BC.
NE is set to TC+BC, and
Static BMC is set to Enabled,
do not change the Clock
to TC.
Step Mode one-step, two-step Specifies whether an IEEE 1588

Default value: one port works in the one-step or
step two-step mode. Only tributary
boards support the setting of
one-step or two-step mode.
mode requires equipment
with high precision and
accuracy.
message.

WDM OTN
PTP Packet VLAN 1 to 4094, or 0xFFFF The PTP Packet VLAN

Default value: 0xFFFF parameter specifies the VLAN
IDs with the PTP packets at a
port. In the scenario of
interconnection with other
contain VLAN IDs.
● 1 to 4094: Indicates that the
specified VLAN ID is equal to
the VLAN ID of the packets.
● 0xFFFF: Indicates that the
VLAN ID is invalid.

Encapsulation Default value: PTP PTP packets.
Format ETH Based on the actual networking,
of PTP packets of the local
mode.

WDM OTN
Current Port MASTER, SLAVE, The Current Port Status

Status PASSIVE, LISTENING, parameter indicates the status of
FAULTY the clock source port on the
status based on the quality and
priority of the clock source.
● SLAVE: Indicates that the
port maintains
synchronization with the
upstream equipment with the
port in the master state on
the path.
master state and does not
maintain synchronization
state. It is neither in the
master state nor synchronous
with the port in the master
state.
order.
when a LOS, AIS, or
LinkDown alarm is reported
for the port.
Reference Clock NE clock ID-port ID Specifies the number of the

Source No. clock that is set as the clock
source for the port to trace.
Domain ID 0–255 Indicates the domain ID.

Default value: 0

WDM OTN

Port Subrack ID (subrack name)-slot Specifies the name of

ID-board name-port ID (port the ports where the
name) PTP clocks are
synchronized.

WDM OTN
P/E Mode Cancel, P2P, E2E Sets and queries the

Default value: E2E P/E mode of a PTP
port.
● P2P: Indicates the
P2P port mode.
● E2E: Indicates the
E2E port mode.
● Cancel: Indicates
no port mode.
TCs are classified into
P2P TCs and E2E TCs
according to different
mechanisms of
processing packets.
● P2P TC: The device
measures the
residence time of
an IEEE 1588v2
packet to be
forwarded and the
transmission delay
of the link
connected to the
port that receives
this IEEE 1588v2
packet. It also
records the
residence time and
link transmission
delay in the IEEE
1588v2 packet for
further processing
on the slave clock
device.
● E2E TC: The device
measures the
residence time of
an IEEE 1588v2
packet to be
forwarded and
records the
residence time in
the IEEE 1588v2
packet for further
processing on the
slave clock device.

WDM OTN
SYNC Packet 4/1024, 8/1024, 16/1024, Specifies the period at

Period(s) 32/1024, 64/1024, 128/1024, which the PTP port
256/1024, 512/1024, 1, 2 transmits Sync
Default value: 8/1024 packets. The delay-to-
respond mechanism
uses the Sync,
and Delay_Resp
packets to achieve
synchronization
between OC and BC
devices.
DELAY Packet 64/1024, 128/1024, 256/1024, Specifies the period at

Period(s) 512/1024, 1, 2, 4, 8, 16 which the PTP port
Default value: 1 transmits Delay
respond mechanism
uses the Sync,
and Delay_Resp
packets to achieve
synchronization
between OC and BC
devices.
set only when P/E
Mode is set to E2E.
PDELAY Packet 64/1024, 128/1024, 256/1024, Specifies the period at

Period(s) 512/1024, 1, 2, 4, 8, 16 which the PTP port
Default value: 1 transmits Pdelay
packets. The
Pdelay_Req,
Pdelay_Resp, and
Pdelay_Resp_Follow_U
p packets are used to
measure the link delay
between two clock
ports where the
Pdelay mechanism
functions.
set only when Work
Mode is set to TC and
P/E Mode is set to
P2P.

WDM OTN
ANNOUNCE 64/1024, 128/1024, 256/1024, Specifies the period at

Packet Period(s) 512/1024, 1, 2, 4, 8, 16 which the PTP port
Default value: 128/1024 transmits ANNOUNCE
packets. The
ANNOUNCE packets
contain the clock
attributes of an NE
and are used to set up
a synchronous system.
NOTE
When the TN52TOG/
TN54TOG/TN54TOA/
TN57TOA/TN54THA/
ELOM/TNF5TOA board
is interconnected with a
PTN device to transmit
IEEE 1588v2 clock
signals, ANNOUNCE
Packet Period(s) must
be set to 64/1028.
Otherwise, the
interconnected PTN
device may fail to trace
the clock source once
the link is faulty.
ANNOUNCE For OSN 8800 TN54TOG, Specifies the timeout

Packet Timeout TN54TOA, TN57TOA, and coefficient of receiving
Coefficient TN54THA and OSN 1800: 3– 255; ANNOUNCE packets.
for other boards: 3–10 By default, if the
For OSN 3800 and OSN 9800, ANNOUNCE packets
the default value is 4. are not received for
four consecutive
For OSN 6800, the default value periods, the packet
is as follows: receiving times out
● TN12ND2 and the link fails.
8
● TN52ND2, TN11ST2,
TN52TOG, TN55TQX,
TN53TDX
4
For the OSN 1800, the default
value is 3.

WDM OTN

Port Subrack ID (subrack name)-slot Specifies the name of

ID-board name-port ID (port the ports where the
name) PTP clocks are
synchronized.
Warp Direction Positive, Negative Indicates the

Default value: Positive transmission time
difference between
the cables in the
directions between
two NEs.
● Positive: Indicates
that the
transmission
distance or
transmission time
in the receive
direction is longer
than that in the
transmit direction.
● Negative: Indicates
that the
transmission
distance or
transmission time
in the transmit
direction is longer
than that in the
receive direction.

WDM OTN
Warp Mode Length, Time Specifies the mode of

Default value: Time warp in transmission
over the cables in the
directions between
two NEs.
● Length: Indicates
of transmission
distance in the
transmit and
receive directions
on the line
between two NEs.
● Time: Indicates
of transmission
time in the
transmit and
receive directions
on the line
between two NEs.
Warp Length(m) OSN 8800/6800/1800: 0– Specifies the warp of

1700000 transmission distance
OSN 9800: 0–3555555 over the cables in the
Default value: 0 directions between
two NEs. Adjust the
time synchronization
according to the
actual warp in
NOTE
This parameter is
Warp Mode parameter
is set to Length.

WDM OTN
Warp Time(ns) 0–8000000 Specifies the warp of

Default value: 0 transmission time over
the cables in the
directions between
two NEs. Adjust the
time synchronization
according to the
actual warp in
transmission time.
NOTE
This parameter is
Warp Mode parameter
is set to Time.
Suggest Positive, Negative Specifies the

Compensate Default value: - suggested
Direction compensation
direction.
NOTE
This function is
supported only when
the system control
board of the OSN 1800
V is UXCMS and the
product version is
V100R009C00 or later.

Length(m) suggested
compensation length.
NOTE
This function is
supported only when
the system control
V is UXCMS and the
product version is

WDM OTN

Time(nm) suggested
compensation time.
NOTE
This function is
supported only when
the system control
V is UXCMS and the
product version is

Port Slot ID-Board Displays the

name-Port port name of
number(Port an NE.
name)
Single-Fiber Two-Way Dispensation Disabled, Specifies

Compensation Enabled whether to
Default value: enable single-
Disabled fiber
bidirectional
dispersion
compensation
.
Remote Transmit Wavelength (nm) Example: Specifies and

1310 displays the
remote
transmit
wavelength.
Setting rule:
This
parameter is
available only
when Single-
Fiber Two-
Way
Dispensation
Compensatio
n is set to
Enabled.

WDM OTN
Fiber Type Example: 255 Specifies and

displays the
fiber type.
Dispersion Slope Value Type Egress, Specifies and

type of the
fiber
dispersion
slope value
(value K).
Dispersion Slope Value Example: 93 Specifies and

displays the
fiber
dispersion
slope value
(value K).
Dispersion Compensation Value Type Egress, Specifies and

type of the
fiber
dispersion
inherent
compensation
(value b).
Dispersion Compensation Value Example: Specifies and

124150 displays the
fiber
dispersion
inherent
compensation
(value b).
NOTE

link status.
Navigation Path

WDM OTN
Parameters

name-optical port
number(optical port
name)

name)-optical port
number(optical port
name)

NE ID: 007E028B

messages from the
no abnormal alarm,

Navigation Path
Clock Subnet tab.
Parameters

WDM OTN
PTP Clock Subnet No. 0 to 255 Specifies the clock

the NE belongs.
clock subnet number
subnet.

Navigation Path
tab.
Parameters
NE Name For example: NE7183 Indicates an NE name.

WDM OTN
A smaller parameter
quality level.
values of the clock
Time Quality Level
Time Quality Level
source for tracing.

WDM OTN

49 in old versions and candidate master clock.
from 0 to 255 in new A smaller parameter
M/U/P subracks and This parameter has an
for other subracks in old the external clock source
versions: 49; for other for tracing. If the PTP
subracks in new versions: Clock Source Priority 1
254 and Time Quality Level
values of the clock
Time Precision

WDM OTN
time source.
Indicates the clock
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the Network Time
Protocol (NTP).
manually set.
OR: Indicates an

WDM OTN

the clock source. A
indicates a higher
priority.
for tracing. This
PTP Clock Source
source for tracing.

the clock source. A
indicates a higher
priority.
PTP Clock Source
PTP Clock Source
source for tracing.

WDM OTN

Deviation Default: Deviation parameter
● OSN 1800 subrack: the deviation of the
65535 master clock from the
● Other subracks: 32768 standard time. A smaller
parameter value
clock signals.
the same, PTP Clock
Source Deviation
tracing.

Navigation Path
tab.

WDM OTN
Parameters
interface the NE.


interface with the
an NE.
for the port.


Navigation Path

WDM OTN
Parameters
interface the NE.
A smaller parameter
quality level.
values of the clock
Time Quality Level
Time Quality Level
source for tracing.

WDM OTN

49 in old versions and candidate master clock.
from 0 to 255 in new A smaller parameter
M/U/P subracks:33; for This parameter has an
for other subracks in old the external clock source
versions: 49; for other for tracing. If the PTP
subracks in new versions: Clock Source Priority 1
33 and Time Quality Level
values of the clock
Time Precision

WDM OTN
time source.
Indicates the clock
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the network time
protocol (NTP).
a clock source
manually set.
OR: Indicates an

WDM OTN

the clock source. A
indicates a higher
priority.
for tracing. This
PTP Clock Source
source for tracing.

the clock source. A
indicates a higher
priority.
PTP Clock Source
PTP Clock Source
source for tracing.

WDM OTN

Deviation Default: Deviation parameter
● OSN 1800 subrack: the deviation of the
65535 master clock from the
● Other subracks: 32768 standard time. A smaller
parameter value
clock signals.
the same, PTP Clock
Source Deviation
tracing.
Local Priority 1 to 255 Indicates the clock

Default: 128 source priority of the
port.

Navigation Path

WDM OTN
Parameters
interface the NE.

NOTE
of a port is set to
only Ingress.
of a port is set to
Ingress and Egress.

option to set the
mode for the clock
Time.
If the delay can be
measured, set this
parameter to Time;
otherwise, set this
the transmission
in terms of length.
the transmission
in terms of time.

WDM OTN

to the actual
adjust the delay in
signals.
Set this parameter
according to the
delay can be
receive end and the
distance. If Enable
compensation at the
set only when
In the case of the
case of the receive
the receive end is
compensated.

WDM OTN

synchronization.
In the case of the
case of the receive
the receive end is
compensated.
set only when

Navigation Path

WDM OTN
Parameters


Compensatio key for
IEEE 1588v2
compensation
value.
NOTE
The value is
displayed as
"********" and
the query is
not
supported.

WDM OTN


securely
returning an
IEEE 1588v2
compensation
value.
Value
description:
The value
contains 12 to
16 characters.
It is
recommended
that the value
contain at
least three
types of the
following
characters:
● Lower-case
letters
● Upper-case
letters
● Digits
● Space or
special
characters
Setting rule:
The values of
New
Password and
Confirm
Password
must be the
same.

WDM OTN

NOTE
The default
key for
securely
returning an
IEEE 1588v2
compensation
value on the
upstream and
downstream
devices is
HW@_77wa.
You are
advised to
change the
default key
when using
the device for
the first time.

Password confirm
password for
securely
returning an
IEEE 1588v2
compensation
value.
Setting rule:
The values of
New
Password and
Confirm
Password
must be the
same.

Navigation Path

WDM OTN
Parameters
Board For example: Indicates the clock

Shelf5(Slave board.
shelf5)-5-54TOA(STND)

sending PTP and SSM
requirements of the
improving the
NOTE
are not supported.)
NOTE
TN54TOA, TN57TOA,
and TN54THA.
TNF6TOA, TNF2ELOM
(STND).
● OSN 1800 I&II
Compact: TNF2ELOM
(STND).
● OSN 1800 II Enhanced:
TNF2ELOM (STND).
3.9.2 Configuring a IEEE 1588v2 Clock (OSN 9800 U Series:

U1CTU/S1CTU)

This topic describes how to configure an IEEE 1588v2 clock.
Figure 3-18 shows the process of configuring an IEEE 1588v2 clock.

WDM OTN
Figure 3-18 IEEE 1588v2 clock configuration flowchart
Table 3-60 provides the detailed procedures for configuring IEEE 1588v2-
compliant frequency and phase synchronization.
NOTE
The procedures provided in Table 3-60 are only used to configure IEEE 1588v2-compliant
and IEEE 1588v2-compliant phase synchronization, configure the physical clock by referring
to 2.9.2.1 Configuration Process and then perform the procedures provided in Table 3-60
to configure IEEE 1588v2 packets.
Table 3-60 Procedures for configuring IEEE 1588v2-compliant frequency and

phase synchronization
Operation Remarks

configuring it for an NE. The number
of available licenses is deducted by 1
each time IEEE 1588v2 is enabled for a
subrack.
NOTE

WDM OTN
Operation Remarks

According to the actual networking,
you need to set the clock
synchronization attributes of each
NE on the U2000, including setting
parameters.
● Configure the BMC static source
selection algorithm is not enabled.
If a port is abnormal, automatic
switching is not triggered.
● Configuring clock subnets. When a
into multiple clock domains, clock
subnets must be configured.
● Set the attributes of the local clock.
you must set the local clock
parameters received by the local
NE, so that the clock selection
module can calculate the best
master clock.

parameters of the cable
time cables.

WDM OTN
Operation Remarks

Interfaces When an NE needs to input or output
external time interface attributes and
the Cable Transmission Warp
parameter.
3.9.2.6 Viewing the Clock Source Mandatory.

Received at the Port After all the clock configuration
processes are completed, users need to
query all ports for the clock
synchronization status to ensure that
the port synchronization status is the
same as that defined in the
networking diagram.

each NE.

You must enable IEEE 1588v2 before configuring it for a NE. The number of
Prerequisites
● The license of IEEE 1588v2 resources is available.
● The corresponding subrack must be created.
Procedure

WDM OTN
NOTE
ITU-T G.8275.1 and IEEE 1588v2 share the same license resources. ITU-T G.8275.1 is enabled
after IEEE 1588v2 is enabled on the U2000.
----End

To ensure normal operation of the PTP clock for each NE in a network, users need
to configure PTP clock global parameter, PTP clock subnet, local clock attributes
for the NE.
Prerequisites

WDM OTN

Based on the actual networking situation, you need to set the clock
synchronization attributes of each NE on the U2000. The attributes include PTP
work mode, PTP system time, and static BMC.
Step 1 Configuring Ptp Profile:
NOTE
The PTP System Time can be set only when the NE traces the local clock source.
Step 3 Configure Ne Clock Type, Static BMC, Slave Only, Packet Multicast Mode,
Protocol Packet Format, Correct UTC Time and select the required value from
the drop-down list respectively. For details about these parameters, see 3.9.2.8.1

WDM OTN
NOTE
The Slave Only parameter is available only when NE Clock Type is set to OC.
----End

subnets in planning the clock network depending on the scheme for the site.
Within each subnet, time synchronization can be implemented for all clocks.
NE.
Step 1 Configure Clock Subnet No. For details about these parameters, see 3.9.2.8.3

WDM OTN
NOTE
● Equipment that is in the BC or OC work mode can belong to only one clock subnet, and
its clock source can be selected only from within the same clock subnet.
----End
Configuring the Local Clock Attributes

Depending on the networking scheme for the site, you need to set the clock
attributes of the local clock sources received at the NE, so that the best master
clock can be calculated by the clock selection module.
Step 1 Configure Time Quality Level, Time Precision, Clock Source Type, Clock Source
Priority 1, Clock Source Priority 2 fields. Then configure the settings for each
parameter. For details about these parameters, see 3.9.2.8.4 Parameters: BMC
(Clock Subnet).

WDM OTN
----End

To ensure that precision time protocol (PTP) ports of every NE on a network work
correctly, users need to create logical PTP ports, configure attributes of PTP
packets, and specify the cable transmission deviation of PTP clock ports.
Prerequisites
● The corresponding board must be created.

● A clock port can be used to trace the PTP clock source. Clock ports are created
to enable a PTP clock port so that PTP packets can be received.
● The clock port is used to synchronize the time between two clock nodes.
Depending on the scheme for the site, several clock ports can be created for a
board to connect to other clock nodes.
Step 1 Configure a clock port. For parameter details, see 3.9.2.8.1 Parameters: Clock

WDM OTN
NOTICE
For a port on each 10GE LAN tributary board installed on an OSN 9800
V100R001C00 or V100R001C01, Port Mapping can be set to MAC Transparent
Mapping (10.7G). After the OSN 9800 is upgraded to V100R001C20, configuring
the port as a PTP port to support IEEE 1588v2 interrupts traffic on the port. The
traffic is restored automatically after the configuration is completed.
NOTE
In the OC work mode, only one clock port can be created.
----End

Configuring the clock source priority table specifies the priority of each required
clock source. This provides a criterion for selecting clock sources in the event that
of clock switching occurs.
Step 1 Configure Clock Source WTR Time(min).

WDM OTN
NOTE
You can set any integer from 0 to 12 for Clock Source WTR Time(min), with a step of 1.
Step 2 Configure Port, Clock Source No, and Clock Source PortNo.

WDM OTN
----End
Configuring the PTP Packet Attributes

To ensure the normal operation of the PTP clock for each NE in the network, you
of each NE.
Step 1 Configure P/E Mode, SYNC Packet Period(s), DELAY Packet Period(s), PDELAY
Packet Period(s), ANNOUNCE Packet Period(s), and ANNOUNCE Packet
Timeout Coefficient. For parameter details, see 3.9.2.8.1 Parameters: Clock

WDM OTN
NOTE
The DELAY Packet Period(s) field is available only when the P/E Mode is set to E2E; the
PDELAY Packet Period(s) field is available only when the P/E Mode is set to P2P.
----End
Configuring the Cable Transmission Deviation for the Clock Port

When the transmission time or length configurations of a cable in the receive and
transmit directions are inconsistent, the transmission deviation of a cable needs to
be set to rectify the PTP clock synchronization process and therefore ensure the
clock synchronization precision.
The transmission deviation of a cable means the time difference of the clock
signals in the cable transmission in the receiving and sending directions between
two NEs. Generally, the actual time difference of cable transmission for the two
directions is calculated by GPS in the deployment. The cable transmission
deviation can be represented by time or by length.
Step 1 Configure Warp Direction, Warp Mode, Warp Length(m), and Warp Time(ns).
For parameter details, see 3.9.2.8.1 Parameters: Clock Synchronization
Attribute.
NOTE
● The value Positive of the Warp Direction field specifies that transmission distance
through the receiving direction is longer than the distance through the sending
direction, or the transmission time of the receiving direction is longer than the time of
the sending direction; the value Negative specifies just the opposite.
● The Warp Length(m) field is available only when the Warp Mode is set to Length; the
Warp Time(ns) field is available only when the Warp Mode is set to Time.
● The values of the Warp Length(m) and Warp Time(ns) are set according to the
----End

WDM OTN
3.9.2.5 Configuring External Time Interfaces

When there are external clock sources for an NE, users need to configure the clock
attributes of the external clock sources, such as configuring attributes of external
time interfaces, and configuring the cable transmission distance permitted by an
external time interface. Based on the configured clock attributes, the clock
selection module can compute which clock is best to use as the best master clock.
Prerequisites
● The CTU board has been created.

of the external time interfaces so that the NE can use the correct external clock.
Step 1 Select an external time interface and configure the settings in the following fields:
External Time Interface Direction, and Interface Protocol Type. For parameter
details, see 3.9.2.8.5 Parameters: Basic Attribute.
Step 2 Configure Bits Type, Bits Clock Class Level, Bits Precision, Bits Time Source, Bits
Priority 1, Bits Priority 2 fields. Then configure the settings for each parameter.
For parameter details, see 3.9.2.8.6 Parameters: BMC (External Time Interface).

WDM OTN
----End
Configuring Cable Transmission Distance Permitted by an External Time

Interface
Step 1 Select an external time interface and configure settings in the following fields:
Input Warp Mode, Input Warp Length(m), Input Warp Time(ns), Output
Warp Mode, Output Warp Length(m), Output Warp Time(ns). For parameter
details, see 3.9.2.8.7 Parameters: Cable Transmitting Distance.

WDM OTN
NOTE
● The Input Warp Length(m) field is available only when the Input Warp Mode is set to
Length; the Input Warp Time(ns) field is available only when the Input Warp Mode is
set to Time.
● The Output Warp Length(m) field is available only when the Output Warp Mode is
set to Length; the Output Warp Time(ns) field is available only when the Output
Warp Mode is set to Time.
● The values of the Input Warp Length(m), Output Warp Length(m), Input Warp
Time(ns), and Output Warp Time(ns) are set depending on the networking scheme
for the site.
----End
3.9.2.6 Viewing the Clock Source Received at the Port

The U2000 supports the function of querying the clock source received at the port.
By using this function, you can query the tracing status of the NE time.
Prerequisites
Procedure
Step 1 Query the information about the clock source received at the port is displayed.
----End

status of each NE.
Prerequisites

WDM OTN
Context
Procedure
menu.
----End
3.9.2.8 Parameters: IEEE 1588v2 (OSN 9800 U Series: U1CTU/S1CTU)


In this user interface, you can configure and query the NE and port attributes,
such as the PTP system time, working mode, packet transmission period on the
port, and transmission deviation of the cable, in the PTP clock system.
Navigation Path
Clock > Clock Synchronization Attribute from Function Tree.
Parameters

parameter.

WDM OTN
+BC, or TC+OC) of the node that
+BC, TC+OC mode. The specific
mode of the NE must be
determined in the network
planning phase.
Static BMC Enable, Disable NOTE

Static BMC can be set to either
Default: Disable Enabled or Disabled to enable or
disable the IEEE 1588v2 protocol.
When it is set to Enabled, users can
manually configure the port status
as master or slave.

Default: No provides an option to set the
NOTE
Enable Automatic Enable, Disable On a ring network, if a fiber is

Compensation Default: Disable cut over or adjusted, the NE
Measurement automatically computes fiber
length variation. In this course,
users do not need to manually
measure the fiber length
variation, but only need to set
compensation parameters. In
this manner, the NE can
maintain time synchronization
with GPS.
NOTE
The WDM/OTN equipment does not
support setting Enable Automatic
Compensation Measurement.

WDM OTN
Packet Multicast Multicast, Partly- In multicast mode, SYNC,

Mode Multicast ANNOUNCE, and DELAY packets
Default: Multicast are multicasted. In part
multicast mode, SYNC and
ANNOUNCE packets are
multicasted, whereas DELAY
packets are unicasted.
Inpartly-multicast mode,
Delay_Req and Delay_Resp
packets are unicasted. In E2E TC
scenarios, this avoids
transmission of delay Req
packets between slave
equipment.
Protocol Packet NMEA, UBX Configures and queries the

Format Default: UBX protocol packet format.
The Protocol Packet Format is
valid only when Interface
Protocol Type of the external
time interface is set to 1PPS
+Time.

Source No. 00259e30007d0050 local clock source of the NE.
Current Master For example: Displays the master clock

Clock No. 00259e30007d0050 number that the NE traces.
Ingress of Current For example: PTP Displays the local clock input
Master Clock interface of the master clock
that the NE traces after you
specify the clock source for the
NE.
Hops of Current For Example: 3 Indicates the number of hops for

Master Clock transmitting clock signals from
the master clock to the current
NE.
For example, the signal route is
NE A (master clock)->NE B->NE
C->NE D. For NE D, Hops of
Current Master Clock is 3.
Correct UTC Time 0 to 255 Correct the UTC time.

Default: 35
Ptp Profile IEEE 1588v2, G.8275.1 Indicates the PTP protocol type

WDM OTN


synchronized.
PTP Packet VLAN 0 to 4094 The PTP Packet VLAN

contain VLAN IDs.
PTP Packet VLAN 0 to 7 Sets the VLAN priority of a port

PTP Packet DSCP 0 to 63 Sets the DSCP priority of a port


mode.
PTP Packet - -
Destination MAC
Address

IP Address
PTP Packet - -
Destination IP
Address
Port Prefigure MASTER+SLAVE, Sets the prefigure status of a

Default: MASTER
+SLAVE
Current Port Master, Slave, Passive, Displays the current status of a

Status Listening port.

WDM OTN
Port Manual Master, Slave, Passive, The Current Port Status

Status Listening parameter indicates the status of
Default: Listening the clock source port on the
status according to the quality
and priority of the clock source.
Port Domain 0 to 255 indicates the domain ID.

Default: 0
Step Module one step, two step Specifies whether an IEEE 1588
Default: one step port works in the one-step or
two-step mode.
● In the one-step mode, the
actual Tx time stamp is sent
through the Sync packet to be
accuracy.
● In the two-step mode, the
actual Tx time stamp is not
added to the Sync packet to
be transmitted. Instead, the
time stamp is sent through
the subsequent Follow-Up
packet.
PTP port type none, BC, TC Specifies PTP port type.

Default: none
PTP Status Enabled, Disabled Specifies whether a port

Default: Enabled supports PTP packets.


synchronized.

WDM OTN
P/E Mode P2P, E2E The P/E Mode parameter

Default: E2E provides an option to set and
query the P/E mode of a PTP
port.
● P2P: Indicates the P2P port
mode.
● E2E: Indicates the E2E port
mode.
● Cancel: Indicates no port
mode.
TCs are classified into P2P TCs
and E2E TCs according to
different mechanisms of
processing packets.
● P2P TC: The device measures
1588v2 packet to be
forwarded and the
transmission delay of the link
connected to the port that
receives this IEEE 1588v2
packet. It also records the
residence time and link
transmission delay in the IEEE
1588v2 packet for further
device.
● E2E TC: The device measures
1588v2 packet to be
forwarded and records the
residence time in the IEEE
1588v2 packet for future
device.
SYNC Packet 4/1024, 8/1024, 16/1024, The SYNC Packet Period(s)

512/1024, 1, 2 port transmits the Sync packets.
Default: 64/1024 The delay-to-respond
and BC.

WDM OTN

Default: 1 port transmits the Delay
packets. The delay-to-respond
and BC.
when P/E Mode is set to E2E.
PDELAY Packet 64/1024, 128/1024, The PDELAY Packet Period(s)

Default: 1 port transmits the Pdelay
packets. The Pdelay_Req,
Pdelay_Resp, and
Pdelay_Resp_Follow_Up packets
are used to measure the link
delay between two clock ports
where the Pdelay mechanism
functions.
when Work Mode is set to TC
and P/E Mode to P2P for the
port.

Packet Period(s) 256/1024, 512/1024, 1, Period(s) parameter provides
2, 4, 8, 16 an option to set the period at
Default: 128/1024 which the PTP port transmits
the ANNOUNCE packets. The
clock attributes of an NE and
are used to set up a
synchronous system.
ANNOUNCE 3 to 10 Specifies the times of the

Packet Timeout Default: 4 ANNOUNCE message period.
Coefficient The value of this parameter
multiplied by the ANNOUNCE
message period is equal to the
timeout interval of receiving
ANNOUNCE packets. When the
port does not receive
set timeout interval, it is
considered that the packets
cannot arrive and the link fails.

WDM OTN


synchronized.
Warp Direction Positive, Negative The Warp Direction parameter

Default: Positive provides an option to set how
the time of transmission over
the cables between two NEs
warps in the transmit and
receive directions.
direction.
direction.
Warp Mode Length, Time The Warp Mode parameter

Default: Time provides an option to set the
mode of warp in transmission
over the cables in the transmit
and receive directions between
two NEs.
between two NEs.
between two NEs.

WDM OTN
Warp Length(m) 0 to 3555555 The Warp Length(m)

set the warp of transmission
distance over the cables in the
transmit and receive directions
between two NEs. Then, adjust
the time synchronization
NOTE
set to Length.
Warp Time(ns) 0 to 8000000 The Warp Time(ns) parameter

Default: 0 provides an option to set the
warp of transmission time over
the cables in the transmit and
NEs. Then, adjust the time
time.
NOTE
set to Time.

receive direction.
Actual Example: 10 The value relies on the deviation

Measurement mode (length or time).
Warp (ns) If a fiber/cable between two NEs
does not have transmission
deviation between the sending
and receiving directions, Actual
Measurement Warp (ns) and
Accept Actual Measurement
Warp are grayed out.
Accept Actual Example: 10 No compensation is required if

Measurement the deviation is within the
Warp accepted range.

WDM OTN

link status.
Navigation Path
tab.
Parameters


receives.

messages from the
the status is Down.

Navigation Path
> Clock Subnet Configuration from the Function Tree. Then, click the Clock
Subnet tab.

WDM OTN
Parameters
Clock Subnet No. 0 to 255 Specifies the clock

the NE belongs.
clock subnet number
subnet.

Navigation Path
tab.

WDM OTN
Parameters
Time Quality Level 0 to 255 The Time Quality Level

option to set the quality
level of the time or
A smaller parameter
quality level.
values of the clock
Time Quality Level
Time Quality Level
source for tracing.

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Time Precision 0 to 255 The Time Precision

precision of the
A smaller parameter
quality level.
and Time Quality Level
values of the clock
Time Precision

WDM OTN
time source.
Indicates the clock
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the Network Time
Protocol (NTP).
manually set.
OR: Indicates an

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the clock source. A
indicates a higher
priority.
for tracing. This
PTP Clock Source
source for tracing.
Clock Source Priority 2 0 to 255 The PTP Clock Source

Default: 128 Priority 2 parameter
the clock source. A
indicates a higher
priority.
PTP Clock Source
PTP Clock Source
source for tracing.

WDM OTN

Navigation Path
Clock > External Time Interface from the Function Tree. Click the External Time
Interface Attribute tab.
Parameters

the NE.

WDM OTN

External Time Interface external clock interface
are as follows:
● Configuration
management of 2
Mbit/s clock sources
in the input and
output directions.
● Configuration
management of 2
Mbit/s output clock
sources.
● 2 Mbit/s clock sources
can function as the
reference clock
sources for system
frequency
synchronization.
The features of an
external time interface
are as follows:
input/output
direction, protocol
type, and interface
time interface.
time, and can also
function as the
for restoring the
system clock
frequency.


WDM OTN

interface with the
an NE.
for the port.

Navigation Path
Parameters

the NE.

WDM OTN

levels of external time
interfaces.
● Manual: You can
quality levels of
external time
interfaces. Quality
Level indicates the
time quality level.
● Auto: NEs obtain the
time quality levels of
external time
interfaces
automatically after
converting 1PPS
status values
according to the
conversion table.
Bits 1PPS Status Available, Atomic Clock 1PPS status values can
Hold, Unavailable, be converted into time
Oscillator Hold, quality levels according
Transport Device Hold, to the conversion table.
Rubidiumc Clock Hold ● Available corresponds
to level 6.
● Atomic Clock Hold,
Unavailable
● Unavailable
255.
● Oscillator Hold
52.
● Transport Device Hold
187.
● Rubidiumc Clock Hold
Bits Quality Level 0 to 255 Indicates the actual time

quality levels of external
time interfaces.

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Bits Clock Class Level 0 to 255 The Bits Clock Class

Default: 6 Level parameter provides
quality level of the time
or frequency allocated by
A smaller parameter
quality level.
Bits Precision 0 to 255 The Bits Precision

precision of the
A smaller parameter
quality level.
Bits Time Source ATOMIC_CLOCK, GPS, The Bits Time Source

TERRESTRIAL_RADIO, parameter provides an
PTP, NTP, HAND_SET, option to set the type of
OTHER, the clock source.
INTERNAL_OSCILLATOR
Default: GPS

option to set the primary
source. A smaller
parameter value
indicates a higher
priority.

option to set the
auxiliary priority of the
clock source. A smaller
parameter value
indicates a higher
priority.


WDM OTN
Navigation Path
Clock > External Time Interface from the Function Tree. Click the Bits
Parameters

the NE.
Input Warp Mode Length, Time The Input Warp Mode

option to set the
mode for the clock
interface of input
Time.
Input Warp Length(m) 0 to 300 The Input Warp

Default: 0 Length(m) parameter
input direction. Set this
clock signals.
Input Warp Time(ns) 0 to 1350 The Input Warp

cable of input direction.
Set this parameter
synchronization.

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Output Warp Mode Length, Time The Output Warp Mode

option to set the
mode for the clock
interface of output
Time.
Output Warp 0 to 300 The Output Warp

output direction. Set this
clock signals.
Output Warp Time(ns) 0 to 1350 The Output Warp

cable of output direction.
Set this parameter
synchronization.

WDM OTN
Clock Synchronization Feature Guide 4 ITU-T G.8275.1/G.8273.2 (OTN & Packet)
4 ITU-T G.8275.1/G.8273.2 (OTN & Packet)
4.1 Introduction of ITU-T G.8275.1/G.8273.2 (OTN &

Packet)
WDM/OTN equipment supports ITU-T G.8275.1 and ITU-T G.8273.2 to implement
clock and time synchronization.
ITU-T G.8275.1 Overview

ITU-T G.8275.1 is a precise time synchronization telecommunications standard
defined based on the IEEE 1588v2 PTP protocol. Compared with IEEE 1588v2, ITU-
T G.8275.1 features the following:
● Simplifies NE models and source selection algorithms, making the standard
more suitable for the telecommunications field.
● Defines packets more specifically, facilitating interconnection and
interworking.
The following figure shows the values of the ITU-T G.8275.1 standard.

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Figure 4-1 ITU-T G.8275.1 values
ITU-T G.8275.1 Application Scenario

Different from physical clocks that recover clock information from service bit
streams, ITU-T G.8275.1 implements frequency and phase synchronization through
PTP packet exchanges, as shown in the following figure. The synchronization is
implemented hop by hop, which requires that all devices in the synchronization
network must support the ITU-T G.8275.1 function.
Figure 4-2 ITU-T G.8275.1 application scenario

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NOTE
ITU-T G.8273.2 Overview

IEEE 1588v2 defines only the time synchronization protocol methods, but does not
define the synchronization performance. ITU-T G.8273.2 clearly defines the time
synchronization performance of each single device from the following aspects:
time error, noise tolerance, noise transfer, transient phase response, and holdover.
WDM equipment complies with the ITU-T G.8275.1 and G.8273.2 standards and
satisfies the carrier-level time synchronization precision requirements.
ITU-T G.8273.2 has the same application scenario as ITU-T G.8275.1. To use ITU-T
G.8273.2, you must configure it with ITU-T G.8275.1.
4.2 Principles
ITU-T G.8275.1 defines the clock standards in the telecommunications field. It
establishes the master-slave relationship between network nodes and accurately
and precisely transmits clock reference information to each control point using the
time synchronization mechanism.

The ITU-T G.8275.1 system uses the master/slave clock structure. The highest-
priority clock, namely, telecom grandmaster (T-GM), transmits clock information
to terminal devices using the telecom boundary clock (T-BC) and telecom time
slave clock (T-TSC) clocks.
NOTE
ITU-T G.8275.1 V2.0 supports T-TC, which is similar to TC of IEEE 1588v2, and only
participates in delay testing as well as transparently transmits time synchronization packets,
but does not synchronize time.
Node Model
Figure 4-3 shows the positions of the three types of clock nodes on a time
synchronization network.

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Figure 4-3 Positions of the three types of clock nodes on a time synchronization
network
NOTE
The T-BC clock functions include the functions of the T-GM and T-TSC clocks.
Master-Slave Clock Hierarchy

In the entire clock system, the optimal clock is the T-GM clock that has the highest
priority. The T-GM clock has the best stability, precision, and certainty. Based on
the precision and levels of clocks on each node and traceability of Coordinated
Universal Time (UTC), the best master clock algorithm (BMCA) automatically
selects the master clock on each subnet (For details, see 4.2.5 Alternative BMC
Algorithm.)
Figure 4-4 describes the process of establishing the master-slave clock hierarchy
between the T-GM, T-BC, and T-TSC clocks in a PTP clock domain.
Figure 4-4 Process of establishing the master-slave clock hierarchy
As shown in Figure 4-4, the T-GM clock is located at the root and therefore is
called as the grandmaster clock. Port 1 of T-BC1 functions as the slave port of the
grandmaster clock and marked as S. The other ports of T-BC1 function as the
master ports of the clock device connected to T-BC1 and therefore are marked as

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M. Therefore, port 1 of T-BC2 functions as a slave port of T-BC1. The rest can be
deduced.
The master-slave clock hierarchy establishment of the PTP clock system mainly
depends on the Announce messages of other clocks received by ports, port data
sets, BMCA, and port state machine. The PTP clock system performs the following
steps to establish the master-slave clock hierarchy:
1. Receives and authenticates the Announce messages from other clock ports.
2. Determines the recommended port status based on the BMCA.
3. Updates the port data sets based on the decision point in the recommended
status using the port status decision algorithm.
4. Determines the actual status of the port based on the recommended status
and status decision event in the port state machine to establish the master-
slave clock hierarchy.
Clock Port Status

Each port of the T-GM, T-BC, and T-TSC has its own PTP state machine. A state
machine defines the allowed states and the rules for conversion between the
states. There are the following port states:
● MASTER: A port in the Master state provides the time source for the
downstream devices on the trail where the port is located.
● SLAVE: A port in the Slave state keeps synchronous with the upstream device
ports in the Master state.
● PASSIVE: A port in the Passive state is isolated from the upstream and
downstream devices. It is neither in the Master state nor synchronous with
the port in the Master state.
● FAULTY: The state of a port changes from Master, Slave, or Passive to Faulty
when a LOS, AIS, LinkDown, or other alarm is reported for the port.
4.2.2 Time Source Port

Time source information can be received through external time ports and service
time ports.

WDM OTN

Type Format
External 1PPS+TOD RJ45 ● Receives time signals

time port from the BITS or other
devices that have the
same port.
● Cascades with other
devices of the same
type at the same site.
● Connects to the lower-
layer PTN/SDH
network.
Service time Ethernet Inband port that Connects to the lower-

port services, runs with services. layer PTN/SDH network
including GE, without equipment room
10GE, and or site sharing
40GE restrictions.
OSC clock OSC OSC optical port Supports time

devices.
Clock Ethernet port GE optical port Used for time

synchroniza synchronization between
tion GE NEs or time cascading
synchronization are
supported. Ethernet
services cannot be
transmitted.
A synchronous network using the IEEE 1588v2 protocol obtains time signals from
the reference time source grandmaster clock using external time ports.
1PPS+TOD Time Signals

1PPS+TOD time signals consist of 1PPS signals and TOD time information.
● 1PPS
1PPS is short for one pulse per second. 1PPS signals are used for time scaling
and work at the RS-422 levels. The pulse frequency of 1PPS is 1 Hz. That is,
one pulse is transmitted per second. The 1PPS signal pulse width ranges from

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20 ms to 200 ms. The rising edge of the pulse is strictly coincident with the
UTC time.
● TOD
TOD is short for time of day. TOD messages provide time in ASCII format.
TOD signals also work at the RS-422 levels and provide a baud rate of 9600
bit/s. A TOD message contains information such as current date/time, time
standard ID, 1PPS status flag, date/time adjusted based on UTC leap seconds,
leap second adjustment directive, and GPS time.
The clock board supports mutual conversion between 1PPS+TOD quality
table.
Table 3-2 provides the mapping between TOD status information and PTP time
quality levels.
Table 4-2 Mapping between TOD status information and PTP levels
TOD Status Information PTP Time Quality Level
0x00: normal 6


0x04: holdover on the transmission 187

equipment

WDM OTN
External Time Ports

Port Port

universal platform
subrack
OSN 8800
universal platform
subrack
OSN 6800

series/M24/P32/
P32C

T32/T64

CLK3/TOD3 CLK3/TOD3

Enhanced
CLK3/TOD3 CLK3/TOD3

Enhanced

Compact
(TNF3SCC)

TMT1SCC

CLK3/TOD3 CLK3/TOD3

WDM OTN

Port Port

TMK5XCH,
TMK6XCH,
TMK5UXCME,
TMK6UXCM,
TMK5XCSb

CLK3/TOD3 CLK3/TOD3

CLK3/TOD3 CLK3/TOD3
NOTE
NOTE
External Time Connection Mode

External time mode: The external time port is used to interconnect with the BITS
or other devices. The output time can be synchronized with the system time of an
NE or the line source specified by the NMS. When a port works in external time
mode, it transmits time signals unidirectionally. Therefore, you need to specify
whether the port is used for signal input or output.
Cascading mode: The external time port is used only for interconnection between
multiple subracks of WDM/OTN products and is always synchronized with the
system time. When a port works in the cascading mode, it transmits time signals
bidirectionally. The system automatically determines the time tracing relationship.
NOTE
is set to Enabled, the cascading mode is used. When this parameter is set to Disabled, the
external time mode is used.

WDM OTN

Time Port Supported Applicable Scenario Networking Diagram
Type Format

time mode work in the where WDM/OTN
external time equipment is
mode. interconnected with
external time source
devices or
WDM/OTN NEs are
interconnected.
Cascading All subracks This mode is Figure 4-6

time mode work in this recommended when
1 cascading master and slave
time mode to subracks are
form ring configured and the
protection. subracks support the
clock cascading
Cascading All subracks mode. Figure 4-7
time mode work in this
NOTE
2 cascading For details about
mode with which products
protection support clock
paths. cascading between
master and slave
subracks, see 2.5
Specifications.
NOTE
the TOD port.
similar.

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Figure 4-5 Connection diagram of the external time mode

WDM OTN
Figure 4-6 Connection diagram of cascading time mode 1

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Figure 4-7 Connection diagram of cascading mode 2


OSN 1800 II Pro
OSN 1800 II TP
OSN 1800 V

WDM OTN

OSN 1800 II Enhanced TMB1MD48AFS HP1 (HP2)

TMK6XCH, TMK5UXCME,
TMK6UXCM, TMK5GSCC

OSN 9800 M05

OSN 9800 M12
OSN 9800 M05

NOTE

NOTE
V100R021C10SPC100.

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separately.
NOTE
protection.


WDM OTN



WDM OTN


4.2.3 ITU-T G.8275.1 Time Synchronization Principles

The ITU-T G.8275.1 clock system uses the Precision Time Protocol (PTP)
synchronization mechanism so that slave clocks can be synchronized with their
master clocks using PTP messages.
ITU-T G.8275.1 Messages

The PTP messages defined by ITU-T G.8275.1 include the following:

WDM OTN
● Announce messages are used to build the master-slave synchronization

hierarchy.
● Sync messages are used by the master clock to initiate a synchronization
request.
● Follow_Up messages are used by two-step clocks to carry timestamps.
● Delay_Req messages are used by save clocks to initiate delay measurement
requests. Delay_Req is used in the E2E mode.
● Delay_Resp messages are used to respond to the delay measurement requests
of slave clocks. Delay_Resp is used in the E2E mode.
NOTE
ITU-T G.8275.1 supports only the E2E working mode.
ITU-T G.8275.1 Clock Synchronization Mechanisms

ITU-T G.8275.1 clocks are based on the precise matching time when synchronous
data messages are transmitted and received. Each slave clock exchanges the
synchronous messages with the master clock so that it can be synchronized with
the master clock.
Figure 4-13 describes the ITU-T G.8275.1 clock synchronization process.
Figure 4-13 ITU-T G.8275.1 clock synchronization process
1. At the time of t1, the master clock sends a Sync message. If the master clock
is a one-step clock, the t1 timestamp is contained in the Sync message and
sent to the slave clock. If the master clock is a two-step clock, then the t1
timestamp is contained in the subsequent Follow_Up message and sent to the
slave clock.
2. At the time of t2, the slave clock receives the Sync message and obtains the t1
timestamp from the Sync message (one-step mode) or from the subsequent
Follow_Up message (two-step mode) message.
3. At the time of t3, the slave clocks send delay request messages.

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4. At the time of t4, the master clocks receive delay request messages.
5. At the time of t5, the master clock sends delay response messages that carry
the information of the time of t4.
The method of calculating the time difference between slave clocks and the
master clock and the link delay is as follows:
Because
t2-t1=Delay+Offset
t4-t3=Delay-Offset
Hence,
Offset=[(t2-t1)-(t4-t3)]/2
Delay=[(t2-t1)+(t4-t3)]/2
NOTE
● Offset: Time difference of a slave clock from the master clock.

● Delay: The delay time caused by network transmission.
4.2.4 ITU-T G.8275.1 Frequency Synchronization Principles

Frequency synchronization is implemented based on the timestamps for receiving
and transmitting Sync messages of ITU-T G.8275.1.
NOTE
● ITU-T G.8275.1-compliant PTP frequency synchronization involves two actions: frequency

gauging and frequency correction. The synchronization precision of this method is lower
than that of frequency synchronization based on physical clocks.
● For Ethernet service ports that support both synchronous Ethernet and PTP frequency
synchronization modes, you are advised to use synchronous Ethernet for frequency
synchronization.
Figure 4-14 shows the time of receiving and transmitting Sync messages between
clock A (slave) and clock B (master) when clock A synchronizes to clock B. Clock A
can correct its clock frequency after comparing the interval between two message
transmitting timestamps with the interval between two message receiving
timestamps. In this manner, clock A synchronizes to clock B. If the changes in the
link delay and residence time are negligible, the clock frequency of clock A can be
corrected using the following formula:
(t1[N] - t1[0])/(t2[N] - t2[0])
● If the value of the "t2[N] - t2[0]" is equal to the value of "t1[N] - t1[0]": This
means that clock A and clock B run at the same rate.
● If the value of the "t2[N] - t2[0]" is greater than the value of "t1[N] - t1[0]":
This means that clock A runs faster than clock B and needs to slow down its
frequency.
● If the value of the "t2[N] - t2[0]" is less than the value of "t1[N] - t1[0]": This
means that clock A runs slower than clock B and needs to accelerate its
frequency.

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NOTE
messages received by clock A.
messages transmitted by clock B.
● In one-step mode, t1[n] is contained in the Sync message. In two-step mode, t1[n] is
contained in the Follow_Up message.
In practical application, transmission delays and the residence times on a TC clock must be
considered and corrected.
Figure 4-14 Sync message time interval
4.2.5 Alternative BMC Algorithm

ITU-T G.8275.1 defines a new type of best master clock algorithm (BMCA), which
optimizes the algorithms for master-slave clock tracing and clock source tracing
when compared with the BMCA defined in IEEE 1588v2.
BMCA Principles
Compared with the BMCA in IEEE 1588v2, the BMCA in ITU-T G.8275.1 has the
following new attributes:
● notSlave attribute:
– This attribute is added to each port to ensure the tracing relationship in
the ITU-T G.8275.1 synchronization network and to avoid the situation
that a T-GM traces a T-BC.
– In a network with a large number of devices and links, setting of the
notSlave attribute guarantees a tree structure of the master-slave tracing
path from top to down and prevents devices at the aggregation layer
from reversely tracing devices at the access layer.
● localPriority attribute: This attribute refers to the local priority and is used to
plan the device tracing sources. The attribute is used only inside local devices
and will not be forwarded to other devices through packets.

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The localPriority attribute is applicable to the following scenarios:

– In a large-scale network, the entire network traces the same clock source.
In this case, the time error may exceed the permitted range on T-BCs far
from the clock source.
– No manual intervention is involved during the source selection of the
BMCA. In this case, no effective maintenance method can be taken in
case of a network fault.
Setting of the localPriority attribute can effectively resolve the clock source
tracing issue. The working principle is as follows.
Figure 4-15 localPriority principle
The following table lists the parameters to be compared in data sets in sequence.
BMCA Parameter Definition Comparison

Sequence
ClockClass Clock class. This value of a clock 1

is 6 when the clock traces the
GPS system, it is 7 when the clock
is in holdover mode and within
holdover specifications, and it is
52 when the clock is in free-run
mode.
ClockAccuracy Clock accuracy, which refers to 2

the maximum time deviation
within a certain time interval.
OffsetScaledlog Clock jitter, which is obtained 3

Variance based on the theory of Allan
deviation.
Priority2 Clock priority, which is manually 4

defined.
localPriority Local priority, which is manually 5

defined.

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BMCA Parameter Definition Comparison

Sequence
GM Clockid GM clock ID, which uniquely 6

identifies a clock source and is
automatically generated by
devices.
NOTE
● For OSN 9800 service boards (with OTN tributary and line functions), when multiple
clock ports are configured, the BMC algorithm determines which port is used as the
clock source based on the port number. The system algorithm complies with the
following rules:
● For the boards that support IEEE 1588v2/ITU-T G.8275.1/ITU-T G.8273.2 only on
ports 1 to 15, the system preferentially selects the port with a smaller port number
as the clock source.
● For the boards that support IEEE 1588v2/ITU-T G.8275.1/ITU-T G.8273.2 in all ports,
ports 1 to 15 and the ports with a number greater than 15 form two groups. The
system preferentially selects the latter group and then the former group. In each
group, the system preferentially selects the port with a smaller number as the clock
source. For example, if ports 3, 7, 16, and 20 are configured as clock ports, the
priority is port 16 > port 20 > port 3 > port 7.
BMCA Application Example

The following uses an example to illustrate how the BMCA computes the time
tracing topology of the entire network. In this example, T-BC1 is connected to
clock source T-GM1, T-BC3 is connected to clock source T-GM2, and base stations
are connected to the network through T-BC6.
Figure 4-16 BMCA networking

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4.2.6 Delay Compensation

When the product connects to a clock device through its external time port,
transmission delay of the cable connecting to the external time port and PTP link
asymmetry can be corrected.
Compensation for the Transmission Delay of the Cable Connecting to the

External Time Port
Time information is required for transmitting electrical signals. Therefore, 1PPS
+TOD time signals need to be sent to a slave clock device through a cable. There
is a difference between the time when the slave clock device receives the
timescale pulse and the time that the pulse actually represents. Accurate time
synchronization can be achieved by correcting the delay introduced by the cable
connecting to the external time port.
NOTE
The external time port on the product is not a PTP port and does not support the ITU-T G.
8275.1 protocol. The transmission delay cannot be measured automatically. Therefore, the
transmission delay of the cable connecting to the external time port must be measured
using a test instrument or computed based on the cable length.
Compensation for PTP Link Asymmetry

The PTP link asymmetry means that the cables for receiving and transmitting PTP
messages between two devices have different lengths. This causes a variation
between the cable transmission delays in the receive and transmit directions.
The ITU-T G.8275.1 packet delay measurement algorithm is based on the

assumption that the PTP link transmission delays in the receive and transmit
directions are the same. If the receive and transmit cables on the PTP link are
asymmetric, the computed delay will differ from the actual transmission delay.
The asymmetric delay correction mechanism defined in ITU-T G.8275.1 uses the
compensation value of the asymmetric transmission offset to correct the
calculation result, thereby achieving accurate time synchronization.
The delay compensation value for the transmission asymmetry can be obtained
according to the length difference between the cables in the signal receive and
signal transmit directions. Alternatively, the value can be obtained according to
the transmission time of a signal on the cables in the receive and transmit
directions using a test instrument. The compensation value takes effect only after
it is manually set for the PTP ports.
NOTE
The ITU-T G.8275.1 protocol can detect the mean transmission delay of two connected PTP
ports but cannot detect the transmission delay caused by the PTP link asymmetry.
Asymmetric delay must be measured with a test instrument or computed based on the
cable lengths.

WDM OTN
Automatic Calculation and Compensation of Ring Network Delay Offset

Automatic calculation and compensation of ring network delay offset are
applicable to two-fiber bidirectional ring networks.
NOTE
EX4, EG10, and UNQ2
After a PTP time synchronization network is commissioned, the length difference

between the transmit and receive fibers on the line may change greatly and the
asymmetric delay may change due to fiber maintenance (such as fiber cut repair
and fiber route change) in the O&M phase of the network. If the compensation
value cannot be set correctly, the time synchronization function will be affected.
The automatic ring network delay calculation function can be used to
automatically calculate the fiber asymmetry compensation value on time nodes
with protection trails, such as on a ring network, and provide a recommended
compensation value. In addition, automatic compensation within the
compensation range is supported, requiring no manual measurement operations.
The basic principle is as follows:
1. The following takes a west fiber as an example. When a fiber cut occurs, the
clock node switches to the PTP port on the east fiber to implement time
synchronization.
2. After the west fiber is repaired, the clock node re-obtains the PTP packets
from the west port and calculates the offset between the time when the west
PTP port is selected as the time source for time synchronization and the
current node's synchronization time through simulation. In this way, a new
compensation value is obtained.
3. When Ring Network Automatic Compensation is set to Enabled:
4. When Ring Network Automatic Compensation is set to Disabled, no
automatic compensation is performed but the FIB_LEN_CHANGE and

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FIBER_ASYMMETRIC_CHANGED alarms are reported. The alarms will be

The offset compensation value needs to be transmitted to the peer NE through
DCN channels and encrypted using the HMAC_SHA256 algorithm.
Single-Fiber Bidirectional Asymmetric Compensation

wavelengths are different, causing delay asymmetry. In this case, automatic delay
compensation is required to ensure that offset is within the allowed range and
clock precision is not affected.
NOTE
EG10

This topic describes the dependencies and limitations of the ITU-T G.8275.1
feature.

WDM OTN

Automatic ● Only the following boards on the following

compensation upon a products support automatic compensation upon a
fiber cut on a ring fiber cut on a ring network:
network – OSN 1800 V (Z-series system control boards)
V100R009C00 and later versions: UNS4, EX4,
EG10, and UNQ2
board):
board):
● Ring networks do not support TC pass-through.
● This function is supported only when the working
mode of the NE is T-BC. After automatic
compensation upon a fiber cut on a ring network is
enabled, the working mode of the NE cannot be
set to other modes.
● Ring network compensation can be enabled only
after an NE achieves time synchronization (traces
the grandmaster clock). Otherwise, the calculated
● If the working mode of the NE before the upgrade
is T-BC, automatic compensation upon a fiber cut
on a ring network is automatically enabled after
the upgrade.
● Optical modules delivered by Huawei must be
used.
● During fiber restoration, ensure that at least one
channel of clock signal and one channel of time
signal have been traced. Otherwise, the calculated
● During automatic compensation, do not perform a
cold reset on the system control board, cross-
connect board, or clock board, or power off the NE.
Otherwise, automatic compensation cannot work
properly.

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Single-fiber ● Only the following boards on the following

bidirectional products support single-fiber bidirectional
asymmetric asymmetric compensation:
compensation – OSN 1800 V (Z-series system control boards)
V100R009C00 and later versions: EX4 and EG10
board): EX10
board): EX10
● The equipment supports only the single-span
single-wavelength scenarios.
Function dependencies ● In scenarios where automatic compensation upon

a fiber cut and single-fiber bidirectional
asymmetrical compensation are enabled
concurrently on the same port:
– For single-fiber bidirectional optical modules,
only single-fiber bidirectional asymmetric
compensation takes effect.
– For two-fiber bidirectional optical modules,
automatic compensation takes effect only upon
a fiber cut on the ring network.
● Static BMC source selection and automatic
compensation upon a fiber cut on a ring network
are mutually exclusive and therefore cannot be
enabled concurrently.
Primary reference clock ● Networks at the aggregation layer should be

(PRC) configured with clock protection and be set with
the primary and secondary PRCs for active/standby
switching of clocks.
● For networks at the access layer, only one PRC is
set on the central NE in most cases, and other NEs
trace the clock of the central NE.
● If the BITS or other external clock equipment with
high precision exists, use the external timing mode
for the NE. Otherwise, use the line timing mode
instead. You are advised to use the internal timing
as a clock source of the lowest level.

WDM OTN
Methods for obtaining ● If there are multiple NEs at a core site of a

frequency and phase WDM/OTN network, the frequency/phase
information information can be obtained in either of the
following ways:
– If physical OSC or ESC connections are
established between the NEs, the OSC or ESC
channels can be used to transmit ITU-T G.8275.1
frequency and phase information between the
NEs.
– ESC two-fiber bidirectional phase
synchronization is easily affected by factors such
as protection switching and board delay
difference. If the east-west delay offset is too
large, phase indicators change and deteriorate.
As a result, frequent network switching occurs
and maintenance cannot be performed.
– If the NEs are deployed in the same
telecommunication room and the intervals
between them are less than 200 m, the external
2M clock ports or 1PPS+TOD time ports on the
NEs can be used to transmit the frequency and
phase information between them.
TN55TTX When the mapping path of the TN55TTX board is

10GE LAN->ODUflex, ITU-T G.8275.1 is not supported.
TN16AUX For the OSN 8800 T16, two TN16AUX boards must be
configured when ITU-T G.8275.1 is required.
Service board ● When ITU-T G.8275.1 signals are transmitted

between OTN devices, line boards or OSC boards
are recommended. When an OTN device is
interconnected with a third-party device to
transmit ITU-T G.8275.1 signals, tributary boards
are recommended.
● Before configuring the clock function, ensure that
● For OTN line ports, G.8275.1 time synchronization
can be used only when lower-order ODUk cross-
services, G.8275.1 time synchronization can be
used only after services are configured for the
ports.
● When the ITU-T G.8275.1 feature is configured on
a tributary board, ITU-T G.8275.1 packets occupy
the port bandwidth. When the port is fully loaded
with traffic, packets may be lost.

WDM OTN
Clock board When the clock synchronization function is required

up each other.
ST2/AST2 ● The ST2 board must be installed in a subrack with

a clock board if the clock function is required.
follows:
board in a cabinet.
the network cable.
● When no clock board is available, an ST2 board
supports ITU-T G.8275.1 signal pass-through at an
OLA site.
● When an ST2 board is configured in an OSN 8800
platform subrack, only physical clock pass-through
and ITU-T G.8275.1 clock pass-through are
supported. The processing of physical-layer clocks
and ITU-T G.8275.1 clocks is not supported.
● When configured in a universal platform subrack,
the ST2 board supports physical-layer clock
processing and ITU-T G.8275.1 clock processing.
2-9.

WDM OTN
ANNOUNCE Packet When the TN54TOA/TN54THA board is

Period(s) interconnected with a PTN device to transmit ITU-T G.
8275.1 clock signals, ANNOUNCE Packet Period(s)
must be set to 64/1028. Otherwise, after a link fault
occurs, the interconnected PTN device may fail to
trace the clock source.
Loopback When the ITU-T G.8275.1 function is configured on a

board port, if loopback commissioning is performed
on the port or the interconnected port, the clock
tracing source of the NE where the port is located
needs to be switched to the protection clock source so
that the clock function is not affected during port
loopback.
NE and port working ● When NE Clock Type of an NE is set to T-BC, NE

modes Clock Type of the port must be set to T-BC.
● The devices whose NE Clock Type is set to T-BC
can belong only to one clock subnet and the clock
sources must be selected from the clock subnet
Interface protocol type ● When an NE works in 1PPS+Time mode, a warm

board switchover and then perform a warm reset
on the standby clock board.
● When an NE works in 1PPS+Time mode, a cold
board switchover and then perform a cold reset on
the standby clock board.
NOTE
The active/standby clock board switchover is not required
before a warm reset on the TN13STG, TN54STG, or TNK3STG
board.

WDM OTN
Frequency source mode ● After PTP Synchronization is enabled for an NE,

the NE automatically switches the frequency
source mode to Physical Synchronization when
Enabled Status of the external clock port on the
NE's clock board changes from Enabled to
Disabled or changes from Unused to Disabled.
Therefore, you need to manually set the frequency
source mode of the NE to PTP Synchronization.
● When the frequency source mode of an NE is set
to PTP Synchronization, you can change the
priority of physical-layer synchronization or SSM
information, but the setting does not take effect.
The settings take effect only when the frequency
source mode of the NE is set to Physical
Synchronization.
● When the external time port of an NE is set to
1PPS+Time input, the frequency source mode of
the NE cannot be set to PTP Synchronization.
Configuring PTP packet ● If the PTP frequency synchronization scheme is

attributes used, to ensure clock synchronization performance,
it is recommended that 128 or more SYNC packets
be sent per second, that is, the SYNC packet period
be lower than or equal to (8/1024)s.
● If the physical-layer synchronization solution is
used, the SYNC packet period can be kept at
(64/1024)s.
Setting clock ● If Time Adjusting is set to Disabled, the time

synchronization synchronization function will be unavailable. When
attributes only PTP frequency synchronization is required and
time synchronization is not, Time Adjusting can be
set to Disabled. By default, it is set to Enabled and
the default setting does not need to be changed in
most cases.
● The PTP System Time field can be set only when
the NE traces local clock sources.

WDM OTN
Setting the ● The Warp Length(m) field is available only when

transmission distance Warp Mode is set to Length.
of an external cable ● The Warp Time(ns) field is available only when
● The Transmitting Length(m) field is available only
when Transmitting Distance Mode is set to
Length.
● The Transmitting Time(ns) field is available only
when Transmitting Distance Mode is set to Time.
● The values of Warp Length(m) and Warp
Time(ns) are set depending on the networking
scheme for the site.
● When Enabled Status of a port is set to Enabled,
Transmitting Direction can be set only to Ingress.
When Enabled Status of a port is set to Disabled,
Transmitting Direction can be set to Ingress and
Egress.
Board interconnection In board interconnection scenarios, the MAC

addresses of the local and peer boards can only be set
to 01-1B-19-00-00-00. This limitation applies to the
following boards:
● OSN 8800: TN55TQX, TN54THA, TN54TOA,
TN55TOX, and TN55TSC
● OSN 6800: TN55TQX
● OSN 9800: TNV3T230, TNV3T220, TNV3T210,
TNV3T404, G404, G402, TNV3T402, TNV3T401,
A212, T212, T206, TNV5T404, T401, M402, M210D
● OSN 1800: TOA, TQX, TNF2LDX, ELOM (STND),
TTA, LDCA, B1LDCD, B1LDC
Locked mode For a PTP port on the TNZ8EX4, TNF5TOA/TNF6TOA,

TNF5TQX, TNF6TTA/TNF7TTA, TNF2ELOM/
TNF3ELOM, TNF2LDX/TNF3LDX, or TNF1LDCA board,
the destination MAC address cannot be set to a non-
forwardable address (01-80-C2-00-00-0E), and cannot
be interconnected with a port whose destination MAC
address is a non-forwardable address (01-80-
C2-00-00-0E). Otherwise, PTP clocks cannot be traced
and the downstream PTP clocks may be affected. As a
result, PTP clock tracing is abnormal.

WDM OTN
CFP optical module For the boards that use CFP optical modules,
compensation for the asymmetrical transmission
delay is required after the boards are powered on or
undergo cold resets, the optical modules are replaced,
or the line code pattern is switched; otherwise, a time
deviation of about 100 ns may be generated.
FlexE port When FlexE ports are used to implement clock

synchronization (frequency synchronization) or time
synchronization, the clock synchronization or time
synchronization function of the corresponding ports
must be enabled on OTN devices to meet the
requirements of the PTP protocol. Otherwise, the
synchronization performance of downstream devices
cannot be ensured.
synchronization, you need to correctly set the fiber
type, fiber length, and fiber dispersion coefficient on
the WDM Interface > Advanced Attributes page of
the NMS.

WDM OTN

Intra-board 1+1 If both ITU-T G.8275.1 and intra-board 1+1 protection

protection or optical or optical line protection are configured, ITU-T G.
line protection 8275.1 time synchronization can be implemented only
in single-fiber bidirectional mode (ST2+SFIU). If ITU-T
G.8275.1 time synchronization is implemented in two-
fiber bidirectional mode (ESC or OSC), fiber
asymmetry will occur after protection switching on
the related boards such as OLP, DCP, and OTU,
affecting the time synchronization precision.
Loopback When the ITU-T G.8275.1 function is configured on a

board port, if loopback commissioning is performed
on the port or the interconnected port, the clock
tracing source of the NE where the port is located
needs to be switched to the protection clock source so
that the clock function is not affected during port
loopback.

WDM OTN
Fiber Doctor system When the ITU-T G.8275.1/G.8273.2 feature works with
the Fiber Doctor system, service running and the IEEE
1588v2/G.8275.1 time synchronization may be
affected. For details, see the feature dependencies and
limitations of the Fiber Doctor system.
If the single-fiber bidirectional OSC board is used to
implement PTP time synchronization and intelligent
fiber management at the same time, pay attention to
the following points when using the Fiber Doctor
system:
● If the OSC_CLK_MISMATCH alarm is found on the
live network, online fiber detection using Default
Mode or Online mode in Advanced Mode is not
allowed.
● If no OSC_CLK_MISMATCH alarm is found on the
live network but more than four OLA sites are
deployed in an OMS, clock boards that meet
requirements need to be configured at the next
OLA site behind every four OLA sites. Otherwise,
online fiber detection using Default Mode or
Online mode in Advanced Mode is not allowed
because PTP time synchronization is affected in
this scenario.
● If online monitoring has been started for an OTS of
an OMS but the monitoring is not completed,
online monitoring cannot be started for other OTSs
on the OMS; otherwise, PTP time synchronization is
affected.
● If PTP time synchronization is also enabled, ensure
that online monitoring is started for no more than
14 OTSs on the entire network; otherwise, PTP
time synchronization is affected.

Client 1+1 protection Client 1+1 protection and ITU-T G.8275.1 are mutually
exclusive. If both are configured, ITU-T G.8275.1 will
become abnormal.
ASON When SFIU boards (including DAPXF boards that

function as SFIU boards) are used to configure or
reserve the ITU-T G.8275.1 function, optical-layer
ASON is not supported.

WDM OTN
Latency measurement When overhead bytes (2 rows, 3 columns) used for

(OTN) latency measurement are the same as the ITU-T G.
8275.1 overhead bytes of the OTN interface (2 rows, 3
columns), and these overhead bytes transmit ITU-T G.
8275.1 protocol packets concurrently, the ITU-T G.
8275.1 transmission will be interrupted during the
measurement, adversely affecting services. Therefore,
ITU-T G.8275.1 and delay measurement cannot be
enabled at the same time in this scenario.
NOTE
The UNS4 and UNQ2 boards of the OSN 1800 V support the
setting of the ITU-T G.8275.1 overhead bytes to a 1 x 13
structure (1 row, 13 columns). This avoids an overhead
conflict between ITU-T G.8275.1 and latency measurement.
Therefore, ITU-T G.8275.1 and latency measurement can be
enabled at the same time for the boards.
4.4 Availability
This topic describes the board types and software versions that support ITU-T G.
8275.1/G.8273.2.

The IEEE 1588v2/ITU-T G.8275.1 feature can be used only when the corresponding
license is obtained on the NMS .
Table 4-9 License function and application description

Function Application
The IEEE 1588v2/ITU-T G.8275.1 Before configuring the IEEE 1588v2/

feature can be used only when the ITU-T G.8275.1 feature for an NE, you
corresponding license is obtained. must enable the feature. One license is
required for enabling this feature on
each NE.

Version Support
This section describes the board types and software versions that support ITU-T G.
8275.1 in the OSN 9800 universal platform subrack.

WDM OTN
Table 4-10 Boards and device versions that support ITU-T G.8275.1 in the OSN
9800 universal platform subrack (optical-layer configuration)
TN13STG V100R003C10
OSC board TN13ST2 V100R003C10
TN12ST2 V100R006C10
TN51AST2, TN11AST2 V100R007C00SPC70

0

multiplexer and
NOTE
Time synchronization can be implemented only when a clock board is configured for a
subrack.

8275.1 in OSN 9800 P series subrack.
NOTE
Table 4-11 Boards and device versions that support ITU-T G.8275.1 in OSN 9800 P
series subracks (optical-layer configuration)

board

board
Optical line TMP1ON32, TMP1ON32P V100R007C00

board

WDM OTN
TMP2ON20HHP, TMP2ON20PHHP, V100R021C10

TMP2ON32HHP, TMP2ON32PHHP,
TMP3ON20HHP, TMP3ON20PHHP

TMP2ON32HEHP, TMP2ON32PHEHP
NOTE
HP: indicates that the board supports high-precision clock synchronization. Only products in
V100R021C10SPC300 (with NCE V100R021C10SPC200) and later versions support high-

8275.1/G.8273.2 in OSN 9800 U series subracks.
NOTE
synchronization.
Table 4-12 Boards and device versions that support ITU-T G.8275.1/G.8273.2Note in
OSN 9800 U series subracks (electrical-layer configuration)
Clock board TNU1CTUNote, TNS1CTUNote V100R003C10
TNU2CTUNote, TNU4CTUHP V100R007C00
TNU5CTUHP V100R019C10

board
Tributary board G402, G404, TNV3T404, TNV3T210, V100R003C10

TNV3T220, TNV3T230, T220E
TNV3T401, TNV3T402 V100R005C00

TNV3G220, TNV6T220, TNV7T402

TNV8T402, TNV7T220, TNV1T410

WDM OTN

TNV6G216a, HP, TNV2E224, TNV2E402,
TNV3E224HP, TNV3E402HP,
TNV3E404HP
TNV6T216b, HP, TNV6T230b, HP, V100R021C00

TNV6G230b, HP, TNV7S216b, HP (OTN
tributary)
TNV4E404HP, TNV4E224HP V100R022C00
Line board TNU4U401, U402 V100R005C00

TNU5U501, TNU6U402, TNU5NP200/
TNU5NP400E

TNU6U402C
TNU6U502 V100R020C10
TNU7U402, TNU6U316 V100R021C00


WDM OTN

NOTICE
Note: When TNU1CTU/TNS1CTU/TNU2CTU is used, only ITU-T G.8275.1 is supported, and
ITU-T G.8273.2 is not supported. ITU-T G.8273.2 is supported only when TNU4CTU/
TNU5CTU is used.
● HP: indicates that the board supports high-precision clock synchronization.
Only products in V100R021C10SPC300 (with NCE V100R021C10SPC200) and
later versions support high-precision clock synchronization. XFIU units do not
affect synchronization precision.
● You are advised to use OSC boards to implement PTP time synchronization
between sites. The single-fiber bidirectional OSC mode supports
commissioning-free and delay compensation-free functions. However, when
line boards are used to configure PTP time synchronization, compensation for
asymmetric delay is required, the construction cost is high, and the
maintainability is poor. Therefore, this mode is not recommended.
● For OTN line ports, G.8275.1 time synchronization can be used only when
lower-order ODUk cross-connections are configured for the ports.
● For the tributary ports that receive Ethernet services, G.8275.1 time
synchronization can be used only after services are configured for the ports.
● TNV3T230/TNV3T220/TNV6T220/TNV6T216/TNV6T230/TNV6G230/
TNU6U316/TNV7U220: Only ports 1 to 15 support ITU-T G.8275.1.
● When an electrical module is installed in a port, the port does not support
ITU-T G.8275.1.
● When working in relay mode, boards do not support ITU-T G.8275.1.
● The boards working together with the TNU2CTU and TNS2CTU system
control boards support ITU-T G.8275.1 since V100R007C00.
● When TNS5NP400/TNS5NP400E is interconnected with TNU5NP400/
● When TNS5N401P/TNS5N401PE is interconnected with TNU5NP400/

WDM OTN
ports that support ITU-T G.8275.1 vary according to the encapsulation type. The
Table 4-13 Support for ITU-T G.8275.1 in different port service mapping paths

Mode (T- on
BC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (inverse
multiplexing)

multiplexing)

mapping (GFP-F)


mapping (GFP-F)
NOTE
When the port working mode is ODUflex non-convergence mode (Any->ODUflex), the T-BC
mode and PTP ETH encapsulation are supported.

WDM OTN

8275.1/G.8273.2 in OSN 9800 M series subracks.
NOTE
Table 4-14 Boards and device versions that support ITU-T G.8275.1/G.8273.2
TMF1AUXa, TNG3CXPHP V100R007C00
TME3CTU, TMF3AUX01HP V100R020C10
TNG4CXPHP V100R021C00

board
TMF1AUXa, HP V100R007C00
TNG3OH20HHP (OSC unit) V100R020C10
TNG2AST4HP, TNG3OH20 (OSC unit) V100R021C00
TNG2AST4EHP, TNG2OH20 (OSC unit), V100R021C10

TNG2OH20HHP (OSC unit)
TNG2OH9HP, b (OSC unit) V100R022C00

OTU board M402 V100R006C00

TNG1M502DM

WDM OTN
TNG1M504DM, TNG1M520SMHP, V100R019C10

TNG1M404DM, TNG2M604SM
TNG1M520SHP, TNG3M402D, V100R021C10

TNG3M504D

TNS5NP400Y

T210, T220, T230

TNV3G220, TNV3T404, TNV3T401,
TNU1G404, TNV6T220, TNV7T402

TNV8T402, TNV7T220, TNV1T410,
TNG2A212 (tributary mode)

TNV3E404HP, TNV6G216HP, TNV2E224,
TNV3E224HP, TNV2E402, TNV3E402HP
TNV6T216HP, TNV6T230HP, V100R021C00

TNV6G230HP, TNG3A204HP (OTN
tributary)

mode), TNV4E404HP, TNV4E224HP
TNG1T210E V100R022C10
Line board TNU5NP200/TNU5NP200E, V100R006C00

TNU5NP400/TNU5NP400E, U402

TNU5U501, TNU6U402

TNU6U402C
TNU6U502 V100R020C10
TNU7U402, TNU6U316 V100R021C00

WDM OTN

NOTE
precision.
● For OTN line ports, G.8275.1 time synchronization can be used only when lower-order
● For the tributary ports that receive Ethernet services, G.8275.1 time synchronization can
be used only after services are configured for the ports.
● TNV1T210: Only ports 1 to 4 support ITU-T G.8275.1.
● TNV3T230/TNV3T220/TNV6T220/TNV6T216/TNV6T230/TNV6G230/TNU6U316/
TNV7U220: Only ports 1 to 15 support ITU-T G.8275.1.
● A port equipped with an electrical module does not support ITU-T G.8275.1.
V100R006C10).
function.
● b: The TNG2OH9 board supports high-precision clock only when it uses the BIDI OSC
module.
10GE channel of the 4 x 10GE services supports IEEE 1588v2.
● When TNS5NP400/TNS5NP400E is interconnected with TNU5NP400/TNU5NP400E or
supported.
● When TNS5N401P/TNS5N401PE is interconnected with TNU5NP400/TNU5NP400E or
supported.

Mode (T- on
BC)

WDM OTN

Mode (T- on
BC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (inverse
multiplexing)

multiplexing)

mapping (GFP-F)


mapping (GFP-F)
NOTE

8275.1 in OSN 8800 subracks.

WDM OTN
ITU-T G.8275.1
Table 4-16 Boards and device versions that support ITU-T G.8275.1 in OSN 8800
subracks
Clock board TN16XCH, TN16UXCM, TN16SCC, V100R011C00

TN52STG, TN54STG, TN12STG,
TN13STG, TNK2STG, TNK3STG
Clock interface TN16ATE, TN52STI V100R011C00

board
TN12ST2 V100R013C00
TN11AST2 V100R013C10

multiplexer and
board
Tributary board TN55TQX, TN54THA, TN54TOA, V100R011C00

TN55TOX
TN55TSC V100R012C00
TN55TTX V100R012C10
Line board TN53NQ2 V100R011C00

NOTE
subrack.

WDM OTN
Mode (T- on
BC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (inverse
multiplexing)

multiplexing)

mapping (GFP-F)


mapping (GFP-F)
NOTE
NOTE
Line boards support only T-BC.

WDM OTN
ITU-T G.8273.2
subracks
Clock board TN54STG, TN16UXCM V100R011C00
Clock interface TN16ATE, TN52STI V100R011C00

board
OSC board TN11ST2, TN12ST2, TN13ST2, V100R011C00

TN11AST2

multiplexer and
board
Tributary board TN55TQX, TN54THA, TN54TOA, V100R011C00

TN55TOX, TN56TOX

8275.1 in OSN 6800 subracks.
subracks

board
Clock board TN11STG, TN12STG, TN13STG V100R011C00

multiplexer and
board
Tributary board TN55TQX V100R011C00

WDM OTN

NOTE
subrack.
configured.
Table 4-20 describes the working modes of ITU-T G.8275.1 ports on each tributary
board intended for OSN 6800.
Table 4-20 Working modes of ITU-T G.8275.1 ports on each tributary board
Board Service Type Port Mapping Clock PTP

Type (T- Packet
BC) Encapsul
ation
Format
TN55TQX 10GE LAN MAC transparent Supported PTP ETH

mapping (10.7G) encapsul
ation
supporte
d

8275.1/G.8273.2 in OSN 1800 V subracks.
Table 4-21 Boards and device versions that support ITU-T G.8275.1/G.8273.2 in
OSN 1800 V subracks
Clock board TNF5UXCM (F5STG), TNF5XCH V100R006C20

(F5STG), TNF5UXCME (F5STG),
TNZ5UXCMS (Z5STG)a

WDM OTN

board
TMB1AUX V100R020C10
TMB2AUX V100R021C10


unit)

multiplexer and



unit)
OTN tributary TOA, TQX, TTA V100R006C20

board

(client side)
LDCA V100R008C10

B1LDCD, B1LDC

WDM OTN
Line board UNS4, Z5UNQ2 V100R009C00
TNZ8UNS4 V100R021C00

(line side)
Packet board EM20b (G.8273.2 not supported) V100R006C20
EX4, EG10 V100R008C10
NOTE
For the ITU G.8275.1 feature:
● When an electrical module is inserted into a board port, ITU-T G.8275.1 is not
supported.
● When the EM20 board works with the Z5UXCMS system control board, ITU-T G.8275.1
is supported since V100R020C10.
● When the service cross-connections on the line board are switched, ITU-T G.8275.1 clock
● a: OSN 1800 V: When the system control board is UXCMS, the tributary board supports
the ITU-T G.8273.2 synchronization since the OSN 1800 V of V100R008C10.
● b: EM20 boards do not support G.8273.2.
● When working in relay mode, line boards do not support ITU-T G.8273.2.
When Ethernet services are received by an OTN board, the working mode of the
port supporting ITU-T G.8275.1 varies according to the encapsulation type. The

WDM OTN
Mode (T- on
BC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (GFP-F)

NOTE
NOTE
● When receiving OTU1 services, the TOA board supports only T-BC but does not support PTP
ETH encapsulation.
● When receiving OTU2/OTU2e services, the TQX board supports only T-BC but does not
support PTP ETH encapsulation.
● When receiving GE or 10GE LAN services, the EM20, EX4 and EG10 boards support only the
T-BC mode and support PTP ETH encapsulation.
● ST2 and AST4 boards support the T-BC mode but do not support PTP ETH encapsulation.

8275.1/G.8273.2 in OSN 1800 II Enhanced subracks.

WDM OTN
OSN 1800 II Enhanced subracks

board
TMB1AUX V100R020C10
TMB2AUX V100R021C10


unit)

multiplexer and


unit)

board

(client side)
F1LDCA V100R008C10

B1LDC
TMB2LDC V100R021C10

WDM OTN
Line board Z8UNQ2, Z8UTX2 V100R019C10

(line side)
Packet board EX4, EG10, UXCL (EX1) V100R008C10
NOTE
supported.
● The Z1UXCL board supports ITU G.8275.1 since V100R007C10, and supports ITU-T G.
8273.2 since V100R008C10.
Mode (T- on
BC)

supported supported

WDM OTN

Mode (T- on
BC)

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (GFP-F)

NOTE
NOTE
ST2 and AST4 boards support the T-BC mode but do not support PTP ETH encapsulation.

8275.1/G.8273.2 in OSN 1800 I&II Compact subracks.
OSN 1800 I&II Compact subracks
Clock board TNF3SCC (F3STG)a V100R006C20

WDM OTN

multiplexer and

(client side)
F1LDCA V100R008C10

B1LDC

(line side)
NOTE
supported.
● a: ITU-T G.8273.2 is supported only when TNF3SCC03/TNF3SCC04 is used.
Mode (T- on
BC)

WDM OTN

Mode (T- on
BC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (GFP-F)

NOTE
NOTE
ST2 and AST4 boards support the T-BC mode but do not support PTP ETH encapsulation.

8275.1/G.8273.2 in OSN 1800 V Pro subracks.
NOTE
Clock board TMK5SXCH (K5STG)HP V100R019C10

WDM OTN
TMK5XCH (K5STG)HP, TMK5UXCME V100R021C00

(K5STG)HP
TMK6UXCM (K6STG)HP, TMK5GSCC V100R021C10

(K5STG)HP
TMK6XCH (K5STG)HP V100R022C10
Clock TMB1AUXHP V100R020C10

interface

TMB2AST2

unit)

(OSC unit)

multiplexer
board


unit)


TMK1MDCAHP

WDM OTN

TMK2MDCAHP

TMB1LTXMPHP

(line mode)

NOTE
precision.
supported.

WDM OTN
Mode (T- on
BC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (GFP-F)

NOTE

8275.1/G.8273.2 in OSN 1800 II Pro subracks.
NOTE

WDM OTN
Clock board TMK2UXCL (K2STG)HP V100R019C10
TMK2UXCLE (K2STG)HP V100R019C10
Clock TNF1AUX V100R019C10

interface

TMB2AST2

unit)

(OSC unit)

multiplexer
board


unit)


TMK1MDCA

WDM OTN

TMK2MDCAHP

TMB1LTXMPHP

(line mode)

NOTE
precision.
supported.

WDM OTN
Mode (T- on
BC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (GFP-F)

NOTE

8275.1/G.8273.2 in OSN 1800 II TP subracks.
NOTE

WDM OTN
Clock board TMB1SCC (B1STG)HP V100R009C00
TMT1SCC (T1STG)HP V100R021C00
Clock interface TMB1AUXHP V100R020C10

board

unit)

(OSC unit)

multiplexer and



unit)

(client side)
TMB1LTXHP, TMB1LDCAHP, TMB1LDCD,
TMB1LDC, TMK1MDCAHP
TMB2LTX, TMB2LDCAHP, V100R021C00

TMK2MDCAHP

WDM OTN

TMB1LTXMPHP

(WDM side) TMB1LDCA, TMK1MDCA
NOTE
precision.
supported.
Mode (T- on
BC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

WDM OTN

Mode (T- on
BC)

(100G)

mapping (GFP-F)

NOTE

8275.1/G.8273.2 in OSN 1800 I Compact subracks.
OSN 1800 I Compact subracks

(client side) TNF3ELOM, TNF3LDX
OTU board TMB2ELOM, TMB2LDX, TMB2LTX V100R022C10

(line side)
NOTE
supported.

WDM OTN

Mode (T- on
BC)

supported supported

mapping (10.7G)


mapping ODU4
(100G)

(100G)

mapping (GFP-F)

NOTE
4.5 Specifications
This section describes the specifications of ITU-T G.8275.1 and ITU-T G.8273.2.
NOTE
Only specific products and boards support high-precision clock synchronization. For details,
see 5 High-Precision Clock Synchronization Solution.
Table 4-35 ITU-T G.8275.1 specifications
Item Specifications
Synchronization SyncE frequency synchronization, ITU-T G.8275.1/G.

scheme 8273.2 frequency synchronization, and ITU-T G.
8275.1/G.8273.2 phase synchronization

WDM OTN
Item Specifications
Device model T-BC, T-TC

NOTE
Only the following models running V100R020C10 and later
versions support the T-TC mode.
● 1800 II Pro
● 1800 V Pro
PTP port type ● Dedicated PTP Synchronization Port: GE optical port

● OSC port
● OTN tributary ports (OTN tributary boards and OTU
boards): GE, 10GE, 25GE, 50GE, 100GE, 200GE, and
400GE optical ports, and FlexE ports
● Ports on packet boards: GE, 10GE, and 100GE optical
ports
NOTE
SFP electrical modules do not support IEEE 1588v2.
Only FlexE ports (100G/200G) on the TNG1M804SM/
TNV1T502 board support ITU-T G.8275.1 and ITU-T G.8273.2
since V100R020C10.
Packet encapsulation PTP ETH, without packet VLAN IDs

NOTE
OTN line ports and OSC ports transmit PTP packets through
overhead bytes, and neither encapsulation format nor VLAN
ID is involved.
Delay mechanism E2E
BMC protocol Automatic/Manual
Local priority Supported and manually configurable
Not-Slave Supported and manually configurable

WDM OTN
Item Specifications
Delay compensation ● Automatic compensation upon a fiber cut on a ring

type network
● Single-fiber bidirectional asymmetric compensation
NOTE
Only the following boards on the following products support
automatic compensation of ring network delay offset. For
details about the restrictions, see 3.3.1 Feature Limitations.
● OSN 1800 V (Z-series system control boards)
V100R009C00 and later versions: UNS4, EX4, EG10, and
UNQ2
● V100R021C10 and later versions: UNS5, UNS4, GTA,
UNQ2, UND3 and EX10
● V100R021C10 and later versions: UNS5, UNS4, GTA,
UNQ2, UND3 and EX10
External time port 1PPS+ToD external time ports supported. For details,
see 4.2.2 Time Source Port.

WDM OTN
Item Specifications
Clock cascading ● OSN 9800:

between master and – Universal platform subrack: The universal
slave subracks platform subracks on the same NE implement
frequency/phase synchronization through clock
In versions earlier than V100R007C00, electrical
subracks on the same NE do not support clock
Therefore, only one electrical subrack on each NE
supports frequency/phase synchronization. You
are advised to configure all boards requiring
frequency and phase synchronization in the same
subrack.
In V100R007C00 and later versions, when the
system control board is TNU2CTU or TNS2CTU,
electrical subracks on the same NE support clock
When the system control board is TNU4CTU or
TNU5CTU, electrical subracks on the same NE
slave subracks.
– M series subracks: Clock cascading between
– P series subracks: Clock cascading between
– Clock cascading between master and slave
subracks cannot be implemented between
universal platform subracks and U/M series
subracks.
● OSN 1800:
– Subracks that use the TMB1AUX board support
subracks since V100R020C10. The ports
optical ports.
– Subracks that use the TMB2AUX/MD48AFS board
slave subracks since V100R021C10. The ports
optical ports. The ports supported by the
MD48AFS board are clock synchronization GE
optical ports.
– Subracks that use the TMK5SXCH/TMK5UXCME/
TMK5XCH/TMK5GSCC board support clock

WDM OTN
Item Specifications
cascading between master and slave subracks

since V100R022C00. The ports supported by the
board are clock synchronization GE optical ports.
– Subracks that use the TMK6XCH board support
subracks since V100R022C10. The ports
supported by the board are clock synchronization
GE optical ports.
● OSN 8800/6800: Clock cascading between master
and slave subracks is supported.
NOTE
Clock cascading between master and slave subracks is
supported only when subracks are configured in master/slave
mode. For details about the specifications and capabilities of
the master and slave subracks, see
● For carriers: WDM OTN Master-Slave Subrack
Management Guide
● For enterprises: WDM OTN Master-Slave Subrack
Management Guide
When the OSN 9800/OSN 8800/OSN 6800 subracks that
support master-slave subrack clock cascading implement the
clock cascading function, two clock boards need to be
configured for each subrack. The master clock subrack can be
configured in the slave service subrack. Master and slave
service subracks can be separated from master and slave clock
subracks.
Item Specifications
Class (Class A corresponds to a Class A Class B

network containing 12 NEs and class B
corresponds to a network containing
22 NEs.)
Absolute time offset (Max|TE|) 100 ns 70 ns
Fixed time offset (cTE) 50 ns 20 ns
Low-frequency MTIE 40 ns 40 ns
jitter time offset
(dTEL) TDEV 4 ns 4 ns
High-frequency jitter time offset 70 ns 70 ns

(dTEH)
Noise transfer PTP-to-PTP It is a low-pass feature. The low-pass

stop frequency ranges from 0.05 Hz to
0.1 Hz, and the passband gain is less
than 0.1 dB.

WDM OTN
Item Specifications
SyncE-to-PTP It is a band-pass feature. The low-pass

stop frequency ranges from 0.05 Hz to
0.1 Hz, the high-pass stop frequency
ranges from 1 Hz to 10 Hz, and the
passband gain is less than 0.2 dB.
NOTE
Only specific products and boards support high-precision clock synchronization. For details,
see 5 High-Precision Clock Synchronization Solution.
NOTE
For details about the device types and boards that support ITU-T G.8273.2, see 4.4
Availability.
4.6 Feature Updates

This topic describes the ITU-T G.8275.1/G.8273.2 feature updates in the product
versions, the reasons for the updates, and the corresponding information updates.
Any product versions that are not listed in the document means that they have no
feature updates.
NOTE

The ITU-T G.8275.1 feature is available since OSN 9800 U V100R003C10. The ITU-T
G.8275.1/G.8273.2 feature is available since OSN 9800 M V100R006C00.

OSN 9800 U/M/P series The product function is 4.4.3 OSN 9800 P Series
subracks (with NCE enhanced. Hardware and Version
V100R021C10SPC200 Support
and later versions) newly 4.4.4 OSN 9800 U Series
support high-precision Hardware and Version
clock synchronization. Support
4.4.5 OSN 9800 M
Series Hardware and
Version Support
Synchronization
Solution

WDM OTN

cascading mode.


packets.


supported.

Update the Change
The OptiX Added a new 4.4.5 OSN 9800 M Series Hardware and
OSN 9800 subrack to Version Support:
M05 subrack support basic Added OptiX OSN 9800 M05 subrack-related
(system functions. information.
control board:
TME1CTU/
TME2CTU) is
added to
support ITU-T
G.8275.1/G.
8273.2.

WDM OTN

Update the Change
series subrack
is added to
support ITU-T
G.8275.1/G.
8273.2.
OSN 9800 enhanced.
M24 subrack
is added to
support ITU-T
G.8275.1/G.
8273.2.

Update the Change
support ITU-T
G.8275.1/G.
8273.2.
series is ● 4.8.1 Configuring ITU-T G.8275.1 (OSN
added to 1800/8800/9800Universal Platform
support ITU-T Subrack/M Series/P Series/(U Series:
G.8275.1. U2CTU/S2CTU/U4CTU/U5CTU)): Added
the TNU4CTU board.
OSN 9800 enhanced.
M24 subrack
is added to
support ITU-T
G.8275.1/G.
8273.2.

WDM OTN

Feature Update Reason for Information Update
the Change
The OSN 9800 P The product 4.4.3 OSN 9800 P Series Hardware and
subrack is function is Version Support:
added to enhanced. Added the description of the OSN 9800 P
support ITU-T G. series subrack.
8275.1.
OSN 9800 U ● 4.8.1 Configuring ITU-T G.8275.1 (OSN
series are added 1800/8800/9800Universal Platform
to support ITU-T Subrack/M Series/P Series/(U Series:
G.8275.1. U2CTU/S2CTU/U4CTU/U5CTU)): Added
TNU2CTU and TNS2CTU.
When equipped The product 4.5 Specifications:

with the function is Added the description that the OSN 9800 U
TNU2CTU or enhanced. series subrack supports master/slave clock
TNS2CTU board, subrack cascading.
the OSN 9800 U
series subrack
supports
master/slave
clock subrack
cascading.

The TN12ST2 board The function is enhanced. 4.4.2 OSN 9800

supports ITU-T G.8275.1. Universal Platform
Subrack Hardware and
Version Support:
Added the TN12ST2
board.

WDM OTN

The OSN 9800 M series ITU-T G.8275.1 and ITU-T Added 4.4.5 OSN 9800
subrack supports ITU-T G.8273.2 are carrier-level M Series Hardware and
G.8275.1/G.8273.2. PTP synchronization Version Support.
standards defined by
ITU-T.
Feature Updates in V100R003C10SPC100

OSN 9800 U series ITU-T G.8275.1 is a The entire chapter is

subrack: The feature is carrier-level PTP added.
available since this synchronization standard
version. defined by ITU-T.

ITU-T G.8275.1 and ITU-T G.8273.2 have been supported since OSN 8800/6800
V100R011C00.

The TN12ST2 board The product function is 4.4.6 OSN 8800

supports ITU-T G.8275.1. enhanced. Hardware and Version
Support:
The TN12ST2 board is
added.
Updates of V100R011C00
The feature is available ITU-T G.8275.1 and ITU-T ● OSN 8800 and OSN
since this version. G.8273.2 are carrier-level 6800: The ITU-T G.
Precision Time Protocol 8275.1 feature is
(PTP) synchronization added.
standards defined by ● OSN 8800 T32 and
ITU-T. T16: The ITU-T G.
8273.2 feature is
added.

WDM OTN

This section describes the start version and change history of ITU-T G.8275.1 and
ITU-T G.8273.2.

ITU-T G.8275.1 ● 1800 V V100R006C20

● 1800 II TP V100R009C00
● 1800 V Pro V100R019C10
● 1800 II Pro V100R019C10
ITU-T G.8273.2 ● 1800 V V100R006C20

● 1800 II TP V100R009C00
● 1800 V Pro V100R019C10
● 1800 II Pro V100R019C10

The 1800 V Pro, 1800 II The product function is 4.4.11 OSN 1800 V Pro
Pro, and 1800 II TP (with enhanced. Hardware and Version
NCE Support
V100R021C10SPC200 4.4.12 OSN 1800 II Pro
and later versions) newly Hardware and Version
support high-precision Support
4.4.13 OSN 1800 II TP
Support
Synchronization
Solution

WDM OTN

The 1800 V Pro and 1800 The product function is 3.3.1 Feature
II Pro chassis (with NCE enhanced. Limitations
V100R021C10SPC200 3.8.1.1 Configuration
and later versions) newly Process
support automatic
compensation for ring 3.8.1.9 Configuring Ring
network delay offset and Network Automatic
automatic single-fiber Compensation
bidirectional
compensation.

Change
The clock The product function 4.2.2 Time Source Port

synchronization GE is enhanced.
supported.
The NEs and ports The product function Added the description of the T-TC
newly support the T- is enhanced. mode and G.8271 packet format.
TC working mode. ● 4.5 Specifications
The external time
port newly supports ● 4.8.1.11.4 Parameters: Clock
G.8271 packets. Synchronization Attribute

Change
The new 1800 V Pro This subrack is new Added 4.4.11 OSN 1800 V Pro
ITU-T G.8275.1/ITU-T should support basic
G.8273.2. device functions.
The new 1800 II Pro This subrack is new Added 4.4.12 OSN 1800 II Pro
ITU-T G.8275.1/ITU-T should support basic
G.8273.2. device functions.

WDM OTN

Change
The OSN 1800 II TP The product function 4.4.13 OSN 1800 II TP Hardware
newly supports ITU- is enhanced. and Version Support
T G.8275.1/ITU-T G.
8273.2.

New line boards are The product function is 4.4.8 OSN 1800 V
added to the OSN 1800 enhanced. Hardware and Version
V to support ITU-T G. Support:
8275.1/ITU-T G.8273.2. Added the descriptions
of line boards.
The OSN 1800 V The product function is 4.8.1.6 Configuring PTP

supports the enhanced. Port Parameters:
configuration of the Added the operation
position and frame tasks and restrictions on
format of PTP clock the position and frame
packets. format of PTP clock
packets.

WDM OTN
The OSN 1800 V The product function is ● 4.2.6 Delay

supports automatic enhanced. Compensation, 4.5
compensation upon a Specifications, and
fiber cut on a ring 4.3.1 Feature
network and single-fiber Limitations: Added
bidirectional asymmetric the descriptions of
compensation when the automatic
system control board is compensation upon a
UXCMS. fiber cut on a ring
network and single-
fiber bidirectional
asymmetric
compensation.
● 4.8.1.1 Configuration
Process: Added the
description of
configuring the IEEE
1588v2 compensation
value backhaul
security key, single-
fiber bidirectional
asymmetric
compensation, Ring
Network
Compensation
Calculation, and Ring
Network Automatic
Compensation.
PTP NEs: Added the
procedure for
configuring a key for
securely returning an
IEEE 1588v2
compensation value.
PTP Port Parameters:
Added the procedure
for configuring single-
fiber bidirectional
asymmetric
compensation.
● 4.8.1.11.4
Parameters: Clock
Synchronization
Attribute: Added the
description of
parameters related to
ring compensation

WDM OTN
value calculation, ring

network automatic
compensation, and
single-fiber
bidirectional
asymmetrical
compensation.
● Added 4.8.1.11.12
Parameters: 1588
Compensation Back
Safe Password.

Update Update
The new This subrack is new to the product and 4.4.9 OSN 1800 II
OSN 1800 should support basic device functions. Enhanced
II Hardware and
Enhanced Version Support:
chassis Added the
supports descriptions of
ITU-T G. ITU-T G.8273.2.
8273.2.
When the The product function is enhanced. 4.4.8 OSN 1800 V

system Hardware and
control Version Support:
board of Deleted the
the OSN description that
1800 V is ITU-T G.8273.2 is
TNZ5UXC not supported
MS, ITU-T when the system
G.8273.2 is control board is
supported. TNZ5UXCMS.

WDM OTN

Update Update
The new This subrack is new to the product and Added 4.4.9 OSN
OSN 1800 should support basic device functions. 1800 II Enhanced
II Hardware and
Enhanced Version Support.
chassis
supports
ITU-T G.
8275.1.
Update Update
The OSN The product function is enhanced. Added the

1800 I&II descriptions of
Compact ITU-T G.8275.1
and OSN and ITU-T G.
1800 V 8273.2.
subracks
newly
support
ITU-T G.
8275.1 and
ITU-T G.
8273.2.

This topic lists the standards and protocols related to ITU-T G.8275.1/G.8273.2.
The following lists the standards and protocols related to ITU-T G.8275.1/G.8273.2:
● ITU-T G.8275.1: Precision time protocol telecom profile for phase/time
synchronization with full timing support from the network
● ITU-T G.8273.2: Timing characteristics of telecom boundary clocks and
telecom time slave clocks
clock
● ITU-T G.8271/Y.1366: Time and phase synchronization aspects of
telecommunication networks

WDM OTN
4.8.1 Configuring ITU-T G.8275.1 (OSN

1800/8800/9800Universal Platform Subrack/M Series/P
Series/(U Series: U2CTU/S2CTU/U4CTU/U5CTU))

This section describes the ITU-T G.8275.1 configuration process.
Figure 4-17 and Table 4-38 show the process of configuring ITU-T G.8275.1
packets to implement time synchronization.
NOTICE
To deploy high-precision clock synchronization, specific products and boards are

required. In addition, NEs and boards must be configured to work in high-precision
mode. For details, see 5 High-Precision Clock Synchronization Solution and
5.9.1 Setting the High-Precision Clock Mode.

WDM OTN
Figure 4-17 Process of configuring ITU-T G.8275.1 packets to implement phase

synchronization
NOTE
Table 4-38 describes the procedure for configuring ITU-T G.8275.1 packets to implement
phase synchronization. To provide physical clock frequency synchronization and ITU-T G.
8275.1-compliant phase synchronization, configure the physical-layer clocks by referring to
2.8.1.1 Configuration Process and then perform the procedure provided in Table 4-38 to
configure ITU-T G.8275.1 packets.

WDM OTN
Table 4-38 Procedure for configuring ITU-T G.8275.1 packets to implement

frequency and phase synchronization
Procedure Remarks
4.8.1.2 Enabling PTP Mandatory.

You must authorize PTP licenses before
configuring ITU-T G.8275.1 for
subracks. One license is consumed by
each subrack for which the ITU-T G.
8275.1 function is enabled.
NOTE
ITU-T G.8275.1 and IEEE 1588v2 share
license resources. After IEEE 1588v2 is
enabled on the NMS, ITU-T G.8275.1 is also
enabled.
4.8.1.3 Configuring the G.8275.1 Mandatory.

Protocol You can set the PTP clock protocol
type of an NE based on the actual
networking planning. PTP Profile can
be set to G.8275.1.
4.8.1.4 Setting the High-Precision Optional.

Clock Mode To deploy high-precision clock
synchronization, allocate high-
precision clock licenses and configure
boards to work in high-precision mode.
Specific subracks and boards of the
OSN 9800 and OSN 1800 support
high-precision clock synchronization.
For details, see 5 High-Precision Clock
Synchronization Solution.
NOTE
When the OSC board is used for high-
precision clock synchronization, you need
to correctly set the fiber type, fiber length,
and fiber dispersion coefficient on the
WDM Interface > Advanced Attributes
page of the NMS.

WDM OTN
Procedure Remarks

parameters.

WDM OTN
Procedure Remarks

Parameters NOTE
as a PTP port or clock cascading port.
● Set PTP Clock Message Location
the same.
transmit or receive ITU-T G.8275.1
causing delay asymmetry. In this
case, automatic delay
that offset is within the allowed
affected.
NOTE
following products support single-fiber
bidirectional asymmetric compensation.
For details about the restrictions, see
control boards) V100R009C00 and
later versions: EX4 and EG10

WDM OTN
Procedure Remarks

time cables.

NOTE
When an OSN 1800 NE is configured with
multiple AUX boards (F1AUX/B1AUX/
B2AUX), you need to set one AUX board as
the main AUX board. For details, see

to Enabled.


WDM OTN
Procedure Remarks
4.8.1.9 Querying the Clock View Mandatory.

Correct clock tracing relationships are
each NE.
4.8.1.10 Configuring Ring Network Optional.

Automatic Compensation When the OSN 1800 is used to form a
ring network, it is recommended that
you set Ring Network Compensation
Enabled.
NOTE
Only the following boards on the following
products support automatic compensation
of ring network delay offset. For details
about the restrictions, see 3.3.1 Feature
Limitations.
● OSN 1800 V (Z-series system control
boards) V100R009C00 and later
control board):
and EX10
K1GDC
control board):
and EX10
K1GDC
4.8.1.2 Enabling PTP

You must authorize PTP licenses before configuring ITU-T G.8275.1 for subracks.
One license is consumed by each subrack for which the ITU-T G.8275.1 function is
enabled.
Prerequisites

WDM OTN
NOTE
ITU-T G.8275.1 and IEEE 1588v2 share license resources. After IEEE 1588v2 is enabled
on the NMS, ITU-T G.8275.1 is also enabled.
Context
In the case of an NE that is equipped with master and slave subracks, an IEEE
1588v2 license needs to be allocated to each subrack that requires PTP clock
synchronization, and clock cascading needs to be correctly configured for the
Procedure

WDM OTN
NOTE
Step 2 Enable IEEE 1588v2 for existing subracks.

WDM OTN
----End
4.8.1.3 Configuring the G.8275.1 Protocol

Before configuring the ITU-T G.8275.1 function for a subrack, set the protocol type
to G.8275.1.
Prerequisites
● Operations in 4.8.1.2 Enabling PTP have been completed.
Procedure
----End

WDM OTN
4.8.1.4 Setting the High-Precision Clock Mode

Prerequisites
Guide.
Precautions
Procedure
NOTICE

WDM OTN
----End
Follow-up Procedure

Prerequisites
● The ITU-T G.8275.1 function has been enabled.

Based on the actual networking, configure the clock synchronization attributes of
each NE on the NCE. The attributes include the PTP working mode, system time,
and time adjustment.

WDM OTN
Step 1 Change PTP System Time.
Step 2 Set NE Clock Type, Slave Only, and PTP Time Adjustment. For details about the
parameters, see 4.8.1.11.4 Parameters: Clock Synchronization Attribute.
NOTE
If an NE requires only frequency synchronization, set PTP Time Adjustment to Disabled; if

an NE requires both frequency and time synchronization, set PTP Time Adjustment to
Enabled.

WDM OTN
NOTICE

----End

PTP clock source computing is specific to clock subnets. In other words, clock
subnets separately compute their current clock sources. An NE can belong to only
one clock subnet at a time. Each T-BC device can be configured only with one
Step 1 Set PTP Clock Subnet No. For details about the parameter, see 4.8.1.11.6
NOTE
● The NEs with the same clock subnet number belong to the same clock subnet.
● The devices whose NE Clock Type is set to T-BC can belong only to one clock subnet
and the clock sources must be selected from the clock subnet
----End

WDM OTN

You can configure the attributes of the local clock of an NE as required. Based on
the configured local clock attributes, the clock selection module of the NE can
Step 1 Set PTP Clock Source Type and Local Priority. For details about the parameters,
see 4.8.1.11.7 Parameters: BMC (Clock Subnet).
----End

Prerequisites

WDM OTN

This structure conflicts with that used for delay measurement. Therefore,
ITU-T G.8275.1 and delay measurement cannot be enabled at the same
time.
structure. This structure does not conflict with that used for delay
measurement. Therefore, ITU-T G.8275.1 and delay measurement can be
● Frame Format:
port.
NOTE
● For OSN 1800, Frame Format can be set for the following boards:
● New OTU boards and OTN line boards (including universal line boards) in
V100R019C10 and later versions.
● UNS4 board of the OSN 1800 V.
● For the OSN 9800, Frame Format can be set for the following boards: new OTU boards
and OTN line boards (including universal line boards) in V100R007C00SPC700 and later
versions.
● After the Frame Format of the UNS4 board on the OSN 1800 V is set to HDLC, the PTP
Clock Message Location parameter can be set.
● PTP Clock Message Location can be set for the Z5UNQ2 board on OSN 1800. When
the overhead in row 1 and column 13 is used, the Frame Format is GFP. When the
overhead in row 2 and column 3 is used, the Frame Format is HDLC.
● For boards on other products, when the Frame Format is set to GFP, the overhead
bytes in row 1 and column 13 are used. When the Frame Format is set to HDLC, the
overhead bytes in row 2 and column 3 are used.

WDM OTN
NOTICE
● When the same type of boards are interconnected, PTP Clock Message
Location and Frame Format can retain the default values.
● When different boards are interconnected, you must query and set PTP Clock
Message Location and Frame Format to ensure that they are consistent on
the interconnected ports.
For example, when a Z5UNS4 board on the OSN 1800 interconnects with a
K1UNS4/K1UNS5 board, PTP Clock Message Location and Frame Format
need to be modified.
● If the ODUk trail delay measurement function is required in the O&M
phase, set the PTP packet frame format to GFP for the Z5UNS4 and
K1UNS4/K1UNS5 boards.
● If the ODUk trail delay measurement function is not required, set PTP
Clock Message Location of the Z5UNS4 board to row 2 and column 3,
and set Frame Format to HDLC at both ends.
● When Frame Format of a local board changes between GFP and HDLC and is
different from that of the interconnected board, clock source tracing will be
affected.
1. Configure PTP Clock Message Location.
2. Configure Frame Format.

WDM OTN


NOTE
If you want to modify a selected port, select the corresponding port in the Selected Port
field, and then click to add the port to Available Port.
----End

Set Not Slave and Local Priority based on the Not Slave status and clock
transmission path of ports in the actual networking.

WDM OTN
Step 1 Set Not Slave and Local Priority. For details about the parameters, see 4.8.1.11.4
----End

of each NE.
Step 1 Select a port and set SYNC Packet Period(s), DELAY Packet Period(s),
ANNOUNCE Packet Period(s), and ANNOUNCE Packet Timeout Coefficient. For
Attribute.
NOTE
In ITU-T G.8275.1, P/E Mode can only be set to E2E.
----End

precision.
changed:

WDM OTN

NOTE
----End


WDM OTN
NOTE
EG10
----End

This function can be used to configure the physical addresses for sending PTP and
SSM packets so that fields can be filled in to the sent packets based on the
requirements of the downstream equipment, improving the configuration
flexibility for interconnection with third-party equipment.
NOTE

● For OSN 8800, this parameter is available only for the TN54TOG, TN54TOA, TN57TOA,
and TN54THA boards.
● For OSN 1800, this parameter is available only for the following boards:
● TNF5TOA, TNF6TOA, and TNF2ELOM (STND)
● New OTU boards and OTN tributary boards in V100R019C10 and later versions

WDM OTN
----End

clock information, including configuring the external port cascading mode for
clock boards, configuring attributes of external time ports, and configuring the
cable transmission distance permitted by an external time port.
Prerequisites
● The required STG boards have been created.
● For the OSN 6800, you have prepared a 120-ohm external clock port cable as
the network cable for external port cascading of clock boards.

The external port of a clock board can be used to receive external time signals. In
multi-subrack NE.
and time signals.
Synchronization.

WDM OTN
----End

the external time ports so that the clock selection module of the NE can compute
which clock is the best to be used as the master clock.
Enabled Status of an external time port must be set to Disabled.
Step 1 Select an external time port and set Direction, Interface Protocol Type, and
Interface Level. For details about the parameters, see 4.8.1.11.8 Parameters:
Basic Attribute.
NOTE
For the Interface Level parameter, the OSN 6800 supports only the value RS422.

WDM OTN
Step 2 Set PTP Clock Source Type and Local Priority. For details about the parameters,
see 4.8.1.11.9 Parameters: BMC (External Time Interface).
manually specified ITU-T G.8275.1 time quality level applies.
into the ITU-T G.8275.1 time quality level based on the predefined conversion
table.
Table 4-39 provides the mapping between the TOD status information and ITU-T
G.8275.1 time quality level.
Table 4-39 Mapping between the TOD status information and ITU-T G.8275.1
time quality level
TOD Status Information ITU-T G.8275.1 Time Quality

Level
0x00: normal 6


----End

WDM OTN

Port
Step 1 Select an external time port and set Transmitting Direction, Transmitting
Length(m), and Transmitting Time(ns). For details about the parameters, see
4.8.1.11.10 Parameters: Cable Transmitting Distance.
NOTE
● Transmitting Length(m) is available only when Transmitting Distance Mode is set to

Length; Transmitting Time(ns) is available only when Transmitting Distance Mode is
set to Time.
● The values of Transmitting Length(m) and Transmitting Time(ns) are set depending
on the networking scheme for the site.
----End

Prerequisites
Querying Port Status


WDM OTN
----End
4.8.1.9 Querying the Clock View

synchronization. In the clock view, you can monitor the clock tracing status of
each NE.
Prerequisites
Context
Procedure
menu.
Step 5 View the clock tracing relationships of NEs.

WDM OTN
----End
4.8.1.10 Configuring Ring Network Automatic Compensation

When the OSN 1800 is deployed on a ring network, you are advised to configure
the ring network automatic compensation function.
Prerequisites
● Ring network automatic compensation can be enabled only after an NE
achieves time synchronization (traces the grandmaster clock). Otherwise, the
calculated compensation value may be inaccurate.
● The compensation value is returned through DCN channels. Ensure that the
DCN links between sites are normal.
Procedure
Step 1 Set Ring Network Compensation Calculation and Ring Network Automatic
Compensation. For details about the parameters, see 3.8.1.10.3 Parameters:
Clock Synchronization Attribute.
Step 2 Set 1588 Compensation Back Safe Password. The values of 1588 Compensation
Back Safe Password must be consistent between the NEs at both ends. For details
about the parameters, see 3.8.1.10.10 Parameters: 1588 Compensation Back
Safe Password.

WDM OTN
----End
Follow-up Operations
If Ring Network Automatic Compensation is set to Disabled, the system
provides the recommended compensation value in the alarm after the
asymmetrical offset value of the ring link changes. You need to set the
compensation value manually.
4.8.1.11 Parameters: ITU-T G.8275.1 (OSN 1800/8800/9800Universal Platform

This section describes the parameters involved in the process of configuration.
4.8.1.11.1 Parameters: PTP Protocol

In this window, you can select the time synchronization protocol type used by the
NE based on the network planning.
Navigation Path
On the NE Explorer, select the NE and choose Configuration > Clock > PTP clock
> PTP Protocol from the navigation tree.
Parameters
PTP Protocol Type IEEE-1588v2 and G. Indicates the PTP

8275.1 protocol type used by
the NE.

WDM OTN

In this window, you can specify the mode of the frequency source that the NE
traces based on the network planning.
Navigation Path
In the NE Explorer, select the NE and choose Configuration > Clock > Frequency
Source Mode from the navigation tree.
Parameters

that the NE traces.

subracks on an NE.
Navigation Path
Parameters

slot number-board
name-external clock
name)-slot number-
board name-external
time interface

WDM OTN

cascading port.
synchronization are
set improperly, the
master and slave
port.
inputs/outputs the
unused.

In this window, you can configure and query the NE and port attributes, such as
the PTP system time, working mode, packet transmission period on the port, and
Navigation Path

WDM OTN
Parameters

PTP System Time Example: 2009-02-01 Displays the PTP system time.
01:01:01 You can manually modify this
parameter.
NE Name Example: NE7183 Indicates an NE name.
NE Clock Type T-BC, T-TC T-BC: A T-BC node has multiple

PTP ports. A T-BC may function
as the source of time when being
a master clock, or may
synchronize to an upstream clock
when being a slave clock. When
functioning as a master clock,
the T-BC can send time
information to downstream
devices through multiple PTP
ports.
T-TC: A T-TC node has multiple T-
TC ports and transparently
transmits time signals between
two T-TC ports. The time of a T-
TC node is not synchronized with
the transparently transmitted
time.
NOTE
Only the following models running
support the T-TC mode.
● 1800 II Pro
● 1800 V Pro

Default: Disabled Enabled or Disabled to enable
or disable ITU-T G.8275.1 When
it is set to Enabled, you can
manually configure the port

WDM OTN

Adjustment Default: Enabled parameter according to the
Protocol Packet NMEA, UBX, G.8271 Configures and queries the

Format Default: UBX protocol packet format of
external time.
1PPS+Time.
NOTE
The TMB1AUX board does not
support NMEA packets.
In the OSN 1800 series, only the
following devices running
● 1800 II Pro
● 1800 V Pro
OSN 9800 series devices running
WTR time (min) 0–12 Specifies the time from detection

Default: 5 of signal recovery to triggered
response of the clock selector.
The WTR time is set to prevent
the clock selector from
responding to a transient signal
recovery. In this manner, the
clock signals are re-selected as
the clock source only when the
synchronous clock signals recover
from a failure and stay valid

WDM OTN
Local PTP Clock For example: Displays the clock number of the
Supplying Code: 30
NE ID: 007E028B
Current Master For example: Indicates the number of the clock

Ingress of Current Shelf ID (shelf name)- Specifies the local clock input
Master Clock slot number-board port for the master clock that an
name-port number NE currently traces.
(port name)

Compensation Default: Disabled compensation calculation.
Calculation NOTE
EG10, and UNQ2
UNQ2, UND3 and EX10
versions: K1GDC
UNQ2, UND3 and EX10
versions: K1GDC

WDM OTN
Ring Network Enabled, Disabled Specifies the automatic ring

Automatic Default: Disabled network compensation.
Compensation After this function is enabled, an
NOTE
EG10, and UNQ2
UNQ2, UND3 and EX10
versions: K1GDC
UNQ2, UND3 and EX10
versions: K1GDC

Port Shelf ID (shelf name)- Specifies the names of the ports

(port name)

WDM OTN
Clock Type T-BC, T-TC ● When Clock Type of an NE is

set to T-BC, Clock Type of a
port can only be set to T-BC.
The master or slave status of
the port is determined by
using the BMC algorithm.
● When Clock Type of an NE is
set to T-TC, Clock Type of a
port can be set only to T-TC. In
this case, this port only
signals and does not have the
master or slave status, and
NEs do not synchronize time.
Step Mode One step, Two step Specifies whether an ITU-T G.

Default: One step 8275.1 port works in the one-step
or two-step mode.
the message to be
of high precision and accuracy.
the message to be
message.
Port Status LISTENING, MASTER, Sets the port preselection status.

PASSIVE, SLAVE

WDM OTN
Current Port Master, SLAVE, Displays the actual status of a

Status PASSIVE, LISTENING, source clock port on the service
FAULTY, INITIALIZING, board. The actual status is
and UNCALIBRATED computed by the BMC algorithm
based on the clock source quality
and clock priorities.
● MASTER: indicates that the
source for downstream devices
on the path.
● SLAVE: indicates that the port
with the upstream device with
the port in the master state on
the path.
● PASSIVE: indicates that the
maintain synchronization with
the port in the master state. It
is neither in the master state
nor synchronous with the port
in the master state.
● LISTENING: indicates that the
master port. This status
order.
when a LOS, AIS, or LinkDown
alarm is reported for the port.
● INITIALIZING: When the WTR
time of the clock source
expires, the port status
SLAVE, or PASSIVE to
INITIALIZING.
● UNCALIBRATED: When the
physical-layer clock source of
the port is lost and the
frequency is in the free-run
mode, the port status is
UNCALIBRATED.
Setting rule:

WDM OTN
The system adopts the BMC

algorithm to compute the port
status according to the clock
tracing relations among NEs.
Association with other
parameters:
This parameter is related to the
clock source attributes of the
upstream and downstream NEs
and is calculated by the BMC
algorithm based on the clock
source attributes.
Reference Clock NE clock ID-port ID This parameter is used to set the

Source No. number of the clock that is set as
the clock source for the port to
trace.
A port processes PTP packets only
when it receives a clock source
with the same number as the
specified clock source. Otherwise,
the port discards the received PTP
packets.
If this parameter is not set for a
port, the port does not match the
clock source number. That is, the
port can receive PTP packets from
all clock sources.
Not Slave Enabled, Disabled Specifies that a port cannot be

Default: Enabled set to the Slave state. You can set
the tracing relationship of a
synchronous network by setting
Not Slave, preventing T-GM from
tracing T-BC.
● Enabled: indicates that a port
cannot be set to the Slave
state.
● Disabled: indicates that a port
can be set to the Slave state.

WDM OTN
Destination MAC 01-1B-19-00-00-00, This parameter is used during

Address 01-80-C2-00-00-0E device interconnection.
Default: ● When two Huawei devices are
01-1B-19-00-00-00 interconnected, the
destination MAC addresses of
both devices must be set to
the same.
● When a Huawei device is
interconnected with a third-
party device, the destination
MAC address of the PTP port
on the third-party device must
be set to 01-1B-19-00-00-00.
Local Priority 0–255 Specifies the local priority of a

Default: 128 local port. The priority is used
only to select a time signal
transmission path and will not be
sent to another port.
Based on the network planning,
Local Priority can be set for
different ports. A smaller value
indicates a higher priority. During
the time source path selection,
the BMC preferentially selects a
port with a higher priority.


(port name)
P/E Mode E2E ITU-T G.8275.1 supports only the

E2E mode.
SYNC Packet 4/1024, 8/1024, Specifies the interval at which a

Period(s) 16/1024, 32/1024, PTP port transmits Sync
64/1024, 128/1024, messages. The delay-to-respond
256/1024, 512/1024, 1, mechanism uses the Sync,
2 Delay_Req, Follow_Up, and
Delay_Resp messages to achieve
synchronization between T-BC
and T-TSC devices.

WDM OTN
DELAY Packet 64/1024, 128/1024, DELAY Packet Period(s): Specifies

Period(s) 256/1024, 512/1024, 1, the interval at which a PTP port
2, 4, 8, 16 transmits Delay messages. The
delay-to-respond mechanism
uses the Sync, Delay_Req,
Follow_Up, and Delay_Resp
messages to achieve
and T-TSC devices.
ANNOUNCE 64/1024, 128/1024, ANNOUNCE Packet Period(s):

Packet Period(s) 256/1024, 512/1024, 1, Specifies the interval at which a
2, 4, 8, 16 PTP port transmits ANNOUNCE
messages. ANNOUNCE messages
contain the clock attributes of an
NE and are used to set up a
synchronous system.
NOTE
When the TN54TOA/TN54THA board
is interconnected with a PTN device
to transmit ITU-T G.8275.1 clock
signals, ANNOUNCE Packet
Period(s) must be set to 64/1028.
Otherwise, after a link fault occurs,
the interconnected PTN device may
fail to trace the clock source.
ANNOUNCE - ANNOUNCE Packet Timeout

Packet Timeout Coefficient: Specifies the timeout
Coefficient coefficient of receiving the
ANNOUNCE messages on a PTP
network. By default, if the
ANNOUNCE messages are not
received for four consecutive
periods, the packet receiving
times out and the link fails.


(port name)

WDM OTN
Warp Direction Positive, Negative Specifies how the time of

Default: Positive transmission over the cables
between two NEs warps in the
transmit and receive directions.
receive direction is longer than
that in the transmit direction.
direction.
Warp Mode Length, Time Specifies the mode of warp in

Default: Time transmission over the cables in
directions between two NEs.
● Length: Indicates that there is
a warp of transmission
between two NEs.
directions on the line between
two NEs.
Warp Length(m) - Specifies the warp of

Default: 0 transmission distance over the
cables in the transmit and receive
During network deployment,
adjust the time synchronization
NOTE
set to Length.

WDM OTN
Warp Time(ns) - Specifies the warp of

Default: 0 transmission time over the cables
in the transmit and receive
Adjust the time synchronization
according to the actual warp in
transmission time.
NOTE
set to Time.
Suggest Positive, Negative Specifies the suggested

Compensate Default: - compensation direction.
Direction NOTE
EG10, and UNQ2
UNQ2, UND3 and EX10
versions: K1GDC
UNQ2, UND3 and EX10
versions: K1GDC

WDM OTN
Suggest - Specifies the suggested

Length(m) compensation length.
NOTE
EG10, and UNQ2
UNQ2, UND3 and EX10
versions: K1GDC
UNQ2, UND3 and EX10
versions: K1GDC

WDM OTN

Time(nm) compensation time.
NOTE
EG10, and UNQ2
UNQ2, UND3 and EX10
versions: K1GDC
UNQ2, UND3 and EX10
versions: K1GDC

Port Slot ID-Board name- Displays the port name of an NE.

Port number(Port
name)
Single-Fiber Two- Enabled, Disabled Specifies whether to enable

Way Dispensation Default: Disabled single-fiber bidirectional
Compensation dispersion compensation
Remote Transmit Example: 1310 Specifies and displays the remote

Wavelength (nm) transmit wavelength.
Setting rule:
when Single-Fiber Two-Way
Dispensation Compensation is
set to Enabled.
Fiber Type Example: 255 Specifies and displays the fiber

type.

WDM OTN
Dispersion Slope Egress, Ingress Specifies and displays the type of

Value Type the fiber dispersion slope value
(value K).
Dispersion Slope Example: 93 Specifies and displays the fiber

Value dispersion slope value (value K).
Dispersion Egress, Ingress Specifies and displays the type of

Compensation the fiber dispersion inherent
Value Type compensation (value b).
Dispersion Example: 124150 Specifies and displays the fiber

Compensation dispersion inherent
Value compensation (value b).
NOTE
EG10

link status.
Navigation Path
Parameters

name-optical port
number(optical port
name)

name)-optical port
number(optical port
name)

WDM OTN

NE ID: 007E028B

messages from the
no abnormal alarm,

Navigation Path
Clock Subnet tab.
Parameters
PTP Clock Subnet No. 24-43 Specifies the configured

Default: 24 clock subnet of the NE.
clock subnet number
subnet.

In this window, you can set the best master clock (BMC) algorithm that the local
clock source uses, so that the system can calculate and select the best clock source
based on the set attributes such as precision and priority.

WDM OTN
Navigation Path
tab.
Parameters
Clock Class 6, 7, 13, 14, 52, 58, 68 to Time Quality Level--

122, 133 to 170, 216 to Specifies the quality level
232, 187, 193, 248, 255 of the time or frequency
Default: 248 allocated by the master
clock device. A smaller
parameter value
indicates a higher quality
level. This parameter is
automatically obtained
using the BMC.
Time Precision 0 to 255 Time Precision--Specifies

Default: 254 the time precision of the
master clock or expected
time precision of the
A smaller parameter
value indicates higher
time precision. This
parameter is
using the BMC.

WDM OTN
PTP Clock Source Type ATOMIC_CLOCK, GPS, PTP Clock Source Type--
TERRESTRIAL_RADIO, Specifies the type of the
PTP, NTP, HAND_SET, clock source.
OTHER, ● ATOMIC_CLOCK:
INTERNAL_OSCILLATOR Indicates an atomic
Default: clock.
INTERNAL_OSCILLATOR ● GPS: Indicates a GPS
time source.
Indicates the clock
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the Network Time
Protocol (NTP).
manually set.
OR: Indicates an

WDM OTN
PTP Clock Source Priority 0 to 255 PTP Clock Source Priority

1 Default: 128 1--Specifies the basis for
determining the clock
priority. The smaller the
value is, the higher the
clock priority is.
for tracing. This
PTP Clock Source
source for tracing.

2 Default: 128 2--Specifies the auxiliary
source. A smaller
parameter value
indicates a higher
priority.
values of Time Quality
Deviation are the same,
this parameter
PTP Clock Source Priority
2 value is of higher
quality and is preferred
tracing.

WDM OTN
PTP Clock Source 65535 PTP Clock Source

Deviation Deviation--Specifies the
deviation of the master
clock from the standard
time. A smaller
parameter value
clock signals. This
parameter is
using the BMC.
Local Priority 1 to 255 Indicates the port

Default: 128 priority during clock
source selection.

Navigation Path
tab.
Parameters
interface the NE.


WDM OTN

interface with the
an NE.
for the port.


the best master clock (BMC) algorithm that the external clock source uses
through the external interface, so that the system can calculate and select the
best clock source based on the set attributes such as precision and priority.
Navigation Path
> External Time Interface from the navigation tree. Click the BMC tab.
Parameters
interface the NE.
Time Quality Level 6, 7, 13, 14, 52, 58, 68 to Time Quality Level--
parameter value
level.

WDM OTN

A smaller parameter
time precision.
Default: clock.
time source.
● TERRESTRIAL_RADIO
: Indicates the clock
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the Network Time
Protocol (NTP).
manually set.
OR: Indicates an

WDM OTN
PTP Clock Source Priority 0–255 PTP Clock Source Priority

source. A smaller
parameter value
indicates a higher
priority.
this parameter
PTP Clock Source
source for tracing.
Not Slave Enabled, Disabled This parameter is used to

Default: Enabled ensure that the port is
not in the slave state.
The Not Slave can be
planned to ensure that
the tracing relationship
of the synchronization
network is synchronized.
In this case, the T-GM
does not trace the T-BC.
● Enabled: The slave
state is not allowed.
● Disabled: This
parameter can be set
to Slave.

WDM OTN
PTP Clock Source — PTP Clock Source

time. A smaller
parameter value
clock signals. This
parameter is
using the BMC.
Local Priority 0–255 Local Priority--Specifies

Default: 128 the local priority of an
external clock source,
which is manually set.
This parameter is used to
help determine the clock
priority. A smaller
parameter value
indicates a higher
priority.
values of PTP Clock
Source Priority 2, Time
Quality Level, Time
Precision, and PTP Clock
Source Deviation, this
parameter determines
the clock quality. That is,
the clock source with a
smaller Local Priority
value is of higher quality

Navigation Path

WDM OTN
Parameters
interface the NE.

NOTE
of a port is set to
only Ingress.
of a port is set to
Ingress and Egress.

option to set the
mode for the clock
Time.
If the delay can be
measured, set this
parameter to Time;
otherwise, set this
the transmission
in terms of length.
the transmission
in terms of time.

WDM OTN

to the actual
adjust the delay in
signals.
Set this parameter
according to the
delay can be
receive end and the
distance. If Enable
compensation at the
set only when
In the case of the
case of the receive
the receive end is
compensated.

WDM OTN

synchronization.
In the case of the
case of the receive
the receive end is
compensated.
set only when

Navigation Path
Parameters
Board Example: Shelf5(Slave Indicates the clock

shelf5)-5-54TOA(STND) board.

WDM OTN

sending PTP and SSM
requirements of the
improving the
NOTE
are not supported.)
NOTE
MAC Address
Configuration is
supported only by the
following boards:
only for the TN54TOG,
TN54TOA, TN57TOA,
and TN54THA boards.
boards:
● TNF5TOA,
TNF6TOA, and
TNF2ELOM (STND)
● New OTU boards
and OTN tributary
boards in
V100R019C10 and
later versions

Navigation Path

WDM OTN
Parameters


Compensatio key for
IEEE 1588v2
compensation
value.
NOTE
The value is
displayed as
"********" and
the query is
not
supported.

WDM OTN


securely
returning an
IEEE 1588v2
compensation
value.
Value
description:
The value
contains 8 to
128
characters. It
is
recommended
that the value
contain at
least three
types of the
following
characters:
● Lower-case
letters
● Upper-case
letters
● Digits
● Space or
special
characters
Setting rule:
The values of
New
Password and
Confirm
Password
must be the
same.

WDM OTN

NOTE
The default
key for
securely
returning an
IEEE 1588v2
compensation
value on the
upstream and
downstream
devices is
HW@_77wa.
You are
advised to
change the
default key
when using
the device for
the first time.

Password confirm
password for
securely
returning an
IEEE 1588v2
compensation
value.
Setting rule:
The values of
New
Password and
Confirm
Password
must be the
same.
4.8.2 Configuring ITU-T G.8275.1 (OSN 9800 U Series: U1CTU/

S1CTU)

Figure 4-18 shows the process of configuring ITU-T G.8275.1 packets to
implement synchronization.

WDM OTN

synchronization
Table 4-47 provides the detailed procedure for configuring ITU-T G.8275.1 packets
to implement phase synchronization and query clock synchronization status.
NOTE
Table 4-47 shows the procedure for configuring ITU-T G.8275.1 packets to implement

Operation Remarks
4.8.2.2 Configuring the PTP Protocol Mandatory.

You can set the PTP clock protocol
networking planning. PTP Profile can
be set to G.8275.1.
4.8.2.3 Enabling ITU-T G.8275.1 Mandatory.

You must enable ITU-T G.8275.1 before
configuring ITU-T G.8275.1 for an NE.
The number of available licenses is
deducted by 1 each time ITU-T G.
8275.1 is enabled for a subrack.

WDM OTN
Operation Remarks

parameters.

transmit or receive ITU-T G.8275.1
time cables.



WDM OTN
Operation Remarks

each NE.
4.8.2.2 Configuring the PTP Protocol

to G.8275.1.
Prerequisites
Procedure
Step 1 Configure Ptp Profile.
----End
4.8.2.3 Enabling ITU-T G.8275.1

Before configuring the ITU-T G.8275.1 function for a subrack, you must authorize
license resources. One license resource is consumed each time when the ITU-T G.
8275.1 function is enabled for an NE.
Prerequisites

WDM OTN
● The license resource of ITU-T G.8275.1 resources is available.
Procedure
NOTE
----End

to configure PTP clock global parameters, PTP clock subnets, and local clock
attributes for the NE.

WDM OTN
Prerequisites

Based on the practical networking, you need to configure the clock
synchronization attributes of each NE on NCE, including the PTP working mode,
system time, and system time calibration.
NOTE
The PTP System Time field can be set only when the NE traces local clock sources.
Step 2 Set Protocol Packet Format and Enable Automatic Compensation

Measurement. For details about the parameters, see 4.8.2.9.1 Parameters:

WDM OTN
Global Configuration.
----End

domain is supported at a time. Each T-BC device can be configured only with one
Step 1 Configure Clock Subnet No.. For details about the parameter, see 3.8.2.8.3

WDM OTN
NOTE
● The devices whose NE Clock Type is set to T-BC can belong only to one clock subnet
and the clock sources must be selected from the clock subnet
----End

Step 1 Set Clock Source Type, Clock Source Priority 2, and Ptp Local Priority. For
----End

To ensure that PTP ports of each NE on a network work correctly, you need to
create PTP ports, configure attributes of PTP packets, and specify the cable
transmission deviation of PTP clock ports.
Prerequisites


WDM OTN
Step 1 Configure a clock port. For details about the parameters, see 4.8.2.9.2
----End

Step 1 Set Clock Source WTR Time(min).

NOTE
The value of Clock Source WTR Time(min) ranges from 0 to 12 with a step of 1 minute.
Step 2 Set Port, Clock Source No, and Clock Source PortNo.

WDM OTN
----End

of each NE.
Attribute.
NOTE
----End

WDM OTN

precision.
Step 1 Select a port and set Warp Direction, Warp Mode, Warp Length(m), and Warp
NOTE
----End

This topic describes how to configure external clock source attributes so that the
external clock information can be properly extracted by a device. The external
clock source attributes include the attributes of external time ports, and cable
transmission distance permitted by an external time port.
Prerequisites

WDM OTN
● The CTU boards have been created.

When there are external time sources for an NE, set the attributes of the external
time sources so that the clock selection module of the NE can calculate the best
master clock (BMC).
Step 1 Select an external time interface and set the External Time Interface Direction
and Interface Protocol Type parameters. For details on parameter settings, see
4.8.2.9.6 Parameters: Basic Attribute.
Step 2 Configure Bits Type and Bits Clock Class Level. For details on parameter settings,
----End

Interface

WDM OTN
Step 1 Select an external time interface and set the following parameters: Input Warp
Mode, Input Warp Length(m), Input Warp Time(ns), Output Warp Mode,
Output Warp Length(m), and Output Warp Time(ns). For details on parameter
settings, see 3.8.2.8.7 Parameters: Cable Transmitting Distance.
NOTE
● The Input Warp Length(m) parameter is available only when Input Warp Mode is set
to Length; the Input Warp Time(ns) parameter is available only when Input Warp
● The Output Warp Length(m) parameter is available only when Output Warp Mode is
set to Length; the Output Warp Time(ns) parameter is available only when Output
● Input Warp Length(m), Output Warp Length(m), Input Warp Time(ns), and Output
Warp Time(ns) needs to be set based on the actual network situations.
----End

Prerequisites

WDM OTN
Procedure
Step 1 Query the information about the clock source received at the port.
----End

Prerequisites
Context
Procedure
Select the desired NE from the navigation tree on the left.
menu.
----End
4.8.2.9 Parameters: ITU-T G.8275.1 (OSN 9800 U Series: U1CTU/S1CTU)

This section describes the parameters in process of configurations.

WDM OTN
4.8.2.9.1 Parameters: Global Configuration

In this window, you can configure and query the global attributes of the PTP clock
system, including the PTP system time, working mode, and PTP protocol mode.
Navigation Path
> Global Configuration from the navigation tree.
Parameters
Table 4-48 Global Configuration

parameter.
NE Clock Type T-BC For the clock nodes compliant

with ITU-T G.8275.1, NE Clock
Type can be set only to T-BC.
T-BC: As a clock device with
domain, T-BC maintains the time
stamp used in the clock domain.
The clock device can function as
a master clock device to provide
a reference clock source or as a
slave clock device to keep
devices.
Enable Automatic Enable, Disable On a ring network, the NE can

Compensation Default: Disable automatically calculate the
Measurement asymmetry values of repaired
fibers after a fiber cut or fiber
adjustment occurs, without
requiring manual measurement.
You only need to manually set
the compensation parameters so
that the NE time and GPS are
synchronous.
NOTE
NG WDM products do not support
this parameter.

WDM OTN
Protocol Packet NMEA, UBX Sets and queries the format of

Format Default: UBX an IEEE 1588 clock protocol
message.
1PPS+Time.
Local Clock Source Example: Displays the clock number of the

No. 00259e30007d0050 local clock source of the NE.
Current Master Example: Current Master Clock No.--

Clock No. 00259e30007d0050 Indicates the number of the
clock source traced by the NE,
that is, the number of the
master clock traced by the NE
source.
Ingress of Current Example: PTP Specifies the local clock input

Master Clock port for the master clock that an
NE currently traces.
Hops of Current Example: 2 Indicates the number of hops

Master Clock traversed when the current
master clock is transmitted to
the current NE.
For example, the clock
transmission sequence on
devices A, B, C, and D is A->B-
>C->D. If device A is the clock
source, the number of hops for
the current master clock on
device D is 3.

Navigation Path

WDM OTN
Parameters

Port Example: Specifies the name of the ports

synchronized.

mode.
PTP Packet 01-1B-19-00-00-00, This parameter is used for

Destination MAC 01-80-C2-00-00-0E interconnection with other
Address Default value: devices.
00-00-00-00-00-00 ● When the port is
interconnected with a Huawei
device, the destination MAC
addresses of the
interconnected devices must
be the same.
● When the port is
on the third-party device
must be set to
01-1B-19-00-00-00.

IP Address
PTP Packet - -
Destination IP
Address
Port Prefigure MASTER+SLAVE, Sets the preselection status of a

Default value: MASTER
+SLAVE

WDM OTN
Current Port Master, Slave, Passive, Displays the actual port status.
Status Listening
Port Manual Master, Slave, Passive, Specifies the status of the clock
Status Listening source port on the service board.
Default value: The BMC algorithm computes
Listening the port status based on the
quality and priority of the clock
source.
Step Module one step, two step Sets the one-step or two-step
Default value: one mode for an IEEE 1588 port.
step Only tributary boards support
the setting of one-step or two-
step mode.
accuracy.
message.
PTP port type T-BC Displays the PTP port model.
PTP Status Enabled Displays the PTP status of a

port, that is, whether the port
supports access of PTP packets.

Default value: Enabled set to the Slave state. You can
set the tracing relationship of a
Not Slave, preventing T-GM
from tracing T-BC.
● Enabled: The clock cannot be
set to the Slave state.
● Disabled: The clock can be

WDM OTN
Bits Local Priority 0–255 Specifies the local priority of a

Default value: 128 local port. The priority is used
transmission path and will not
be sent to another port.
indicates a higher priority.
During the time source path
selection, the BMC preferentially
selects a port with a higher
priority.


synchronized.

E2E mode.
SYNC Packet 4/1024, 8/1024, The SYNC Packet Period(s)

256/1024, 512/1024, 1, port transmits Sync packets. The
2 delay-to-respond mechanism
Default value: 64/1024 uses the Sync, Delay_Req,
packets to achieve
and T-TSC devices.

Default value: 1 port transmits Delay packets.
The delay-to-respond
and T-TSC devices.

WDM OTN

Packet Period(s) 256/1024, 512/1024, 1, Period(s) parameter provides an
2, 4, 8, 16 option to set the period at which
Default value: 1 the PTP port transmits
ANNOUNCE packets. The
clock attributes of an NE and are
used to set up a synchronous
system.
ANNOUNCE 3–10 Specifies the timeout coefficient

Packet Timeout Default value: 4 for receiving ANNOUNCE
Coefficient packets.
If a port does not receive
period specified by the
parameter, it determines that
the link fails.


synchronized.
Warp Direction Positive, Negative Indicates the transmission time

Default value: Positive difference between the cables in
direction.
direction.

WDM OTN

Default value: Time transmission over the cables in
between two NEs.
between two NEs.
Warp Length(m) 0–3555555 Specifies the warp of

Default value: 0 transmission distance over the
cables in the transmit and
NEs. Adjust the time
distance.
NOTE
when Warp Mode is set to Length.

Default value: 0 transmission time over the
time.
NOTE
when Warp Mode is set to Time.

receive direction.

WDM OTN
Actual Example: 10 The value depends on the

Measurement corresponding warp mode
Warp (ns) (length or time).
If the warp of transmission time
directions of a fiber/cable
between two NEs is the same,
Actual Measurement Warp
(ns) and Accept Actual
Measurement Warp are
unavailable.
Accept Actual Example: 10 Indicates the acceptable warp

Measurement range. No warp compensation is
Warp required if the warp is within
this range.

link status.
Navigation Path
tab.
Parameters


receives.

messages from the
the status is Down.

WDM OTN

Navigation Path
> Clock Subnet Configuration from the navigation tree. Click the Clock Subnet
tab.
Parameters
Clock Subnet No. 0-255 Specifies the configured

clock subnet number
subnet.

Navigation Path

WDM OTN
Parameters
Default: clock.
time source.
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the Network Time
Protocol (NTP).
manually set.
OR: Indicates an

WDM OTN
PTP Clock Source Priority 0-255 PTP Clock Source Priority

source. A smaller
parameter value
indicates a higher
priority.
Level are the same, this
smaller PTP Clock
Source Priority 2 value
is of higher quality and is
source for tracing.
Local Priority 0-255 Local Priority--Specifies

Default: 128 the local priority of a
clock source, which is
manually set. This
parameter is used to
priority. A smaller
parameter value
indicates a higher
priority.
values of PTP Clock
Source Priority 2 and
Time Quality Level are
the same, this parameter
priority. That is, the clock
Local Priority value is of
higher priority and is
source for tracing.

WDM OTN

the interface attributes of the external clock source so that the NE can extract the
Navigation Path
In the NE Explorer, select the NE and choose Configuration > Clock > PTP clock >
External Time Interface from the navigation tree. Click the Basic Attribute tab.
Parameters
External Time Interface Example: bits2 Displays the port name

of the external time
source on the NE.

WDM OTN

External Time Interface external clock port are as
follows:
● Configuration
management of 2M
clock sources in the
input and output
directions
● Configuration
management of 2M
output clock sources
● 2M clock sources can
function as the
reference clock
sources for system
frequency
synchronization
The features of an
external time port are as
follows:
input/output
direction, protocol
type, and interface
time interface.
time, and can also
function as the
for restoring the
system clock
frequency.


WDM OTN
Interface Protocol Type 1PPS+Time Interface Protocol Type--

Default: 1PPS+Time Specifies the interface
protocol type of an
external time source on
an NE. 1PPS+Time
indicates that the second
frame header
information and time
information are
transmitted separately.
Status is set to
Disabled.

Navigation Path
Parameters

source on the NE.

WDM OTN

level of an external time
port.
● Manual: You can
quality level of an
external time port
based on the value of
Bits Quality Level.
● Auto: The NE
software can
automatically obtain
the time quality level
of an external time
port based on the
1PPS status and the
conversion table.
Bits Quality Level 0-255 Indicates the actual time

quality level of an
external time interface.
Bits Clock Class Level 0-255 Bits Clock Class Level--

Default: 6 Specifies the quality level
of the time or frequency
allocated by the master
parameter value
level.
the external time source
for tracing. The clock
Bits Clock Class Level
time source for tracing.

WDM OTN
Bits Precision 0-255 Bits Precision--Specifies

A smaller parameter
time precision.
values of Bits Clock
Class Level of two clock
sources are the same,
smaller Bits Precision
value has higher clock
as the time source for
tracing.

WDM OTN
Bits Time Source ATOMIC_CLOCK, GPS, Bits Time Source--

Default: GPS clock.
time source.
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the Network Time
Protocol (NTP).
manually set.
OR: Indicates an

WDM OTN
Bits Priority 2 0-255 Bits Priority 2--Specifies

Default: 128 the auxiliary priority of
the clock source. A
indicates a higher
priority.
values of Bits Time
Source and Bits
Precision of two clock
this parameter
source quality. That is,
smaller Bits Priority 2

WDM OTN
Bits Local Priority 0-255 Bits Local Priority--

Default: 128 Specifies the local
priority of an external
manually set. This
priority. A smaller
parameter value
indicates a higher
priority.
values of Bits Priority 2,
Bits Quality Level, and
Bits Precision of two
clock sources are the
source priority. That is,
smaller Bits Local
Priority value is of
source for tracing.

Navigation Path
Parameters

source on the NE.

WDM OTN
Input Warp Mode Length, Time Specifies the

Default: Time transmission distance
mode for the time
interface in the input
direction. The parameter
value can be set to
Length or Time.
Input Warp Length(m) 0-300 Specifies the length of

Default: 0 the cable in the input
direction of an external
time source. This
parameter is set as
required to modify the
time delay during the
transmission.
Input Warp Time(ns) 0 to 1350 Specifies the delay in

Default: 0 transmitting the time
source over the cable in
the input direction. This
parameter is set as
required to adjust the
Output Warp Mode Length, Time Specifies the

mode for the time
interface in the output
value can be set to
Length or Time.
Output Warp Length(m) 0-300 Specifies the length of

Default: 0 the cable in the output
time source. This
parameter is set as
transmission.
Output Warp Time(ns) 0-1350 Specifies the delay in

the output direction. This
parameter is set as

WDM OTN
4.9.1 Configuring ITU-T G.8275.1 (OSN 1800/8800/9800

Universal Platform Subrack/M Series/P Series/(U Series:
U2CTU/S2CTU/U4CTU))

Figure 4-19 shows the process of configuring ITU-T G.8275.1 packets to

implement synchronization.

synchronization
Table 4-52 provides the detailed procedure for configuring ITU-T G.8275.1 packets
to implement phase synchronization and query clock synchronization status.
NOTE
Table 4-52 shows the procedure for configuring ITU-T G.8275.1 packets to implement

Procedure Remarks
4.9.1.2 Configuring Mandatory.

the PTP Protocol You can set the PTP clock protocol type of an NE based
on the actual networking planning. PTP Profile can be
set to G.8275.1.
4.9.1.3 Enabling ITU- Mandatory.

T G.8275.1 You must enable ITU-T G.8275.1 before configuring
ITU-T G.8275.1 for an NE. The number of available
licenses is deducted by 1 each time ITU-T G.8275.1 is
enabled for a subrack.

WDM OTN
Procedure Remarks

PTP NEs ● Configure a password for securely returning an IEEE
1588v2 compensation value. This operation is
mandatory when ring-network compensation needs
to be configured for an NE. The values of 1588
Compensation Back Safe Password must be
consistent between the NEs at both ends.
NOTE
This function is supported only when the system control
board of the OSN 1800 V is UXCMS and the product
version is V100R009C00 or later. For details about the
restrictions, see 4.3.1 Feature Limitations.
● Set clock synchronization attributes. According to
the practical networking, you need to set the clock
synchronization attributes of each NE on the U2000,
including the PTP working mode, system time, and
system time calibration parameters.
● Configure clock subnets. This operation is
mandatory when a physical OTN needs to be
divided into multiple clock domains.
● Set Ring Network Compensation Calculation and
Ring Network Automatic Compensation to
Enabled.
NOTE
● Set local clock attributes. According to the practical
networking, you must set the local clock parameters
received by the local NE, so that the clock selection
module can calculate the best master clock.

WDM OTN
Procedure Remarks

PTP Port Parameters ● Set PTP Clock Message Location and Frame
Format. To ensure successful board interconnection,
the values of PTP Clock Message Location and
Frame Format set for two interconnected boards
must be the same.
● Create a clock port and set port packet attributes.
The ports that transmit or receive G.8275.1 packets
must be configured as PTP ports to trace PTP clock
sources.
● Configure single-fiber bidirectional asymmetric
compensation. In a single-fiber bidirectional system
consisting of single-fiber bidirectional optical
modules, dispersion occurs during transmission
because receive and transmit wavelengths are
different, causing latency asymmetry. In this case,
automatic latency compensation is required to
ensure that deviation is within the allowed range
and clock precision is not affected.
NOTE
● Set the Cable Transmission Warp parameter of the
clock port. Set the parameters related to cable
transmission deviation according to the actual
situation to compensate for the delay generated by
external time cables.
● Set MAC addresses. The physical addresses for
sending PTP and SSM packets can be configured so
that fields can be filled in to the sent packets based
on the requirements of the downstream equipment,
improving the configuration flexibility for
interconnection with third-party equipment.

WDM OTN
Procedure Remarks
4.9.1.6 Configuring Optional.

External Time Ports When an NE needs to input or output external time
signals, you must enable the port cascading function
and set external time port attributes and the Cable
Transmission Warp parameter.
NOTE
When an NE is equipped with master and slave subracks, you
need to specify a subrack with a clock board as the clock
center subrack. If other subracks receive clock signals from the
upstream or output time signals to the downstream, you need
to set the clock cascading relationship between these subracks
and the clock center subrack and correctly connect the
subracks. For details, see 2.8.1.4 Configuring the Clock
Center Subrack under 2.8.1.1 Configuration Process.
For details, see 2.9.1.4 Configuring the Clock Center Subrack
4.9.1.7 Viewing the Mandatory.

Port Status After all the clock configuration operations are
completed, query all ports and ensure that the port
synchronization status is the same as that in the
networking diagram.
4.9.1.8 Viewing the Mandatory.

Clock Tracing Status Correct clock tracing relationships are critical to ensure
network-wide clock synchronization. Using U2000, you
can monitor the clock tracing status of each NE.

to G.8275.1.
Prerequisites
Procedure

WDM OTN
----End

Before configuring the ITU-T G.8275.1 function for an NE, you must authorize
Prerequisites
● The license resources of ITU-T G.8275.1 are available.
Procedure
Step 1 Add a subrack and set its IEEE 1588v2 attribute to Enabled.

WDM OTN
NOTE

WDM OTN
NOTE
● OSN 9800:
– Universal platform subrack: The universal platform subracks on the same NE
implement frequency/phase synchronization through clock cascading between
In versions earlier than V100R007C00, electrical subracks on the same NE do not
support clock cascading between master and slave subracks. Therefore, only one
electrical subrack on each NE supports frequency/phase synchronization. You are
advised to configure all boards requiring frequency and phase synchronization in
the same subrack.
In V100R007C00 and later versions, when the system control board is TNU2CTU or
TNS2CTU, electrical subracks on the same NE support clock cascading between
master and slave subracks. When the system control board is TNU4CTU or
TNU5CTU, electrical subracks on the same NE support clock cascading between
– M series subracks: Clock cascading between master and slave subracks is
supported.
– P series subracks: Clock cascading between master and slave subracks is supported.
– Clock cascading between master and slave subracks cannot be implemented
between universal platform subracks and U/M series subracks.
● OSN 1800:
– Subracks that use the TMB1AUX board support clock cascading between master
and slave subracks since V100R020C10. The ports supported by the TMB1AUX
board are external clock/time ports and clock synchronization GE optical ports.
– Subracks that use the TMB2AUX/MD48AFS board support clock cascading between
master and slave subracks since V100R021C10. The ports supported by the
TMB2AUX board are external clock/time ports and clock synchronization GE optical
ports. The ports supported by the MD48AFS board are clock synchronization GE
optical ports.
– Subracks that use the TMK5SXCH/TMK5UXCME/TMK5XCH/TMK5GSCC board
support clock cascading between master and slave subracks since V100R022C00.
The ports supported by the board are clock synchronization GE optical ports.
– Subracks that use the TMK6XCH board support clock cascading between master
and slave subracks since V100R022C10. The ports supported by the board are clock
● OSN 8800/6800: Clock cascading between master and slave subracks is supported.
Step 2 Set the IEEE 1588v2 attribute of an existing subrack to Enabled.

WDM OTN
----End

To ensure normal operation of the PTP clock for each NE in a network, users need
to configure clock synchronization attributes, static BMC, the frequency source
mode, PTP clock subnet, local clock attributes for the NE, and configure a
Prerequisites
● The ITU-T G.8275.1 has been enabled.

each NE on the U2000. The attributes include the PTP working mode, system time,

WDM OTN
Step 1 Change PTP System Time.
Step 2 Configure PTP Time Adjustment and Protocol Packet Format. For details on
parameter settings, see 4.9.1.9.4 Parameters: Clock Synchronization Attribute.
NOTE
If an NE requires only frequency synchronization, set PTP Time Adjustment to Disabled; if
an NE requires both frequency and time synchronization, set PTP Time Adjustment to
Enabled.

WDM OTN
NOTICE
Exercise caution when performing this operation. If PTP Time Adjustment is set
to Disabled, the time synchronization function will be unavailable. When only PTP
frequency synchronization is required and phase synchronization is not, PTP Time
Adjustment can be set to Disabled. By default, it is set to Enabled and the
default setting does not need to be changed in most cases.
----End

subnets in planning the clock network depending on the scheme for the site.
Within each subnet, time synchronization can be implemented for all clocks to
satisfy customers' requirements.
subnet. The messages sent from different clock subnets are discarded by the NE.
Step 1 Configure in PTP Clock Subnet. For details on parameter settings, see 4.9.1.9.6
NOTE
● Devices in the T-BC working mode can belong to only one clock subnet, and its clock
source can be selected only from the same clock subnet.
----End

You can configure the clock attributes of the local clock sources received at the NE
so that the best master clock (BMC) can be calculated by the clock selection
module.

WDM OTN
Step 1 Configure Clock Source Type and Local Priority. For details on parameter
settings, see 4.9.1.9.7 Parameters: BMC (Clock Subnet).
----End
Configuring a Password for Securely Returning an IEEE 1588v2

Compensation Value
Configure a password for securely returning an IEEE 1588v2 compensation value
when ring-network compensation needs to be configured for an NE.
Step 1 Configure 1588 Compensation Back Safe Password:
----End


WDM OTN
Prerequisites

This structure conflicts with that used for delay measurement. Therefore,
ITU-T G.8275.1 and delay measurement cannot be enabled at the same
time.
structure. This structure does not conflict with that used for delay
measurement. Therefore, ITU-T G.8275.1 and delay measurement can be
● Frame Format:
port.
NOTE
● Before configuring a port on a board as a PTP port, you need to configure the position
and frame format of PTP clock packets.
● PTP Clock Message Location is available only when Frame Format is set to HDLC.
● Only the UNS4 and UNQ2 boards of the OSN 1800 V support the setting of PTP Clock
Message Location.
● Frame Format can be set only when the UNS4 board of the OSN 1800 V works with
TNZ5UXCMS.
● When Frame Format of a local board changes between GFP and HDLC and is different
from that of the interconnected board, clock source tracing will be affected.

WDM OTN
----End

WDM OTN


NOTE
If you want to modify a selected port, select the corresponding port in the Selected Port
field, and then click to add the port to Available Port.
----End

Set Not Slave and Local Priority based on the Not Slave status and clock
transmission path of ports in the actual networking.
Step 1 Set Not Slave and Local Priority. For details about the parameters, see 4.9.1.9.4

WDM OTN
----End

of each NE.
Attribute.
NOTE
----End

WDM OTN

precision.
changed:

WDM OTN
NOTE
----End

NOTE
----End

The physical addresses for sending PTP and SSM packets can be configured so that
fields can be filled in to the sent packets based on the requirements of the
downstream equipment, improving the configuration flexibility for interconnection
with third-party equipment.

WDM OTN
NOTE

----End

clock source attributes include the external port cascading mode for clock boards,
attributes of external time ports, and cable transmission distance permitted by an
external time port.
Prerequisites
● STG boards have been created.
● For the OSN 6800, when the external port cascading mode is configured for
clock boards, the 120-ohm external clock port cable must be used as the
network cable for cascading.

WDM OTN

The external ports on a clock board can receive clock or time signals, or can be
used to cascade clock boards on multiple subracks on an NE.
concatenate and transmit the clock or timing signals among multiple
to disabled state. One NE supports a maximum of two ports for the input or
output of external clock and timing signals.
Synchronization.
Step 1 Configure Enabled Status. For details on parameter settings, see 4.9.1.9.3
----End

of the external time interfaces so that the clock selection module of the NE can
calculate the best master clock (BMC).
Enabled Status of an external time interface is set to Disabled.
Step 1 Select an external time interface and set the following parameters: Direction,
Interface Protocol Type, and Interface Level. For details on parameter settings,
see 4.9.1.9.8 Parameters: Basic Attribute.

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NOTE
For the Interface Level parameter, OSN 6800 only supports the value RS422.
Step 2 Configure Clock Source Type and Local Priority. For details on parameter
settings, see

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manually specified ITU-T G.8275.1 time quality level applies.
STG clock board automatically converts the quality information carried in the
TOD into the ITU-T G.8275.1 time quality level based on the predefined
conversion table.
Table 4-53 provides the mapping between the TOD status information and ITU-T
G.8275.1 time quality level.
Table 4-53 Mapping between the TOD status information and ITU-T G.8275.1
time quality level
TOD Status Information ITU-T G.8275.1 Time Quality
Level
0x00: normal 6


Other (remain) 255
----End

Interface
Step 1 Select an external time port and set the following parameters: Transmitting
Direction, Transmitting Length(m), and Transmitting Time(ns). For details on
parameter settings, see 4.9.1.9.10 Parameters: Cable Transmitting Distance.

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NOTE
● The Transmitting Length(m) parameter is available only when Transmitting Distance

Mode is set to Length; the Transmitting Time(ns) parameter is available only when
Transmitting Distance Mode is set to Time.
● The values of Transmitting Length(m) and Transmitting Time(ns) are set based on
the actual networking situation.
----End
4.9.1.7 Viewing the Port Status

The U2000 supports the function of querying the clock source traced by a port.
Using this function, you can query the tracing status of the NE time.
Prerequisites
Viewing the Port Status


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----End
Viewing the Clock Source Received at a Port

Step 1 Query the clock source received at a port.
----End

within the entire network. Using the U2000, you can monitor the clock tracing
status of each NE.
Prerequisites
Context

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Procedure
Step 1 In the Main Topology window, select Clock View from the Current View drop-
down list. Select the desired NE from the navigation tree on the left.
Step 2 In Clock View on the right, right-click and choose Search Clock Link from the
shortcut menu.
Step 3 In the Search Clock Link window, set Clock Type and Search Mode, and select
the NE to be queried. Click OK.
----End
4.9.1.9 Parameters: ITU-T G.8275.1 (OSN 1800/8800/9800 Universal Platform

Subrack/M Series Subrack/P Series Subrack/U Series Subrack: U2CTU/S2CTU/
U4CTU)
4.9.1.9.1 Parameters: PTP Protocol

In this window, you can select the time synchronization protocol type used by the
NE based on the network planning.
Navigation Path
On the NE Explorer, select the NE and choose Configuration > Clock > PTP clock
> PTP Protocol from the navigation tree.
Parameters
PTP Protocol Type IEEE-1588v2 and G. Indicates the PTP

8275.1 protocol type used by
the NE.

In this window, you can specify the mode of the frequency source that the NE
traces based on the network planning.
Navigation Path
In the NE Explorer, select the NE and choose Configuration > Clock > Frequency
Source Mode from the navigation tree.

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Parameters

that the NE traces.

subracks on an NE.
Navigation Path
Parameters

slot number-board
name-external clock
name)-slot number-
board name-external
time interface

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cascading port.
synchronization are
set improperly, the
master and slave
port.
inputs/outputs the
unused.

This section describes how to query and set NE and port attributes for a PTP clock
system, including the PTP system time, working mode, inter-packet periods, and
cable transmitting warp.
Navigation Path

WDM OTN
Parameters

parameter.
NE Name Example: NE7183 Displays the NE name.

Type can only be set to T-BC.
devices.

Default value: Disabled Enabled or Disabled to enable
or disable G.8275.1. When it is
set to Enabled, you can
manually configure the port

Adjustment Default value: Enabled parameter according to the
Protocol Packet NMEA, UBX Set and query the format of

Format Default value: UBX external clock protocol packets.
external time port is set to 1PPS
+Time.

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WTR time (min) 0–12 Specifies the time from detection

Default value: 5 of signal recovery to triggered
Local PTP Clock Example: Displays the clock number of the

Supplying Code: 30
NE ID: 007E028B
Current Master Example: Indicates the number of the clock

Ingress of Current Subrack ID (subrack Specifies the local clock input

Master Clock name)-slot ID-board port for the master clock that an
name-port ID (port NE currently traces.
name)

Compensation Default value: Disabled compensation calculation.
Calculation NOTE

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Ring Network Enabled, Disabled Specifies whether to enable

Automatic Default value: Disabled automatic ring network
Compensation compensation.
After this function is enabled, an
NOTE

Port Subrack ID (subrack Specifies the names of the ports

name)
Clock Type T-BC For the clock nodes compliant

with ITU-T G.8275.1, Clock Type
can only be set to T-BC.
devices.

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Step Mode one-step, two-step Specifies whether an ITU-T G.

Default value: one step 8275.1 port works in the one-step
or two-step mode.
mode requires equipment with
high precision and accuracy.
message.
Port Status LISTENING, MASTER, Sets the port preselection status.

PASSIVE, SLAVE

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Current Port MASTER, SLAVE, Displays the actual status of a

Status PASSIVE, LISTENING, source clock port on the service
FAULTY, INITIALIZING, board. The actual status is
UNCALIBRATED computed by the BMC algorithm
based on the clock source quality
and clock priorities.
● SLAVE: Indicates that the port
with the upstream equipment
with the port in the master
state on the path.
maintain synchronization with
the port in the MASTER state.
It is neither in the master state
nor synchronous with the port
in the Master state.
order.
changes from MASTER, SLAVE,
or PASSIVE to FAULTY when a
LOS, AIS, or LinkDown alarm
is reported for the port.
● INITIALIZING: When the WTR
time of the clock source
expires, the port status
changes from MASTER/
SLAVE/PASSIVE to
INITIALIZING.
● UNCALIBRATED: When the
physical-layer clock source of
the port is lost and the
frequency is in the free-run
mode, the port status is
UNCALIBRATED.
Setting rule:

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The system adopts the BMC

algorithm to compute the port
status according to the clock
tracing relations among NEs.
Association with other
parameters:
This parameter is related to the
clock source attributes of the
upstream and downstream NEs
and is calculated by the BMC
algorithm based on the clock
source attributes.
Reference Clock NE clock ID-port ID Specifies the number of the clock

Source No. that is set as the clock source for
the port to trace.
A port processes PTP packets only
when it receives a clock source
with the same number as the
specified clock source. Otherwise,
the port discards the received PTP
packets.
If this parameter is not set for a
port, the port does not match the
clock source number. That is, the
port can receive PTP packets from
all clock sources.

Default value: Enabled set to the Slave state. You can set
the tracing relationship of a
Not Slave, preventing T-GM from
tracing T-BC.
● Disabled: The clock can be set
to the Slave state.

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Destination MAC 01-1B-19-00-00-00, This parameter is used for

Address 01-80-C2-00-00-0E interconnection with other
Default value: devices.
01-1B-19-00-00-00 ● When the port is
addresses of the
be the same.
on the third-party device must
be set to 01-1B-19-00-00-00.
Local Priority 0–255 Specifies the local priority of the

Default value: 128 port. The local priority is not sent
to other ports and is used only
for selecting the path for
transmitting time signals.
indicates a higher priority. During
the time source path selection,
the BMC preferentially selects a
port with a higher priority.


name)

E2E mode.

WDM OTN
SYNC Packet 4/1024, 8/1024, Specifies the interval at which a

Period(s) 16/1024, 32/1024, PTP port transmits Sync packets.
64/1024, 128/1024, The delay-to-respond mechanism
256/1024, 512/1024, 1, uses the Sync, Delay_Req,
2 Follow_Up, and Delay_Resp
For the OSN 1800, the packets to achieve
default value is synchronization between T-BC
64/1024. For other and T-TSC devices.
products, the default
value is 8/1024.
DELAY Packet 64/1024, 128/1024, Specifies the interval at which a

Period(s) 256/1024, 512/1024, 1, PTP port transmits Delay packets.
2, 4, 8, 16 The delay-to-respond mechanism
For the OSN 1800, the uses the Sync, Delay_Req,
default value is Follow_Up, and Delay_Resp
64/1024. For other packets to achieve
products, the default synchronization between T-BC
value is 1. and T-TSC devices.
ANNOUNCE 64/1024, 128/1024, Specifies the interval at which a

Packet Period(s) 256/1024, 512/1024, 1, PTP port transmits ANNOUNCE
2, 4, 8, 16 messages. ANNOUNCE messages
For the OSN 1800, the contain the clock attributes of an
default value is NE and are used to set up a
128/1024. For other synchronous system.
products, the default NOTE
value is 1. When the TN54TOA/TN54THA board
is interconnected with a PTN device
to transmit ITU-T G.8275.1 clock
signals, ANNOUNCE Packet
Period(s) must be set to 64/1028.
Otherwise, after a link fault occurs,
the interconnected PTN device may
fail to trace the clock source.
ANNOUNCE For OSN 8800 Specifies the timeout coefficient

Packet Timeout TN54TOA/TN54THA, of receiving the ANNOUNCE
Coefficient the value ranges from 3 packets on a PTP network. By
to 255. For other default, if the ANNOUNCE
boards, the value packets are not received for four
ranges from 3 to 10. consecutive periods, the packet
For other products, the receiving times out and the link
value ranges from 3 to fails.
255.
For the OSN 1800, the
default value is 3. For
other products, the
default value is 4.

WDM OTN


name)
Warp Direction Positive, Negative Specifies how the time of

Default value: Positive transmission over the cables
between two NEs warps in the
transmit and receive directions.
receive direction is longer than
that in the transmit direction.
direction.

● Length: Indicates that there is
a warp of transmission
between two NEs.
directions on the line between
two NEs.
Warp Length(m) OSN 8800/6800/1800: Specifies the warp of

0–1700000 transmission distance over the
OSN 9800: 0–3555555 cables in the transmit and receive
Default value: 0 During network deployment,
adjust the time synchronization
NOTE

WDM OTN

Default value: 0 transmission time over the cables
Adjust the time synchronization
according to the actual warp in
transmission time.
NOTE
Suggest Positive, Negative Specifies the suggested

Compensate Default value: - compensation direction.
Direction NOTE

Length(m) compensation length.
NOTE

Time(nm) compensation time.
NOTE

Port Slot ID-Board name- Displays the port name of an NE.

Port number(Port
name)
Single-Fiber Two- Disabled, Enabled Specifies whether to enable

Way Dispensation Default value: Disabled single-fiber bidirectional
Compensation dispersion compensation.

WDM OTN
Remote Transmit Example: 1310 Specifies and displays the remote

Wavelength (nm) transmit wavelength.
Setting rule:
when Single-Fiber Two-Way
Dispensation Compensation is
set to Enabled.
Fiber Type Example: 255 Specifies and displays the fiber

type.
Dispersion Slope Egress, Ingress Specifies and displays the type of

Value Type the fiber dispersion slope value
(value K).
Dispersion Slope Example: 93 Specifies and displays the fiber

Value dispersion slope value (value K).
Dispersion Egress, Ingress Specifies and displays the type of

Compensation the fiber dispersion inherent
Value Type compensation (value b).
Dispersion Example: 124150 Specifies and displays the fiber

Compensation dispersion inherent
Value compensation (value b).
NOTE

link status.
Navigation Path

WDM OTN
Parameters

name-optical port
number(optical port
name)

name)-optical port
number(optical port
name)

NE ID: 007E028B

messages from the
no abnormal alarm,

Navigation Path
Clock Subnet tab.
Parameters

WDM OTN
PTP Clock Subnet No. 24-43 Specifies the configured

clock subnet number
subnet.

Navigation Path
tab.
Parameters
Clock Class 6, 7, 13, 14, 52, 58, 68 to Time Quality Level--

parameter value
using the BMC.

A smaller parameter
parameter is
using the BMC.

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Default: clock.
time source.
Indicates the clock
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the Network Time
Protocol (NTP).
manually set.
OR: Indicates an

WDM OTN

1 Default: 128 1--Specifies the basis for
determining the clock
priority. The smaller the
value is, the higher the
clock priority is.
for tracing. This
PTP Clock Source
source for tracing.

source. A smaller
parameter value
indicates a higher
priority.
this parameter
PTP Clock Source Priority
2 value is of higher
quality and is preferred
tracing.

WDM OTN
PTP Clock Source 0 to 65535 PTP Clock Source

Deviation Default: Deviation--Specifies the
● OSN 1800 subrack: clock from the standard
65535 time. A smaller
● Other subracks: 32768 parameter value
clock signals. This
parameter is
using the BMC.
Local Priority 1 to 255 Indicates the port

Default: 128 priority during clock
source selection.

Navigation Path
tab.
Parameters
interface the NE.


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interface with the
an NE.
for the port.


Navigation Path
> External Time Interface from the navigation tree. Click the BMC tab.
Parameters
interface the NE.

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Time Quality Level - Time Quality Level--

Specifies the quality level
parameter value
using the BMC.
Time Precision - Time Precision--Specifies

the time precision of the
A smaller parameter
parameter is
using the BMC.

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Default: clock.
time source.
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the Network Time
Protocol (NTP).
manually set.
OR: Indicates an

WDM OTN

source. A smaller
parameter value
indicates a higher
priority.
this parameter
PTP Clock Source
source for tracing.
Not Slave Enabled, Disabled This parameter is used to

Default: Enabled ensure that the port is
not in the slave state.
The Not Slave can be
planned to ensure that
the tracing relationship
of the synchronization
network is synchronized.
In this case, the T-GM
does not trace the T-BC.
● Enabled: The slave
state is not allowed.
● Disabled: This
parameter can be set
to Slave.

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PTP Clock Source — PTP Clock Source

time. A smaller
parameter value
clock signals. This
parameter is
using the BMC.

Default: 128 the local priority of an
external clock source,
which is manually set.
This parameter is used to
priority. A smaller
parameter value
indicates a higher
priority.
values of PTP Clock
Source Priority 2, Time
Quality Level, Time
Precision, and PTP Clock
Source Deviation, this
smaller Local Priority

Navigation Path

WDM OTN
Parameters
interface the NE.

NOTE
of a port is set to
only Ingress.
of a port is set to
Ingress and Egress.

option to set the
mode for the clock
Time.
If the delay can be
measured, set this
parameter to Time;
otherwise, set this
the transmission
in terms of length.
the transmission
in terms of time.

WDM OTN

to the actual
adjust the delay in
signals.
Set this parameter
according to the
delay can be
receive end and the
distance. If Enable
compensation at the
set only when
In the case of the
case of the receive
the receive end is
compensated.

WDM OTN

synchronization.
In the case of the
case of the receive
the receive end is
compensated.
set only when

Navigation Path
Parameters
Board For example: Indicates the clock

Shelf5(Slave board.
shelf5)-5-54TOA(STND)

WDM OTN

sending PTP and SSM
requirements of the
improving the
NOTE
are not supported.)
NOTE
TN54TOA, TN57TOA,
and TN54THA.
TNF6TOA, TNF2ELOM
(STND).
● OSN 1800 I&II
Compact: TNF2ELOM
(STND).
● OSN 1800 II Enhanced:
TNF2ELOM (STND).

Navigation Path

WDM OTN
Parameters


Compensatio key for
IEEE 1588v2
compensation
value.
NOTE
The value is
displayed as
"********" and
the query is
not
supported.

WDM OTN
New Example: Test_1234 Sets the password for

Password securely returning an IEEE
Value description:
The value contains 12 to 16
characters. It is recommended
that the value contain at
least three types of the
following characters:
● Lower-case letters
● Upper-case letters
● Digits
● Space or special characters
Setting rule:
The values of New Password
and Confirm Password must
be the same.
NOTE
The default key for securely
returning an IEEE 1588v2
compensation value on the
upstream and downstream
devices is HW@_77wa. You are
advised to change the default
key when using the device for
the first time.
Confirm Example: Test_1234 Sets the confirm password for

Password securely returning an IEEE
Setting rule:
The values of New Password
and Confirm Password must
be the same.
4.9.2 Configuring ITU-T G.8275.1(OSN 9800 U Series: U1CTU/

S1CTU)

Figure 4-20 shows the process of configuring an ITU-T G.8275.1 clock.

WDM OTN
Figure 4-20 ITU-T G.8275.1 clock configuration flowchart
Table 4-61 provides the detailed procedures for configuring ITU-T G.8275.1
NOTE
Table 4-61 shows the procedure for configuring ITU-T G.8275.1 phase synchronization. To
implement both frequency and phase synchronization at the physical layer, configure
physical-layer clocks based on 2.9.2.1 Configuration Process of physical-layer clocks and
then configure ITU-T G.8275.1 messages with reference to Table 4-61 to implement phase
synchronization.
Table 4-61 Procedures for configuring ITU-T G.8275.1 frequency and phase
synchronization
Operation Remarks
4.9.2.2 Configuring the PTP Protocol Mandatory.

You can set the PTP clock protocol
networking planning. Ptp Profile can
be set to G.8275.1.
4.9.2.3 Enabling ITU-T G.8275.1 Mandatory.

configuring ITU-T G.8275.1 for an NE.
The number of available licenses is

WDM OTN
Operation Remarks

you need to set the clock
synchronization attributes of each
NE on the U2000, including setting
parameters.
● Configuring clock subnets. When a
into multiple clock domains, clock
subnets must be configured.
● Set the attributes of the local clock.
you must set the local clock
parameters received by the local
NE, so that the clock selection
module can calculate the best
master clock.

transmit or receive G.8275.1 packets
must be configured as PTP ports to
trace PTP clock sources.
parameters of the cable
time cables.

external time signals, you must set
external time interface attributes and
the Cable Transmission Warp
parameter.

WDM OTN
Operation Remarks
4.9.2.7 Querying the Port Status Mandatory.

processes are completed, users need to
query all ports for the clock
synchronization status to ensure that
the port synchronization status is the
same as that defined in the
networking diagram.

each NE.

to G.8275.1.
Prerequisites
Procedure
Step 1 Configure Ptp Profile.
----End

WDM OTN

Before configuring the ITU-T G.8275.1 function for a subrack, you must authorize
Prerequisites
● The license resource of ITU-T G.8275.1 resources is available.
Procedure

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NOTE
ITU-T G.8275.1 and IEEE 1588v2 share the same license resources. ITU-T G.8275.1 is enabled
after IEEE 1588v2 is enabled on the U2000.
----End

To ensure that Precision Time Protocol (PTP) ports of every NE on a network work
correctly, you need to configure PTP clock global parameters, PTP clock subnets,
and local clock attributes.
Prerequisites

each NE on the U2000. The attributes include the PTP working mode, system time,
NOTE
PTP System Time can be successfully set only when the NE traces local clock sources.
Step 2 Configure Protocol Packet Format and Enable Automatic Compensation

Measurement to set them. For details on parameter settings, see 4.9.2.9.1

WDM OTN
Parameters: Global Configuration.
----End

subnets when planning the clock network. Within each subnet, time
synchronization can be implemented for all clocks to satisfy customers'
requirements.
subnet. The messages sent from different clock subnets are discarded by the NE.
Step 1 Configure in PTP Clock Subnet. For details on parameter settings, see 3.9.2.8.3

WDM OTN
NOTE
● Devices in the T-BC working mode can belong to only one clock subnet, and its clock
source can be selected only from the same clock subnet.
----End

You can configure the clock attributes of the local clock sources received at the NE
so that the best master clock (BMC) can be calculated by the clock selection
module.
Step 1 Configure Clock Source Type, Clock Source Priority 2, and Ptp Local Priority to
set them. For details on parameter settings, see 4.9.2.9.5 Parameters: BMC
(Clock Subnet).
----End

To ensure that Precision Time Protocol (PTP) ports of each NE on a network work
correctly, you need to create clock ports, configure attributes of PTP messages,
and specify the cable transmission deviation of PTP clock ports.
Prerequisites
● Required boards have been created.

● A clock port can be used to trace the PTP clock source. Clock ports are created
to enable a PTP clock port so that PTP packets can be received.

WDM OTN
● The clock port is used to synchronize the time between two clock nodes.
Depending on the actual networking, several clock ports can be created for a
board to connect to other clock nodes.
Step 1 Configure a clock port. For details on parameter settings, see 4.9.2.9.2
----End

This operation specifies the priority of each required clock source. This provides a
criterion for selecting clock sources in case of a clock switching event.
Step 1 Configure Clock Source WTR Time(min).
NOTE
You can set Clock Source WTR Time(min) to 0-12 minutes, with a step of 1 minute. The
default value is 5.

WDM OTN
Step 2 Configure Port, Clock Source No, and Clock Source PortNo.
----End
Configuring the PTP Message Attributes

To ensure the normal operation of the PTP clock for each NE in the network, you
of each NE.
Step 1 Select a port and the set the following parameters for the port: SYNC Packet
Period(s), DELAY Packet Period(s), ANNOUNCE Packet Period(s), and
ANNOUNCE Packet Timeout Coefficient. For details on parameter settings, see

WDM OTN
NOTE
In ITU-T G.8275.1, P/E Mode can be set only to E2E.
----End
Configuring the Cable Transmission Deviation for the Clock Port

When the transmission time or length configurations of a cable in the receive and
transmit directions are inconsistent, the transmission deviation of a cable needs to
be set to rectify the PTP clock synchronization process and therefore ensure the
clock synchronization precision.
The transmission deviation of the cable means the cable transmission time
difference of the clock signals in the receive and transmit directions between two
NEs. The cable transmission deviation can be represented by time or by length.
Step 1 Select a port and set the following parameters: Warp Direction, Warp Mode,
Warp Length(m), and Warp Time(ns). For details on parameter settings, see

WDM OTN
NOTE
● The Warp Length(m) parameter is available only when Warp Mode is set to Length.
The Warp Time(ns) parameter is available only when Warp Mode is set to Time.
● The values of Warp Length(m) and Warp Time(ns) are set based on the actual
networking situation.
----End

clock source attributes include the attributes of external time ports, and cable
transmission distance permitted by an external time port.
Prerequisites
● The CTU boards have been created.

When there are external time sources for an NE, set the attributes of the external
time sources so that the clock selection module of the NE can calculate the best
master clock (BMC).

WDM OTN
Step 1 Select an external time interface and set the External Time Interface Direction
and Interface Protocol Type parameters. For details on parameter settings, see
4.9.2.9.6 Parameters: Basic Attribute.
Step 2 Configure Bits Type and Bits Clock Class Level. For details on parameter settings,
----End

Interface
Step 1 Select an external time interface and set the following parameters: Input Warp
Mode, Input Warp Length(m), Input Warp Time(ns), Output Warp Mode,

WDM OTN
Output Warp Length(m), and Output Warp Time(ns). For details on parameter
settings, see 3.9.2.8.7 Parameters: Cable Transmitting Distance.
NOTE
● The Input Warp Length(m) parameter is available only when Input Warp Mode is set
to Length; the Input Warp Time(ns) parameter is available only when Input Warp
● The Output Warp Length(m) parameter is available only when Output Warp Mode is
set to Length; the Output Warp Time(ns) parameter is available only when Output
● Input Warp Length(m), Output Warp Length(m), Input Warp Time(ns), and Output
Warp Time(ns) needs to be set based on the actual network situations.
----End
4.9.2.7 Querying the Port Status

The U2000 supports the function of querying the clock source traced by a port.
Using this function, you can query the tracing status of the NE time.
Prerequisites

WDM OTN
Procedure
Step 1 Query the clock source received at a port.
----End

within the entire network. Using the U2000, you can monitor the clock tracing
status of each NE.
Prerequisites
Context
Procedure
Step 1 In the Main Topology window, select Clock View from the Current View drop-
down list. Select the desired NE from the navigation tree on the left.
Step 2 In Clock View on the right, right-click and choose Search Clock Link from the
shortcut menu.
----End
4.9.2.9 Parameters: ITU-T G.8275.1 (OSN 9800 U Series: U1CTU/S1CTU)


WDM OTN
4.9.2.9.1 Parameters: Global Configuration

In this window, you can configure and query the global attributes of the PTP clock
system, including the PTP system time, working mode, and PTP protocol mode.
Navigation Path
> Global Configuration from the navigation tree.
Parameters
Table 4-62 Global Configuration

parameter.

Type can be set only to T-BC.
devices.
Enable Automatic Enable, Disable On a ring network, the NE can

Compensation Default: Disable automatically calculate the
Measurement asymmetry values of repaired
fibers after a fiber cut or fiber
adjustment occurs, without
requiring manual measurement.
You only need to manually set
the compensation parameters so
that the NE time and GPS are
synchronous.
NOTE
NG WDM products do not support
this parameter.

WDM OTN
Protocol Packet NMEA, UBX Sets and queries the format of

Format Default: UBX an IEEE 1588 clock protocol
message.
1PPS+Time.
Local Clock Source Example: Displays the clock number of the

No. 00259e30007d0050 local clock source of the NE.
Current Master Example: Current Master Clock No.--

Clock No. 00259e30007d0050 Indicates the number of the
clock source traced by the NE,
that is, the number of the
master clock traced by the NE
source.
Ingress of Current Example: PTP Specifies the local clock input

Master Clock port for the master clock that an
NE currently traces.
Hops of Current Example: 2 Indicates the number of hops

Master Clock traversed when the current
master clock is transmitted to
the current NE.
For example, the clock
transmission sequence on
devices A, B, C, and D is A->B-
>C->D. If device A is the clock
source, the number of hops for
the current master clock on
device D is 3.

Navigation Path

WDM OTN
Parameters


synchronized.

mode.
PTP Packet 01-1B-19-00-00-00, This parameter is used for

Destination MAC 01-80-C2-00-00-0E interconnection with other
Address Default value: devices.
00-00-00-00-00-00 ● When the port is
addresses of the
be the same.
on the third-party device
must be set to
01-1B-19-00-00-00.

IP Address
PTP Packet - -
Destination IP
Address
Port Prefigure MASTER+SLAVE, Sets the preconfiguration status

Status MASTER, SLAVE of a port.
Default value: MASTER
+SLAVE

WDM OTN
Current Port Master, Slave, Passive, Displays the actual port status.
Status Listening
Port Manual Master, Slave, Passive, Specifies the status of the clock
Status Listening source port on the service board.
Default value: The BMC algorithm computes
Listening the port status based on the
quality and priority of the clock
source.
Step Mode one step, two step Sets the one-step or two-step
Default value: one mode for an IEEE 1588 port.
step Only tributary boards support
the setting of one-step or two-
step mode.
accuracy.
message.
PTP port type T-BC Displays the PTP port model.
PTP Status Enabled Displays the PTP status of a

port, that is, whether the port
supports access of PTP packets.

Default value: Enabled set to the Slave state. You can
set the tracing relationship of a
Not Slave, preventing T-GM
from tracing T-BC.
● Disabled: The clock can be

WDM OTN
Bits Local Priority 0–255 Specifies the local priority of a

Default value: 128 local port. The priority is used
transmission path and will not
be sent to another port.
indicates a higher priority.
During the time source path
selection, the BMC preferentially
selects a port with a higher
priority.


synchronized.

E2E mode.
SYNC Packet 4/1024, 8/1024, The SYNC Packet Period(s)

256/1024, 512/1024, 1, port transmits Sync packets. The
2 delay-to-respond mechanism
Default value: 64/1024 uses the Sync, Delay_Req,
packets to achieve
and T-TSC devices.

Default value: 1 port transmits Delay packets.
The delay-to-respond
and T-TSC devices.

WDM OTN

Packet Period(s) 256/1024, 512/1024, 1, Period(s) parameter provides an
2, 4, 8, 16 option to set the period at which
Default value: 1 the PTP port transmits
ANNOUNCE packets. The
clock attributes of an NE and are
used to set up a synchronous
system.
ANNOUNCE 3–10 Specifies the timeout coefficient

Packet Timeout Default value: 4 for receiving ANNOUNCE
Coefficient packets.
If a port does not receive
period specified by the
parameter, it determines that
the link fails.


synchronized.
Warp Direction Positive, Negative Indicates the transmission time

Default value: Positive difference between the cables in
direction.
direction.

WDM OTN

between two NEs.
between two NEs.
Warp Length(m) 0–3555555 Specifies the warp of

Default value: 0 transmission distance over the
distance.
NOTE

Default value: 0 transmission time over the
time.
NOTE

receive direction.

WDM OTN
Actual Example: 10 The value depends on the

Measurement corresponding warp mode
Warp (ns) (length or time).
If the warp of transmission time
directions of a fiber/cable
between two NEs is the same,
Actual Measurement Warp
(ns) and Accept Actual
Measurement Warp are
unavailable.
Accept Actual Example: 10 Indicates the acceptable warp

Measurement range. No warp compensation is
Warp required if the warp is within
this range.

link status.
Navigation Path
tab.
Parameters


receives.

messages from the
the status is Down.

WDM OTN

Navigation Path
> Clock Subnet Configuration from the navigation tree. Click the Clock Subnet
tab.
Parameters
Clock Subnet No. 0-255 Specifies the configured

clock subnet number
subnet.

Navigation Path

WDM OTN
Parameters
Default: clock.
time source.
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the Network Time
Protocol (NTP).
manually set.
OR: Indicates an

WDM OTN

source. A smaller
parameter value
indicates a higher
priority.
Level are the same, this
smaller PTP Clock
Source Priority 2 value
is of higher quality and is
source for tracing.

Default: 128 the local priority of a
manually set. This
priority. A smaller
parameter value
indicates a higher
priority.
values of PTP Clock
Source Priority 2 and
Time Quality Level are
the same, this parameter
priority. That is, the clock
Local Priority value is of
source for tracing.

WDM OTN

the interface attributes of the external clock source so that the NE can extract the
Navigation Path
In the NE Explorer, select the NE and choose Configuration > Clock > PTP clock >
External Time Interface from the navigation tree. Click the Basic Attribute tab.
Parameters

source on the NE.

WDM OTN

External Time Interface external clock port are as
follows:
● Configuration
management of 2M
clock sources in the
input and output
directions
● Configuration
management of 2M
output clock sources
● 2M clock sources can
function as the
reference clock
sources for system
frequency
synchronization
The features of an
external time port are as
follows:
input/output
direction, protocol
type, and interface
time interface.
time, and can also
function as the
for restoring the
system clock
frequency.


WDM OTN
Interface Protocol Type 1PPS+Time Interface Protocol Type--

Default: 1PPS+Time Specifies the interface
protocol type of an
external time source on
an NE. 1PPS+Time
indicates that the second
frame header
information and time
information are
transmitted separately.
Status is set to
Disabled.

Navigation Path
Parameters

source on the NE.

WDM OTN

level of an external time
port.
● Manual: You can
quality level of an
external time port
based on the value of
Bits Quality Level.
● Auto: The NE
software can
automatically obtain
the time quality level
of an external time
port based on the
1PPS status and the
conversion table.
Bits Quality Level 0-255 Indicates the actual time

quality level of an
external time interface.
Bits Clock Class Level 0-255 Bits Clock Class Level--

Default: 6 Specifies the quality level
parameter value
level.
for tracing. The clock
Bits Clock Class Level

WDM OTN
Bits Precision 0-255 Bits Precision--Specifies

A smaller parameter
time precision.
values of Bits Clock
Class Level of two clock
smaller Bits Precision
value has higher clock
as the time source for
tracing.

WDM OTN
Bits Time Source ATOMIC_CLOCK, GPS, Bits Time Source--

Default: GPS clock.
time source.
source synchronized
through any of the
radio distribution
systems that
distribute time and
frequency tied to
international
standards.
the PTP protocol.
the Network Time
Protocol (NTP).
manually set.
OR: Indicates an

WDM OTN
Bits Priority 2 0-255 Bits Priority 2--Specifies

Default: 128 the auxiliary priority of
the clock source. A
indicates a higher
priority.
values of Bits Time
Source and Bits
Precision of two clock
this parameter
source quality. That is,
smaller Bits Priority 2

WDM OTN
Bits Local Priority 0-255 Bits Local Priority--

Default: 128 Specifies the local
priority of an external
manually set. This
priority. A smaller
parameter value
indicates a higher
priority.
values of Bits Priority 2,
Bits Quality Level, and
Bits Precision of two
clock sources are the
source priority. That is,
smaller Bits Local
Priority value is of
source for tracing.

Navigation Path
Parameters

source on the NE.

WDM OTN
Input Warp Mode Length, Time Specifies the

mode for the time
interface in the input
value can be set to
Length or Time.
Input Warp Length(m) 0-300 Specifies the length of

Default: 0 the cable in the input
time source. This
parameter is set as
transmission.
Input Warp Time(ns) 0 to 1350 Specifies the delay in

the input direction. This
parameter is set as
Output Warp Mode Length, Time Specifies the

mode for the time
interface in the output
value can be set to
Length or Time.
Output Warp Length(m) 0-300 Specifies the length of

Default: 0 the cable in the output
time source. This
parameter is set as
transmission.
Output Warp Time(ns) 0-1350 Specifies the delay in

the output direction. This
parameter is set as

WDM OTN
Clock Synchronization Feature Guide 5 High-Precision Clock Synchronization Solution
5 High-Precision Clock Synchronization

Solution
Huawei WDM/OTN products support the high-precision clock synchronization

solution.
5.1 High-Precision Clock Synchronization Solution

The WDM/OTN high-precision clock synchronization solution meets the new time
accuracy requirements of service networks.
Definition
High-precision clock synchronization means that on the PTP time synchronization
network that complies with IEEE 1588v2 or ITU G.8275.1, the performance of each
clock node meets the requirements of ITU G.8273.2 Class C.
Figure 5-1 WDM/OTN high-precision clock synchronization example

WDM OTN
NOTE
This document describes the high-precision clock synchronization solution (high-precision

time synchronization solution). Before reading this document, you should get familiar with
the basic concepts and principles of IEEE 1588v2 and G.8275.1.
In this document, common precision complies with the basic requirements of IEEE 1588v2,
and high precision complies with the requirements of ITU-T G.8273.2 Class C. In some
scenarios, clock synchronization that complies with ITU-T G.8273.2 Class C or higher
standards is also called ultra-high-precision clock synchronization.
Objectives and Benefits

WDM/OTN devices supporting high-precision clock synchronization bring the
following benefits:
● Meet the synchronization requirements of new services such as inter-site
coordination on 5G NR mobile communication networks.
● Support a longer holdover time in the case of a typical clock link (a maximum
of 20 transmission network nodes) when the primary reference clock (PRC)
fails.
● Support more nodes on a clock link in specific scenarios when the
requirement for end-to-end synchronization precision remains unchanged.
● Reduce the dependency on space-based time synchronization devices (such as
GPS antennas and satellite cards) that are based on the Global Navigation
Satellite System (GNSS). Alternatively, form a ground time synchronization
network to provide protection and backup for a space-based time
synchronization network.
● Improve the positioning accuracy based on mobile communication networks
and support more new applications.
NOTE
Typically, a BITS device can function as both a PRC and a primary reference time clock
(PRTC). Its frequency source is an atomic clock, and its time source can be obtained from
the GNSS.
● It is recommended that core WDM/OTN devices obtain time synchronization signals
from the PRTC through PTP ports and the PRTC also function as the GM clock (defined
as T-GM in G.8275.1) in the PTP time domain.
● Core WDM/OTN devices can also obtain time synchronization signals from other PTP
devices such as PTN devices or core routers through PTP ports. However, it is
recommended that WDM/OTN devices be directly connected to the PRTC.
The GNSS includes the Global Positioning System (GPS), BeiDou Navigation Satellite
System, and GLONASS, which can provide precise UTC time source signals.
5.2 Networking Schemes

Figure 5-2 and Table 5-1 show the typical high-precision clock synchronization
networking schemes supported by WDM/OTN devices.

WDM OTN
Figure 5-2 High-precision clock synchronization networking schemes
NOTE
You can configure BITSs at multiple core nodes to enhance the protection for reference
clock/time sources.
Table 5-1 High-precision clock synchronization scenarios

Scenario Applicable Scheme Description Typical
Configuratio
n
(A) Reference A.1 Dedicated PTP Dedicated PTP Synchronization Ports 5.3.1
clock input Synchronization support synchronous Ethernet and IEEE Reference
Port (HP optical 1588v2/G.8275.1 and can implement Clock Input
port) both frequency synchronization and
interconnection time synchronization.
(B) Inter-site B.1 Single-fiber Single-fiber bidirectional high-precision 5.3.3 Inter-

clock bidirectional high- OSC modules (BIDI) with an operating Site Clock
synchronization precision OSC wavelength of 1506 nm/1514 nm are Synchronizat
interconnection used to implement both frequency ion
synchronization and high-precision time
synchronization between sites.

WDM OTN

Configuratio
n
(C) Intra-site C.1 Dedicated PTP Dedicated PTP Synchronization Ports can 5.3.2 Intra-
clock Synchronization only be used for clock synchronization, Site Clock
synchronization Port (HP optical and can implement both frequency Synchronizat
port) synchronization and time ion
interconnection synchronization. Dedicated PTP
Synchronization Ports cannot be used to
transmit services.
● If clock cascading is implemented
between master and slave subracks
on the same NE, the Dedicated PTP
Synchronization Ports work in
cascading mode.
● If NEs are interconnected through
Dedicated PTP Synchronization Ports,
the Dedicated PTP Synchronization
Ports work in non-cascading mode.
C.2 Ethernet service If Ethernet service ports are

port interconnected in back-to-back mode
interconnection between WDM/OTN devices at a site,
the Ethernet service ports that support
synchronous Ethernet and IEEE
1588v2/G.8275.1 can be used to
implement both frequency
synchronization.
(D) Client-side D.1 Ethernet service WDM/OTN devices can interconnect 5.3.4 Client-
clock port with client-side devices such as base Side Clock
synchronization interconnection stations or routers through Ethernet Synchronizat
service ports that support synchronous ion
Ethernet and IEEE 1588v2/G.8275.1 to
synchronization.
D.2 Dedicated PTP When Ethernet service ports (for

Synchronization example, inventory service ports) do not
Port (HP optical support high-precision clock
port) synchronization, WDM/OTN devices can
interconnection interconnect with client-side devices
such as base stations or routers through
Dedicated PTP Synchronization Ports to
synchronization.

WDM OTN

Configuratio
n
(E) OLA site E.1 Clock pass- Frequency signals and PTP time packets 5.3.5 OLA
clock schemes through over OSC are transparently transmitted from Site Clock
upstream OSC ports to downstream OSC Schemes
ports. NEs do not participate in
synchronization.
E.2 Clock If an OLA site needs to output clock/

synchronization time signals to other devices, configure
over OSC the site to work in synchronization
mode.
NOTE
This table provides typical clock synchronization schemes for each scenario. In actual deployment, select one
scheme to implement synchronization. Multiple channels of signals or multiple schemes can be used for
protection.
5.3 Typical Configuration Scenarios
5.3.1 Reference Clock Input

This topic describes the typical scheme for configuring core nodes to receive
master reference clock sources, as listed in Table 5-2.
Table 5-2 Typical configuration (for reference clock input)

Scenario Board (Port) Port Diagram
Reference clock TNG3CXP, TNG4CXP HP1, HP2 Figure 5-3

input on the
M24 subrack
Reference clock TME1CTU, TME2CTU HP1, HP2 Figure 5-4

input on the
M12 subrack TME3CTU HP1
TMF3AUX01 HP1
Reference clock TMP2CTU, TMP3CTU HP1, HP2 Figure 5-5

input on the
P32/P32C
(OXC) subrack
Reference clock TNU4CTU, TNU5CTU TX1/RX1, TX2/RX2 Figure 5-6

input on the
U32E/U64E
subrack

WDM OTN
Scenario Board (Port) Port Diagram
Reference clock TMK5SXCH, TMK5XCH, HP1, HP2 Figure 5-7

input on the TMK6XCH, TMK5UXCME,
1800 V Pro TMK6UXCM
subrack
5.3.1.1 Reference Clock Input on the M24 Subrack

The M24 subrack can receive reference clock signals through the Dedicated PTP
Synchronization Port.
Figure 5-3 Reference clock input on the M24 subrack (through the Dedicated PTP
Synchronization Port)
5.3.1.2 Reference Clock Input on the M12 Subrack

The M12 subrack can receive reference clock signals through the Dedicated PTP
Synchronization Port.
NOTE
In the following figure, the CTU board is used as an example. The TMF3AUX01 board can
also be used. One E1CTU/E2CTU board provides two Dedicated PTP Synchronization Ports,
and one E3CTU/F3AUX01 board provides only one Dedicated PTP Synchronization Port.

WDM OTN
Figure 5-4 Reference clock input on the M12 subrack (through the Dedicated PTP
Synchronization Port)
5.3.1.3 Reference Clock Input on the P32/P32C Subrack

The P32/P32C subrack can receive reference clock signals through the Dedicated
PTP Synchronization Port.
Figure 5-5 Reference clock input on the P32/P32C subrack (through the Dedicated
PTP Synchronization Port)
5.3.1.4 Reference Clock Input on the U32E/U64E Enhanced Subrack

The U32E/U64E enhanced subrack can receive reference clock signals through the
Dedicated PTP Synchronization Port.

WDM OTN
Figure 5-6 Reference clock input on the U32E/U64E enhanced subrack (through
the Dedicated PTP Synchronization Port)
5.3.1.5 Reference Clock Input on the 1800 V Pro Subrack

The 1800 V Pro subrack can receive reference clock signals through the Dedicated
PTP Synchronization Port.
Figure 5-7 Reference clock input on the 1800 V Pro subrack (through the
Dedicated PTP Synchronization Port)
5.3.2 Intra-Site Clock Synchronization

For multiple WDM/OTN devices at a site, you can configure clock synchronization
based on the site requirements.
Clock Synchronization Between Master and Slave Subracks

For master and slave subracks on the same NE, Dedicated PTP Synchronization
Ports can be used to enable inter-subrack clock synchronization, as shown in
Figure 5-8 and Figure 5-9.
● It is recommended that the clock center subrack be used for receiving the
external clock source. The clock center subrack can synchronize with the clock

WDM OTN
of an upstream NE using the OSC board, or synchronize with the clock of an

upper-layer NE or intra-site BITS using the Dedicated PTP Synchronization
Ports.
● The Dedicated PTP Synchronization Ports used for interconnection between
the master and slave subracks must be set to the cascading mode.
● If Dedicated PTP Synchronization Ports are used for intra-site clock
synchronization, it is recommended that the clock center subrack be directly
connected to the clock source to reduce the number of NEs on the clock link.
If the subrack supports multiple Dedicated PTP Synchronization Ports, two
connections can be deployed to implement protection.
● It is recommended that a star or tree topology with protection links be used
for inter-subrack clock synchronization. It is recommended that the number of
subracks on an intra-site clock synchronization link be fewer than or equal to
three. (That is, cascading can be performed twice at most.) If there are a large
number of subracks, you are advised to configure clock distribution boards to
enable the star topology. On the OSN 1800, the TMB1AUX/TMB2AUX board
supports a maximum of 4 Dedicated PTP Synchronization Ports.
NOTE
In the following figures, HP ports are used as Dedicated PTP Synchronization Ports. The
number and names of Dedicated PTP Synchronization Ports vary depending on the board
type. For details, see 5.4.1 Dedicated PTP Synchronization Port (HP Optical Port).
When a board supports multiple HP ports, you are advised to configure active/standby
protection. If a site supports only one HP port, first/last node protection can be configured.
Figure 5-8 Example of intra-site clock synchronization (Dedicated PTP

Synchronization Ports for both external clock source input and interconnection)

WDM OTN
Figure 5-9 Example of intra-site clock synchronization (OSC ports for external
clock source input and Dedicated PTP Synchronization Ports for interconnection)
Inter-NE Clock Synchronization

For multiple NEs at a site, Dedicated PTP Synchronization Ports can be used to
enable clock synchronization. In this case, the inter-NE connections for clock
synchronization are similar to those in the reference clock input scenario. For
details, see 5.3.1 Reference Clock Input.
● If master and slave subracks are configured on NEs, you are advised to
connect the NEs through the clock center subrack to implement clock
synchronization.
● The Dedicated PTP Synchronization Ports used for interconnection between
NEs must be set to the non-cascading mode.
NOTE
If WDM/OTN devices at a site need to transmit clock synchronization signals to other

bearer network devices such as PTN devices, see 5.3.4 Client-Side Clock Synchronization.
5.3.3 Inter-Site Clock Synchronization

In the high-precision clock synchronization solution, high-precision OSC (1506 nm/
1514 nm) interconnection is required for inter-site clock synchronization.
High-precision OSC (1506 nm/1514 nm) interconnection uses the single-fiber
bidirectional transmission mode. One OSC or two OSCs can be configured based
on the board capability and network plan.
NOTE
For details about the number of high-precision OSCs supported by a board, see the
Hardware Description.

WDM OTN
Figure 5-10 Inter-site clock synchronization (high-precision OSC interconnection)
5.3.4 Client-Side Clock Synchronization

In the high-precision clock synchronization solution, WDM/OTN devices can
transmit clock signals to client-side devices through service ports and Dedicated
PTP Synchronization Ports.
● It is recommended that service ports be used to implement client-side clock
synchronization.
– For details about service boards that support high-precision clock
synchronization on WDM/OTN devices, see 5.6 Availability.
– For OTN tributary ports (on OTN tributary boards or OTU boards), the
service types and mapping paths of the ports must meet the
requirements described in Table 5-4.
– For details about the port service types supported by a board, see the
functions and features of the board in Hardware Description.
● If service ports do not support high-precision clock synchronization, Dedicated
PTP Synchronization Ports can be used.
NOTE
When service ports work in FlexE mode, high-precision clock synchronization is not
supported. In this scenario, Dedicated PTP Synchronization Ports can be used to connect to
customer devices and implement high-precision clock synchronization.

WDM OTN
Figure 5-11 Example of client-side clock synchronization
5.3.5 OLA Site Clock Schemes

If an OLA site (or ROADM/FOADM site) does not need to output clock signals to
other devices, clock pass-through can be configured.
In clock pass-through mode, the physical clock information and PTP time
synchronization packets received by upstream OSC ports are transparently
transmitted to downstream OSC ports, and the NE does not participate in clock
synchronization.
● For OLA clock pass-through sites, the mapping between the source and sink
OSC ports need to be specified. Clock pass-through can be configured only
between ports on the same AST2/AST4 board.
● For OLA clock synchronization sites, OSC ports need to be configured as the
clock source and time source, which is similar to the inter-site clock
synchronization scheme.

WDM OTN
Figure 5-12 Clock scheme for OLA sites
NOTE
● Clock pass-through is bidirectional. That is, clock and time signals can be transparently
transmitted in both RM1->TM2 and RM2->TM1 directions.
● In the preceding figure, one OSC is configured in each direction. The scheme for dual-
OSC configuration is similar.
● For OLA sites on the same OMS, if single-fiber bidirectional OSC interconnection is
configured, the OLA sites must use the OSC ports connecting to the same fiber for clock
pass-through or synchronization.
5.4 Ports Supporting High-Precision Clock

Synchronization
NOTE
In the high-precision clock synchronization solution, external clock ports or external time
ports cannot be used for synchronization.
5.4.1 Dedicated PTP Synchronization Port (HP Optical Port)

Dedicated PTP Synchronization Port, also called ultra-high-precision clock PTP
synchronization port, supports high-precision clock synchronization. In some
scenarios, it is also called clock synchronization GE optical port or HP optical port.
Dedicated PTP Synchronization Port supports both physical clock synchronization
and PTP time synchronization and both common-precision PTP and high-precision
PTP, but does not support Ethernet service transmission. Table 5-3 lists the boards
that support Dedicated PTP Synchronization Ports.
Table 5-3 Dedicated PTP Synchronization Port
Product Type Board Name Port Silkscreen

WDM OTN
Product Type Board Name Port Silkscreen
OSN 9800 M12 TME3CTU, TMF3AUX01 HP1

OSN 9800 M05
OSN 9800 M24 TNG2AST4 HP1 (HP2)

OSN 9800 M12
OSN 9800 M05
OSN 9800 U32E/U64E TNU4CTU, TNU5CTU TX1/RX1, TX2/RX2
OSN 1800 V Pro TMB1AUX, TMB2AUX HP1 (HP2), HP3

OSN 1800 II Pro (HP4)
OSN 1800 II TP TMB1MD48AFS HP1 (HP2)

TMK6XCH, TMK5UXCME,
TMK6UXCM, TMK5GSCC
NOTE
a: The HP1 (HP2) port of the TMK5SXCH, TMK5XCH, TMK5UXCME, TMK6UXCM, and
TMK5GSCC boards supports the clock synchronization GE optical port function since
V100R022C00SPC100.
5.4.2 High-Precision OSC Port (1506 nm/1514 nm)

High-precision OSC ports (1506 nm/1514 nm) can transmit OSC signals and clock/
time signals at the same time. Only specific OSC boards support high-precision
clock synchronization. On OSC ports, PTP messages and SSM messages are
transmitted in proprietary protocol overheads.
For details about the OSC boards that support high-precision clock
synchronization, see 5.6 Availability.
5.4.3 Ethernet Service Port

Ethernet service ports include OTN tributary ports (Ethernet service mode) on
OTN tributary boards and OTU boards and Ethernet service ports on packet
boards.
Only Ethernet service ports on specific boards support high-precision clock

synchronization.
● For details about service boards that support high-precision clock

synchronization on WDM/OTN devices, see 5.6 Availability.
● For OTN tributary ports (on OTN tributary boards or OTU boards), the service
types and mapping paths of the ports must meet the requirements described
in Table 5-4.

WDM OTN
● For details about the port service types supported by a board, see the
functions and features of the board in Hardware Description.
NOTE
When service ports work in FlexE mode, high-precision clock synchronization is not
supported. In this scenario, Dedicated PTP Synchronization Ports can be used to connect to
customer devices and implement high-precision clock synchronization.
Table 5-4 Requirements of the high-precision clock synchronization solution for

the service types and mapping paths of OTN tributary ports
Port Service Type Service Mapping Path Encapsulation
Mode
GE GE (GFP-T) GFP-T
10GE LAN MAC transparent mapping GFP-F

(10.7G)
25GE MAC transparent mapping GFP-F
50GE MAC transparent mapping GFP-F
100GE MAC transparent mapping ODU4 GFP-F

(100G)
200GE MAC transparent mapping MAC (IMP)

(inverse multiplexing)
5.5 Specifications
High-precision clock synchronization performance complies with ITU-T G.8273.2
Class C.
NOTE
This topic describes only the special requirements for high-precision clock synchronization.
For details about general specifications, see 3.5 Specifications of 3 IEEE 1588v2 (OTN &
Packet) and 4.5 Specifications of 4 ITU-T G.8275.1/G.8273.2 (OTN & Packet) .
Table 5-5 High-precision clock synchronization specifications

Item IEEE 1588v2 Protocol ITU G.8275.1 Protocol
Clock model NE working mode: BC, OC NE working mode: T-BC

Port working mode: BC, OC Port working mode: T-BC
Clock source BMC Algorithm Alternate BMC algorithm

selection
algorithm

WDM OTN
Item IEEE 1588v2 Protocol ITU G.8275.1 Protocol
PTP port type ● Dedicated PTP Synchronization Port: GE optical port

● OSC port (1506 nm/1514 nm)
boards): GE, 10GE, 50GE, 100GE, and 200GE optical ports
● Ports on packet boards: GE, 10GE, and 100GE optical
ports
NOTE
● OTN tributary ports support PTP time synchronization only when
the service mapping path requirements are met. For details, see
Table 5-4.
● When an OTN tributary port works in FlexE mode, it does not
support high-precision clock synchronization.
Delay ● Dedicated PTP Synchronization Port: E2E mode, two-step

measurement mode
● OSC port: E2E mode. The step mode cannot be set.
boards): E2E mode, two-step mode
● Ports on packet boards: E2E mode, two-step mode
Packet ● PTP packet encapsulation formats: Ethernet 802.3 (PTP

encapsulation ETH), UDP/IPv4 (PTP IP)
format ● PTP packet VLAN IDs: supported
NOTE
● For ports on packet boards, the encapsulation format of PTP
packets can be set to PTP ETH or PTP IP, and the VLAN IDs can
be set.
● When receiving Ethernet services, OTN tributary ports only
support the PTP ETH encapsulation mode, and VLAN IDs can be
set.
● Dedicated PTP Synchronization Ports only support the PTP ETH
encapsulation mode, and VLAN IDs can be set.
● OTN line ports and OSC ports transmit PTP packets through
overhead bytes, and neither encapsulation format nor VLAN ID is
involved.
Clock Dedicated PTP Synchronization Ports are used to implement

synchronization inter-subrack synchronization.
between master
and slave
subracks

Item Specifications
Level Class A Class B Class C

WDM OTN
Item Specifications
Absolute time offset (Max|TE|) 100 ns 70 ns 30 ns
Fixed time offset (cTE) ±50 ns ±20 ns ±10 ns
Low-frequency MTIE 40 ns 40 ns 10 ns
jitter time offset
(dTEL) TDEV 4 ns 4 ns 2 ns
High-frequency jitter time 70 ns 70 ns (To be

offset (dTEH) determined)
Noise transfer PTP-to- It is a low-pass feature. The low-pass cutoff

PTP frequency ranges from 0.05 Hz to 0.1 Hz, and
the passband gain is less than 0.1 dB.
SyncE-to- It is a band-pass feature. The low-pass cutoff

PTP frequency ranges from 0.05 Hz to 0.1 Hz, the
high-pass cutoff frequency ranges from 1 Hz to
10 Hz, and the passband gain is less than 0.2
dB.
5.6 Availability
This topic describes the license requirements for the high-precision clock
synchronization solution, and corresponding devices, boards, and versions.

An NE can implement the high-precision clock synchronization function only after
obtaining the corresponding license.
Table 5-7 License support for high-precision clock synchronization

License Code Name Applicable Product
82601633 Frame high-precision clock Function OSN 9800

Fee (per board)
82601559 Chassis high-precision clock Function OSN 1800

Fee (per board)
NOTE
High-precision clock synchronization is based on IEEE 1588v2. Therefore, in addition to the

preceding licenses, the IEEE 1588v2 license is required. For details, see 3.4.1 License
Support.

WDM OTN

Table 5-8 Boards and versions that support high-precision clock in OSN 9800 M
series subracks
Clock board TNG3CXP, TNG4CXP, TNG5CXP, V100R021C10

TMF1AUX, TMF2AUX01, TMF3AUX01,
TME1CTU, TME2CTU, TME3CTU
OSC board (OSC TNG2AST4, TNG3OH20H, V100R021C10

unit) TNG2OH20H, TNG2AST4E
TNG2OH9a (OSC unit) V100R022C00
OTU board TNG1M520SM, TNG1M520S V100R021C10

TNS5NP400Y
Tributary board TNV6T216, TNV6T230, TNV1T502, V100R021C10

TNV1T402E, TNV3T220E, TNV1T402X,
TNG3A204, TNV6G216, TNV6G230,
TNV7S216, TNV3E224, TNV3E402,
TNV3E404
TNV4E404, TNV4E224 V100R022C00
TNG1T210E V100R022C10
NOTE
● For OTN tributary ports (on OTN tributary boards or OTU boards), the service types and
mapping paths of the ports must meet the requirements described in Table 5-4.
● T216/T230/T220E/G216/G230: Only ports 1 to 15 support PTP synchronization.
● a: The TNG2OH9 board supports high-precision clock only when it uses the BIDI OSC
module.
● TNG1T210E: High-precision clock is not supported when its port type is VP.
● TNG1M828SM: Ports IN/OUT and TX1/RX1 to TX8/RX8 do not support high-precision
clock.
5.6.3 OSN 9800 U32E/U64E Subrack Hardware and Version

Support
NOTE

synchronization.

WDM OTN
Table 5-9 Boards and versions that support high-precision clock in OSN 9800
U32E/U64E subracks
Clock board TNU4CTU, TNU5CTU V100R021C10
Tributary board TNV6T216, TNV6T230, TNV1T502, V100R021C10

TNV1T402E, TNV3T220E, TNV1T402X,
TNV6G216, TNV6G230, TNV7S216
TNV3E224, TNV3E402, TNV3E404
TNV4E404, TNV4E224 V100R022C00

NOTE
For OTN tributary ports (on OTN tributary boards or OTU boards), the service types and

Table 5-10 Boards and versions that support high-precision clock in OSN 9800 P
series subracks
Clock board TMP2CTU V100R021C10
TMP3CTU V100R022C10
Optical line board TMP2ON32H, TMP2ON32PH, V100R021C10

(OSC unit) TMP3ON20H, TMP3ON20PH,
TMP2ON20H, TMP2ON20PH
TMP2ON32HE, TMP2ON32PHE V100R022C00

Table 5-11 Boards and versions that support high-precision clock in the OSN 1800
V Pro
Clock board TMK5SXCH, TMK5XCH, TMK5UXCME, V100R021C10

TMK6UXCM
TMK5GSCC V100R022C00
TMK6XCH V100R022C10
Clock interface TMB1AUX, TMB2AUX V100R021C10

board

WDM OTN
OSC board TMB1MR4FS/TMB2MR4FS (OSC unit), V100R021C10

TMB1MR4AFS/TMB2MR4AFS (OSC

unit)
OTU board TMB1ELOM, TMB1LDX, TMB1LDCA/ V100R021C10

TMB2LDCA, TMK1MDCA/TMK2MDCA,
TMB1LTX/TMB2LTX

board (tributary mode), TMK1GDC (tributary
mode)
NOTE

II Pro
Clock board TMK2UXCL, TMK2UXCLE V100R021C10

board


unit)

TMB1LTX/TMB2LTX

WDM OTN

board (tributary mode), TMK1GDC (tributary
mode)
NOTE

II TP
Clock board TMB1SCC, TMT1SCC V100R021C10

board


unit)

TMB1LTX/TMB2LTX

NOTE

Table 5-14 Boards and device versions that support high-precision clock in OSN
1800 I Compact subracks

WDM OTN
OTU board (client TMB2ELOM, TMB2LDX, TMB2LTX V100R022C10

side)
OTU board (line TMB2ELOM, TMB2LDX, TMB2LTX V100R022C10

side)
NOTE

This topic describes the dependencies and limitations of the high-precision clock
synchronization solution. For details about general dependencies and limitations,
see 3.3 Dependencies and Limitations of 3 IEEE 1588v2 (OTN & Packet) and
4.3 Dependencies and Limitations of 4 ITU-T G.8275.1/G.8273.2 (OTN &
Packet) .
Table 5-15 Dependencies and limitations of the high-precision clock

synchronization solution
Item Dependency and Limitation Details
Clock networking High-precision clock synchronization is supported only

when all NEs on the clock synchronization path meet the
following requirements. Otherwise, only common-
precision clock synchronization can be implemented.
● Clock boards (including system control, switching, and
timing boards), clock interface boards, and optical-
layer or electrical-layer boards used as synchronization
sources support high-precision clock synchronization.
● The high-precision clock synchronization license has
been deployed on the NEs.
● The high-precision clock synchronization mode has
been enabled for NEs and boards.
Intra-site clock It is recommended that the number of subracks on an

synchronization intra-site clock synchronization link be fewer than or
equal to three. (That is, cascading can be performed
twice at most.) If there are a large number of subracks,
you are advised to configure clock distribution boards to
enable the star topology.
Step mode In high-precision mode, Ethernet service ports support

only the two-step mode and do not support the one-step
mode.

WDM OTN
Item Dependency and Limitation Details
FlexE port When service ports work in FlexE mode, high-precision

clock synchronization is not supported. In this scenario,
Dedicated PTP Synchronization Ports can be used to
connect to customer devices and implement high-
External time port, External time (TOD) ports and external clock (CLK) ports
external clock port do not support high-precision clock synchronization.
External time ports and external clock ports cannot be
used to implement high-precision clock synchronization
in scenarios such as BITS interconnection and clock
synchronization, you need to correctly set the fiber type,
fiber length, and fiber dispersion coefficient on the WDM
Interface > Advanced Attributes page of the NMS.
Networking While enhancing the PTP protocol, the high-precision

compatibility clock synchronization solution is forward compatible.
That is, high-precision and common-precision clock nodes
can be deployed together.
● High-precision clock nodes can select the source and
link with the optimal precision, achieving the highest
synchronization precision. High-precision clock
synchronization performance can be achieved only
when all nodes on the clock synchronization path are
high-precision clock nodes.
● Common-precision devices on the live network can
still work properly without being upgraded or
modified.
TNG2AST4 ● In high-precision clock mode, the TM3/RM3 and

TM4/RM4 ports on the TNG2AST4 board do not
● When working with TNG3SRAPXF, the TNG2AST4
board does not support BIDI OSC modules and high-
5.8 Feature Updates

OSN 9800 U/M/P series subracks support high-precision clock synchronization
since V100R021C10SPC300.

WDM OTN

Update
OSN 9800 U/M/P series The product Added the description of the
subracks (with NCE function is high-precision clock
V100R021C10SPC200) newly enhanced. synchronization solution.
support high-precision clock
synchronization.

The 1800 V Pro, 1800 II Pro, and 1800 II TP support high-precision clock
synchronization since V100R021C10SPC300.

Feature Update Reason for Information Update
Update
The 1800 V Pro, 1800 II Pro, The product Added the description of the
and 1800 II TP (with NCE function is high-precision clock
V100R021C10SPC200) newly enhanced. synchronization solution.
support high-precision clock
synchronization.
5.9 Configuration Guide
5.9.1 Setting the High-Precision Clock Mode

Prerequisites
Guide.
Precautions

WDM OTN

Procedure
NOTICE
----End
Follow-up Procedure

WDM OTN

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Trademarks and Permissions

Huawei Technologies Co., Ltd.

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. i

About This Document

Product Name Start Version

OSN 9800 V100R001C20

OSN 8800 V100R002C00

OSN 6800 V100R005C00

OSN 1800 V100R003C05

● Network planning and design engineers

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. ii

Indicates a hazard with a high level of risk which,

Indicates a hazard with a medium level of risk

Indicates a hazard with a low level of risk which,

Indicates a potentially hazardous situation which,

Supplements the important information in the

Boldface Buttons, menus, parameters, tabs, window, and

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. iii

> Multi-level menus are in boldface and separated

Public IP Address Usage Declaration

2.4 Availability Modified Availability is updated to match V100R022C10.

2.4 Availability Modified Availability is updated to match V100R022C00.

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. iv

2.4 Availability Modified Availability is updated to match OSN

2.2.2.3 New The description of preventing physical-layer

5 High-Precision New The description of the high-precision clock

2.2.3 Clock Modified The clock synchronization GE optical ports of

3.8.1.1 Modified The guidance for setting the high-precision

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. v

2.4 Availability Modified Availability is updated to match OSN

3.8.1.10.3 Modified The external time port of OSN 9800 newly

2.4 Availability Modified Availability is updated to match OSN

2.5 Modified OSN 1800: Subracks that use the TMB1AUX

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. vi

Topic Update Description

2.8.1.1 Modified/ OSN 1800:

Updates in Issue 07 (2020-11-30)

Updates in Issue 06 (2020-09-30)

Updates in Issue 05 (2020-07-30)

Updates in Issue 04 (2020-05-30)

Updates in Issue 03 (2020-01-20)

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. vii

Updates in Issue 02 (2019-04-30)

Updates in Issue 01 (2018-08-30)

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. viii

About This Document................................................................................................................ ii

2 Physical Clocks (OTN & Packet & SDH)...........................................................................11

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. ix

2.4.9 OSN 1800 I Enhanced Hardware and Version Support........................................................................................72

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. x

2.8.1.15.12 Parameters: Clock Source Reversion Parameter....................................................................................... 146

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. xi

2.9.1.13.1 Parameters: Frequency Source Mode............................................................................................................. 214

3 IEEE 1588v2 (OTN & Packet)............................................................................................283

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. xii

3.2.2 IEEE 1588v2 Clock Architecture..................................................................................................................................285

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. xiii

3.8.1.9 Configuring Ring Network Automatic Compensation.................................................................................... 399

Issue 12 (2023-03-30) Copyright © Huawei Technologies Co., Ltd. xiv

3.9.1.8.2 Parameters: Clock Port Link..................................................................................................................................508

4 ITU-T G.8275.1/G.8273.2 (OTN & Packet) .................................................................... 585