ANIL NEERUKONDA INSTITUTE OF TECHNOLOGY & SCIENCES

(UGC AUTONOMOUS)
(Affiliated to AU, Approved by AICTE &Accredited by NBA)
Sangivalasa-531162, Bheemunipatnam Mandal, Visakhapatnam.
Phone: 08933- 225084,226395
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

M. TECH (VLSI AND EMBEDDED SYSTEMS)

Subject Code MTVES121 Subject Name LOW POWER VLSI

Class - Sem I-II Examination Mid-I Max. Marks 40
Date 10-08-2023 Time 12.00 – 1.30 PM A. Y 2022-2023

Unit-I
Q.No. Question Mark CO Level
s
1. a) Explain the various sources of power dissipation in CMOS 10 1 L2
circuits.
b) Explain the MIS structure with suitable band diagram for flat 10 1 L2
band, negative gate bias, and positive gate bias.
(OR)
Q.No. Question Mark CO Level
s
2 a) Explain the short channel effects in sub-micron MOSFETs. 10 1 L2
b) Explain in detail about low power VLSI design limits. 10 1 L2
Unit-II
Q.No. Question Mark CO Level
s
3 a) Explain the power reduction in clock networks. 10 2 L2

b) Explain CMOS floating node and low power bus. 10 2 L2

(OR)

Q.No Question Marks CO Level

.
4 a) Explain with suitable diagram of low power techniques 10 2 L2
for SRAM.

b) Explain charge keeper circuit in Domino CMOS logic. 10 2 L2