2004 35lh A n n u l IEEE Power Elecrronics Specialisls Conference
2004
Transformer Based Resonant DC link Inverter for Brushless DC Motor Drive System
Z. Y. Pan and F. L. Luo
School of Electrical & Electronic Engineering
Nanyang Technological University
Email: panzhiyang(CJpmail.ntu.edu.sg; eflluo@ntu.edu.sg
AbsImCI- Brushless DC motor has been widely used in
industrial applications because of its low inertia, fast response.
high power density, high reliability and maintenance-he. It is
usually supplied by a hard-switching PWM inverter, which
normally has low efficiency since the switching power losses
across the switching devices are high. In order to reduce the
losses, a lot of soft switching inverters have been designed.
Unfortunately, there are many drawbacks, such as high device
voltage stress, large DC link voltage ripple, complex control
scheme and so on. This paper introduces a soft-switching
inverter based on transformer which can generate DC link
voltage notches during chopping switches commutation to
guarantee all switches working in zero voltage switching
condition. The operation principle and control scheme of the
inverter are analyzed. Simulation and experimental results are
proposed to verify the theoretical analysis.
I. INTRODUCTION
Brushless DC motor (BDCM) has been widely used in
industrial applications because of its low inertia, fast
response, high power density, high reliability and
maintenance-free. It exhibits the operating characteristics of
a conventional commutated DC permanent magnet motor but
eliminates the mechanical commutators and brushes. Hence,
many problems associated with brushes are eliminated such
as radio-frequency interfenrence and sparking which is the
potential source of ignition in inflammable atmosphere, It is
usually supplied by a hard-switching PWM inverter, which
normally has low efficiency since the switching power losses
across the switching devices are high. In order to reduce the
losses, many soft switching inverters have been designed.
Soft switching operation of power inverter has attracted
much attention in recent decades. In electric motor drive
applications, soft-switching inverters are usually classified
into three categories, namely resonant pole inverters,
resonant DC link inverters and resonant AC link inverters
[I]. Resonant pole inverter has the disadvantage conlaining a
considerably large number of additional components, in
comparison to other hard- and soft-switching inverter
topologies. Resonant AC link inverter is not suitable to
BDCM drivers.
In medium power applications, the resonant DC link
concept [2] offered a first practical and reliable way to
reduce commutation losses and to eliminate individual
snubbers. Thus, it allows high operating frequency and
improves efficiency. The 6 main switches of the inverter is
quite simple to get the zero voltage switching, (ZVS)
condition only by adding one auxiliary switch. However, the
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inverter has the drawbacks of high voltage stress of the
switches, high DC link voltage ripple. It is with discrete
pulse modulation (DPM) control that is hard to achieve real
PWM control and will result in sub-harmonics. Furthermore,
the inductor power losses of the inverter are also
considerable as the inductor always conducts. To overcome
the drawback of high voltage stress across the switches,
actively clamped resonant DC link inverter was introduced
[3-61. The control scheme of the inverter is too complex and
the output also contains sub-harmonic. In addition, these
inverters still did not overcome the drawback of high
inductor power losses.
In order to generate voltage notches of the DC link at
controllable instants and reduce the power losses of the
inductor, several quasi-parallel resonant schemes were
proposed [7-91. As a dwell time is generally required after
every notch, severe interferences occur, mainly in
multiphase inverters, appreciably worsening the modulation
quality. A novel DC-rail parallel resonant zero voltage
transition (ZVT) voltage source inverter [IO] is introduced,
it overcome many drawbacks mentioned above. However, it
requires a stiff DC link capacitor bank that is center taped to
accomplish commutation. The center voltage of DC link is
susceptible to drift that may affect the operation of the
resonant circuit. In addition it requires two ZVT per PWM
cycle, it would worsen the output voltage and limit the
switch frequency of the inverter.
On the other hand, the majority of soft-switching inverters
proposed in the recent years have been aimed at the
induction motor drive applications. So it is necessary to
research on the novel topology of soft-switching inverter and
special control circuit for BDCM drive systems. This paper
proposed a resonant DC link inverter based on transformer
for BDCM drive system to solve the problems mentioned
above. The inverter possesses the advantage of low
switching power loss, low inductor power loss, low DC link
voltage ripple, small device voltage stress and simple control
scheme. The structure of the soft-switching inverter is shown
in Figure I . The system contains an uncontrolled rectifier, a
resonant circuit, a conventional three-phase inverter and
control circuit. The resonant circuit consists of three
auxiliary switches (SL, Se, S,) and comesponding built in
freewheeling diode (D,,, Do, Db), one transformer with turn
ratio 1: n and one resonant capacitor. All auxiliary switches
work under ZVS or zero current switching (ZCS) condition.
It generates voltage notches of the DC link to guarantee the
main switches (S,-S,)of the inverter operating in ZVS
condition.
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 2004 35fhAnnual IEEE Power Elecrronics Specialists Conference Aachen, Germany, 2004

Fig. I. The structure ofthe resonant DC link inverter for BDCM drive system

II. RESONANT CIRCUIT

The resonant circuit consists of three auxiliary switches,
one transformer and one resonant capacitor. The auxiliary
switches are controlled at certain instant to obtain the
resonance between transformer and capacitor. Thus, the DC
link voltage reaches zero temporarily (voltage notch) and the
main switches of the inverter get ZVS condition for
commutation. Since the resonant process is very short, the
load current can be assumed constant. The equivalent circuit
is shown in Figure 2. Where V,y is the DC power supply
voltage, Io is the load current. The corresponding waveforms Fin. 2. The equivalent circuit of the inverter
of the auxiliary switches gate signal, PWM signal, resonant
capacitor voltage (uc,) (i.e. DC link voltage), the transformer
primary winding current (i,.,) and current of switch S , (6)
are illustrated in Figure 3. The DC link voltage is reduced to
zero and then rises to supply voltage again is called one zero
voltage transition (ZVT) process or one DC link voltage
notch. The operation of the ZVT process in one PWM cycle
can be divided into 8 modes.
Mode 0 (shown in Figure 4-a) 0 < I < lo.Its operation is
the same as conventional inverter. Current flows from DC
power supply through SL to the load. The voltage across C,
(uc,) is equal to the supply voltage (Y7).The auxiliary
switches Sa and S, are turned off.
Mode I (shown in Figure 4-h) to < f < 1 , . When it is the
instant for phase current commutation or PWM signal is
flopped from high to low, switch So is turned on with ZCS (
the iL, can not change suddenly due to the transformer
inductance) and switch S, is turned off with ZVS (the uc,
can not change suddenly due to C), at the same time. The
transformer primary winding current iL, begins to increase
Fig. 3. Key waveforms ofthe equivalent circuit
and the secondary winding current i,,., also begins to rise

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2004 35th Annual IEEE Power Electronics Specialists Conference Aacken, Germany, 2004

through diode Db to DC link. The terminal voltages of during this mode. Load current flows through the
primary and secondary windings of the transformer are DC freewheeling diode D.
link voltage ucr and supply voltage V, respectively.
Capacitor C, resonates with transformer, the DC link voltage
U=, is decreased. Neglecting the resistances of windings,
using the m s f o r m e r equivalent circuit (referred to the
primary side) [ I I], the transformer current iL,, il,, and DC
link voltage uc,obey the equation:

Where LtI and Lt2are the primary and secondary winding

leakage inductance respectively, a is the transformer turn
ratio 1: n. The transformer has a high magnetizing
inductance. We can assume that iL, = iLJn, with initial
(c) Mode 2 (d) Mode 3
condition u , ( o ) = ys, ;,(I)) = 0 , solve the Equation (I),
get

1 n
Where L.. = L,,.. + L,,._i n 2is the equivalent inductance of the
transformer, 0, = is the natural angular resonance
frequency. Rewrite the Equation (2) get

Fig. 4. Operation mode of the resonant Dc link inverter

Mode 4 (shown in Figure 4-e) 6 < f < t4. As the main

is a number which is slightly less than 2 (the selection reason
of such a number will be explained late), iL, will decay to
zero faster than uc,. Let j D ( t ) = o , the duration of the
resonance can be determined
When iL, is reduced to Zero, auxiliary switch S,, can be
turned off with ZCS condition. At I = f t , the corresponding
DC link voltage uc, is
2-n
%(f, ) = --vs
n fxmsfonner primary and secondary windings are zero and
Mode 2 (shown in Figure 4-c) I , < t < I*. When the
transformer current is reduced to zero, the resonant capacitor
is discharged through load from initial condition as Equation
(5). The interval of this mode can be determined by:
AI2 = I , -1, = C , Y A - 4
nfo
(6)
switches have turned on or turned off, auxiliary switch S, is
turned on with ZCS (the iL, can not change suddenly due to
the transformer inductance) and the transformer secondary
current i,,,$ starts to build up linearly. The transformer
primary current iL, also begins to conduct through diode 0,
to the load. The current in the freewheeling diode D begins
to fall linearly. The load current is slowly diverted from the
freewheeling diodes to the resonant circuit. DC link voltage
ucr is still equal to zero before the transformer primary
current is greater than load current. The terminal voltages of
(5)
DC link voltage Vs respectively. Redefine the initial time, we
obtain
0 = L,, I
di r( t ) + a 2 L , 2 d[i,(O/aI +avs (7)
dt di
Since the transformer current iLr.,= it,Jn as in mode 1,

As it has mentioned that n is a number which is slightly

less than 2, the interval is normally very short.
rewrite the equation (7) as
d i u - v\
--
df
-_nL,
(8)

Mode 3 (shown in Figure 4-d) t2 < f < 4. The DC link The transformer primary current iL, is increased reverse
voltage (uc,) is zero. The main switches of the inverter can linearly from zero, the mode is end when iL, = -lo, the
now be either turned on or turned off under ZVS condition interval of this mode can be determined

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 2004 351h A n n u l IEEE Power Elecrronics Specialists Conference
At I,, iL, equals the negative load current -Io and the
current through the diode D becomes zero. Thus the
freewheeling diode turns off under zero-current condition,
the diode reverse recovery problems are reduced.
Mode 5 (shown in Figure 4-9 1, < I < is.Absolute value of
i,.r is increased continuously from lo and uCr is increased
from zero when the freewheeling diode D is turned off.
Redefine the initial time, we can get the same equation as
Equation (I). The initial condition is U ~ , ( O ) = O ,
i, (o)= -io, neglect the inductor resistance, solve the
When
1 On the other hand, from Equation (5) (6) it is expected
Ai5 = I 5 - I 4 =-arccos(1-n)
U,
U=, = vs, auxiliary switch S, is turned on with ZVS (due
to CJ. The interval is independent from load current. At I =
i5. the corresponding transformer primary current iL, is
i,,(i5) = - I ~- Y~II,.
(2 - W ,
The peak value of the transformer primary current can be
also determined:
Mode 6 (shown in Figure 4-g) is< f < is. Both the terminal
voltages of primary and secondary windings are equal to
supply voltage Vs after auxiliary switch SL is turned on.
Redefine the initial time, we obtain
v, = L,, -
d L ( 0 + a2 L,2 d[i, (Olal +a?,
(14)
di di
Since the transformer current i,, = if~Jnas in mode I ,
rewrite the Equation (14) as:
--
diu --( n - W,
di nL,
The transformer primary current i, decays linearly, the
mode is end when if,, = -lo again. With initial condition
Equation (12), the interval of this mode can be determined:
AI,=l,-I,= 4 T x c n-1
The interval is also independent from load current. As it
has mentioned that n is a number which is slightly less than
2, the interval is also very short.
Mode 7 (shown in Figure 4-h) f6 < I < 1,. The transformer
primary winding current iL, decays linearly from negative
load current -loto zero. Partial load current flows through
the switch S,. The sum current flowing through switch Sf.
and transformer is equal to the load current I,. Redefine the
initial time, the transformer winding current obeys the
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Equation (15) with the initial condition i,(o)=-~,. The
., interval of this mode is:
Then auxiliary switch S, can be also turned off in (ZCS)
condition after iL, decays to zero (at any time after I,).
Ill. DESIGNCONSIDERATION
It is assumed that the inductance of BDCM is much higher
than bansformer leakage inductance. From the analysis
presented previously, the design considerations can be
summarized as follows:
Determine the value of resonant capacitor C,, and the
- parameter of transformer.
Select of the main switches and auxiliary switches.
Design the gate signal for the auxiliary switches.
The turn ratio (1 :n) of the transformer can be determined
ahead. From Equation (1 1) n must satisfy:
n<2 (18)
(11)
that n is as close 2 as possible so that the duration of mode 2
would be not very long and ucr would be small enough at the
end of model. Normally, n can be selected at the range 1.1-
1.9. The equivalent inductance of the transformer
(12)
L, = L,, + L,, in‘ is inversely proportional to the rising rate
of switch current when turn on the auxiliary switches. It
means that the equivalent inductance L, should be big
enough to limit the rising rate of the switch current to work
in ZCS condition. The selection of L, can be referenced from
the rule depicted in [ 121.
L, 4i,Vs /I,,, (19)
Where I,,. is the turn on time of a switch, lo,, is the
maximum load current. The resonant capacitance C, is
inversely proportional to the rising rate of switch voltage
drop when turn off the switch S,. It means that the
capacitance is as high as possible to limit the rising rate of
the voltage to allow SL work in ZVS condition. The selection
of the resonant capacitor can be determined as
c, = 410d0mLy I “s (20)
(15) Where lor is the turn off time of a switch. However, as the
capacitance increases, more energy is stored on it, the peak
value of transformer current will be also high. The peak
value of iL, should be limited to twice peak load current.
From Equation ( I 3) we obtain
(16)
The DC link voltage rising transition time is expressed as
T, = ~i~ +AI, = =+ ~ ~ , c , a r c m s (-i n) (22)
“s
For high switching frequency, T, should be as short as
possible. Select the equivalent inductance L, and snubber
capacitance C, to satisfy the Equations (18) - (21), L, and C,
should be as small as possible.
Main switches S14 work under ZVS condition, the voltage
stress is equal to the DC power supply voltage V,. The
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2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, Germany, 2004

device current rate can be load current. Auxiliary switch SL inverter can be divided into PWM operation and full duty
works under ZVS condition, its voltage and current stress is cycle operation.
the same as main switches. Auxiliary switches Sa,,, work
under ZCS or ZVS condition, the voltage stress is also equal
to the DC link voltage ys. The peak current flowing through
them is limited to double maximum load current. As the
auxilialy switches so,, carry the peak current only during
switch transitions, they can be rated lower continuous
current rating.
The design of gate signal for auxiliary switches, can be
referenced from Figure 3. The trailing edge of the gate
signal for auxiliary switch S, is the same as that of PWM,
the leading edge is determined by the output of DC link
voltage sensor. The gate signal for auxiliary switch Sa is a
positive pulse with leading edge the same as PWM trailing
edge, it5 width ATa should be greater than At,. From
-
: From rotor position ~enmr

Equation (4), Atl is maximum when the load current is zero. Fig. 5. Commutation logical circuit for main switches
So ATa can be a fixed value determined by:

The gate signal for auxiliary switch Sh is also a pulse with

leading edge the same as that of PWM, its width ATh should
be longer than t , - t , (i.e. At, + AI5 +At, + Ati ). ATh
can be determined from Equation (9), (1 I), (16), ( I 7:) that:

IV. CONTROL
SCHEME
When the duty of PWM is loo%, i.e. full duty cycle, the
main switches of the inverter work under the commutation
frequency. When it is the instant to commutate the phase
current of the BDCM, we control the auxiliary switches S,,
Sh, SL and resonant occurs between transformer L, and
capacitor C,. The DC link voltage reach zero temporarily,
thus ZVS condition of the main switches is obtained. When
the duty of PWM is less than loo%, the auxiliary switch S ,
works as chop. The main switches of the inverter do not
switch within a PWM cycle when the phase current needs
not commutate. It has the benefit of reducing phase current
drop during the PWM is off. The phase current is
commutated during the DC link voltage becomes zero. There
is only one DC link voltage notch per PWM cycle. It is very
important especially for very low or very high duty of PWM.
Otherwise the interval between two voltage notches is very
short even overlapped which will limit the tuning range.
The commutation logical circuit of the system is shown in
Figure 5. It is similar to conventional BDCM commutation
logical circuit except adding six D flip-flops to the output.
Thus the gate signal of the main switches is controlled by the
synchronous pulse CK that will be mentioned late and the
commutation can be synchronized with auxiliary switches
control circuit (shown in Figure 6). The operation of the
Fig. 6 . Control circuit for the auxiliary switches
A . Full duty cycle operation
When the duty of PWM is loo%, i.e. full duty cycle, the
whole ZVT process (model - mode7) occurs when the
phase current commutation is on going. The monostable flip-
flop Mj will generate one narrow negative pulse. The width
, +T', where T;
of the pulse AT, is determined by ~ t+AI*
is a constant consider the turn on/off time of main switches.
If n is close 2, AI*would be very short or uc, would be small
enough at the end of model, AT, can be determined by:
AT3 = A l , l , , + T , = i ? ~ + T , (25)
Where T, is a constant which is greater than T<'.The data
selector makes the output of monostable flip-flop M3active.
The monostable flip-flop MI generates a positive pulse when
the trailing edge of M3 negative pulse is coming. The pulse
is the gate signal for auxiliary switch S, and its width is AT,
which is determined by Equation (23). The gate signal for
switch S, is flopped to low at the same time. Then mode 1
begins and the DC link voltage is reduced to zero.
Synchronous pulse CK is also generated by a monostable
flip-flop M4,the pulse width AT,should be greater than

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 2004 35th Annul IEEE Power Electronics Specidisis Conference Aachen, Germany, 2004

maximum A/, (i.e. n m ) . If the D flip-flops are rising current are shown in Figure 7. The figure shows that the
edge active, then CK is connected to the negative output of inverter worked well under various load currents.
the M4,otherwise connected to the positive output. Thus the
active edge of pulse CK is within mode3 when the voltage of
DC link is zero and the main switches of the inverter get
ZVS condition. The monostable flip-flop M2 generates a
positive pulse when the leading edge of M, negative pulse i s
coming. The pulse width of M 2is AT, that is determined by
Equation (24). Then mode 4-7 occurs, the DC link voltage is
increased to that of supply again. The leading edge of the
gate signal for switch S, is determined by DC link voltage
sensor signal. In a word in full cycle operation when the
phase current commutation is on going, the resonant circuit
generates a DC link voltage notch to let main switches of the
inverter switch under ZVS condition.
B. PWM operation
In this operation, the data selector makes PWM signal (a) Under IOW load current (b) Under high'loadc u m 1
active. The auxiliary switch SL works as chop, but the main (lo = 5A) (h=20A)
switches of the inverter do not turn on or tum off within a Fig. 1. Wavefoms of uc,. ih, isdim, PWM, auxiliary s\\itches gale signal
single PWM cycle when the phase current needs not under various load current
commutate. The load current is commutated during the DC In order to verify the theoretical analysis and simulation
link voltage becomes zero. (As the PWM cycle is very short, results. The proposed soft switching inverter was tested on
.
it does not affect the operation of the motor).
When PWM signal is flopped down, mode I begins,
pulse signal for switch S, is generated by MI and gate
an experimental prototype rated as:
DC link voltage: 240V;
Power of the BDCM: 3.3Hp;
signal for switch Sr. is dropped to low. However the Rated phase current: 10.8A;
voltage of DC link does not increase until PWM Switching frequency 2OkHz.
signal is flipped up. Pulse CK is also generated by M4 Select 50A/1200V BSM 35 G B 120 DN2 dual IGBT
to let active edge ofCK locate in mode 3 . module as main inverter switches SlSaand auxiliary switch
8
When PWM signal is flipped up, mode 4 begins, Sr., 30Ai600V IMBH30D-060 IGBT as auxiliary switches S.
pulse signal for switch Sb is generated at the moment. and S,. With datasheets of these switches and Equation (18)
Then when the voltage of the DC link is increased to -
(21), the value of capacitance and the parameter of
supply voltage VS, the gate signal for switch SL is transformer can be determined. A polyester capacitor of
flipped to high level. O.IpF, IOOOV was adopted as DC link resonant capacitor C,.
Thus, only one ZVT occurs per PWM cycle: mode I,2 for A high magnetizing inductance transformer with tum ratio
PWM turning off, mode 4,5,6,7 for PWM turning on. And 1:l.S was employed in the experiment. The equivalent
the switching frequency would be not greater than PWM inductance is about XpH. The switching frequency is 20
frequency. kHz. The monostable flip-flop is set up by 74LS123 IC,
variable resistor and capacitor. The logical gate can be
V. SIMULATION AND EXPERIMENT replaced by programmable logical device to reduce the
The proposed system is verified by simulation software number of 1C. AT,, ATb, AT3 and AT, are set to be 3ps. 6p,
PSim. The DC link voltage V,, is 300V. the maximum load 4 . 5 and ~ ~3.31srespectively.
current is 25A. The parameter of the resonant circuit was The system is tested in light and high load. The
determined from Equations (18) - (21). The transformer turn waveforms resonant DC link voltage uc, and transfomer
ratio is I: 1.8, the leakage inductances of the primary primary winding current iL, in low and high load currents are
secondary windings are 5pH and 9pH respectively. So the shown in Figure 8-a and Figure 8-b respectively. The
equivalent transformer inductance L, is about 8pH. The transformer based resonant DC link inverter works well
resonant capacitance C, is O.IpF. Switch S,, gate signal under various load currents. The waveforms of auxiliary
width ATa and AT, are set to he 3ps and 6ps respectively. switch Si, voltage US{,and its current isLare shown in Figure
The narrow negative pulse width AT3 in full duty cycle is set 8-c. There is little overlap between the switch SL voltage and
to be 4.5ps, the delay time for synchronous pulse CK ATd i s its current during the switching under soft switching
set to he 3 . 5 ~ 5 .The frequency of the PWM is 2OkHz. condition, so the switching power losses are low. The
Waveforms of DC link voltage uc,, transformer primary waveforms of resonant DC link voltage U,-, and synchronous
winding current iL, switch S , and diode DL current i,y/jiDI,, signal CK are shown in Figure 8-d, which the main switches
PWM, auxiliary switch gate signal under low and high load can switch under ZVS condition during commutation. The
design of the system is successful.

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 2004 35th A n n u l IEEE Power Elecrronics Specialists Conference Aachen. Germanv, 2W4

- All switches work under soft-switching condition, so

their power losses are small.
Voltage stress on all the switches would be not

- greater than DC Supply voltage.

Only one DC link voltage notch is needed during one
PWM cycle, and the switching frequency of the
auxiliary switches would not higher than PWM
frequency.

(a) U , and ir, under low load C U I “ ( IOOVIdiv, IOAIdiv) .

1 Simple auxiliary switches control scheme.
Freewheeling diodes turned off under zero current
condition and this greatly reduced the reverse
recovery problem of the diodes.
Soft switching results in considerably less noise as
the switching frequency can be high to outside the
audio spectrum.
1 The topology also applicable to induction motor
drive system.

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