3 RTSys SS2024 Lecture7+8 WorkSheets 240513 w Notes

Prof. Dr.-Ing. B.
Mysliwetz Electrical Engineering and

Real-Time Systems Information Technology
...
W1 Structure of a General Purpose Multi-User Operating System
W2a Basic Process Model, Process States and State Transitions
1
Prof. Dr.-Ing. B. Mysliwetz Electrical Engineering and
W2b Switching/multiplexing the CPU between multiple tasks

[from: J.Labrosse, MicroC/OS-II, CMP Books 1999]
2
W3a Task State Model of µC/OS [from: J. Labrosse, MicroC/OS-II, CMP Books 1999]
W3b Windows NT Process Model [from: R. Brause, Betriebssysteme, Springer 2001]
3
Assigning Task Priorities – Introductory Example

The design of a real-time application plans two cyclic tasks with the following repeat
periods Ti and execution times Ei :
Task A TA = 100 ms EA = 50 ms
Task B TB = 20 ms EB = 5 ms
The timer-tick rate of the real-time multitasking kernel to be used is 100 Hz.
Task-switching times can be neglected.
a) Determine the resulting CPU-load, b) draw the tasks' timing diagrams, c) discuss the
design as a whole (i.e. does it work or not ?) and d) what is the start time jitter (worst case
delay vs. the ideal start time) of the low priority task for both cases below ?
Case 1) Task A is assigned high priority, task B has low priority.

Task A
Task B
0 25 50 75 100 125 150 t [ms]
Case 2) Task B is assigned high priority, task A has low priority.

Task A
Task B
0 25 50 75 100 125 150 t [ms]
W3c Assigning Task Priorities – Introductory Example
4
Fixed Task Priorities – Rate Monotonic Approach Example 1
The design of a real-time application plans three periodic tasks with the following repeat
cycle periods Pi and execution times Ei :
Task A P1 = 8 ms E1 = 2.0 ms
Task B P2 = 10 ms E2 = 4.0 ms
Task C P3 = 40 ms E3 = 10.0 ms
Task A has the highest, task C the lowest priority. Task-switching times can be neglected.
The deadline of each task is equal to the end of its period.
design as a whole (i.e. does it work or not ?) and d) what is the start time jitter (worst case
delay vs. the ideal start time) of the low priority tasks below ?
Task A
Task B
Task C
0 10 20 30 40 50 60 t [ms]
W3d Fixed Task Priorities – Rate Monotonic Approach Example 1
5
Fixed Task Priorities – Rate Monotonic Approach Example 2
The design of a real-time application plans three periodic tasks with the following repeat
cycle periods Pi and execution times Ei :
Task A P1 = 20 ms E1 = 4.0 ms
Task B P2 = 10 ms E2 = 5.0 ms
Task C P3 = 50 ms E3 = 10.0 ms
Task A has the highest, task C the lowest priority. Task-switching times can be neglected.
The deadline of each task is equal to the end of its period.
a) Determine the resulting CPU-load, b) draw the tasks' timing diagram, c) discuss the
design as a whole.
Task A
Task B
Task C
0 10 20 30 40 50 60 t [ms]
W3e Fixed Task Priorities – Rate Monotonic Approach Example 2
6
Dynamic Task Priorities – Earliest Deadline First Approach vs. RMA

The design of a real-time application plans two cyclic tasks with the following repeat
periods Pi and execution times Ei :
Task A PA = 50 ms EA = 20 ms
Task B PB = 70 ms EB = 40 ms
Task-switching times can be neglected. The deadline of each task is equal to the end of
its period.
design as a whole, i.e. is the schedule feasible ?
Using EDF – Scheduling (task A is executed first)

Task A
Task B
0 50 100 150 200 250 300 t [ms]
Using RMA – Scheduling (task A has high, task B low priority)

Task A
Task B
0 25 50 75 100 125 150 t [ms]
W3f Dynamic Task Priorities – Earliest Deadline First Approach vs. RMA
7
W4a Shared Resources & Mutual Exclusion via Semaphores

[from: J. Labrosse, MicroC/OS-II, CMP Books 1999]
W4b Shared Resources & Mutual Exclusion via Semaphores

8
Sema
Task 1
Task 2
W4c Task Timing & Semaphore Operations for Mutual Exclusion
9
W5a Task Synchronisation via Semaphores (’Unilateral Rendezvous’)

W5b Mutual Task Synchronisation via Semaphores (’Bilateral Rendezvous’)

10
Sema
ISR
Task
W5c Event Signalling / ISR -> Task Synchronization Timing Example
11
W6a Priority Inversion Problem [from: J. Labrosse, MicroC/OS-II, CMP Books 1999]
W6b Priority Inheritance [from: J. Labrosse, MicroC/OS-II, CMP Books 1999]
12
W7a General Interrupt Mechanism [from: J. Labrosse, MicroC/OS-II, CMP Books 1999]
W7b Interrupt Nesting & OS-Notification [from: J.Labrosse, MicroC/OS-II, CMP Books 1999]
13
W7c Interrupt & Preemptive Multitasking [from: J.Labrosse, MicroC/OS-II, CMP Books 1999]
W8 Interrupt - Handling on the Hardware Level (80x86 Architecture)
14
W9a Delaying a Task for one Tick [from: J.Labrosse, MicroC/OS-II, CMP Books 1999]
W9b Delaying a Task for one Tick [from: J.Labrosse, MicroC/OS-II, CMP Books 1999]
15
µC/OS Basic Configuration Parameters and Memory Usage
W10 µC/OS Basic Configuration and Memory Usage (V2.00 for 80186)
16
W11a µC/OS System Calls and Configuration Parameters

17
W11b µC/OS System Calls and Configuration Parameters

18
main( )
{
…
}
StartUpTask( )
{
…
}
UserTask1( )
{
…
}
UserTask2( )
{
…
}
IdleTask( )
{
…
}
StatisticsTask( )
{
…
}
OSXXX( ) – System Calls
’Runtime-Library’
W12 Basic µC/OS Application Structure & Key Functions
19
W13 Basic µC/OS Application Structure - Modules
20

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Prof. Dr.-Ing. B.

Mysliwetz Electrical Engineering and

W1 Structure of a General Purpose Multi-User Operating System

W2a Basic Process Model, Process States and State Transitions

W2b Switching/multiplexing the CPU between multiple tasks

W3b Windows NT Process Model [from: R. Brause, Betriebssysteme, Springer 2001]

Assigning Task Priorities – Introductory Example

Case 1) Task A is assigned high priority, task B has low priority.

0 25 50 75 100 125 150 t [ms]

Case 2) Task B is assigned high priority, task A has low priority.

0 25 50 75 100 125 150 t [ms]

W3c Assigning Task Priorities – Introductory Example

Fixed Task Priorities – Rate Monotonic Approach Example 1

W3d Fixed Task Priorities – Rate Monotonic Approach Example 1

Fixed Task Priorities – Rate Monotonic Approach Example 2

W3e Fixed Task Priorities – Rate Monotonic Approach Example 2

Dynamic Task Priorities – Earliest Deadline First Approach vs. RMA

Using EDF – Scheduling (task A is executed first)

0 50 100 150 200 250 300 t [ms]

Using RMA – Scheduling (task A has high, task B low priority)

0 25 50 75 100 125 150 t [ms]

W4a Shared Resources & Mutual Exclusion via Semaphores

W4b Shared Resources & Mutual Exclusion via Semaphores

W4c Task Timing & Semaphore Operations for Mutual Exclusion

W5a Task Synchronisation via Semaphores (’Unilateral Rendezvous’)

W5b Mutual Task Synchronisation via Semaphores (’Bilateral Rendezvous’)

W5c Event Signalling / ISR -> Task Synchronization Timing Example

[from: J. Labrosse, MicroC/OS-II, CMP Books 1999]

W6b Priority Inheritance [from: J. Labrosse, MicroC/OS-II, CMP Books 1999]

W8 Interrupt - Handling on the Hardware Level (80x86 Architecture)

µC/OS Basic Configuration Parameters and Memory Usage

W11a µC/OS System Calls and Configuration Parameters

W11b µC/OS System Calls and Configuration Parameters

OSXXX( ) – System Calls

W12 Basic µC/OS Application Structure & Key Functions

W13 Basic µC/OS Application Structure - Modules

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