E520.30_datasheet

Smoke Detector Controller E520.
30
Preliminary Information – Jan 28, 2014
Features Brief Functional Description

• Designed for network addressable optical smoke The device provides a high current driver for a transmit-
detectors ter LED and a high impedance I-V conversion for the
• 2-wire programmable bus operation with 8V...50V photo current of the receiver diode. Optimized response
supply of both amplifier and ADC allow short transmitter pulses
• Low quiescent current (down to 88 µA) while keeping high detection efficiency. The amplifier's
• Embedded 8-bit micro controller with 4-KB FLASH band pass filter characteristics remove noise from the
(µ-code) and 128 Byte RAM signal.
• 28+4 Byte E²PROM for configuration data Transmitter pulses and signal acquisition as well as sig-
• Configurable 500mA LED driver nal evaluation are controlled by the embedded micro
controller allowing the user to take full control over the
• Configurable modulation current (240mA)
system performance with the user defined program code
• Photo current input range (1.5 ... 45) nA running from FLASH memory.
• Input bandpass filter: 0.45 .. 4.5 kHz
The configurable address allows bus operation with up
• 10 Bit ADC to 255 detectors on each bus.
• Thermistor input
• Programmable Bus interface
• 4 digital general purpose IOs Ordering Information
• JTAG debug and programming interface
• Minimum number of external components Order Code Temperature Range Package
E52030A54D -40 °C to +85°C SO14
Application
E52030A01Z -40 °C to +85°C Die *
• Simplifies design of addressable smoke detectors
required by legislation * Contact factory for bare die specifications
• Fully programmable smoke detectors with minimum
of external components
Typical Operating Circuit
Detector module
D5 LN24
C1:
220µF
10V DSUP
LED1
ELMOS
PD
520.30
DIN
Bus
Ln24
Ln0
LED
(optional)
LED2
RED
RV red
VTSEN
ϑ RT
VTDRV LN0
(optional)
This document contains information on a pre-production product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.
Elmos Semiconductor AG Data Sheet QM-No. 25DS0163E.00
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Smoke Detector Controller E520.30
Block Diagram and Application Example
DSUP LN24
D5
Alarm Driver
Supply/Reference
Communication
Transceiver
C1
GPIO /
PD JTAG
LED1 AMP 10 bit 4
DIN ADC
GPIO / JTAG
LED LED 5 bit
Driver DAC 8 bit uC 4KB FLASH
RED RED 128B RAM

AMP
LED2 28B+4B E²PROM
RED
RV Driver
VTSEN Oscillator
ϑ
RT POR
VTDRV LN0
Figure 1: Block Diagram
Table 1: Application Circuit Parameters (proposal)

Symbol Parameter
PD SFH2500/FA
LED1 SFH4500
LED2 WP710A10LSRD
C1 tantalum capacitor 220 uF x 6V, typ B45196-H1107-M309 20%
RV resistor 150k, typ B54101 2%
RT thermistor 100k, typ B57891M0104 1%
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Pin Configuration
LED 1 14 LN24
LN0 IO0
D5 IO1
RED IO2
DIN IO3
DSUP TEN
VTDRV 7 8 VTSEN
Figure 2: Package top view (not to scale)
Pin Description
Table 2: Pin Description
No Name Type Description
1 LED A_O Transmitter LED driver output
2 LN0 S Negative bus / supply connection , Ground (reference potential)
3 D5 A_O Tank capacitor charging output
4 RED A_IO Indicator red LED driver output and alarm simulation input
5 DIN A_I Receiver diode current input
6 DSUP A_O Receiver diode supply output
7 VTDRV A_O Temperature half bridge driver output
8 VTSEN A_I Temperature measurement channel input
9 TEN D_I Test/debug enable; three level pad; pull down
10 IO3 D_IO General purpose IO 3 , if TEN=1 JTAG clock (TCK); pull up
11 IO2 D_IO General purpose IO 2 , if TEN=1 JTAG test mode select (TMS); pull up
12 IO1 D_IO General purpose IO 1 , if TEN=1 JTAG data input (TDI); pull up
13 IO0 D_IO General purpose IO 0 , if TEN=1 JTAG data output (TDO); pull up
14 LN24 HV_S Positive bus / supply connection
Explanation of Types:
A = Analog, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage
ESD: More details according this topic are described in the ESD chapter (2).
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1 Absolute Maximum Ratings

Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. Any
other condition beyond those indicated is not implied. Exposure to absolute maximum rated conditions for extended
periods may affect device reliability.
All voltages referred to V(LN0). Currents flowing into terminals are positive, those drawn out of a terminal are neg-
ative.
Table 1-1: Maximum Ratings
No. Description Condition Symbol Min Max Unit
1 Bus Supply voltage Continuous VLN24 -0.3 +50 V
2 Bus Supply voltage reverse polarity pro- VLN24 -40 +50 V
tection, current limit-
ation via pin LN24 ≤
70mA
3 Bus Supply voltage tPULSE < 100 ns, VLN24 +60 V
tPULSE,PERIOD > 10 µs,
max. 75 consecutive
pulses (1 burst),
tBURST,PERIOD > 300 ms,
overvoltage protec-
tion
4 Voltage at digital I/O pins VDPIN -0.3 5.5 V
5 Input current at digital pins IDPIN -20 +20 mA
6 Voltage at analog pins VAPIN -0.3 VD5+0.3 V
7 Input current at analog pins IAPIN -20 +20 mA
8 Voltage at pin DIN VAPDIN -0.3 3.6 V
9 Junction temperature J -40 +90 °C
10 Ambient temperature AMB -40 +85 °C
1)
11 Storage temperature STO -40 +90 °C
12 Power dissipation average PTOT,AVG 20 mW
1) Storage is not considering packing materials such as tapes, reels, dry packs, foils, etc. Please contact ELMOS
for packing material specifications. Packaged devices before soldering: For moisture sensitive devices refer to
JEDEC standard J-STD-033 for handling and using details. Storage at temperatures > 90°C for more than 96 h
may affect the solderability of the devices.
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2 ESD Protection
Table 2-1: ESD Parameter
Description Condition Symbol Min Max Unit
ESD HBM Protection at all pins 1)
VESD(HBM) -2 +2 kV
ESD CDM Protection at all pins 2)
VESD(CDM) -500 500 V
ESD CDM Protection at edge pins 2)
VESD(CDM,C) -750 750 V
1) According to AEC-Q100-002 (HBM = human body model) chip level test: C = 100pF, R = 1.5kΩ
2) According to AEC-Q100-011 (CDM = charged device model) chip level test
3 Recommended Operating Conditions

The recommended operating conditions must not be exceeded in order to ensure proper functionality of the device.
All parameters specified in the following sections refer to these recommended operating conditions if not otherwise
stated.
All voltages referred to V(LN0). Currents flowing into terminals are positive, those drawn out of a terminal are neg-
ative.
Table 3-1: Recommended Operating Conditions
No. Description Condition Symbol Min Typ Max Unit
1 Bus supply voltage 1)
VLN24 8 24 50 V
2 Operating ambient temperature AMB,B -25 75 °C
3 Extended operating ambient temperature VD5 ≥ VTH,MON5 AMB,B,EXT -40 85 °C
4 Photo diode capacitance 2 V ≤ VREVERSE CPD 11 25 pF
≤5V
5 External tank capacitor for max.200mA pin D5 to LN0 C1, 200mA 80 100 1000 µF
LED current ILED < 200mA
6 External tank capacitor for high LED cur- pin D5 to LN0 C1, 500mA 200 250 1000 µF
rent 200mA < ILED
< 500mA
7 D5 resistive load pin D5 to RLOAD 1000 Ω
VTDRV
8 VTDRV sink pulse current t < 50 µs; IVTDRV 0 6 mA
duty cycle < 10-3
9 DSUP source current IDSUP -10 0 µA
1) During bus communication VLN24 can decrease down to to 0V
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4 Electrical Characteristics
4.1 Analog Part
4.1.1 Supply and References
(VLN24 = 8V to 50V, Tamb = -25°C to +75°C, unless otherwise noted. Typical values are at V LN24 = 24V and
Tamb = +25°C. Positive currents flow into the device pins.)
Table 4.1.1-1: Supply Interface Parameters
Supply Interface
1 Supply voltage, pin LN24 1)
Normal operation VLN24 8 24 50 V
2 Supply current, pin LN24 2)
SUP_MODE = 00b ILN24,0 88 µA
SUP_MODE= 01b ILN24,1 130 µA
6 LN24 monitor threshold voltage, falling VTH,LN24LOW,FALL 7.1 V
edge, pin LN24 1)
7 LN24 monitor threshold voltage, rising VTH,LN24LOW,RISE 7.4 V

edge, pin LN24 1)
8 LN24 monitor detection delay, falling edge, tLN24LOW 3.4 ms

pin LN24 1)
VLN24 ≤ 6.7 V
9 Output voltage, pin D5 ID5_CONST=-30µA, VD5 4.8 5.2 5.5 V
SUP_MODE=00b,
No ext. capacitor
10 Start-up time until voltage on D5 VLN24:0 to >8V TSTARTDELAY 0.7 1.0 1.6 s
reached the VTH,MON5 level. C1 = 220uF
*) 2)
VD5_Start= 0V
VD5_End=VTH,MON5
11 Start-up current. SUP_MODE = 00b ILN24,start up 0.65 1.0 1.4 mA
*) 3)
only during start up
12 Supply monitor threshold voltage VD5 rising VTH,MON5 4.4 4.64 4.8 V
13 Supply monitor hysteresis VTH,MON5_HYST 20 120 mV
Photo Diode Supply
*)
14 Output voltage -0.1µA ≤ IDSUP VDSUP 4.3 4.6 VD5 V
< 0µA
*)
Not production tested
1) During bus communication VLN24 can be decreased down to 0 V.
2) To achieve the short start up time the start-up current is used during start up.
3) Only used during start-up to achieve the short start up time. This current is flowing directly from LN24 BUS
Supply into the D5 capacitor during start up.
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4.1.2 Physical Interface via Bus Terminal LN24

Table 4.1.2-1: Physical Interface Parameters
1 Threshold voltage programming step 1)
n = 0,...,31 VTH,STEP 0.5 1 1.5 V
(n = PROT_THR1,2:
5-bit binary)
2 Demodulator threshold 1, MODT[1:0]= 00b VTH1(MOD1) (4+n)*
absolute (referred to LN0), n = 0,..., 31 VTH,STEP
Modulation Type 1 (n = PROT_THR1)
3 Demodulator threshold 1 MODT[1:0]= 1xb ΔVTH1(MOD2/3) (n-18)*

relative to LN24 (DC-level), n = 0,..., 31 VTH,STEP
Modulation Type 2, 3 2)
(n 18),
(n = PROT_THR1)
4 Demodulator threshold 2 MODT[1:0]=11b, ΔVTH2(MOD3) 2*(m-8)
relative to LN24 (DC-level), m = 0,..., 7 * VTH,STEP
2) (m = PROT_THR2,
Modulation Type 3
3-bit binary)
5 Maximum programmable modulation VLN24 ≥ 8V IMOD_MAX 180 240 300 mA
current *)
6 Modulation current programming step *)

VLN24 ≥ 8V IMOD_STEP 4 7.6 12 mA
7 Voltage drop at modulator ILN24 = 100mA, VMOD_DROP 0.7 1.2 1.7 V
TXD_CUR[4:0]=11
111b, TXD=H
8 Voltage drop at modulator ILN24 = 50mA, VMOD_DROP_50 0.35 0.6 0.85 V
TXD_CUR[4:0]=11
111b, TXD=H
*) Not production tested
1) Detection threshold of the demodulator receiver in either mode is defined as multiples of the step size, i.e.
VTH,STEP = VTH1(n)- VTH1(n-1).
2) Relative threshold definition referred to DC-level at LN24: VTH= ΔVTH+VLN24. It is realized by software. The LN24
voltage will be measured and the threshold will be tracked. The tracking steps are 0.5V. Absolute voltage threshold
is min. 0.5V and max 48V.
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4.1.3 LED Driver for Smoke Chamber

Table 4.1.3-1: LED Driver Parameters
1 Maximum LED current programming VLED = 1.5 V ILED_MAX 340 420 500 mA
*) 1)
TJ = 25°C
2 LED current programming step *)
5 bit resolution, ILED_STEP 9 14 19 mA
VLED = 1.5 V,
TJ = 25°C
3 LED current temperature coefficient *)
VLED ≥ 1.5 V ILED_TEMP 0.24 %/K
1) Typical LED current at TJ = 25°C:ILED_TYP = 460mA at VLED = 3.5 V; ILED_TYP = 500mA at VLED = 5 V
4.1.4 Smoke Detection and Temperature Measurement Channel

Table 4.1.4-1: Photo Current Detector Parameters
Photo Current Detector (AMP)
1 Full scale input current range *)
IDIN 1.5 45 nA
2 Detector conversion factor programmable FCONV 0.02 0.7 V/nA
range *) 1)
3 Detector conversion factor programming AMP_GAIN = FCONV,STEP +0.8 +2 +3.2 dB

step 1)
1100b to 0000b,
f = 1 kHz
4 Detector conversion factor FCONV,TEMP -10 +10 %
*)
temperature drift
5 Input bandpass lower corner -3 dB @ fAMP,L fAMP,L 0.45 kHz
*)
frequency
6 Input bandpass upper corner frequency *) -3 dB @ fAMP,H fAMP,H 4.5 kHz
Temperature Measurement Channel (VTSEN, VTDRV)
*)
7 Input voltage range VVTSEN 0 VREF2 V
- 0.3
8 On resistance of switch via VTDRV ON_TEMP = H, RVTDRV,ON 6 14 35 Ω
IVTDRV < 6mA
9 Time before sampling *)
TTEMP,AP 10 µs
10 Input capacitance *) 2)
CIN 5 pF
10-bit ADC
Reference voltage *)
VREF2 2.4 V
Sampling time *) 3)
TSAMP 2 µs
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*) 3)
Conversion time TCONV 8 µs
*)
Resolution N 10 LSB
1) For lab verification photo current detector output voltage is measured after 100us input current pulse I DIN
2) Capacitance is loaded from 0 V to VVTSEN during sampling time TSAMP
3) Timing specification is referenced to F OSC8M = 8 MHz.
4.1.5 RED Light Interface

Table 4.1.5-1: RED Light Interface Parameters
1 Red LED source current, pulsed Transmit mode, IRED,pu -10 -5.5 -3 mA
*) 1)
pulsed is on
2 constant "ON" Red LED current Transmit mode, IRED,co -3 -2 -1.3 mA
*) 2)
constant "ON"
3 Red LED current pulse duration Transmit mode, tRED,DUR 1 2 3 ms
duty cycle < 2*10-3
4 Input voltage high threshold Receive mode VTH,RED_H 0.3 V
5 Input voltage low threshold Receive mode VTH,RED_L 0.2 V
6 Input impedance Receive mode, RRED,IN 0.7 1 1.7 MΩ
VRED < 0.4 V,
TJ = 25°C
7 Temperature coefficient of input RRED,IN_TEMP 0.4 %/K
*)
impedance
1) LED is pulsed with the duty cycle tRED,DUR. Current source is the D5 voltage.
2) In "permanent-ON" mode the current source is the bus voltage LN24.
4.1.6 Oscillators
Table 4.1.6-1: Oscillator Parameters
1 Frequency of slow oscillator trimmed fOSC100K 96 100 104 kHz
2 Frequency of fast oscillator trimmed fOSC8M 7.2 8 8.8 MHz
3 Start-up time of fast oscillator *) 90% fOSC8M TSTART,OSC8M 2 µs
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4.2 Digital Characteristics

4.2.1 Central Processing Unit and Memory
Table 4.2.1-1: CPU and Memory Features
CPU
1 Data bus width BBUS 8 Bit
2 Address bus width BADR 16 Bit
3 Bus clock frequency FBUS 4 MHz
4 Stack-point bit width BSTACK 6 Bit
5 Number interrupt vectors NINT 8
EEPROM
7 Memory size NEEPROM 28+4 Byte
*)
8 Data retention time J ≤ 85° tRET 10 years
9 Endurance *)
J ≤ 85° NEND 10 5
prog.
cycles
10 Wake-up time *)
tWAKEUP,EE 50 µs
11 Erase or write time *)
tPROG,EE 9.2 ms
12 Shut-down write time tSDWR,EE 3.2 ms
Flash Memory
13 Memory size NFLASH_4k 4 kByte
14 Wake-up time *)
tWAKEUP,FL 20 µs
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4.2.2 Periphery
Table 4.2.2-1: Measurement Control Unit Parameters
Measurement Control Unit
1 LED current pulse duration duty cycle < 10-3 TLED 100 µs
Physical Interface Control Unit
2 Protocol bit time range TBIT 0.15 2.5 ms
Red Light Interface Control Unit 1)
3 Red light test alarm trigger period *) ALPER = 00b TALARM,0 670 750 830 µs
4 '' ALPER = 01b TALARM,1 450 500 550 µs
5 '' ALPER = 10b TALARM,2 290 330 370 µs
6 '' ALPER = 11b TALARM,3 220 250 280 µs
7 Red light pulse duration *) TRED,DUR 2 ms
General Purpose IOs
*)
8 Low level of Open-Drain Outputs IPIN=4mA VOL 0.4 V
*)
9 Input pull-up current VPIN=0V IPU 0.3 1.5 uA
*)
10 High level Input Voltage VIH 2.6 V
*)
11 Low level Input Voltage VIL 0.8 V
*)
12 Input Voltage hysteresis VIHyst 0.4 V
1) Timing specification is referenced to fOSC100K = 100 kHz
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5 Functional Description
5.1 General Functional Description
The basic function of this device is to periodically trigger an optical smoke sensor, to evaluate the sensor signal,
and to indicate a smoke alarm if detected.
The optical smoke sensor is a chamber with a light emitting diode LED1 and a photo diode PD. Commonly a
reflective detection is used, therefore the inner walls of the detection chamber are virtually non-reflective and the
LED1 does not directly illuminate the photo diode PD. Short, high power light pulses from the LED light up the
chamber. If smoke is present inside the chamber, a certain amount of light is scattered at the smoke and reaches
the photo diode.
The device architecture comprises an LED driver (LED DRV), a current to voltage converter (AMP) with a sub-
sequent analog-to-digital converter (ADC) for acquiring the photo current, a micro controller (CPU) for data evalu-
ation and system control, and a physical interface to the 2-wire bus which provides the power supply and links the
smoke detector module to a central control instance. Up to 255 detector modules can be attached to the bus.
For status indication a driver for a red light emitting diode LED2 is provided. This red LED driver can be
configured to indicate device healthy state by short pulses or the alarm case, with the LED2 turned on
permanently. Also, with an appropriate hand held device light pulse sequences can be applied to the red LED2 in
order to emulate an alarm for diagnosis purpose in the field. The red LED2 is used as photo diode to convert the
light pulses into a current/voltage signal. The signal is decoded and made available for the micro controller.
Additionally the device provides a temperature measurement channel to detect and evaluate the temperature as a
complementary signal to the optical sensor output. The temperature signal is fed to the ADC and is processed by
the micro controller.
DSUP LN24
D5
Alarm Driver
Supply/Reference Communication
Transceiver
C1
GPIO /
PD
LED1 AMP 10 bit 4 JTAG
DIN ADC
GPIO / JTAG
LED LED 5 bit
Driver DAC 8 bit uC 4KB FLASH
RED RED 128B RAM

AMP
LED2 28B+4B E²PROM
RED
RV Driver
VTSEN Oscillator
ϑ
RT POR
VTDRV LN0
Figure 5.1-1: Detailed Block Diagram E520.30
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5.1.1 Start-up behaviour

In the initial operation phase, when the module is connecting to LN24 bus voltage, the C1 capacitor on PIN D5 is
charged with a higher start-up current which is defined in table Supply Interface. The start-up current flows until the
VD5 voltage reached the threshold VTH,MON5. Until the threshold VTH,MON5 is reached, the ASIC is in reset mode.
After reset mode the microprocessor starts with initialisation. Then the charge current is the programmed LN24
supply current ILN24 (88...220uA).
VD5
in V 6
VTH,MON5 5
4
3
2
1
1 2 3 t in s
Figure 5.1.1-1: Start-up behaviour
5.1.2 Smoke Detection

For the smoke detection a special measurement sequence is executed. The execution can be initiated periodically
in two ways depending on register MECONF.MEMODE:
1. MEMODE=0b : Controlled by the µC based on software and protocol.

Periodical measurement requests received via the physical interface protocol are interpreted by the µC to start a
measurement, acquire the measurement values, determine the result, and transmit the result to the master unit.
2. MEMODE=1b : Automatically controlled by the configurable measurement timer.

After power-up the µC configures the dedicated timer. In operation the µC is periodically interrupted (woken up) to
acquire the measurement values, determine the result. In parallel, there might be a protocol request to be pro-
cessed.
The measurement sequence is generated by the measurement control unit (MEAS_CTRL):
1) The receiving current-to-voltage converter/amplifier (AMP) is initialized.
2) The analog-to-digital conversion is started with a configurable sampling rate or each conversion is started
by the µC to digitalize the output of the current-to-voltage converter/amplifier, i.e. the photo current from the
receiving photo diode PD.
3) The light emitting diode LED1 is driven by the LED driver with a configurable current I LED1 for a configurable
time TLED1.
4) During 2) and 3) the µC acquires the noise signal (LED1 off) and the smoke signal (LED1 on).
5) LED1 is switched off but µC can continue acquiring the smoke signal (LED1 off)
6) Stop ADC conversion, then µC can process the data and determine the results.
For details refer the chapter 5.2.2.2.
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5.1.3 Temperature Measurement

For temperature measurements a half bridge RV - RT can be connected. It is driven via pin VTDRV and measured
via pin VTSEN.
Enabled by the register MECTRL.TME_EN a temperature measurement can be performed by driving VTDRV and
connecting VTSEN to the ADC as a part of the measurement sequence. The time between start of driving VTDRV
and start of analog-to-digital conversion is T TEMP,AP . For details refer the chapter 5.2.2.2.
5.1.4 Bus Interface via Supply Terminal LN24

The physical interface via the supply terminal LN24 is capable to handle a wide range of bit serial communication
protocols. The Smoke Detector can receive voltage modulation with configurable polarity and thresholds and it can
transmit current modulation with configurable modulation current.
The physical interface control unit builds the interface to the CPU. It can provide interrupts/wake-ups from received
RXD events and force answers via TXD with configurable delay and duration.
5.1.5 Red Light Interface

Via the pin RED the red light emitting diode LED2 can be connected to realize a light interface with two functions:
1. Send periodically pulsed red light driven by the red light driver (RED_DRV) in the measurement pauses as
an indicator of the device state. The µC software should periodically set REDCTRL.EN_RED bit to start
RED lighting impulse. RED impulse bit REDCTRL.EN_RED is automatically reset. The pulse duration
TRED_DUR is fixed to 2ms. To increase the RED pulse duration few following impulses can be used. LED cur-
rent source is the capacitor C1 on D5.
2. In case of an alarm detected the red light driver (RED_DRV) can be turned on permanently when the cor-
responding configuration bit REDCONF.ALARMON (see Table REDCONF) is set to indicate the alarm
state additionally to the signals transferred on the LN24 physical interface. In this mode the LED current is
lower as in pulsed mode and the current source is the LN24 voltage.
3. Receive an alarm request. This interface is intended to receive an emulated alarm for diagnosis purpose
via an appropriated hand held device.
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5.2 Detailed Description and Digital Control

The Digital part consist of the two global blocks. The universal microprocessor (CPU) and special purpose digital
periphery. The periphery part is intended to provide independent processing of the LN24 communication protocol,
the measurement cycle and the RED light emitting. Thus microprocessor controls time duration of the periphery
modes but timing control, analogue signal forming and priority processing are done by periphery base on the hard-
ware-coded finite state machines.
The digital part uses two clock frequencies. The high frequency system clock for Central Processing Unit (CPU)
and the low frequency clock for the special purpose periphery. The low frequency clock is continuously generated
for timing control of the bus communication, the measurement and the emitting RED light. The high frequency clock
is only generated in specific conditions to reduce the CPU's power consumption.
The CPU is connected to the memory (FLASH, EEPROM and RAM) and the peripheral modules via the internal
system bus. The system bus provides a 16 bit address space and allows 8 bit data transfers.
The memory contains the program code and the data. Memory and registers are mapped according to the global
Memory Map (refer to 5.2.1.2) and can be accessed through all memory related operation provided by the CPUs
instruction set.
The Interrupt Controller collects requests from all interrupt sources and provides an interrupt signal to the CPU.
Interrupt sources can be masked within the interrupt controller. Interrupts are generated by the modules and hold
until they are cleared within the modules.
5.2.1 Central Processing Unit (CPU)

5.2.1.1 CPU EL3.5 Core
1. 6805 instruction set compatible including 8 by 8 multiplication
2. 15 Interrupt vectors
3. 1 Reset vector
4. 16 bit address bus width
5. 64 KByte data/program address space (0x0000 - 0xFFFF)
6. Clock frequency 0-4MHz
7. 6 Bit Stack-Pointer
8. 16 Bit extended Program counter
7 0
ACCUMULATOR A
7 0
INDEX RESIGTER X
15 7 5 0
0 0 0 0 0 0 0 0 1 1 STACK POINTER SP
15 0
PROGRAM COUNTER PC
CONDITION CODE REGISTER 1 1 1 H I N Z C CCR
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
Figure 5.2.1.1-1: Programming model
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These internal actions occur as result of any CPU reset:

1. All registers are set to reset value
2. Stack pointer forced to (0x00FF)
3. I bit in the CCR set to 1 to inhibit maskable interrupts
4. External interrupt latch cleared
As the computer leaves reset, the PC is loaded from the two highest memory location (0xFFFF).
The standard interrupt controller accepts up to 15 different interrupts.
To accept interrupts the CCR I-Bit has to be cleared with the CLI instruction.
Debug Interface
To access the debug structures of the EL3.5 CPU a 4-wire standard JTAG interface is used. The JTAG interface
can be accessed via 4 GPIO pins when the TEN pin is set to 3.3V. TEN pin set to zero resets all test and debug
structures and the ASIC operates in normal mode.
CPU Registers
The Accumulator A is used for general calculations. The X Register is used for indirect and indexed addressing.
The stack pointer SP is used internally by the CPU. The first 2 Bits of the SP-Register are fixed to one. This is to
protect the rest of the RAM in case of a stack overflow.
The program counter is 16-Bit long. So the maximum addressable code area is 64KByte.
Table 5.2.1.1-1: CPU Registers

Name Size Description
CCR 5 bit Condition Code Register
PC 16 bit Program Counter
SP 6 bit Stack Pointer
X 8 bit Index Register
A 8 bit Accumulator
STACK 64 bytes Stack 64 byte LIFO (last-in-first-out)
Table 5.2.1.1-2: Condition Code Register

Bit Name Description
4 H Half-Carry (from bit 3)
3 I Interrupt mask
2 N Negative flag
1 Z Zero flag
0 C Carry bit
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Instruction Set
Figure 5.2.1.1-2: Instruction Set Summary (Sheet 1 of 6)
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Figure 5.2.1.1-8: Instruction Set Opcode Map
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5.2.1.2 Memory Map - Base Address Table

Table 5.2.1.2-1: Base Address Table
Base Address Size Modul Name Reference
0xF000 0x1000 FLASH 4K X 8 5.2.1.6
1)
0x0100 0xEFFF unused invalid addresses
0x0080 0x0080 RAM 128 x 8 5.2.1.4
1)
0x007C 0x0004 reserved invalid addresses
0x0060 0X001C E²PROM 28 X 8 5.2.1.5
1)
0x0055 0x000B reserved invalid addresses
0x0050 0x0005 E²PROM Control Registers (EE_CTRL) 5.2.1.5
1)
0x0048 0x0008 reserved invalid addresses
0x0040 0x0008 Universal Timer (TIMER) 5.2.2.7
1)
0x0038 0x0001 Red Light Interface Control Unit (IR_RED_CTRL) 5.2.2.4
1)
0x0030 0x0006 Measurement Control Unit (MEAS_CTRL) 5.2.2.2
1)
0x002A 0x0006 reserved invalid addresses
0x0020 0x000A Physical Interface Control Unit (LN24_CTRL) 5.2.2.3
1)
0x0010 0x0009 Special Function Registers (SFR), 5.2.2.8
locked by SYSCTRL.CONFLOCK
0x000C 0x0004 General Purpose IOs (GPIO) 5.2.2.5
0x0009 0x0003 reserved invalid addresses 1)
0x0008 0x0001 Watchdog (WATCHDOG) 5.2.2.6

0x0007 0x0001 reserved invalid address 1)
0x0001 0x0006 Main Control Unit (MAIN_CTRL) 5.2.2.1

0x0000 0x0001 reserved invalid address 1)
1)
Note : An invalid address access will cause a system reset (refer to 5.2.2.1).
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5.2.1.3 Interrupt vector

The following Table 5.2.1.3-1 shows all interrupt vectors in descending priority.
Table 5.2.1.3-1: Reset and Interrupt vectors list
Number Block Vector Address Source
0 POR 0xFFFE - 0xFFFF Power drop
0 WATCHDOG 0xFFFE - 0xFFFF Watchdog reset
0 CPU 0xFFFE - 0xFFFF Invalid address access
1 CPU 0xFFFC - 0xFFFD Software interrupt (SWI)
2 IR_RED_CTRL 0xFFFA - 0xFFFB RED interface alarm interrupt
3 LN24_CTRL 0xFFF8 - 0xFFF9 Physical interface interrupt
4 MEAS_CTRL 0xFFF6 - 0xFFF7 Measurement interrupt (Start)
5 GPIO 0xFFF4 - 0xFFF5 GPIO interrupt
6 TIMER 0xFFF2 - 0xFFF3 TIMER interrupt
7 MAIN_CTRL 0xFFF0 - 0xFFF1 Power monitor interrupt
8 EE_CTRL 0xFFEE - 0xFFEF EEPROM interrupt
9 MEAS_CTRL 0xFFEC - 0xFFED ADC interrupt
10 - 15 - 0xFFE0 - 0xFFEB 6 Interrupt vectors reserved
5.2.1.4 RAM
This Random Access Memory (RAM) module is a static volatile memory block.
The module contains a 128-word by 8-bit RAM array. RAM address range 0x80 to 0xBF is used to keep CPU vari-
able. RAM address range 0xC0 to 0xFF is fixed by hardware to be used as CPU stack.
5.2.1.5 E²PROM
The embedded E²PROM block provides 32 bytes divided into 28 bytes of the USER part and 4 bytes of INFO part.
USER part address range is 0x60 to 0x7B. The address range 0x64 to 0x67 is shared between USER and INFO
part. To get read access to the INFO part the bit EECFG.INFO (0x50) has to be set.
The INFO part of E²PROM is reserved to hold factory trimming data for oscillators and ELMOS ID code as
described in Table 5.2.1.5-1.
Table 5.2.1.5-1: E²PROM Info Area (EECFG.INFO = 1b)
Address Name Description
0x64 OSC_TRIM Oscillator trimming (refer to 5.2.2.1)
0x65 UDIN_H ELMOS Device ID, byte 1
0x66 UDIN_M ELMOS Device ID, byte 2
0x67 UDIN_L ELMOS Device ID, byte 3
After power-up one of the first CPU action, after EEPROM wake-up time, has to be the transfer of the oscillator
trimming values to the corresponding register OSC_TRIM (refer to chapter 5.2.2.1).
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In the USER part 28 bytes are free to hold for example:

• Customer IDs
• Smoke detector gain setting: AMP_GAIN[3:0] (4 bit)
• LED driver current setting: LED_DAC[4:0] (5 bit)
• Supply mode: SUP_MODE[1:0] (2 bit)
• Input threshold settings of physical interface: PROT_THR1 and PROT_THR2
• Modulation current setting of physical interface: TXD_CUR[4:0] (5 bit)
• Modulation type setting of physical interface: MODT[1:0] (2 bit)
• ...
For reliability it is recommended to periodically refresh the registers with corresponding E²PROM contents.
The E²PROM is organized in 12 bit wide words. Data word consists of 8 bit data and 4 bit ECC (one bit error detec-
tion and correction).
E²PROM Locking
To prevent unintended E²PROM programming a lock mechanism is implemented. Incorrect handling of the unlock-
ing procedure during attempt to erase or program generates a system reset that can be found by high state of
SYSSTAT.EERES.
Erase and Program Procedure

In the following Table 5.2.1.5-2 and Table 5.2.1.5-3 the procedures for erasing and programming of E²PROM con-
tent is described. To change any data on a E²PROM cell it is necessary to first erase this cell.
Table 5.2.1.5-2: Erasing Procedure
Step Description
1 • If E²PROM is disabled (sleepmode, SYSCTRL.EN_EE = 0b), write 1b to SYSCTRL.EN_EE,
else goto step 4.
2 • Wait for flag EESTAT.IRQ_WU or use interrupt EE_IRQ, which are set after internal timer counts
50 us of E²PROM wake-up time. During E²PROM wake-up CPU should stay active.
3 • Write a 0b to EESTAT.IRQ_WU to clear the flag.
4 • Write 0xA0 to EEPCLK register to initialize lock state (INIT).
5 • Write 0x0A to EEPCLK register to unlock erasing (state ERASE).
6 • Write 0x00 data to selected E²PROM address (range 0x60-0x7B).
7 • Write a b1 to EECFG.ER to start automatic erasing, EECFG.LOCK will be set by hardware.
8 • Write a b1 to EECTRL.ENIRQ_ER to enable the local interrupt flag.
9 • If erasing is handled just by wake-up goto step 10,
• else if erasing is handled by interrupt goto step 11.
10 • Write a 1b to WUEN.EE_WE to enable the wake-up by E²PROM event.
Then goto step 12.
11 • Write a 1b to INTM.EE_IM to enable the interrupt by E²PROM event.
12 • Write a 1b to SYSCTRL.CPU_OFF to go to sleepmode.
13 • After 9 ms erasing cycle bits EECFG.ER and EECFG.LOCK will be cleared and a wake-up by
E²PROM event happens (via step 10) or interrupt EE_INT is generated (via step 11). Lock state is
automatically reset to state RESET.
14 • Write a 0b to EESTAT.IRQ_ER to clear the flag.
15 • To write now data to the E²PROM go on with step 4 in Programming Procedure (Table 5.2.1.5-3).
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If an E²PROM cell is already erased, new data can be programmed directly by the following programming proced-
ure (Table 5.2.1.5-3). If the Erasing Procedure has been just finished the Programming Procedure can be star-
ted with step 4.
Table 5.2.1.5-3: Programming Procedure
Step Description
1 • If E²PROM is disabled (sleepmode, SYSCTRL.EN_EE = 0b), write 1b to SYSCTRL.EN_EE,
else goto step 4.
2 • Wait for flag EESTAT.IRQ_WU or use interrupt EE_INT, which are set after internal timer counts 50
us of E²PROM wake-up procedure. During wake-up process CPU should stay active.
3 • Write a 0b to EESTAT.IRQ_WU to clear the flag.
4 • Write 0xA0 to EEPCLK register to initialize lock state (INIT).
5 • Write 0x0A to EEPCLK register to unlock erasing (state ERASE).
6 • Write again 0x0A to EEPCLK register to unlock programming (state PROGRAM).
7 • Write data to selected EEPROM address (range 0x60-0x7B).
8 • Write a 1b to EECFG.PGM to start automatic programming, EECFG.LOCK will be set by hardware.
9 • Write a 1b to EECTRL.ENIRQ_PGM to enable the local interrupt flag.
10 • If E²PROM event handling is already selected by Erasing Procedure (Table 5.2.1.5-2) go directly to
step 13,
• else
• if programming is handled just by wake-up goto step 11,
• else if programming is handled by interrupt goto step 12.
11 • Write a 1b to WUEN.EE_WE to enable the wake-up by E²PROM event.
• Then goto step 13.
12 • Write a 1b to INTM.EE_IM to enable the interrupt by E²PROM event.
13 • Write a 1b to SYSCTRL.CPU_OFF to go to sleepmode.
14 • After 9 ms programming cycle bits EECFG.PGM and EECFG.LOCK will be cleared and a wake-up by
E²PROM happens (via step 11) or interrupt EE_INT is generated (via step 12). Lock state is automat-
ically reset to state RESET.
15 • Write a 0b to EESTAT.IRQ_PGM to clear the flag.
16 • If E²PROM programming is finished write 0b to SYSCTRL.EN_EE to keep E²PROM in its sleep-mode,
else goto step 4 in Erasing Procedure (Table 5.2.1.5-2).
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E²PROM Control and Status Registers

Table 5.2.1.5-4: EEPROM Control and Status Register
Register Name Address Description
EECFG 0x50 EEPROM Configuration Register
EEPLCK 0x51 EEPROM Programming Lock Register
EECTRL 0x52 EEPROM Control Register
EESTAT 0x53 EEPROM Status Register
EEMIRQ 0x54 EEPROM Masked Interrupt Requests Flags (read only)
Legend:
Internal access : from view of HW block . External access : from view of CPU (programmer).
R : read , W : write , S : set , C : clear.
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Table 5.2.1.5-5: Register EECFG (0x50)

MSB LSB
Content [7] PGM ER VHI VLO INFO LOCK ECCERR
Reset value 0 0 0 0 0 0 0 0
Access 0 R/S R/S R/W R/W R/W R R
Bit Description [7] : reserved
PGM : Selects programming of memory
• bit is set by writing a 1b to this location,
• bit is cleared automatically after programming has finished.
Note: It is not allowed to set both PGM and ER at the same time.
ER : Selects erasing of memory
• bit is set by writing a 1b to this location,
• bit is cleared automatically after erasing has finished.
Note: It is not allowed to set both PGM and ER at the same time.
VHI : Enable verify mode with high read voltage reference
The control bits VHI and VLO are used to verify the success of the programmed data or the long
term data retention. By setting one of the bits, the internal bias voltage is skewed either up (VHI
= 1b) or down (VLO = 1b). The high read reference voltage (VHI = 1b) is used to verify the pro-
grammed state '1' (erase state). The low read reference voltage (VLO = 1b) verifies the pro-
grammed state '0' (programmed state). If the read out data is unchanged (and no ECCERR is
detected) for both read voltages a robust value for normal read out (VHI, VLO = 0b) is verified.
Note: Both bits VHI and VLO must not be set at the same time.
Note: Changing the read reference voltage by setting VHI or VLO, or after a write cycle the set-
tling of the read reference voltage needs 50 us. This settling time has to be considered by the
software.
• 0b : normal read voltage
• 1b : increased read voltage, VLO have to be 0b !
VLO : Enable verify mode with low read voltage reference
For description refer to bit VHI.
• 0b : normal read voltage
• 1b : decreased read voltage, VHI have to be 0b !
INFO : Enables access to the INFO part
The INFO bit allows access to a portion of the array reserved for factory use, called INFO part.
The INFO part shares addresses 0x64 - 0x67 with the USER part.
• 0b : USER part is selected,
• 1b : INFO part is selected.
LOCK : E²PROM Lock Status Flag
This flag indicates that an E²PROM wake-up, a programming or an erasing is in progress (refer
to 5.2.1.5).
• flag is set if an E²PROM wake-up, a programming or an erasing is initiated,
• flag is automatically cleared by hardware, if E²PROM wake-up, programming or erasing has
finished.
ECCERR : Error Correction Code error flag
• flag is set if an ECC error has happened in last read access to the E²PROM,
• flag is cleared, if last read access was without error.
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Table 5.2.1.5-6: Register EEPLCK (0x51)

MSB LSB
Content EEPLCK[7:3] LCKST[2:0]
Reset value 0 111
Access W R(W)
Bit Description EEPLCK[7:3] : Lock command
There is no read access to the upper 5 bits EEPLCK[7:3]. Entire 8 bit register EEPLCK[7:0]
should be written to change lock state:
• 0xA0 - go from any state to state INIT,
• 0x0A - go from state INIT to state ERASE or from state ERASE to state PROGRAM,
• 0x55 - go from state PROGRAM to state SHUTDOWN,
• any other value leads to state RESET
LCKST[2:0] : Lock State (read only)

For details refer to MISSING ELEMENT: 2514671.
• b111 : RESET
• b000 : INIT, lock initialization
• b001 : ERASE, erasing is unlocked
• b010 : PROGRAM, programming is unlocked
• b100 : SHUTDOWN, shutdown erasing/programming is unlocked
Table 5.2.1.5-7: Register EECTRL (0x52)

MSB LSB
Content [7:4] ENIRQ_WU ENIRQ_SHD ENIRQ_PGM ENIRQ_ER
Reset value 0000 0 0 0 0

Access 0 R/W R/W R/W R/W
Bit Description [7:4] : reserved
ENIRQ_WU : Enable flag IRQ_WU to generate an interrupt/wakeup.
ENIRQ_SHD : Enable flag IRQ_SHD to generate an interrupt/wakeup.
ENIRQ_PGM : Enable flag IRQ_PGM to generate an interrupt/wakeup.
ENIRQ_ER : Enable flag IRQ_ER to generate an interrupt/wakeup.
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Table 5.2.1.5-8: Register EESTAT (0x53)

MSB LSB
Content [7:4] IRQ_WU IRQ_SHD IRQ_PGM IRQ_ER
Access 0 R/C R/C R/C R/C
IRQ_WU : Flag for activated EEPROM after wake-up
• flag is set when EEPROM timer count 50 us after peripheral wake-up event if
SYSCTRL.EN_EE = 1b, or if CPU write SYSCTRL.EN_EE = 1b,
• flag is cleared by writing a 0b to this location.
Flag can be enabled to generate an interrupt/wakeup by ENIRQ_WU.
IRQ_SHD : Flag for programmed EEPROM in shutdown mode
• flag is set when EEPROM timer count 3 ms after EECFG.PGM/ER was set,
Flag can be enabled to generate an interrupt/wakeup by IRQ_SHD.
IRQ_PGM : Flag for programmed EEPROM in normal mode
• flag is set when EEPROM timer count 9 ms after EECFG.PGM was set,
Flag can be enabled to generate an interrupt/wakeup by IRQ_PGM.
IRQ_ER : Flag for erased EEPROM
• flag is set when EEPROM timer count 9 ms after EECFG.ER was set,
Flag can be enabled to generate an interrupt/wakeup by IRQ_ER.
Table 5.2.1.5-9: Register EEMIRQ (0x54)

MSB LSB
Content [7:4] MIRQ_WU MIRQ_SHD MIRQ_PGM MIRQ_ER

Access 0 R R R R
MIRQ_WU : Masked flag for activated EEPROM after wake-up
= IRQ_WU and ENIRQ_WU
MIRQ_SHD : Masked Flag for programmed EEPROM in shutdown mode
= IRQ_SHD and ENIRQ_SHD
MIRQ_PGM : Masked flag for programmed EEPROM in normal mode
= IRQ_PGM and ENIRQ_PGM
MIRQ_ER : Masked flag for erased EEPROM
= IRQ_ER and ENIRQ_ER
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5.2.1.6 FLASH
The FLASH provides 4 KBytes of non-volatile program code memory. It's equipped with Error Correction Code
(ECC) method for enhanced data storage reliability.
Features:
• 4 KBytes Flash Memory;
• Error Correction Code (ECC);
• Programming up to 16 Bytes at once;
• Two mode erasing - Page and Mass Erase;
• Data verification for erased and programmed states;
• Read access time 50 ns.
5.2.2 Periphery
5.2.2.1 Main Control Unit
Clock and Reset Control Unit
Clocks :
The Smoke Detector operates with two clock sources:
1. The slow oscillator OSC100K with a nominal frequency of 100 kHz (CLK100K) is running continuously. All tasks
and timings, which have to be done continously are controlled on the slow clock domain to keep the overall cur-
rent consumption low.
2. The fast oscillator OSC8M with a nominal frequency of 8 MHz is used only in short time intervals. This oscillator
output is internally divided to provide a system clock of 4 MHz (CLK4M). To save power consumption the fast
oscillator is stopped most of the time and only woken up for short time, when the CPU is active. To stop the fast
oscillator the CPU writes a 1b to register SYSCTRL.CPU_OFF. The CPU keeps its recent state and the FLASH
changes into sleep mode. After an interrupt or an enabled wake-up event first the fast oscillator and the FLASH
and then the CPU are reactivated (refer to 5.2.2.1)
Both oscillators have trimming inputs determined during productional test. The trim-values are stored in the INFO
part of the E²PROM (refer to 5.2.1.5) on address 0x64. It is essential to copy this trimming values to the corres-
ponding register OSCTRIM (address 0x10, refer to 5.2.2.1) during system start-up.
Resets :
The following sources can reset the system:
1. The power-on reset (POR) during system power-up or insufficient supply.

2. An invalid address access caused by unexpected software behavior (refer to 5.2.1.2).
3. A watchdog reset (refer to 5.2.2.6) also caused by unexpected software behavior.
4. A reset caused by attempt to erase/program in wrong E²PROM lock state (refer to 5.2.1.5).
5. A software reset by writing a 1b to register SYSCTRL.CPU_RST.
6. A debug reset forced during debug mode.
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Interrupt and Wakeup Control Unit

The interrupt and wakeup control unit provides two possibilities to react on events with a wakeup:
Interrupts :
An interrupt is generated, if an interrupt request flag is set on register IRQSTAT and the corresponding bit on the
interrupt mask register INTM is set to enable the interrupt. An active interrupt forces a jump to the address of the
corresponding interrupt vector (refer to chapter 5.2.1.3).
If the CPU is in sleepmode (SYSCTRL.CPU_OFF = 1b) an active interrupt also activates (wakes-up) the system
clock, the CPU, FLASH and if SYSCTRL.EN_EE = 1b the E²PROM.
Note: There is one exception, the ADC interrupt (IRQ_MSKD.ADC_INT) does not wake-up the CPU, FLASH and
E²PROM and the interrupt is not handled immediately in sleep-mode.
Wake-ups :
An enabled wake-up activates (wakes-up) the system clock, the CPU, the FLASH and if SYSCTRL.EN_EE = 1b
the E²PROM, and the program is continued from the recent program location. The advantage is a faster software
reaction with the disadvantage of a complexer software development.
A wake-up is generated if an interrupt request flag is set on register IRQSTAT and the corresponding bit on the
enable wake-up register WUEN is set to enable the wake-up.
Main Control Register Description

Table 5.2.2.1-1: Main Control Registers
IRQSTAT 0x01 Interrupt Request Status Register
INTM 0x02 Interrupt Unmask Register, locked by SYSCTRL.CONFLOCK
WUEN 0x03 Wake-up Enable Register, locked by SYSCTRL.CONFLOCK
SYSCTRL 0x04 System Control Register
IRQ_MSKD 0x05 Masked Interrupt Status
SYSSTAT 0x06 System Status Register
OSCTRIM 0x10 Oscillators Trimming Register,
located in SFR, locked by SYSCTRL.CONFLOCK
POWCONF 0x11 Power Configuration Register,
Legend:
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Table 5.2.2.1-2: Register IRQSTAT (0x01)

MSB LSB
Content RED_IRQ PHY_IRQ ME_IRQ GPIO_IRQ TIM_IRQ PMON_IRQ EE_IRQ ADC_IRQ
Reset value 0 0 0 0 0 0 0 0
Access R R R R R R R R
Bit Description RED_IRQ : Interrupt request from red light interface control (alarm request),
refer to chapter 5.2.2.4). (read only, this bit is mapped from REDCTRL.RED_IRQ),
• bit is cleared by writing a 0b to REDCTRL.RED_IRQ.
PHY_IRQ : Combined interrupt request from physical interface,
refer to chapter 5.2.2.3. (read only),
• bit is reset by clearing all active interrupts on PHYSTAT.
ME_IRQ : Interrupt request from measurement control unit,
refer to chapter 5.2.2.2. (read only ,this bit is mapped from MECTRL.ME_IRQ),
• bit is cleared by reading any of the ADC_VAL registers or by writing a 0b to
MECTRL.ME_IRQ
GPIO_IRQ : Combined interrupt request from GPIOs,
• bit is reset by clearing all active interrupts on GPIOSTAT.
TIM_IRQ : Combined interrupt request from universal timer,
• bit is reset by clearing all active interrupts on TSTAT.
PMON_IRQ : Combined interrupt request from voltage monitor for V5D and LN24 (read
only , PMON_IRQ = SYSSTAT.MON5LOW or SYSSTAT.LN24LOW),
• bit is reset by clearing SYSSTAT.LN24LOW and SYSSTAT.MON5LOW.
EE_IRQ : Combined interrupt request from E²PROM control block,
• bit is reset by clearing all active interrupts on EESTAT.
ADC_IRQ : Interrupt request from ADC,
refer to chapter 5.2.2.2. (read only, this bit is mapped from MECTRL.ADC_IRQ),
• bit is cleared by reading any ADC_VAL register.
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Table 5.2.2.1-3: Register INTM (0x02)

MSB LSB
Content RED_IM PHY_IM ME_IM GPIO_IM TIM_IM PMON_IM EE_IM ADC_IM
Reset value 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description RED_IM : Interrupt unmask for RED_IRQ:
• 0b : RED_IRQ is masked (disabled),
• 1b : RED_IRQ is unmasked (enabled).
PHY_IM : Interrupt unmask for PHY_IRQ:
• 0b : PHY_IRQ is masked (disabled),
• 1b : PHY_IRQ is unmasked (enabled).
ME_IM : Interrupt unmask for ME_IRQ:
• 0b : ME_IRQ is masked (disabled),
• 1b : ME_IRQ is unmasked (enabled).
GPIO_IM : Interrupt unmask for GPIO_IRQ:
• 0b : GPIO_IRQ is masked (disabled),
• 1b : GPIO_IRQ is unmasked (enabled).
TIM_IM : Interrupt unmask for TIM_IRQ:
• 0b : TIM_IRQ is masked (disabled),
• 1b : TIM_IRQ is unmasked (enabled).
PMON_IM : Interrupt unmask for PMON_IRQ:
• 0b : PMON_IRQ is masked (disabled),
• 1b : PMON_IRQ is unmasked (enabled).
EE_IM : Interrupt unmask for EE_IRQ:
• 0b : EE_IRQ is masked (disabled),
• 1b : EE_IRQ is unmasked (enabled).
ADC_IM : Interrupt unmask for ADC_IRQ:
• 0b : ADC_IRQ is masked (disabled),
• 1b : ADC_IRQ is unmasked (enabled).
Table 5.2.2.1-4: Register WUEN (0x03)

MSB LSB
Content RED_WE PHY_WE ME_WE GPIO_WE TIM_WE PMON_WE EE_WE [0]
Reset value 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W 0
Bit Description RED_WE : Wake-up enable for RED_IRQ
PHY_WE : Wake-up enable for PHY_IRQ
ME_WE : Wake-up enable for ME_IRQ
GPIO_WE : Wake-up enable for GPIO_IRQ
TIM_WE : Wake-up enable for TIM_IRQ
PMON_WE : Wake-up enable for PMON_IRQ
EE_WE : Wake-up enable for EE_IRQ
[0] : reserved
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Table 5.2.2.1-5: Register SYSCTRL (0x04)

MSB LSB
Content [7:6] CPU_RST CONFLOCK EN_GPIO EN_EE [1] CPU_OFF
Reset value 00 0 0 0 1 0 0
Access 0 S R/W R/W R/W R/W S
Bit Description [7:6] : unused
CPU_RST : Reset command
• write a b1 to CPU_RST to reset system,
• bit is automatically cleared after reset.
CONFLOCK : Lock configuration registers (SFR, refer to 5.2.2.8)
• 0b : unlocked, CPU write access to configuration registers is enabled,
• 1b : locked, CPU write access to configuration registers is disabled.
EN_GPIO : Enable for General Purpose IO Unit
• 0b : GPIO unit disabled,
• 1b : GPIO unit enabled.
EN_EE : Enable for EEPROM
• 0b : EEPROM is constantly switched to sleep mode,
• 1b : EEPROM is activated synchronous with CPU wake-up.
[1] : reserved :
• Always write 0b !
CPU_OFF : Switch CPU, FLASH & E²PROM to sleep mode
• write a 1b to CPU_OFF to stop CPU in sleep mode,
• bit is cleared automatically by a wake-up.
Table 5.2.2.1-6: Register IRQ_MSKD (0x05)

MSB LSB
Content RED_INT PHY_INT ME_INT GPIO_INT TIM_INT PMON_INT EE_INT ADC_INT
Reset value 0 0 0 0 0 0 0 0
Bit Description RED_INT : Interrupt from red light interface control
= RED_IRQ and RED_IM (read only)
PHY_INT : Interrupt from physical interface control
= PHY_IRQ and PHY_IM (read only)
ME_INT : Interrupt from measurement control
= ME_IRQ and ME_IM (read only)
GPIO_INT : Interrupt from GPIOs
= GPIO_IRQ and GPIO_IM (read only)
TIM_INT : Interrupt from universal timer
= TIM_IRQ and TIM_IM (read only)
PMON_INT : Interrupt from voltage monitoring
= PMON_IRQ and PMON_IM (read only)
EE_INT : Interrupt from EEPROM control
= EE_IRQ and EE_IM (read only)
ADC_INT : Interrupt from ADC
= ADC_IRQ and ADC_IM (read only)
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Table 5.2.2.1-7: Register SYSSTAT (0x06)

MSB LSB
Content [7:6] EERES INVARES WDRES PUP MON5LOW LN24LOW
Reset value 00 0 0 0 1 0 0
Access 0 R/C R/C R/C R/C R/C R/C
Bit Description EERES : Invalid attempt to erase or program E²PROM (refer to 5.2.1.5)
• bit is set by invalid attemp (wrong E²PROM lock state) to set EECFG.ER/PGM, system reset
was generated,
• bit is cleared by writing a 0b to this bit location.
INVARES : Invalid address reset status bit
• bit is set if invalid address has been detected, system reset has been generated,
WDRES : Watchdog reset status bit
• bit is set if watchdog reset has happened ,system reset has been generated,
• cleared by writing a 0b to this bit location.
PUP : Power-up reset status bit
• bit is set by power-on reset,
MON5LOW : Status bit for analog monitor of the V5D voltage
• bit is set if voltage is below monitor threshold,
LN24LOW : Status bit for analog monitor of the LN24
• bit is set if voltage is below monitor threshold,
Table 5.2.2.1-8: Register OSCTRIM (0x10)

MSB LSB
Content OSC8M_TRIM[2:0] OSC100K_TRIM[4:0]
Reset value 0 1
Access R/W R/W
Bit Description OSC8M_TRIM[2:0] : 3 bit trimming of 8 MHz oscillator
• have to be copied after power-up from E²PROM INFO part address 0x64 to this location.
OSC100K_TRIM[4:0] : 5 bit trimming of 100 kHz oscillator
• have to be copied after power-up from E²PROM INFO part address 0x64 to this location.
Table 5.2.2.1-9: Register POWCONF (0x11)

MSB LSB
Content [7:2] SUP_MODE[1:0]
Reset value 0 0
Access 0 R/W
SUP_MODE[1:0] : Supply current mode
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5.2.2.2 Measurement Control Unit

The Measurement Control Unit (MEAS_CTRL) is intended to control smoke and temperature measurements. There
are two possibilities to wake-up and start a smoke measurement:
1. MEMODE = 0b: CPU controlled measurement cycle.
2. MEMODE = 1b: Periodical measurement cycle with defined time period controlled by the measurement
timer.
In both cases temperature measurements or LN24 level measurements can be started automatically by setting the
enable bit MECTRL.TME_EN or MECTRL2.SMLN24. The measured value then is saved in the ADC register and
should be read by CPU before starting the smoke measurement otherwise this value will be lost. In case of LN24
voltage measurement a threshold voltage for the LN24 comparators may be calculated. The results has to be
stored in THR1 and THR2 registers and will be applied to the comparators by means of DAC.
A 10 bit ADC is used to sample amplified chamber photo diode current as well as temperature sensor voltage.
There are two ADC sampling modes for smoke measurement depending on MECONF.AAC_EN:
1. AAC_EN = 0b: Sampling mode is irregular controlled by CPU.
2. AAC_EN = 1b: Regular ADC sampling with 2 possible configuration (10 or 20 us time per sample).
To use interrupts/wake-ups from the measurement control unit first the global interrupt mask (INTM.ME_IM) or the
global wake-up enable (WUEN.ME_WE) have to be set (refer to 5.2.2.1).
To automate the control of the measurement cycles a finite state machine is used.
This state machine has three states:

1. IDLE
• After a reset the measurement FSM starts in IDLE state.
• During this state analog part is switched off.
• Depending on MECONF.MEMODE there are two different events to switch to INIT state:
• MEMODE = 0b: Writing 1b to MECTRL.SSME starts initialization,
• MEMODE = 1b: Measurement timer starts initialization, period is configurable with MECONF.ME_PR[1:0].
2. INIT
• In this state the amplifiers are initialized.
• If the temperature measurement is enabled with MECTRL.TME_EN = 1b a temperature measurement is auto-
matically performed during this state.
• If the LN24 voltage measurement is enabled with MECTRL2.SMLN24 = 1b a LN24 voltage measurement is
automatically performed during this state.
• After initialization time tINIT the state changes to ACTIVE and the interrupt flag MECTRL.ME_IRQ should be
used to wake-up the CPU.
3. ACTIVE
• After wake-up the CPU can first read the temperature value from the ADC register, if the temperature meas-
urement was enabled.
• Depending on MECONF.AAC_EN the ADC conversion is started by writing a 1b to MECTRL.SOC.
• AAC_EN = 0b : A single ADC conversion is started.
• AAC_EN = 1b : An automatically, regular ADC conversion is started.
• With writing a 1b to MECTRL.LED_EN the smoke chamber LED1 is switched on with a current pulse of length
tLED.
• After the measurement, i.e. stopping ADC conversion with subsequent post-processing state changes back to
IDLE by going into sleep-mode (SYSCTRL.CPU_OFF = 1b).
At any time and any state a measurement cycle is stopped and the measurement timer is restart in IDLE state by
first writing MECTRL.SSME = 0b and then writing SYSCTRL.CPU_OFF = 1b.
38 / 86
The following chapters show examples of different configured measurements.
Measurement Cycle controlled by Timer

Figure 5.2.2.2-1 depicts an example of a measurement cycle controlled by timer.
1 2 3 45 67 8 9 10
MEAS_TIMER
State IDLE INIT ACTIVE IDLE INIT

tINIT
registers tCYCLE
MECTRL.SSME Set by timer Cleared by CPU
MECTRL.ME_IRQ Set by timer Cleared by CPU

wake-up
SYSCTRL.CPU_OFF Cleared by wake-up Set by CPU
MECTRL.SOC
MECTRL.LED_EN Set by CPU Cleared automatically
Pin LED tLED
Amplifier output
ADC Post
conversion processing
Figure 5.2.2.2-1: Example : Measurement Cycle controlled by timer (MECONF.MEMODE = 1b)
Settings:
• MECONF.MEMODE = 1b, timer controlled measurements,
• INTM.ME_IM = 1b or WUEN.ME_WE = 1b to enable wake-up/interrupt by measurement timer.
1. The measurement timer changes the state from IDLE to INIT and sets the bit MECTRL.SSME.
2. During state INIT the amplifiers are initialized and a temperature measurement can be enabled (for
details refer to Figure 5.2.2.2-3 in chapter 5.2.2.2).
3. The measurement timer set the interrupt request flag MECTRL.ME_IRQ and generates a wake-up/inter-
rupt. The state changes to ACTIVE.
4. The wake-up activates the CPU (SYSCTRL.CPU_OFF = 0b).
5. The CPU has to clear the interrupt request, writing a 0b to MECTRL.ME_IRQ.
6. The CPU starts to control the ADC (MECTRL.SOC, for details refer to chapter 5.2.2.2). First the noise
level is measured (before the LED pulse).
7. The CPU set the bit MECTRL.LED_EN. After synchronization a current pulse of length t LED is forced to
pin LED.
8. The measurement is stoped by clearing the bit MECTRL.SSME.
9. After post processing the CPU switches to sleepmode (SYSCTRL.CPU_OFF = 1b) and the state
changes to IDLE.
10.The measurement timer starts the next measurement cycle.
39 / 86
Measurement Cycle controlled by CPU

Figure 5.2.2.2-2 is an example of a measurement cycle controlled by CPU.
1 23 4 5 67 89 10 11 12
State IDLE INIT ACTIVE IDLE INIT

tINIT
registers tCYCLE
MECTRL.SSME Set by CPU Cleared by CPU

wake-up
Cleared by wake-up
SYSCTRL.CPU_OFF Set by CPU Cleared by wake-up Set by CPU
MECTRL.SOC
Pin LED tLED
Amplifier output
ADC Post
Figure 5.2.2.2-2: Example : Measurement Cycle controlled by CPU (MECONF.MEMODE = 0b)
Settings:
• MECONF.MEMODE = 0b, CPU controlled measurements
• INTM.ME_IM = 1b or WUEN.ME_WE = 1b to enable wake-up/interrupt by measurement timer
1. The CPU wakes-up by protocol for a measurement request.

2. The CPU changes the state from IDLE to INIT by setting the bit MECTRL.SSME.
3. The CPU switches to sleepmode (SYSCTRL.CPU_OFF = 1b).
4. During state INIT the amplifiers are initialized and a temperature measurement can be enabled (for
details refer to Figure 5.2.2.2-4 in chapter 5.2.2.2).
5. After tINIT the measurement timer set the interrupt request flag MECTRL.ME_IRQ and generates a wake-
up/interrupt. The state changes to ACTIVE.
7. The CPU has to clear the interrupt request flag, writing a 0b to MECTRL.ME_IRQ.
8. The CPU starts to control the ADC (MECTRL.SOC, for details refer to chapter 5.2.2.2). First the noise
level is measured (before the LED pulse).
9. The CPU set the bit MECTRL.LED_EN. After synchronization a current pulse of length t LED is forced to
pin LED.
10.The measurement is stoped by clearing the bit MECTRL.SSME.
11.After post processing the CPU switches to sleepmode (SYSCTRL.CPU_OFF = 1b) and the state
changes to IDLE.
12.The next measurement cycle starts after a measurement request via protocol.
40 / 86
Temperature and LN24 Voltage Measurement

An example of a temperature or LN24 voltage measurement in the timer controlled mode is illustrated in Figure
5.2.2.2-3.
The timing diagram for LN24 measurement is identically, with the only difference that instead of MECTRL.TME_EN
MECTRL2.SMLN24 has to be set.
It should be noticed, that LN24 voltage must be measured when no data transfer is in progress. It is recommended
to perform measurement several times and check plausibility of the result.
12 3 45 6 78
MEAS_TIMER
State ACTIVE IDLE INIT ACTIVE IDLE

tINIT
registers tINACTIVE tACTIVE
MECTRL.SSME Set by timer Cleared by CPU
MECTRL.TME_EN Set by CPU Cleared automatically

wake-up
MECTRL.SOC
tTEMP_DELAY
Pin VTDRV ADC conversion

of temperature value
tTEMP
Pin LED tLED
Amplifier output
Figure 5.2.2.2-3: Example : Cycle incl. Temperature controlled by timer (MECONF.MEMODE = 1b)
Settings:
• MECONF.MEMODE = 1b, timer controlled measurements
1. At the end of last measurement cycle the CPU sets MECTRL.TME_EN or MECTRL2.SMLN24 to enable
a temperature or LN24 voltage measurement for the next measurement cycle.
2. End of last measurement by going to sleepmode (SYSCTRL.CPU_OFF = 1b).
3. The measurement timer changes the state from IDLE to INIT and sets the bit MECTRL.SSME.
4. After tTEMP_DELAY an automized temperature or LN24 measurement is started.
5. After tTEMP the measurement is finished and the ADC converted temperature or LN24 voltage value is
available on register ADCVAL.
6. After amplifier initialization the measurement timer set the interrupt request flag MECTRL.ME_IRQ and
generates a wake-up. The state changes to ACTIVE.
8. The CPU read the temperature value from register ADCVAL. With this read access the interrupt request
flag is reset (MECTRL.ME_IRQ = 0b).
41 / 86
An example of a temperature measurement in the CPU controlled mode is shown in Figure 5.2.2.2-4.
The timing diagram for LN24 measurement is identically, with the only difference that instead of MECTRL.TME_EN
MECTRL2.SMLN24 has to be set.
1 2 34 56 7 89
State ACTIVE IDLE INIT ACTIVE IDLE

tINIT
registers tINACTIVE tACTIVE
MECTRL.SSME Set by CPU Cleared by CPU
MECTRL2.SMLN24 Set by CPU Cleared automatically

wake-up
Cleared by wake-up
MECTRL.SOC
tTEMP_DELAY
Pin VTDRV ADC conversion

of LN24 voltage value
tTEMP
Pin LED tLED
Amplifier output
Figure 5.2.2.2-4: Example : Cycle incl. LN24 controlled by CPU (MECONF.MEMODE = 0b)
Settings:
• MECONF.MEMODE = 0b, CPU controlled measurements
1. The end of the last measurement by going to sleepmode (SYSCTRL.CPU_OFF = 1b).

2. The CPU wakes-up by protocol for a measurement request.
3. The CPU changes the state from IDLE to INIT by setting the bits MECTRL.SSME and MECTRL2.SML-
N24 to enable the LN24 voltage measurement.
4. The CPU switches to sleepmode (SYSCTRL.CPU_OFF = 1b).
5. After tTEMP_DELAY an automized LN24 voltage measurement is started.
6. After tTEMP the LN24 measurement is finished and the ADC converted voltage value is available on
register ADCVAL.
7. After amplifier initialization the measurement timer set the interrupt request flag MECTRL.ME_IRQ and
generates a wake-up. The state changes to ACTIVE.
9. The CPU read the voltage value from register ADCVAL. With this read access the interrupt request flag
is reset (MECTRL.ME_IRQ = 0b).
42 / 86
Smoke Measurement Phase

Figure 5.2.2.2-5 shows an example of the smoke measurement phase with regular ADC conversion.
1 2 34 5 6 78 9 10 11
...
State INIT ACTIVE IDLE
registers
MECTRL.SSME Cleared by CPU
MECTRL.ME_IRQ Cleared by CPU

wake-up
SYSCTRL.CPU_OFF Cleared
Set by CPU
by wake-up
MECTRL.SOC
MECTRL.EOC
MECTRL.ADC_IRQ
ADCVAL
tSAMP
Set by CPU Cleared automatically

MECTRL.LED_EN
Pin LED tLED
Amplifier output
ADC Post
Figure 5.2.2.2-5: Example : Automatic ADC conversion (MECONF.AAC_EN = 1b)
Settings:
• MECONF.MEMODE = 0b or 1b
• MECONF.AAC_EN = 1b
3. The CPU has to clear the interrupt request by writing a 0b to MECTRL.ME_IRQ or reading ADCVAL.
4. The CPU sets MECTRL.SOC to start an automized ADC sampling. MECTRL.EOC is reset by hardware
when an ADC conversion starts.
5. MECTRL.EOC and MECTRL.ADC_IRQ are set when the an ADC conversion has finished. The conver-
ted value is available on register ADCVAL.
6. When MECTRL.EOC becomes 0b the next ADC conversion is started.
7. The CPU reads register ADCVAL. With this read access MECTRL.ADC_IRQ is reset.
8. The CPU set the bit MECTRL.LED_EN. After synchronization a current pulse is forced to pin LED.
9. After tLED the current pulse is finished and MECTRL.LED_EN is automatically reset.
10.The measurement and the automatic ADC convesion are stopped by clearing the two bits MEC-
TRL.SSME and MECTRL.SOC.
11.After post processing the CPU switches to sleepmode (SYSCTRL.CPU_OFF = 1b) and state changes
to IDLE.
43 / 86
Figure 5.2.2.2-6 depicts an example of a smoke measurement phase with single ADC conversion, i.e. the CPU
starts each single ADC conversion.
1 2 3 4 5 67 8 9 10 11 12
...
State INIT ACTIVE IDLE
registers
MECTRL.SSME Cleared by CPU
MECTRL.ME_IRQ Cleared by CPU

wake-up
SYSCTRL.CPU_OFF Cleared
Set by CPU
by wake-up
MECTRL.SOC
MECTRL.EOC
MECTRL.ADC_IRQ
ADCVAL
Set by CPU Cleared automatically

MECTRL.LED_EN
Pin LED tLED
Amplifier output
ADC Post
Figure 5.2.2.2-6: Example : CPU controlled ADC converion (MECONF.AAC_EN = 0b)
Settings:
• MECONF.MEMODE = 0b or 1b
• MECONF.AAC_EN = 0b
3. The CPU has to clear the interupt request, writing a 0b to MECTRL.ME_IRQ or reading ADCVAL.
4. The CPU sets MECTRL.SOC to start a single ADC sampling.
5. MECTRL.SOC and MECTRL.EOC are reset by hardware when the ADC conversion starts.
6. MECTRL.EOC and MECTRL.ADC_IRQ are set when the ADC conversion has finished. The converted
value is available on register ADCVAL.
7. The CPU reads ADCVAL and MECTRL.ADC_IRQ is reset.
8. The CPU set the bit MECTRL.LED_EN. After synchronization a current pulse is forced to pin LED.
9. After tLED the current pulse is finished and MECTRL.LED_EN is automatically reset.
10.The CPU reads the last ADC value.
11.The resets MECTRL.SSME to stop the measurement.
12.After post processing the CPU switches to sleepmode (SYSCTRL.CPU_OFF = 1b) and state changes
to IDLE.
44 / 86
Timing Definitions
Table 5.2.2.2-1: Measurement Timing Table
Name Time Description
tINIT 7.8 ms Time for initialization of amplifier from setting MECTRL.SSME to setting
of interrupt flag ME_IRQ
tTEMP_DELAY 1000 us Time for initialization of amplifier from setting MECTRL.SSME until start
of temperature measurement
tTEMP 20 us Duration of temperature measurement
Measurement Control Register Description

Table 5.2.2.2-2: Measurement Control Registers
LEDCONF 0x15 LED1 configuration register,
AMPCONF 0x16 Current-to-voltage converter/amplifier configuration register,
locked by SYSCTRL.CONFLOCK.
MECONF 0x17 Measurement configuration register,
ADCVAL10_H 0x30 High byte 10 bit ADC value
ADCVAL10_L 0x31 Low byte 10 bit ADC value
ADCVAL8 0x32 8 bit ADC value
MECTRL 0x33 Measurement Control Register
MECTRL2 0x34 Measurement Control Register 2
THR1 0x35 LN24 Comparator Threshold Voltage Level 1. In Modulation Type 3 used as
SYNC Level
THR2 0x36 LN24 Comparator Threshold Voltage Level 2. In Modulation Type 3 used as Data
Level. Not used in other modulation types1)
1)
Modulation Type 3 only
Legend:
45 / 86
Table 5.2.2.2-3: Register LEDCONF (0x15)

MSB LSB
Content [7:5] LED_DAC[4:0]
Reset value 0 0
Access 0 R/W
LED_DAC[4:0] : LED DAC (current) setting :

• 00000b : ILED = 0 mA
• 00001b : ILED = 16.13 mA
• ... (+ 16.13 mA steps)
• 11111b : ILED = 500.0 mA
Table 5.2.2.2-4: Register AMPCONF (0x16)

MSB LSB
Content [7:6] ON_MUX AMP_TSW AMP_GAIN[3:0]
Reset value 00 0 0 0000
Access 0 R/W R/W R/W
ON_MUX : Connect ADC input

• 0b : unconnected, ADC input is open,
• 1b : connected, multiplexer is connected to ADC.
AMP_TSW : Test switch control
• 0b : unconnected,
• 1b : connect amplifier output to VTSEN.
AMP_GAIN[3:0] : Current-to-voltage conversion factor setting
• 1111b : FCONV = 0.022 V/nA
• 1110b : FCONV = 0.022 V/nA
• 1101b : FCONV = 0.022 V/nA
• 1100b : FCONV = 0.045 V/nA
• 1011b : FCONV = 0.065 V/nA
• 1010b : FCONV = 0.085 V/nA
• 1001b : FCONV = 0.105 V/nA
• 1000b : FCONV = 0.135 V/nA
• 0111b : FCONV = 0.165 V/nA
• 0110b : FCONV = 0.21 V/nA
• 0101b : FCONV = 0.27 V/nA
• 0100b : FCONV = 0.34 V/nA
• 0011b : FCONV = 0.43 V/nA
• 0010b : FCONV = 0.53 V/nA
• 0001b : FCONV = 0.61 V/nA
• 0000b : FCONV = 0.67 V/nA (default)
46 / 86
Table 5.2.2.2-5: Register MECONF (0x17)

MSB LSB
Content [7:5] ADCRA ME_PR[1:0] AAC_EN MEMODE
ADCRA : ADC sampling rate

Valid if AAC_EN = 1b
• 0b : 10 µs
• 1b : 20 µs
When AAC_EN = 0b this bit is unused.
ME_PR[1:0] : Measurement cycle period
The measurement cycle period consists of:
tCYCLE = tINACTIVE + tACTIVE, where
tINACTIVE is the sum of IDLE time and INIT time. tINACTIVE is configurable with:
• 00b : tINACTIVE = 0.8s
tACTIVE is software depending in the range of 0.2 - 4 ms.
AAC_EN : Enable automatic ADC conversion
• 0b : each individual SOC pulse is generated by the CPU,
• 1b : SOC pulses are generated automatically with sampling rate MECONF.ADCRA.
MEMODE : Measurement mode
• 0b : measurement period is controlled by CPU,
• 1b : measurement period controlled by measurement timer.
Table 5.2.2.2-6: Register ADCVAL10_H (0x30)

MSB LSB
Content [7:2] ADCVAL[9:8]
Reset value 000000 00
Access 0 R
Bit Description [7:2] : unused ; filled with 0´s, if read.
ADCVAL[9:8] : High byte (2 MSBs) of 10 bit ADC value (unsigned)
Table 5.2.2.2-7: Register ADCVAL10_L (0x31)

MSB LSB
Content ADCVAL[7:0]
Reset value 00000000
Access R
Bit Description ADCVAL[7:0] : Low byte (8 LSBs) of 10 bit ADC value
47 / 86
Table 5.2.2.2-8: Register ADCVAL8 (0x32)

MSB LSB
Content ADCVAL[9:2]
Access R
Bit Description ADCVAL[9:2] : 8 bit ADC value (unsigned)
Table 5.2.2.2-9: Register MECTRL (0x33)

MSB LSB
Content ME_IRQ EOC ADC_IRQ DLOST LED_EN SOC TME_EN SSME
Reset value 0 1 0 0 0 0 0 0
Access R/C R R/C R/C R/S R/W R/S S
Bit Description ME_IRQ : Measurement interrupt flag
• flag is set by hardware after amplifier initialization phase,
• flag is cleared by reading any of the ADC_VAL registers or by writing a 0b to this bit position.
EOC : End of analog-to-digital conversion
• bit is set, if conversion is ready,
• bit is cleared with next SOC pulse.
ADC_IRQ : ADC interrupt request flag (Data valid flag)
• flag is set with rising edge of EOC, new ADC data is valid,
• flag is cleared by reading any of the ADC_VAL registers.
DLOST : Data lost flag
• flag is set with rising edge of EOC, when ADC_IRQ is already set, i.e. previous data were not
read by CPU,
• flag is cleared by reading any of the ADC_VAL registers.
LED_EN : LED enable
• with writing a 1b to this location the LED1 is switched on, synchronized by CLK100K.
• LED1 is switched off by internal timer after 100 µs and LED_EN is automatically cleared.
SOC : Start of analog-to-digital conversion
Case 1 : ME_CONF.AAC_EN = 0b
• writing a 1b to this location starts a single analog-to-digital conversion.
• bit is automatically cleared, after starting conversion cycle
Case 2 : ME_CONF.AAC_EN = 1b
• writing a 1b to this location starts automated analog-to-digital conversion with constant
sampling rate according to ME_CONF.ADCRA.
TME_EN : Temperature measurement enable
• if this bit is set a temperature measurement is performed during initialization of a measure-
ment sequence,
• after temperature measurement this bit is cleared automatically.
SSME : Start smoke measurement sequence
• writing a 1b to this location starts a measurement sequence,
• writing a 0b to this bit together with SOC = 0b stops the ADC conversion and switch off analog
part to conserve energy.
Note : If Automatic ADC conversion is used (AAC_EN='1') measurement should be stopped
before going in sleep mode.
48 / 86
Table 5.2.2.2-10: Register MECTRL2 (0x34)

MSB LSB
Content - - - - - - - SMLN24
Reset value 0 0 0 0 0 0 0 0
Access R R R R R R R R/W
Bit Description SMLN24 : Start LN24 Measurement Sequence
Table 5.2.2.2-11: Register THR1 (0x35)

MSB LSB
Content reserved THR1[6:0]
Reset value 0 10h
Access R R/W
Bit Description THR1[6:0] : threshold setting for LN24 sync and data comparator
VTH1=(THR1)/2 + 0,5V
min: 0000000b : 0,5V
max: 1011111b : 48V
to be calculated according to
MODT=00b THR1 = (PROT_THR1)*2 + 7

MODT=1xb THR1 = (ADCVAL8)/2 + (PROT_THR1)*2 - 37
Table 5.2.2.2-12: Register THR2 (0x36)

MSB LSB
Content reserved THR2[6:0]
Reset value 0 10h
Access R R/W
Bit Description THR2[6:0] : threshold setting for LN24 data comparator for modulation Type 3
VTH2=(THR2)/2 + 0,5V
min: 0000000b : 0,5V
max: 1011111b : 48V
to be calculated according to
THR2 = ((ADCVAL8)+1)/2 + (PROT_THR2)*4 - 33
49 / 86
LN24
TH2 TH1
9.3125M* R1 State machine
312.125k* R2 Register
ADC
MUX ADC ADCVAL8
Register
375.375k* R3
CPU THR1 DAC1
Register
PROT_THR1 THR2 DAC2
* typical values
PROT_THR2
Figure 5.2.2.2-7: Bus receiver threshold calculation
BUS receiver threshold calculation

Absolute Threshold:
Demodulator threshold 1,absolute (referred to LN0),MODT=00b
The CPU calculated the THR1 register value for the DAC1 directly from the register PROT_THR1:
THR1 = (PROT_THR1)*2 + 7
Relative Threshold:
First the LN24 voltage is measured by ADC in the moment, when no modulation is on the BUS. Normally before
every smoke measurement, the LN24 voltage can be measured. The CPU calculate the receiver threshold with the
ADC value from LN24 voltage and the PROT_THR register. The result will be stored in the THR1 and THR2
register until the next LN24 voltage measurement.
Calculation formula:
Demodulator threshold 1, relative to LN24 (DC-level),MODT=10b or 11b
THR1 = (ADCVAL8)/2 + (PROT_THR1)*2 - 37
Demodulator threshold 2, relative to LN24 (DC-level),MODT=11b

THR2 = (ADCVAL8+1)/2 + (PROT_THR2)*4 - 33
50 / 86
5.2.2.3 Physical Interface Control Unit

The Physical Interface Control Unit (LN24_CTRL) is intended to support the CPU in processing a wide range of dif-
ferent one wire protocols. In most cases only one interrupt/wakeup per bit is needed to interpret the received data
and to force the answer. The CPU is kept in sleep mode as long as possible to decrease its current consumption.
Receiving
Voltage modulation on pin LN24 are converted to a digital level in the analog part of the physical interface by com-
parison with one or two configurable thresholds.
Depending on the setting of the modulation type defined in register PHYCONF3.MODT[1:0] the threshold is defined
referred to LN0 (ground level) in Type 1 or referred to the DC-level of LN24 in Type 2.
In modulation of type 2 pulses below or above the DC-level of LN24 can be detected depending on the interface
requirements. In Modulation Type 3 two configurable thresholds are used.
In Modulation Type 1 and Type 2 only the threshold V TH1 is used. It is generated by a DAC from a digital value
stored in the register THR1 and will be derived from the setting of register PHYCONF1.PROT_THR1[4:0] and the
voltage of LN24 line (Type 2 only).
In case of type 2 modulation, the actual value of V TH1 has to be calculated by software after measurement of LN24
voltage (see chapter Measurement control logic).
The measurement has to be repeated periodically to ensure that the threshold will follow the deviation of LN24
voltage.
All type of modulation use the pulse length modulation concept using one level V TH1 comparator as described in this
section. The output of this comparator will form the signal RXD.
The second comparator used in type 3 is for synchronisation purposes only.
Two different receiving modes according to Table 5.2.2.3-1 and Figure 5.2.2.3-1 are configurable to handle differ-
ent protocols depending on register PHYCONF1.RXDMODE. The two modes differ in the definition of the leading
edge (bit-start) and the captured time (RXDCAP), or in other words, if the protocol uses up or down modulation.
The leading edge resets and starts two 8 bit timers, the receiving capture/compare timer (RXD_TIMER) and the
transmitting delay/duration timer (TXD_TIMER). Both timers run with the slow clock CLK100K. Additionally the
interrupt flag PHYSTAT.IRQ_LE is set by the leading edge, it can be configured to generate an interrupt/wakeup
with PHYCTRL.ENIRQ_LE.
The timer capture function provides the measured time between two RXD edges (from leading edge to trailing
edge). The captured time can be read on register RXDCAP. After capturing the interrupt flag PHYSTAT.IRQ_CAP
is set. It can be enabled with PHYCTRL.ENIRQ_CAP to generate an interrupt/wakeup.
If the RXD_TIMER reaches its maximum value 0xFF the overflow flag PHYSTAT.RXD_TOF is set and the
RXD_TIMER is stopped. This flag can also be configured to generate an interrupt/wakeup with
PHYCTRL.ENIRQ_TOF.
Table 5.2.2.3-1: Receiving modes

RXDMODE Leading edge Trailing edge Captured time (RXDCAP)
0b Falling edge of RXD Rising edge of RXD Falling to rising edge of RXD
1b Rising edge of RXD Falling edge of RXD Rising to falling edge of RXD
51 / 86
leading edge (bit start) trailing edge next leading edge (next bit)
RXDMODE = 0b
RXD
RXDMODE = 1b
RXD
RXD_TIMER ... 0 1 2 ... ... ... ... 0 1 2 ...
timer reset captured time timer reset

RXDCAP
Figure 5.2.2.3-1: Timing Diagram for Receiving Modes
The CPU can write two compare values to registers RXDCMP1 and RXDCMP2. With this functions it is possible to
observe both, a low phase as well as a high phase on RXD.
1. The first compare function is started with the leading edge and if the recent timer value RXD_TIMER =
RXDCMP1 before the trailing edge the flag IRQ_CMP1 is set.
2. The second compare function is started with the trailing edge, so the captured time RXDCAP between
leading and trailing edge is already available. If (RXD_TIMER - RXDCAP) = RXDCMP2 the flag
IRQ_CMP2 is set.
If RXDCMP1/2 compares an RXD low or high phase is determined by PHYCTRL.RXDMODE. Both flags PHYS-
TAT.IRQ_CMP1 and PHYSTAT.IRQ_CMP2 can be used to generate an interrupt/wakeup. This is enabled by
PHYCTRL.ENIRQ_CMP1 and PHYCTRL.ENIRQ_CMP2
Table 5.2.2.3-2: Compare Functions

RXDMODE RXDCMP1 RXDCMP2
0b Compare low phase between leading and trail- Compare high phase between trailing and next
ing edge leading edge
1b Compare high phase between leading and Compare low phase between trailing and next
trailing edge leading edge
52 / 86
RXDMODE = 0b
RXD
RXDMODE = 1b
RXD
IRQ_CMP1 is not set IRQ_CMP2 is not set
RXD_TIMER ... 0 1 2 ... ... ... ... 0 1 2 ...
RXDCAP
RXDCMP1 RXDCMP2
Flag IRQ_CMP1 is set, if Flag IRQ_CMP2 is set, if

RXD_TIMER = RXDCMP1 RXD_TIMER - RXDCAP = RXDCMP2
before trailing edge before next leading edge
Figure 5.2.2.3-2: Timing Diagram for Compare Functions
Besides the capture function the physical interface provides an additional possibility to automatically read a
received bit.
The CPU can write a defined time to register RXDREAD. If the timer value RXD_TIMER reaches the strobe time
RXDREAD the recent level of RXD is stored to PHYSTAT.RXD_RD and the flag PHYSTAT.IRQ_READ is set (refer
to Figure 5.2.2.3-3). This flag can be used to generate an interrupt/wakeup enabled by PHYCTRL.ENIRQ_READ.
RXD_RD = 1
RXDMODE = 0b
RXD
RXD_RD = 0
RXD_RD = 1
RXDMODE = 1b
RXD
RXD_RD = 0
RXD_TIMER ... 0 1 2 ... ... ... 0 1 2 ...
RXDREAD
If RXD_TIMER = RXDREAD
Flag IRQ_READ is set, and recent
level of RXD is stored to PHYSTAT.RXD_RD
Figure 5.2.2.3-3: Timing Diagram for RXD Read Function (RXDSAMP = 0b)
The delay time between different slaves caused by long wires can vary. For a robust reading two methods of
sampling the RXD_RD signal are implemented. PHYCONF1.RXDSAMP selects if just one or two subsequent
53 / 86
samples are used for RXD_RD and PHYCONF1.RXDGATE selects how the two samples are combined to the final
RXD_RD (refer to Table 5.2.2.3-3).
Table 5.2.2.3-3: RXD read sampling configuration

RXDSAMP RXDGATE Description
0b Xb Just one sample is generating the RXD_RD bit.
1b 0b Two subsequent samples (sampling rate 10 us) are used to generate the
RXD_RD bit, where this samples are combined by an AND-gate.
IRQ_READ is set with taking the 2. sample.
1b 1b Two subsequent samples (sampling rate 10 us) are used to generate the
RXD_RD bit, where this samples are combined by an OR-gate.
IRQ_READ is set with taking the 2. sample.
To prevent unintended or self-induced timer resets and interrupts by forcing current on LN24 (via TXD) or disturb-
ances on LN24, the interface control unit provides a blockage function:
1. After the 1. trailing edge any possible leading edge is blocked to reset RXD_TIMER and the interrupt
flag PHYSTAT.IRQ_LE is suppressed until RXD_TIMER reaches the value on register RXDBLK.
2. After the 1. trailing edge any possible 2. trailing edge is blocked to capture the recent timer value and
the interrupt flag PHYSTAT.IRQ_CAP is suppressed until RXD_TIMER reaches the value on register
RXDBLK.
Depending on PHYCONF1.RXDMODE there are two cases for blockage function, refer to Figure 5.2.2.3-4 and Fig-
ure 5.2.2.3-5.
TXD
LN24 is pulled down

by current modulation
→ RXD is influenced by TXD
RXDMODE = 0b
RXD
2. Trailing edge
is blocked:
RXD_TIMER ... 0 1 2 ... Leading edge → no 2. capture ... 0 1 2 ...
is blocked: → no interrupt
→ no timer reset from edge
timer reset → no interrupt timer reset
1. Trailing is valid: from edge
→ capture function active
→ interrupt flag is set
→ blocking is activated
RXDBLK
Figure 5.2.2.3-4: Timing Diagram for Blockage Function : RXDMODE = 0b
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TXD
LN24 is pulled down

by current modulation
→ RXD is influenced by TXD
RXDMODE = 1b
RXD
2. Trailing edge
is blocked:
RXD_TIMER ... 0 1 2 ... Leading edge → no 2. capture ... 0 1 2 ...
is blocked: → no interrupt
→ no timer reset from edge
timer reset → no interrupt
timer reset
from edge
1. Trailing is valid:
→ capture function active
→ interrupt flag is set
→ blocking is activated
RXDBLK
Figure 5.2.2.3-5: Timing Diagram for Blockage Function : RXDMODE = 1b
In Mode 3 the data detection is performed with two different comparators for data and synchronization information
separately.
Additional to the data- and sync level detection performed by one comparator with a configurable threshold V TH1 , a
second comparator with threshold VTH2 for data level detection is implemented (see Figure 5.2.2.3-6).
The threshold of the second comparator is configurable according to Table 4.1.2-1 by a parameter defined in
register PHYCONF3.PROT_THR2[2:0] and LN24 voltage.
The output of VTH1 comparator in this case too will form the TXD Signal mentioned in the timing diagrams. The out-
put value of VTH2 comparator will only influence register PHY_STAT2. By evaluation of this register it is possible to
distinguish between data and sync pulses.
Figure 5.2.2.3-6: Receiver Detection according to Modulation Type 3
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Transmitting
For transmitting data, i.e. force a modulation current to pin LN24, the bit to transmit have to be written to register
PHYCTRL.TXD. This bit is internally buffered and has to be written before the leading edge to be transmitted after
the leading edge. The bit for the next leading edge can be written during or even before actual transmission (cur-
rent forcing). With the leading edge PHYCTRL.TXD is internally buffered and automatically cleared. Also with lead-
ing edge PHYCTRL.TXD is latched to PHYCTRL.TXD_LAT, to be able to read what will be or is transmitted in
recent bit time.
For timing the transmitting delay/duration timer (TXD_TIMER) is used. If PHYCTRL.TXD is high the transmitting
timer generates a current modulation pulse IMOD with current setting determined by PHYCONF2.TXD_CUR[4:0. The
current pulse is generated with two configurable timings, a delay from leading edge (bit-start) to TXD-pulse and the
duration of the pulse (refer to Figure 5.2.2.3-1). If PHYCTRL.TXD is low no pulse is generated.
The delay is determined by register TXDDEL and the pulse duration is according to register TXDDUR. The PHYC-
TRL.TXD has to be written before the leading edge. In the special case that the delay is 0 (TXDDEL = 0x00), the
current force is immediately and the TXD_TIMER is directly loaded with duration value TXDDUR (refer to Figure
5.2.2.3-10).
leading edge (bit start) next leading edge (next bit)
RXDMODE = 0b
RXD
RXDMODE = 1b
RXD
TXD_DUR
TXD_DEL
TXD_TIMER ... ... 0 ... ... 0 0 1 2 ...
PHYCTRL.TXD has to timer reset

load timer with delay, load timer with duration
be written before the
after synchronization
leading edge,
force current
otherwise it is TXD if PHYCTRL.TXD=1
transmitted after the
next leading edge
TXDDEL TXDDUR
Figure 5.2.2.3-7: Timing Diagram for Transmitting
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Interrupts
To use interrupts/wake-ups from the physical interface first the global interrupt mask (INTM.PHY_IM) or the global
wake-up enable (WUEN.PHY_WE) have to be set (refer to 5.2.2.1). After this six different flags can be locally
enabled to generate an interrupt/wakeup (refer to Table 5.2.2.3-4 and registers PHYSTAT and PHYCTRL):
Table 5.2.2.3-4: Physical Interface Interrupts

Flag on PHYS- Enable interrupt on PHYC- Description
TAT TRL
IRQ_LE ENIRQ_LE Interrupt request generated from leading edge on RXD
IRQ_CAP ENIRQ_CAP Interrupt request generated from trailing edge on RXD, when
RXDCAP is captured
IRQ_CMP1 ENIRQ_CMP1 Interrupt request generated from RXD_TIMER, if recent timer
RXD_TIMER = RXDCMP1 before the trailing edge. Refer to
Figure 5.2.2.3-2.
IRQ_CMP2 ENIRQ_CMP2 Interrupt request generated from RXD_TIMER, if RXD_TIMER -
RXDCAP = RXDCMP2 before the next trailing edge. Refer to
Figure 5.2.2.3-2.
IRQ_READ ENIRQ_READ Interrupt request generated from RXD_TIMER, if recent timer
RXD_TIMER = RXDREAD independent of the trailing edge.
Refer to Figure 5.2.2.3-3.
IRQ_TOF ENIRQ_TOF Interrupt request generated from RXD_TIMER, if timer has an
overflow, i.e. the timer stops at 0xFF.
Figure 5.2.2.3-8 depicts all details about generation of physical interface interrupt/wakeup generation
(refer also to chapter 5.2.2.1), incl. the global interrupt mask and wake-up enable registers.
Physical Interface Interrupt Control Interrupt and Wake-up Control Unit
addr 0x28 addr 0x02

PHYSTAT INTM
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
IRQ_LE
ENIRQ_LE AND 7 PHY_IM
PHY_IRQ AND PHY_INT
IRQ_CAP 6
ENIRQ_CAP AND
5
IRQSTAT
IRQ_CMP1
4
ENIRQ_CMP1 AND
PHY_IRQ 3
IRQ_CMP2 OR
2
ENIRQ_CMP2 AND
1 OR WAKEUP
addr 0x01
IRQ_READ PHY_WE AND

ENIRQ_READ AND 0
IRQ_TOF
ENIRQ_TOF AND
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
PHYCTRL addr 0x27 addr 0x03

WUEN
Figure 5.2.2.3-8: Physical Interface Interrupts/Wakeups
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Synchronization
The received signal RXD is synchronized to CLK100K. For this reason any timing derived from RXD have a
sampling jitter of TRXD,JIT = 10 µs and a synchronization time of T RXD,SYNCH = 5 µs.
Figure 5.2.2.3-9 depicts the RXD synchronization.
Sampling jitter Synchronization time

TRXD,JIT= 0 – 10 us TRXD,SYNCH = 10 us
RXD
CLK100K
RXD_RE ↑:
RXD_FE ↓:
RXD_RE2 ↑:
LOAD1_TIMER =
not RXD_FE and RXD_RE2
RXD_TIMER X 0 1 2 3 4
TXD_TIMER 0 TXDDEL
=3
2 1 TXDDUR TXDDUR
-1
LOAD_TXDDUR
PHY_TXD
Figure 5.2.2.3-9: RXD Synchronization , TXDDEL > 0
Figure 5.2.2.3-10 shows the special case for TXDDEL = 0x00.
Sampling jitter Synchronization time

TRXD,JIT= 0 – 10 us TRXD,SYNCH = 10 us
RXD
CLK100K
RESET_RXD_TIMER =
not RXD_RE and RXD_FE
RXD_TIMER X 0 1 2 3 4 5
LOAD_TXDDEL =
not RXD_FE and RXD_RE2
TXD_TIMER 0 TXDDUR
=4
3 2 1 0
LOAD_TXDDUR
PHY_TXD
Figure 5.2.2.3-10: RXD synchronization , TXDDEL = 0
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Interface Control Register Description

Table 5.2.2.3-5: Physical Interface Control Registers
PHYCONF1 0x12 Physical Interface Configuration Register 1,
TXDDEL 0x20 Transmitter Configuration : Transmitting delay
TXDDUR 0x21 Transmitter Configuration : Transmitting duration
RXDCMP1 0x22 Receiving Timer Compare Value 1
RXDBLK 0x24 Receiving Timer Blockage Time
RXDREAD 0x25 Receiving Timer Read Time
RXDCAP 0x26 Receiving Timer Captured Value
PHYCTRL 0x27 Physical Interface Control Register
PHYSTAT 0x28 Physical Interface Status Register
PHYMIRQ 0x29 Physical Interface Masked Interrupt Requests Flags (read only)
PHYSTAT2 0x2A Physical Interface Status Register 2
Legend:
59 / 86
Table 5.2.2.3-6: Register PHYCONF1 (0x12)

MSB LSB
Content RXDGATE RXDSAMP RXDMODE PROT_THR1[4:0]
Reset value 0 0 0 1
Access R/W R/W R/W R/W
Bit Description RXDGATE : Select gate for RXD read function with two samples
This bit is unused if PHYCONF1.RXDSAMP = 0b.
• 0b : RXD_RD = sample(n) AND sample(n+1),
• 1b : RXD_RD = sample(n) OR sample(n+1).
where n is the read time RXDREAD.
RXDSAMP : Select number of samples in RXD read function
• 0b : 1 sample,
• 1b : 2 samples, combination is selected by PHYCONF1.RXDGATE.
RXDMODE : Receiving mode (refer to chapter 5.2.2.3)
• 0b : falling edge is leading edge,
• 1b : rising edge is leading edge.
PROT_THR1[4:0] : Protocol receiver thresholds(refer to chapter 4.1.2 Physical Interface via
Bus Terminal LN24)

MSB LSB
Content [7:5] TXD_CUR[4:0]
Reset value 0 0
Access 0 R/W
TXD_CUR[4:0] : Transmitter current setting
• 00000b : IMOD = 0 mA (default)
• 00001b : IMOD = 7.6 mA
• ... (+ 7.6 mA steps)
• 11111b : IMOD = 240 mA

MSB LSB
Content - - - MODT[1] MODT[0] PROT_THR2[2:0]
Reset value 0 0 0 0 0 0
Access R R R R/W R/W R/W
Bit Description MODT[1] : MODT[1:0] : Modulation Type Setting
00b : Modulation Type 1, with data detection threhold referred to LN0 (default)
01b : Modulation Type 1 (identical to 00b)
10b :Modulation Type 2, with data detection threshold referred to LN24 (DC-level)
11b : Modulation Type 3 with separate synchronization detection comparator. Both thresholds
VTH1 (data) and VTH2 (sync) referred to LN24 (DC-level)
PROT_THR2[2:0] : Sync.detection threshold defined by multiples of m = PROT_THR2[2:0]
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Table 5.2.2.3-9: Register TXDDEL (0x20)

MSB LSB
Content TXDDEL[7:0]
Access R/W
Bit Description TXDDEL[7:0] : Transmitter delay (TTXD,DEL)
• 00000000b : 0 us (TXD forced directly)
• 00000001b : 20 us
• 00000010b : 30 us
• ... (+ 10 us steps)
• 11111111b : 2560 us
Please Note :
1. All timings are referenced to nominal clock frequency 100kHz.
2. The total delay from RXD edge to TXD edge for TXDDEL > 0 is: T TXD,DEL,TOTAL = TTXD,DEL +
TRXD,JIT (refer to Figure 5.2.2.3-9 and Figure 5.2.2.3-10).
3. Reset value = 200 us
Table 5.2.2.3-10: Register TXDDUR (0x21)

MSB LSB
Content TXDDUR[7:0]
Access R/W
Bit Description TXDDUR[7:0] : TXD pulse duration (TTXD,DUR)
• 00000000b : 0 us
• 00000001b : 10 us
• ... (+ 10 us steps)
• 11111111b : 2550 us
Please Note :
1. All timing are referenced to nominal clock frequency 100kHz.
2. For the case TXDDEL = 0x00 the duration is increased by 10 us synchronization time and
TRXD,JIT (refer to Figure 5.2.2.3-10)
3. Reset value = 400 us
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Table 5.2.2.3-11: Register RXDCMP1 (0x22)

MSB LSB
Content RXDCMP1[7:0]
Access R/W
Bit Description RXDCMP1[7:0] : Receiving timer compare value 1
Started from leading edge, sets flag PHYSTAT.IRQ_CMP1 if RXD_TIMER = RXDCMP1 before
trailing edge (refer to Figure 5.2.2.3-2).
• 00000000b : compare function disabled (default)
• 00000001b : 20 us
• 00000010b : 30 us
• ... (+ 10 us steps)
• 11111111b : 2560 us
Table 5.2.2.3-12: Register RXDCMP2 (0x23)

MSB LSB
Content RXDCMP2[7:0]
Access R/W
Bit Description RXDCMP2[7:0] : Receiving timer compare value 2
Started from trailing edge, sets flag PHYSTAT.IRQ_CMP2 if RXD_TIMER - RXDCAP = RXD-
CMP2 before next leading edge (refer to Figure 5.2.2.3-2).
• 00000000b : compare function disabled (default)
• 00000001b : 20 us
• 00000010b : 30 us
• ... (+ 10 us steps)
• 11111111b : 2560 us
Table 5.2.2.3-13: Register RXDBLK (0x24)

MSB LSB
Content RXDBLK[7:0]
Access R/W
Bit Description RXDBLK[7:0] : RXD_TIMER blockage time (refer to Figure 5.2.2.3-4)
• 00000000b : blockage function disabled (default)
• 00000001b : 20 us
• 00000010b : 30 us
• ... (+ 10 us steps)
• 11111111b : 2560 us
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Table 5.2.2.3-14: Register RXDREAD (0x25)

MSB LSB
Content RXDREAD[7:0]
Access R/W
Bit Description RXDREAD[7:0] : RXD_TIMER read time
If RXD_TIMER reaches RXDREAD recent RXD level is stored in PHYSTAT.RXD_RD and flag
PHYSTAT.IRQ_READ is set.
• 00000000b : read function disabled (default)
• 00000001b : 20 us
• 00000010b : 30 us
• ... (+ 10 us steps)
• 11111111b : 2560 us
Table 5.2.2.3-15: Register RXDCAP (0x26)

MSB LSB
Content RXDCAP[7:0]
Access R
Bit Description RXDCAP[7:0] : RXD timer captured value (read only)
refer to chapter 5.2.2.3).
RXDCAP is captured with the trailing edge, with this event flag PHYSTAT.IRQ_CAP is set.
Table 5.2.2.3-16: Register PHYCTRL (0x27)

MSB LSB
Content TXD TXD_LAT ENIRQ_TOF ENIRQ_READ ENIRQ_CMP2 ENIRQ_CMP1 ENIRQ_CAP ENIRQ_LE
Reset value 0 0 0 0 0 0 0 0
Access R/S R R/W R/W R/W R/W R/W R/W
Bit Description TXD : Bit to be transmitted
This bit is internally buffered and has to be written before the leading edge to be transmitted after
the leading edge. The bit for the next leading edge can be written during or even before actual
transmission (current forcing). With the leading edge PHYCTRL.TXD is first internally buffered
and then automatically cleared.
• 0b : no current
• 1b : force modulation current IMOD .
TXD_LAT : Latched TXD
This bit is TXD latched with leading edge.
ENIRQ_TOF : Enable RXD_TOF to generate an interrupt/wakeup.
ENIRQ_READ : Enable IRQ_READ to generate an interrupt/wakeup.
ENIRQ_CMP2 : Enable IRQ_CMP2 to generate an interrupt/wakeup.
ENIRQ_CMP1 : Enable IRQ_CMP1 to generate an interrupt/wakeup.
ENIRQ_CAP : Enable IRQ_CAP to generate an interrupt/wakeup.
ENIRQ_LE : Enable IRQ_LE to generate an interrupt/wakeup.
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Table 5.2.2.3-17: Register PHYSTAT (0x28)

MSB LSB
Content RXD RXD_RD IRQ_TOF IRQ_REA IRQ_CMP IRQ_CMP IRQ_CAP IRQ_LE
D 2 1
Reset value 0 0 0 0 0 0 0 0
Access R R R/C R/C R/C R/C R/C R/C
Bit Description RXD : Recent level of receiving comparator RXD
Synchronized to CLK4M.
• 0b : VLN24 < VTH
• 1b : VLN24 > VTH
RXD_RD : Stored level of RXD at reading time
Refer to Figure 5.2.2.3-3).
• 0b : At time RXDREAD after leading edge RXD was 0b,
• 1b : at time RXDREAD after leading edge RXD was 1b.
IRQ_TOF : Overflow flag of RXD_TIMER
Timer is stopped at 0xFF.
• bit is set by timer overflow,
• bit is cleared by writing a 0b to this location.
Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_TOF.
IRQ_READ : Flag for reading function
• bit is set if RXD_TIMER = RXDREAD,
Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_READ.
IRQ_CMP2 : Flag for compare function 2
• bit is set if (RXD_TIMER - RXDCAP) = RXDCMP2 before next leading edge,
Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_CMP2.
IRQ_CMP1 : Flag for compare function 1
• bit is set if RXD_TIMER = RXDCMP1 before trailing edge,
Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_CMP1.
IRQ_CAP : Flag for timer capture
• bit is set by trailing edge on RXD,
• bit is cleared by reading register RXDCAP or by writing a 0b to this location.
Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_CAP.
IRQ_LE : Flag for leading edge on RXD
• bit is set by leading edge (determined by RXDMODE),
Flag can be enabled to generate an interrupt/wakeup by PHYCTRL.ENIRQ_LE.
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Table 5.2.2.3-18: Register PHYMIRQ (0x29)

MSB LSB
Content [7:6] MIRQ_TO MIRQ_RE MIRQ_CM MIRQ_CM MIRQ_CA MIRQ_LE
F AD P2 P1 P
Reset value 00 0 0 0 0 0 0
Access 0 R R R R R R
MIRQ_TOF : Masked overflow flag of RXD_TIMER
= IRQ_TOF and ENIRQ_TOF
MIRQ_READ : Masked flag for reading function
= IRQ_READ and ENIRQ_READ
MIRQ_CMP2 : Masked flag for compare function 2
= IRQ_CMP2 and ENIRQ_CMP2
MIRQ_CMP1 : Masked flag for compare function 1
= IRQ_CMP1 and ENIRQ_CMP1
MIRQ_CAP : Masked flag for timer capture
= IRQ_CAP and ENIRQ_CAP
MIRQ_LE : Masked flag for leading edge on RXD
= IRQ_LE and ENIRQ_LE
Table 5.2.2.3-19: Register PHYSTAT2 (0x2A)

MSB LSB
Content - - - - - - RXD_DAT RXD
A
Reset value 0 0 0 0 0 0 0 0
Bit Description RXD_DATA : State of the Data only comparator
RXD : State of the RXD Comparator
5.2.2.4 Red Light Interface Control Unit

The Red Light Interface Control Unit (IR_RED_CTRL) provides two functions:
1) Transmit current pulses to the external red LED2 at pin RED.
2) In case of alarm detected, activate the external LED2 at pin RED permanently, if REDCONF.ALARMON is
set
3) Receive an interrupt condition via red LED2, to initiate an alarm request.
Red Light Transmitting

To start a pulse on red LED2 the CPU has to write a 1b to register REDCTRL.EN_RED. After t RED,DUR (refer to
Table 4.1.5-1) this bit is automatically cleared.
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Red Light Receiving

Via the red LED2 an interrupt request (alarm request) can be forced by illuminating LED2 with a high energy red
laser pointer. The red light control unit monitors falling edges on pin LED to detect a configurable period T ALARM
(refer to Table 4.2.2-1).
The detectable period can be configured with REDCONF.ALPER[1:0]. If 8 subsequent falling edges with a period of
TALARM are detected, the interrupt request RED_IRQ is set. The final interrupt or wake-up have to be enabled with
INTM.RED_IM or WUEN.RED_WE (refer to 5.2.2.1).
Note: To get write access to register REDCONF the configuration lock bit SYSCTRL.CONFLOCK have to be
cleared before.
66 / 86
Red Light Control Register Description
Table 5.2.2.4-1: Light Interface Registers

REDCONF 0x18 Light Interface Configuration Register,
REDCTRL 0x38 Light Interface Control Register
Legend:
Table 5.2.2.4-2: Register REDCONF (0x18)

MSB LSB
Content ALARMON ALPER[1] ALPER[0]
Reset value 0 0 0 0 0 0 1 0
Access 0 0 0 0 0 R/W R/W R/W
Bit Description ALARMON : ALARMON : Alarm indication by red LED
0 : no alarm indication by red LED
1 :alarm indication by red LED (permanently ON)
ALPER[1] : Alarm period (refer to Table 4.2.2-1)
• 00b : 750 µs (1.3 kHz)
• 01b : 500 µs (2 kHz)
• 10b : 330 µs (3 kHz, default)
• 11b : 250 µs (4 kHz)
Note: Nominal timing is referenced to clock frequency 100kHz.
Table 5.2.2.4-3: Register REDCTRL (0x38)

MSB LSB
Content RED_IRQ RED EN_RED
Reset value 0 0 0 0 0 0 0 0
Access 0 0 0 0 0 R/C R R/S
Bit Description RED_IRQ : Red light interrupt request
• bit is set if pulsed light with configured period (ALPER) is detected, i.e. 8 subsequent falling
edges,
RED : Red light status (read only)
• 0b: receiving no light,
• 1b: receiving light.
EN_RED : Enable red light emitting
• bit is set by CPU to start light pulse,
• bit is cleared automatically when pulse duration (refer to t RED,DUR) has elapsed, except for the
case of an alarm with bit REDCON.F.ALARMON set.
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5.2.2.5 General Purpose IOs

The Smoke Detector provides a free programmable digital interface via pins IO[3:0].
The GPIO unit is activated by setting control bit SYSCTRL.EN_GPIO = 1b.
The register GPIODIR.DIR[3:0] determines the signal direction. A 0b configures the corresponding pad to an input
and a 1b to an output pin.
On register GPIOSTAT.GPIO[3:0] the recent status of the pins IO[3:0] can be read (input) or forced (output)
depending on its direction GPIODIR.DIR[3:0].
A rising edge or a falling edge on an input pin sets an interrupt request flag on register GPIOSTAT.IRQ_IO[3:0].
GPIOCTRL.IOEDGE[3:0] selects if the flag is set by an rising edge (1b) or an falling edge (0b).
With the local mask GPIOCTRL.ENIRQ_IO[3:0] the flags GPIOSTAT.IRQ_IO[3:0] are masked to determine the
interrupt request GPIO_IRQ, which can be read on IRQSTAT.GPIO_IRQ.
The final interrupt or wake-up have to be enabled with INTM.GPIO_IM or WUEN.GPIO_WE (refer to 5.2.2.1).
IO3 IO2 IO1 IO0
GPIO Unit
edge detection
1 0 IOEDGE[0]
1 0 IOEDGE[1]
1 0 IOEDGE[2]
1 0 IOEDGE[3]
'0'
0 1 3
Interrupt and Wake-up Control Unit
GPIODIR
'0'
0 1 2
'0'
addr 0x0C
addr 0x02
INTM
0 1 1
'0'
0 1 0 7 6 5 4 3 2 1 0
set set set set addr 0x0E
7 6
GPIOSTAT
5 4 3 2 1 0 7
IRQ_IO[0] 6
ENIRQ_IO[0] AND
IRQSTAT
5 GPIO_IM
IRQ_IO[1] GPIO_IRQ GPIO_IRQ AND GPIO_INT
4
ENIRQ_IO[1] AND
3
IRQ_IO[2] OR
2
ENIRQ_IO[2] AND
OR WAKEUP
addr 0x01
1
IRQ_IO[3] GPIO_WE AND
ENIRQ_IO[3] AND 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
GPIOCTRL addr 0x0D addr 0x03

WUEN
Figure 5.2.2.5-1: Block Diagram of GPIO Unit
68 / 86
GPIO Register Description

Table 5.2.2.5-1: General Purpose IO Registers
GPIODIR 0x0C General Purpose IO Direction Register
GPIOCTRL 0x0D General Purpose IO Control Register
GPIOSTAT 0x0E General Purpose IO Status Register
GPIOMIRQ 0x0F Masked Interrupt Request Flags (read only)
Legend:
Table 5.2.2.5-2: Register GPIODIR (0x0C)

MSB LSB
Content [7:4] DIR3 DIR2 DIR1 DIR0
DIR3 : Direction of pin IO3
• 0b : IO3 is input
• 1b : IO3 is output
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Table 5.2.2.5-3: Register GPIOCTRL (0x0D)

MSB LSB
Content ENIRQ_IO3 ENIRQ_IO2 ENIRQ_IO1 ENIRQ_IO0 IOEDGE3 IOEDGE2 IOEDGE1 IOEDGE0
Reset value 0 0 0 0 0 0 0 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Bit Description ENIRQ_IO3 : Local interrupt enable for pin IO3
• 0b : disabled,
• 1b : enabled.
ENIRQ_IO2 : Local interrupt enable for pin IO2
• 0b : disabled,
• 1b : enabled.
• 0b : disabled,
• 1b : enabled.
• 0b : disabled,
• 1b : enabled.
IOEDGE3 : Select edge for interrupt flag on pin IO3
• 0b : falling edge on IO3 sets the interrupt request flag GPIOSTAT.IRQ_IO3 if GPIODIR.DIR3
= 0b.
• 1b : rising edge on IO3 sets the interrupt request flag GPIOSTAT.IRQ_IO3 if GPIODIR.DIR3 =
0b.
= 0b.
0b.
= 0b.
0b.
= 0b.
0b.
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Table 5.2.2.5-4: Register GPIOSTAT (0x0E)

MSB LSB
Content IRQ_IO3 IRQ_IO2 IRQ_IO1 IRQ_IO0 GPIO3 GPIO2 GPIO1 GPIO0
Reset value 0 0 0 0 0 0 0 0
Access R/C R/C R/C R/C R/W R/W R/W R/W
Bit Description IRQ_IO3 : Interrupt request flag for IO3
• bit is set by an edge on IO3, if GPIODIR.DIR3 = 0b (input), GPIOCTRL.IOEDGE3 selects if
this bit is set by a rising edge (1b) or a falling edge (ob),
• bit is cleared by writing a 0b to GPIO3.
IRQ_IO2 : Interrupt request flag for IO2
GPIO3 : Status bit on pin IO3
Depending on GPIODIR.DIR3, CPU can read recent input or force the output.
Table 5.2.2.5-5: Register GPIOMIRQ (0x0F)

MSB LSB
Content MIRQ_IO3 MIRQ_IO2 MIRQ_IO1 MIRQ_IO0 [3:0]
Access R R R R R
Bit Description MIRQ_IO3 : Masked interrupt request flag for IO3
= IRQ_IO3 and ENIRQ_IO3
MIRQ_IO2 : Masked interrupt request flag for IO2
GPIOMIRQ[3:0] : reserved
71 / 86
5.2.2.6 Watchdog
To provide reliability of software the watchdog unit covers two functions:
1. Configurable time-out for CPU active time
2. Configurable slow watchdog trigger
After power-up both watchdog functions are immediately enabled with default setting (T ACT = 8 ms , TWD = 2 s , i.e.
WDCONF = 0x0D).
The first write access to register WDCONF should write watchdog configuration to lock configuration until next reset
(all reset source, refer to 5.2.2.1). For this the CPU should write value unequal to 0x5 to the high nibble of
WDCONF.
If first written value is watchdog trigger 0x55, then watchdog configuration is locked with default values.
Timeout for CPU Active Time

With WDCONF.ACTTIME[1:0] the maximum allowed active time TACT can be selected between 1 ms and 8 ms.
If TACT has elapsed the watchdog generates a system reset. This prevents to run out of power by a too long active
time of CPU. This function runs with the slow clock CLK100K. Its timer is reseted with a sleep command
SYSCTRL.CPU_OFF = 1b and enabled with a CPU wake-up.
Slow Watchdog
The slow timer observes if the CPU is hooked unintentionally in sleep mode.
To trigger the watchdog a 0x55 has to be written to address 0x08 before the watchdog time T WD has elapsed. With
a valid trigger the watchdog timer is restarted. A missing trigger after watchdog time leads to a system reset. This
function also runs with the slow clock CLK100K.
Watchdog Register Description

Table 5.2.2.6-1: Watchdog Registers
WDCONF 0x08 Watchdog Configuration Register,
automatically locked after first write access.
Legend:
72 / 86
Table 5.2.2.6-2: Register WDCONF (0x08)

MSB LSB
Content WDCONF[7:4] ACTTIME[1:0] WDTIME[1:0]
Reset value 1 0
Access W R/W R/W
Bit Description WDCONF[7:4] : Note:
The first write access to this register serves as first watchdog trigger and locks the configuration
(ACTTIME[1:0] and WDTIME[1:0]) for any further write access.
First write access:
• WDCONF[7:4] = 0x5 : default watchdog setting is locked,
• WDCONF[7:4] 0x5 : WDCONF[3:0] is configured and locked.
Any next trigger is generated by writing 0x55 to this register address
ACTTIME[1:0] : CPU active time
• 00b : TACT = 0.96 ms
• 01b : TACT = 2.24 ms
• 10b : TACT = 4.16 ms
• 11b : TACT = 8.00 ms
WDTIME[1:0] : Watchdog trigger time
• 00b : TWD = 1.024 s
• 01b : TWD = 2.048 s
• 10b : TWD = 3.072 s
• 11b : TWD = 4.096 s
5.2.2.7 Universal Timer

The timer is implemented as a 16 bit up counter. The timer uses low frequency clock.
To ensure the readout of consistent timer values the timer low byte is latched if the timer high byte is read. The
capture register can be used to generated defined timer capture interrupts.
The special multiplexer can be used to capture one of the input channels such as the four gpio input, physical RXD
or red RXD.
Universal Timer Register Description

Table 5.2.2.7-1: Universal Timer Registers
TSTAT 0x40 Timer Status Register
TCTRL 0x41 Timer Control Register
TIMH 0x42 Recent Timer Value (high byte)
TIML 0x43 Recent Timer Value (low byte)
TCMPH 0x44 Timer Compare Register (high byte)
TCMPL 0x45 Timer Compare Value (low byte)
TCAPH 0x46 Timer Captured Value (high byte)
TCAPL 0x47 Timer Captured Value (low byte)
Legend: Internal access : from view of HW block . External access : from view of CPU (programmer).
73 / 86
Table 5.2.2.7-2: Register TSTAT (0x40)

MSB LSB
Content ICF OCF TOF [4:2] CMPR RST
Access R/C R/C R/C 0 R/W W
Bit Description ICF : Flag for input capture
• flag is set by timer hardware when timer value is captured,
• flag is cleared by reading low byte of captured value (TCAPL) or writing a 0b to this location.
OCF : Flag for output compare
• flag is set by timer hardware when values of TIMH/TIML and of TCMPH/TCMPL register
matches. No further comparison is made until the OCF bit is cleared,
• flag is cleared by reading of the TCMPL register or writing a 0b to this location.
TOF : Flag for timer overflow
• flag is set by timer hardware in case of overflow,
[4:2] : reserved
CMPR : Enable compare timer reset
• 0b : disabled,
• 1b : enabled, timer is reset if it reaches compare value TCMPH/TCMPL.
RST : Reset command for timer
• write 1b to reset timer value,
• bit is automatically cleared.
74 / 86
Table 5.2.2.7-3: Register TCTRL (0x41)

MSB LSB
Content ICIE OCIE TOFIE INTD CSEL[2:0] EDGE
Access R/W R/W R/W R/W R/W R/W
Bit Description ICIE : Interrupt enable for input capture
• 0b : disabled,
• 1b : enabled.
OCIE : Interrupt enable for output compare
• 0b : disabled,
• 1b : enabled.
TOFIE : Interrupt enable for timer overflow
• 0b : disabled,
• 1b : enabled.
INTD : Interrupt disable for all timer interrupts
• 0b : not disabled,
• 1b : all interrupts are disabled.
CSEL[2:0] : Select capture signal
• 000b : capture function is disabled (default)
• 001b : IO[0]
• 010b : IO[1]
• 011b : IO[2]
• 100b : IO[3]
• 101b : PHY RXD
• 110b : RED RXD
• 111b : capture function is disabled
EDGE : Select capture edge
• 0b : falling edge,
• 1b : rising edge.
Table 5.2.2.7-4: Register TIMH (0x42)

MSB LSB
Content TIM[15:8]
Access R
Bit Description TIM[15:8] : High byte of timer register (read only)
75 / 86
Table 5.2.2.7-5: Register TIML (0x43)

MSB LSB
Content TIM[7:0]
Access R
Bit Description TIM[7:0] : Low byte of timer register (read only)
Table 5.2.2.7-6: Register TCMPH (0x44)

MSB LSB
Content TCMP[15:8]
Access R/W
Bit Description TCMP[15:8] : High byte of timer compare register
Table 5.2.2.7-7: Register TCMPL (0x45)

MSB LSB
Content TCMP[7:0]
Access R/W
Bit Description TCMP[7:0] : Low byte of timer compare register
Table 5.2.2.7-8: Register TCAPH (0x46)

MSB LSB
Content TCAP[15:8]
Access R
Bit Description TCAP[15:8] : Low byte of timer capture register (read only)
Table 5.2.2.7-9: Register TCAPL (0x47)

MSB LSB
Content TCAP[7:0]
Access R
Bit Description TCAP[7:0] : Low byte of timer capture register (read only)
76 / 86
5.2.2.8 Special Function Registers (SFR)

The following registers are implemented in the special function register block, but described in other chapters. All
SFR registers are locked (not writable), if SYSCTRL.CONFLOCK = 1b.
Table 5.2.2.8-1: Special Function Registers

Register Description Address
OSCTRIM Oscillator trimming register 0x10
POWCONF Power configuration regfister 0x11
PHYCONF1 Physical interface configuration register 1 0x12
LEDCONF LED configuration register 0x15
AMPCONF Amplifier configuration register 0x16
MECONF Measurement configuration register 0x17
REDCONF Red light interface configuration register 0x18
77 / 86
5.2.3 Power Management

The IC is basically supplied from the tank capacitor C1 connected to pin D5. The constant current drawn from the
loop line (pin LN24) is set by SUP_MODE (Table 5.2.3-1). While the IC is in sleep mode the charge current out of
pin D5 into C1 is limited by current drawn from the loop line except current fraction that is consumed by always act-
ive IC blocks. Once the IC is woken up for taking a measurement the current at pin D5 reverses and discharges
C1, while the current drawn from the loop line remains constant. Overall the average current into D5 must be less
than the current limit set by SUP_MODE in order to avoid the charge in C1 fading away. The following table shows
the IC's current consumption at pin D5 for all active operating modes. From these you can calculate the average
current for a measurement cycle considering your individual configurations.
Table 5.2.3-1: Current Consumption

Mode Symbol Register State Current into pin Duration Time in
D5 measuring cycle
Sleep mode - 23uA 0.8s .. 4s
program depended
Start-up after power tCPU_POR SYSCTRL.EEWU_EN=1 1.7mA 2ms (*)
on only after power on
LN24 RXD pro- tCPU_RXD SYSCTRL.EEWU_EN=0 1.0mA 5us/bit (*)
cessing
RED RXD pro- tCPU_RED SYSCTRL.EEWU_EN=0 1.0mA 5us/bit (*)
cessing
Measure: amplifier tINIT MECONF.MEMODE=0 0.4mA 7.4ms
initialisation refer to MECTRL.SSME=1
or
MECONF.MEMODE=1
Temperature meas- tTEMP MECTRL.TME_EN=1 0.54mA + external 20us
urement refer to temperature half
bridge current
Measure: CPU pro- tACTIVE SYSCTRL.EEWU_EN=0 1.5mA 0.3ms .. 2ms
cessing refer to program depended
LED flash tLED MECTRL.LED_EN=1 4.5mA + 1.5mA 0.1ms
refer to SYSCTRL.EEWU_EN=0 CPU + (0..500mA)
LED current
RED flash tRED_DUR REDCTRL.EN_RED=1 5mA 2ms
78 / 86
6 Register Table
Table 6-1: Register Table
IRQSTAT 0x01 Interrupt Request Status Register
INTM 0x02 Interrupt Unmask Register, locked by SYSCTRL.CONFLOCK
WUEN 0x03 Wake-up Enable Register, locked by SYSCTRL.CONFLOCK
SYSCTRL 0x04 System Control Register
IRQ_MSKD 0x05 Masked Interrupt Status
SYSSTAT 0x06 System Status Register
WDCONF 0x08 Watchdog Configuration Register,
automatically locked after first write access.
GPIODIR 0x0C General Purpose IO Direction Register
GPIOCTRL 0x0D General Purpose IO Control Register
GPIOSTAT 0x0E General Purpose IO Status Register
GPIOMIRQ 0x0F Masked Interrupt Request Flags (read only)
OSCTRIM 0x10 Oscillators Trimming Register,
POWCONF 0x11 Power Configuration Register,
LEDCONF 0x15 LED1 configuration register,
AMPCONF 0x16 Current-to-voltage converter/amplifier configuration register,
MECONF 0x17 Measurement configuration register,
REDCONF 0x18 Light Interface Configuration Register,
TXDDEL 0x20 Transmitter Configuration : Transmitting delay
TXDDUR 0x21 Transmitter Configuration : Transmitting duration
RXDBLK 0x24 Receiving Timer Blockage Time
79 / 86

RXDREAD 0x25 Receiving Timer Read Time
RXDCAP 0x26 Receiving Timer Captured Value
PHYCTRL 0x27 Physical Interface Control Register
PHYSTAT 0x28 Physical Interface Status Register
PHYMIRQ 0x29 Physical Interface Masked Interrupt Requests Flags (read only)
PHYSTAT2 0x2A Physical Interface Status Register 2
ADCVAL10_H 0x30 High byte 10 bit ADC value
ADCVAL10_L 0x31 Low byte 10 bit ADC value
ADCVAL8 0x32 8 bit ADC value
MECTRL 0x33 Measurement Control Register
MECTRL2 0x34 Measurement Control Register 2
THR1 0x35 LN24 Comparator Threshold Voltage Level 1. In Modulation Type 3 used as
SYNC Level
THR2 0x36 LN24 Comparator Threshold Voltage Level 2. In Modulation Type 3 used as Data
Level. Not used in other modulation types1)
REDCTRL 0x38 Light Interface Control Register
TSTAT 0x40 Timer Status Register
TCTRL 0x41 Timer Control Register
TIMH 0x42 Recent Timer Value (high byte)
TIML 0x43 Recent Timer Value (low byte)
TCMPH 0x44 Timer Compare Register (high byte)
TCMPL 0x45 Timer Compare Value (low byte)
TCAPH 0x46 Timer Captured Value (high byte)
TCAPL 0x47 Timer Captured Value (low byte)
EECFG 0x50 EEPROM Configuration Register
EEPLCK 0x51 EEPROM Programming Lock Register
EECTRL 0x52 EEPROM Control Register
EESTAT 0x53 EEPROM Status Register
EEMIRQ 0x54 EEPROM Masked Interrupt Requests Flags (read only)
1)
Modulation Type 3 only
80 / 86
7 Package Information
The product is available in a Pb free, RoHS compliant, 14 lead Small Outline SO14 plastic package according to
JEDEC MS-012-F, variant AB. The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to
JEDEC J-STD-020 with a soldering peak temperature of (260 + 5)°C.
Note: Thermal resistance junction to ambient RTH,JA is 97 °C/W, based on standard JESD-51-5.
Figure 7-1: Package Drawing
Figure 7-2: Package Dimensions

Note: Dimensions in mm are true; dimensions in inch contain rounding errors.
81 / 86
8 Marking
8.1 Top Side
• Elmos (Logo)
• 52030A
• YWW*#
• XXXXU
Table 8.1-1: Marking of the Devices

Signature Explanation
52030 ELMOS project number
A ELMOS project revision code
Y Year of assembly (1 digit, e.g. 2014)
WW Week of assembly (2 digits)
* Mask revision code
# ELMOS internal code
XXXX Production lot number (1 to 4 digits)
U Assembler Code
82 / 86
9 General
9.1 Disclaimer
9.1.1 WARNING - Life Support Applications Policy
ELMOS Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability
to physical stress. It is the responsibility of the buyer, when utilising ELMOS Semiconductor AG products, to
observe standards of safety, and to avoid situations in which malfunction or failure of an ELMOS Semiconductor
AG Product could cause loss of human life, body injury or damage to property. In development your designs,
please ensure that ELMOS Semiconductor AG products are used within specified operating ranges as set forth in
the most recent product specifications.
9.1.2 General Disclaimer

Information furnished by ELMOS Semiconductor AG is believed to be accurate and reliable. However, no respons-
ibility is assumed by ELMOS Semiconductor AG for its use, nor for any infringements of patents or other rights of
third parties, which may result from its use. No license is granted by implication or otherwise under any patent or
patent rights of ELMOS Semiconductor AG.
ELMOS Semiconductor AG reserves the right to make changes to this document or the products contained therein
without prior notice, to improve performance, reliability, or manufacturability.
9.1.3 Application Disclaimer

Circuit diagrams may contain components not manufactured by ELMOS Semiconductor AG, which are included as
means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is
not necessarily given. The information in the application examples has been carefully checked and is believed to be
entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not
convey to the purchaser of the semiconductor devices described any license under the patent rights of ELMOS
Semiconductor AG or others.
83 / 86
9.2 Contact Information

Headquarters
Elmos Semiconductor AG
Heinrich-Hertz-Str. 1, D-44227 Dortmund (Germany)
: +49 2317549100 : sales-germany@elmos.com Web: www.elmos.com
Sales and Application Support Office North America

Elmos NA. Inc.
32255 Northwestern Highway, Suite 220 Farmington Hills, MI 48334 (USA)
: +1 2488653200 : sales-usa@elmos.com
Sales and Application Support Office Korea and Japan

B-1007, U-Space 2, #670 Daewangpangyo-ro,
Sampyoung-dong, Bunddang-gu, Sungnam-si
Kyounggi-do 463-400 Korea
: +82 317141131 : sales-korea@elmos.com
Sales and Application Support Office China

Elmos Semiconductor Technology (Shanghai) Co., Ltd.
Unit London, 1BF GC Tower, No. 1088 Yuan Shen Road,
Pudong New District, Shanghai, PR China, 200122
: +86 2151785178 : sales-china@elmos.com
Sales and Application Support Office Singapore

Elmos Semiconductor Singapore Pte Ltd.
3A International Business Park
# 09-13 ICON@IBP, 609935 Singapore
: +65 6908 1261 : sales-singapore@elmos.com
© Elmos Semiconductor AG, 2014. Reproduction, in part or whole, without the prior written consent of
Elmos Semiconductor AG, is prohibited.
84 / 86
10 Index
Table of Content
Features...................................................................................................................................................................... 1
Application.................................................................................................................................................................. 1
Brief Functional Description........................................................................................................................................ 1
Typical Operating Circuit............................................................................................................................................. 1
1 Absolute Maximum Ratings..................................................................................................................................... 4
2 ESD Protection........................................................................................................................................................ 5
3 Recommended Operating Conditions...................................................................................................................... 5
4 Electrical Characteristics.......................................................................................................................................... 6
4.1 Analog Part...................................................................................................................................................... 6
4.1.1 Supply and References............................................................................................................................ 6
4.1.2 Physical Interface via Bus Terminal LN24............................................................................................... 7
4.1.3 LED Driver for Smoke Chamber.............................................................................................................. 8
4.1.4 Smoke Detection and Temperature Measurement Channel....................................................................8
4.1.5 RED Light Interface.................................................................................................................................. 9
4.1.6 Oscillators................................................................................................................................................ 9
4.2 Digital Characteristics.................................................................................................................................... 10
4.2.1 Central Processing Unit and Memory.................................................................................................... 10
4.2.2 Periphery............................................................................................................................................... 11
5 Functional Description .......................................................................................................................................... 12
5.1 General Functional Description...................................................................................................................... 12
5.1.1 Start-up behaviour................................................................................................................................. 13
5.1.2 Smoke Detection.................................................................................................................................... 13
5.1.3 Temperature Measurement................................................................................................................... 14
5.1.4 Bus Interface via Supply Terminal LN24................................................................................................ 14
5.1.5 Red Light Interface................................................................................................................................. 14
5.2 Detailed Description and Digital Control........................................................................................................ 15
5.2.1 Central Processing Unit (CPU).............................................................................................................. 15
5.2.1.1 CPU EL3.5 Core............................................................................................................................ 15
5.2.1.2 Memory Map - Base Address Table............................................................................................... 24
5.2.1.3 Interrupt vector............................................................................................................................... 25
5.2.1.4 RAM............................................................................................................................................... 25
5.2.1.5 E²PROM........................................................................................................................................ 25
5.2.1.6 FLASH........................................................................................................................................... 32
5.2.2 Periphery............................................................................................................................................... 32
5.2.2.1 Main Control Unit........................................................................................................................... 32
5.2.2.2 Measurement Control Unit............................................................................................................. 38
5.2.2.3 Physical Interface Control Unit....................................................................................................... 51
5.2.2.4 Red Light Interface Control Unit..................................................................................................... 65
5.2.2.5 General Purpose IOs..................................................................................................................... 68
5.2.2.6 Watchdog....................................................................................................................................... 72
5.2.2.7 Universal Timer.............................................................................................................................. 73
5.2.2.8 Special Function Registers (SFR).................................................................................................. 77
5.2.3 Power Management............................................................................................................................... 78
6 Register Table........................................................................................................................................................ 79
7 Package Information.............................................................................................................................................. 81
8 Marking.................................................................................................................................................................. 82
8.1 Top Side........................................................................................................................................................ 82
9 General.................................................................................................................................................................. 83
9.1 Disclaimer...................................................................................................................................................... 83
9.1.1 WARNING - Life Support Applications Policy........................................................................................ 83
9.1.2 General Disclaimer................................................................................................................................ 83
85 / 86
9.1.3 Application Disclaimer............................................................................................................................ 83

9.2 Contact Information........................................................................................................................................ 84
10 Index.................................................................................................................................................................... 85
86 / 86

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Smoke Detector Controller E520.

Features Brief Functional Description

Typical Operating Circuit

Block Diagram and Application Example

RED RED 128B RAM

Figure 1: Block Diagram

Table 1: Application Circuit Parameters (proposal)

Figure 2: Package top view (not to scale)

1 Absolute Maximum Ratings

3 Recommended Operating Conditions

7 LN24 monitor threshold voltage, rising VTH,LN24LOW,RISE 7.4 V

8 LN24 monitor detection delay, falling edge, tLN24LOW 3.4 ms

4.1.2 Physical Interface via Bus Terminal LN24

3 Demodulator threshold 1 MODT[1:0]= 1xb ΔVTH1(MOD2/3) (n-18)*

6 Modulation current programming step *)

4.1.3 LED Driver for Smoke Chamber

4.1.4 Smoke Detection and Temperature Measurement Channel

3 Detector conversion factor programming AMP_GAIN = FCONV,STEP +0.8 +2 +3.2 dB

No. Description Condition Symbol Min Typ Max Unit

4.1.5 RED Light Interface

4.2 Digital Characteristics

RED RED 128B RAM

Figure 5.1-1: Detailed Block Diagram E520.30

5.1.1 Start-up behaviour

5.1.2 Smoke Detection

1. MEMODE=0b : Controlled by the µC based on software and protocol.

2. MEMODE=1b : Automatically controlled by the configurable measurement timer.

5.1.3 Temperature Measurement

5.1.4 Bus Interface via Supply Terminal LN24

5.1.5 Red Light Interface

5.2 Detailed Description and Digital Control

5.2.1 Central Processing Unit (CPU)

CONDITION CODE REGISTER 1 1 1 H I N Z C CCR

Figure 5.2.1.1-1: Programming model

These internal actions occur as result of any CPU reset:

Table 5.2.1.1-1: CPU Registers

Table 5.2.1.1-2: Condition Code Register

Figure 5.2.1.1-2: Instruction Set Summary (Sheet 1 of 6)

Figure 5.2.1.1-3: Instruction Set Summary (Sheet 2 of 6)

Figure 5.2.1.1-4: Instruction Set Summary (Sheet 3 of 6)

Figure 5.2.1.1-5: Instruction Set Summary (Sheet 4 of 6)

Figure 5.2.1.1-6: Instruction Set Summary (Sheet 5 of 6)

Figure 5.2.1.1-7: Instruction Set Summary (Sheet 6 of 6)

Figure 5.2.1.1-8: Instruction Set Opcode Map

5.2.1.2 Memory Map - Base Address Table

0x0008 0x0001 Watchdog (WATCHDOG) 5.2.2.6

0x0001 0x0006 Main Control Unit (MAIN_CTRL) 5.2.2.1

5.2.1.3 Interrupt vector

In the USER part 28 bytes are free to hold for example:

Erase and Program Procedure

E²PROM Control and Status Registers

Table 5.2.1.5-5: Register EECFG (0x50)

Table 5.2.1.5-6: Register EEPLCK (0x51)

LCKST[2:0] : Lock State (read only)

Table 5.2.1.5-7: Register EECTRL (0x52)

Reset value 0000 0 0 0 0

Table 5.2.1.5-8: Register EESTAT (0x53)

Table 5.2.1.5-9: Register EEMIRQ (0x54)

Reset value 0000 0 0 0 0

1. The power-on reset (POR) during system power-up or insufficient supply.

Interrupt and Wakeup Control Unit

Main Control Register Description

Table 5.2.2.1-2: Register IRQSTAT (0x01)

Table 5.2.2.1-3: Register INTM (0x02)