Chapter 8

Sample and Hold (S/H)
 “Sample and Hold” (often referred to as “Track and hold”(T/H))

 Identical in both function & circuit implementation in most cases
 Only distinction: How they are used in the system
 S/H: Samples the input for a short time and stays in the hold
mode for the remainder of the cycle
 T/H: Spends most of the time tracking the input and is switched
into the hold mode for only brief interval
 In data acquisition systems operating at sampling rates greater than
1MHz  The terms S/H and T/H lose their distinction
 In general: These two terms are used interchangeably
 Necessary components in many data-acquisition systems such as A/D
converters
 In many cases, the use of a S/H can greatly minimize errors due to
slightly different delay times in the internal operation of the converter
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 8-1 郭泰豪, Analog IC Design, 2018
Performance Parameters in characterization of S/Hs
 Sampling pedestal or a hold step
 Error that occurs each time a sample and hold goes from sample
mode to hold mode
 During this change in operation, there is always a small error in the
voltage being held that makes it different from the input voltage at
the time of sampling.
 Obviously, this error should be as small as possible. Perhaps more
importantly, this error should be signal independent; otherwise it can
introduce nonlinear distortion.
 How isolated the sampled signal is from the input signal during hold
mode
 Ideally, the output voltage will no longer be affected by changes in
the input voltage
 In reality, there is always some signal feedthrough, usually through
parasitic capacitive coupling from the input to the output. In well-
designed sample and holds, this signal feedthrough can be greatly
minimized.
Performance Parameters in characterization of
S/Hs(Cont.)
 The speed at which a sample and hold can track an input signal, when
in sample mode.
 In this mode, a sample and hold will have both small-signal and
large-signal limitations due to its -3dB bandwidth and finite slew rate,
respectively.
 Both the -3dB bandwidth and slew rate should be maximized for
high-speed operation.
 Droop rate in hold mode

 Somewhat less important in high-speed designs
 This error is a slow change in output voltage, when in hold mode,
caused by effects such as leakage currents due to the finite base
currents of bipolar transistors and reverse-biased junctions.
 In most CMOS designs using advanced processes, this droop rate is
so small and can often be ignored.
Performance Parameters in characterization of
S/Hs(Cont.)
 Aperture jitter or aperture uncertainty
 Result of the effective sampling time changing from one sampling
instance to the next
 More pronounced for high-speed signals. Specifically, when high-
speed signals are being sampled, the input signal changes rapidly,
resulting in small amounts of aperture uncertainty causing the held
voltage to be significantly different from the ideal held voltage.
 Other parameters such as

 Dynamic range
 Linearity
 Gain
 Offset error
 Etc.
Testing S/Hs
 Beat test, a popular method for testing S/Hs
 Test setup
Output signal with frequency ∆f Spectrum
analyzer
Vin  Ain sin[2(fsmpl  f )t ] S/H
Clk
A/D and
Beat frequency f smpl computer
Sampling signal with sampling frequency fsmpl
Where the S/H is operating at it’s maximum sampling

frequency
 Only a relatively low-frequency output signal must be monitored.
Testing S/Hs (Cont.)
 Example waveforms for the above test setup
Output signal of sample and hold
Input signal
Sampling signal
 The ideal sinusoidal wave at the beat frequency is subtracted from the
measured signal. The error signal is then analyzed for RMS content and
spectral components using FFT (Fast Fourier Transform).
MOS S/H Basics
 clk
 Two error sources due to switch
a. channel charge injection
Vin
b. clock feedthrough
where b is usually smaller than a. VCM
 Time jitter
 Caused by clock waveforms having finite slopes
V
t s1actual 
th Vin clk
t s1ideal t s 2ideal
t s 2actual
Vth
Sampling jitter
 When Vin is above 0V, the true sampling time is earlier than the
ideal sampling time.
 When Vin is less than 0V, the true sampling time is late.
Methods for Minimizing Signal-Dependent Switch Error
 Replace n-channel switches by CMOS transmission gates.
 Transistor turn-off times are signal dependent and this signal
dependence causes the n-channel transistor to turn off at different
times than the p-channel transistor.
 clk
 PMOS and NMOS have different amount
of channel charges, e.g., when Vin is closer Vin
to VDD , the charge from the p-channel clk
VCM
transistor is greater than that from the
n-channel transistor
 clk clk
 Add a dummy switch (better with fast clock)
 When clock waveforms are fast, this Q1 Q2
Vin
technique usually can minimize the W, L W 2, L
hold pedestal to less than about one-fifth VCM
the value it would have without it.
 The clock of Q2 changes slightly after that of Q1. This guarantees
that the cancelling charge of Q2 can’t escape through Q1.
Methods for Minimizing Signal-Dependent Switch Error(Cont.)
 Include an OPAMP in  clk
a feedback loop of a S/H Q1
Vin 1 Vout
 High input impedance
C hld
 The speed of operation can
VCM
be seriously degraded due to the necessity
of guaranteeing that the loop is stable when it is closed.
 When in hold mode, the OPAMP is open loop, resulting in its output
almost certainly saturating at one of the power supply voltages.
 When the S/H goes back into track mode, it will take some time for
the OPAMP output to slew back to its correct  clk
closed-loop value. This Q3
slewing time can be
clk
greatly minimized by  clk
Q2
adding two additional
Q1
transistors 1 Vout
Vin
C hld
VCM
 A feedback S/H with a Miller capacitor as a holding capacitor.
 The voltages on both sides of switch Q1 are very nearly signal
independent.
 Charge injection results in just a dc offset and will be signal
independent.
 The use of Q2 greatly speeds up the time it takes the S/H to return to
track mode. The use of Q2 also greatly minimizes signal feedthrough
when the S/H is in hold mode.
 There are two OPAMPs in the loop.  Speed is degraded.
 clk C hld
Opamp1
Vin Q1 Vout
clk Q2 Opamp2
VCM VCM
 A feedback S/H with clock-feedthrough cancellation circuitry
 To match charge injection by introducing Chld’ (=Chld)
 The major limitation is a second-order effect caused by a mismatch

in impedance levels at the left of Q1 and the bottom of Q2.
 clk C hld
Opamp1
Q1
Vin Vout
Opamp2
clk Q3  clk Q2 C'hld  C hld
VCM VCM VCM
CMOS Multiplier Circuit
 CMOS differential pair can be employed in a multiplier circuit [1][2]
Assume: Ma, Mb are identical in saturation
region, the drain current is given by IMa IMb
I D  k (VGS  VT H ) 2
Ma Mb
we have VCM + 0.5vi
I Ma  I Mb  ISS vi Vs
IMa  k(VX  0.5vi )2 VCM - 0.5vi
IMb  k(VX  0.5vi )2 ISS
where VX  VCM  VS  VTH
ISS kv i 2ISS I kv 2ISS

 IMa    vi2 , IMb  SS  i  vi2 - - - - - - (1)
2 2 k 2 2 k
2ISS
 I  I Ma  I Mb  kv i  vi2 - - - - - - - - - - - - - - - - - - - - - - (2)
k
CMOS Multiplier Circuit (Cont.)
 This MOS version of Gilbert’s six-transistor cell is the basic multiplier.
 vx and vy can be made positive or negative: Four-quadrant multiplier
I7 I8
VCM1 - 0.5vx
vx
M3 M4 M5 M6
VCM1 + 0.5vx
VCM2 + 0.5vy M1 M2
vy
VCM2 - 0.5vy
ISS
CMOS Multiplier Circuit (Cont.)
 Define: input signal vx and vy , the output current Iout = I7 - I8
 I out  I 7  I8  (I M 3  I M 5 )  (I M 4  I M 6 )  (I M 3  I M 4 )  (I M 6  I M 5 )
 Refer to 8-12, equation (1)
ISS kv y 2ISS 2 ISS kv y 2ISS
 IM1    v y , IM2    v2y
2 2 k 2 2 k
 Refer to 8-12, equation (2) and assuming vx is sufficient small
2
ISS 2ISS ISS v y vy 2
 I M 3  I M 4  kv x  vy  v y  v x  kv x (
2 2
  )
k k k 2 2
2
ISS 2ISS ISS vy 2 vy
 I M 6  I M 5  kv x  vy  v y  v x  kv x (
2 2
  )
k k k 2 2
 I out  (I M 3  I M 4 )  (I M 6  I M 5 )  2kv x v y
References:
[1]J. N. Babanezhad and G. C. Temes, “A 20-V four-quadrant CMOS analog multiplier”, IEEE J. Solid-State
Circuits, vol. SC-20, pp.1158-1168, Dec. 1985.
[2]Gunhee Han and Edgar Sanchez-Sinencio, “CMOS Transconductance Multipliers: A Tutorial”, IEEE Trans.
Circuit Syst. II, vol. 45, pp.1550-1563, Dec. 1998.
Voltage and Current References
 Circuits that yield a precise DC voltage or current independent of
external influences are called voltage references(Vref) or current
references (Iref)
 Two major specs on Vref and Iref

 Temperature Coefficient
 Power Supply Sensitivity
Power Supply Sensitivity of Vref/Iref
 The sensitivity of Vref to change in a power supply Vxx (VDD or GND) is
given as:
VREF / VREF
SVVREF  lim
VXX 0 VXX / VXX
XX
VXX  VREF 
  
VREF  VXX 
V REF
 Once S VXX is known, we obtain
VREF  VXX 
 SVVREF
XX  
VREF  VXX 
 Besides,
IREF
SIVREF and can be similarly obtained
VXX
XX
Temperature Coefficient of VREF/IREF
1 VREF 1 VREF 1 IREF
 TC VREF   ST ; TC IREF 
1
 STIREF
VREF T T IREF T T
 Examples(resistor divider): VXX

 Voltage Sensitivity
 R2  VXX VREF R1
VREF  VXX   S VREF
 1
 R1  R 2  VREF VXX
VXX
 Temperature Coefficient
R2 VREF
1 VREF Vxx    R 2 
TC VREF    
VREF T VREF  T  R1  R 2 
Vxx  1 R 2 1  R1 R 2 
   R 2 
 
R1  R 2  
2
VREF  R1  R 2 T T T 
VXX R1R 2  1 R 2 1 R1 
 2 
 
VREF R1  R 2   R 2 T R1 T 
If TC(R1)=TC(R2), then TC(VREF)=0

Supply Independent Current Source
 Neglecting base current
IREF  VBE1 / R 2  Vt / R 2 lnIIN / IS1
IIN  VCC  2VBE / R1 VCC
VCC IREF
S IREF
 R1 IIN IREF
IREF VCC
Vcc
Q2
VCC Vt R1IS1 1
 Q1
IREF R 2 VCC  2VBE R1IS1
VBE R2
 Assuming VCC>>2VBE
Vt
S IREF
Vcc 
IREFR 2
Reducing TC(VREF) by using the combination of
Breakdown diode and pn diode
 Breakdown diodes and pn junction diodes(or transistor connected
diodes) have opposite temperature coefficients.
VREF 
R2
Vz  3VBE  VBE
R1  R 2
 R2   R2  R1
  VZ  2  VBE  VBE Io
 R1  R 2   R1  R 2  R1  R 2 Q1
VREF
 Let 0, then D1
T
Vz
R1
T  R1  2 VZ
VBE R 2
T R2
Vz o 1 VBE
Assuming  3mV C and  2mV o C 1 VREF
T T D2
R1
then R 2  3.5 and VREF  1.4V
Bandgap Voltage Reference
 Model
VCC VBE( on ) VT  kT
q
 2mV / o C
I1  3300 ppm / o C   0.085 mV / o C
T T
VBE( on )
Sum Vref  VBE(on )  GVT
VT VT G  VT
generator G
 Rough calculation
VBE has a temperature coefficient of –2 mV/oc at room temperature
VT has a temperature coefficient of 0.085 mV/oc
VREF=VBE+GVT
 Assuming VBE=0.65V, then G=23.5 & VREF=1.26V =>TC=0
Bandgap Voltage Reference (Cont.)
 The most popular approach to realize voltage reference for CMOS and
bipolar ICs
 Cancelling the negative temperature dependence of a pn junction with a
positive temperature dependence from a PTAT(proportional-to-
absolute-temperature) circuit
 Accurate calculation
A forward-biased base-emitter junction of a bipolar transistor has an I-V
relationship given by qVBE
kT
I C  ISe
where Is is the transistor scale (reverse saturation) current and, although
not shown, has a strong dependence on temperature.
Writing the base-emitter voltage as a function of collector current and
temperature, it can be shown that [Brugler, 1967; Tsividis, 1980]
 T T mkT  T 0  kT  JC 
VBET   VG 01    VBE0  ln   ln 
 T0  T0 q  T  q  JC 0 
Bandgap Voltage Reference(Cont.)
Here, VG0 is the bandgap voltage of silicon extrapolated to 0ok
(approximately 1.206V), k is Boltzmann’s constant, and m is a
temperature constant approximately equal to 2.3. Also, JC and T are the
collector current density and temperature, respectively, while the
subscript 0 designates an appropriate quantity at a reference
temperature, T0 .
Specifically, JC0 is the collector current density at the reference
temperature, T0, whereas JC is the collector current density at the true
temperature, T. Also, VBE0 is the junction voltage at the reference
temperature, T0, whereas VBE is the base-emitter junction voltage at the
true temperature, T.
Vref T   VBET   GVT

kT  T0 
 VG 0  m  1 1  ln 
q  T
if G is properly taken
Bandgap Voltage Reference(Cont.)
Vref V
1.290
To  400 o K
1.280 (a )
Vref
1.270 0
(b) To  300 o K T
1.260
Vref
0
T
1.250
(c)
To  200 o K
1.240
Vref
0
T o
T C
 60  40  20 0 20 40 60 80 100 120
 Temperature coefficient
Vref T  k  T0 
 m  1  ln 
T q T
Bipolar Bandgap Voltage Reference
I2 IS1
 —— ①
VDD I1 IS3
VBE4 VBE2
I1  IS4e Vt
and I2  IS2e Vt
 VBE2   VBE4  VR1
VR1 R 1 Q5
VBE From 1
  VBE4  VR1 
VREF IS2exp 
Q2 Q4 I2 IS1  Vt  IS2  VR1 
   exp 
VR 2 R2 I1 IS3   VBE4  IS4  V t 
I1 IS4exp 
I2  Vt 
IE IS1IS4
Q1 Q3  VR1  Vtln
Q6 IS2IS3
IS6
VREF  VBE  IER2  VBE  I1 R2
IS3
VR1 IS6
 VBE  R2
R1 IS3
 R2  IS6   IS1IS4 
 VBE    Vtln 
 R1  IS3   IS2IS3 
CMOS Bandgap Voltage Reference in Weak Inversion
 A CMOS bandgap voltage reference operating in weak inversion
 Operational principle:
 Initial loop gain is greater than 1
loop current increases
 Equilibrium is achieved when the loop gain is reduced to one by
the voltage VR1 across R
 S1S4 
VR1  Vt ln 
 S2S 3 
 R 2  S6   S1S4 
VREF  VBE    Vt ln 
 R1  S3   S2S3 
CMOS Bandgap Voltage Reference in Weak Inversion (Cont.)
 Weak inversion (I-V is similar to bipolar)
log IDS IDS
near off  weak inversion

on  strong inversion
VGS VGS
 1   1  
W  VBS        
VDS
 VGS  VTh
IDS  ID 0 exp   nVt   Vt   1  exp Vt  exp nVt
 
L  
kT
where Vt  and VTh is threshold voltage
q
 Parasitic bipolar transistor is needed.
p+
(Example with N-well process) n-well
p-substrate
CMOS Bandgap Voltage Reference in Weak
W
Inversion (Cont.)
 VBS VBS VGS  VTh 
W IDS   ID0exp    
  M1  L  nVt Vt nVt 
 CMOS circuit I2  L 

If VDS>>Vt  W W  VGB  Vth VBS 
I1
  M3    ID0exp  
 
L  L   nV t V t 
VDD
I2 (W/L)M1 W  VGB2  VT h VBS2 
=  I2   M2ID0exp   M1 M3 M6
I1 (W/L)M3 L  nVt Vt 
W  VGB4  VT h VBS4 
If channel length I1   M4ID0exp   I2
I1
modulation L  nVt Vt  R2 VR2
M2 M4
effect is ignored  VBS2  VBS4, VBS2  0, VBS4  -V
VR1
R1 VBE VREF
Q5
W VR1 R1
Let    S
Let
L
 Precautions:
 M2 and M4 must be in weak inversion
 Leakage currents must be minimized
 Large output resistance of the devices for good current mirrors.
Using long channel or various mirrors presented before.

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Chapter 8

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Copyright:

Available Formats

Sample and Hold (S/H)

 “Sample and Hold” (often referred to as “Track and hold”(T/H))

 Droop rate in hold mode

 Other parameters such as

Sampling signal with sampling frequency fsmpl

Where the S/H is operating at it’s maximum sampling

Output signal of sample and hold

 The major limitation is a second-order effect caused by a mismatch

IMb  k(VX  0.5vi )2 ISS

where VX  VCM  VS  VTH

ISS kv i 2ISS I kv 2ISS

 Two major specs on Vref and Iref

 Examples(resistor divider): VXX

If TC(R1)=TC(R2), then TC(VREF)=0

 Assuming VBE=0.65V, then G=23.5 & VREF=1.26V =>TC=0

Vref T   VBET   GVT

near off  weak inversion

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