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Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

Computer Architecture
Harimohan Khatri

Computer Arithmatic
• Integer representation
• Integer arithmetic
• Unsigned binary addition and subtraction
• Unsigned binary multiplication algorithm
• Booth’s algorithm
• Unsigned binary division algorithm
• Floating point representation
• BCD arithmetic unit
• BCD adder

BECE-PU 1
Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

Integer representation
• In the binary number system, arbitrary numbers can be represented
with just the digits zero and one, the minus sign (for negative
numbers), and the period, or radix point (for numbers with a
fractional component).
• -1101.01012 = - (1*23 + 1*22 + 0*21 + 1*20+ 0*2-1 + 1*2-2 + 0*2-3 *1-4)
=-13.312510
• For purposes of computer storage and processing, we do not have the
benefit of special symbols for the minus sign and radix point. Only
binary digits (0 and 1) may be used to represent numbers.

Integer representation
• If we are limited to nonnegative integers, the representation is straight
forward.

• In general, if an n-bit sequence of binary digits an-1an-2 …a1a0 is interpreted


as an unsigned integer A, its value is
A = ∑$%& 𝑖
!"# 2 𝑎𝑖

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Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

Sign magnitude representation


• Representing positive as well as negative numbers include most significant
(leftmost) bit in the word as a sign bit. If the sign bit is 0, the number is positive; if
the sign bit is 1, the number is negative.
• The simplest form of representation that employs a sign bit is the sign-magnitude
representation. In an n-bit word, the rightmost n - 1 bits hold the magnitude of
the integer. For example: +18 = 00010010 and -18 = 10010010 (sign magnitude)
• The general case can be expressed as follows:

Sign magnitude representation


• There are several drawbacks to sign-magnitude representation.
• One is that addition and subtraction require a consideration of both the signs
of the numbers and their relative magnitudes to carry out the required
operation.
• Another drawback is that there are two representations of 0:
010 = 00000000
- 010 = 10000000 (sign magnitude)
• Because of these drawbacks, sign-magnitude representation is rarely
used in implementing the integer portion of the ALU. Instead, the
most common scheme is twos complement representation.

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Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

Two’s complement representation


• Like sign magnitude, twos complement representation uses the most
significant bit as a sign bit, making it easy to test whether an integer is
positive or negative.
• It differs from the use of the sign-magnitude representation in the way that
the other bits are interpreted.
• Consider an n-bit integer, A, in twos complement representation. If A is
positive, then the sign bit, an - 1, is zero. The remaining bits represent the
magnitude of the number in the same fashion as for sign magnitude:
A = ∑$%( 𝑖
!"# 2 𝑎𝑖
• The number zero is identified as positive and therefore has a 0 sign bit and
a magnitude of all 0s.

Two’s complement representation


• The range of positive integers that may be represented is from 0 (all
of the magnitude bits are 0) through 2n-1 - 1 (all of the magnitude bits
are 1). Any larger number would require more bits.
• Now, for a negative number A(A < 0), the sign bit, an-1, is one. The
remaining n-1 bits can take on any one of 2n-1 values. Therefore, the
range of negative integers that can be represented is from -1 to -2n-1.
• Two’s complement representation for both positive and negative
numbers
A= -2n-1an-1+∑$%&
!"# 2 𝑎𝑖
𝑖

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Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

Two’s complement representation

Range extension
• It is sometimes desirable to take an n-bit integer and store it in m bits, where m >
n. This expansion of bit length is referred to as range extension, because the
range of numbers that can be expressed is extended by increasing the bit length.

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Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

Range extension of signed numbers


• In sign-magnitude notation, this is easily accomplished: simply move the sign bit
to the new leftmost position and fill in with zeros.

• This procedure will not work for twos complement negative integers. Using the
same example,

11

Range extension of signed numbers


• Instead, the rule for twos complement integers is to move the sign bit
to the new leftmost position and fill in with copies of the sign bit.
• For positive numbers, fill in with zeros, and
• for negative numbers, fill in with ones.
• This is called sign extension.

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Fixed point representation


• The representations discussed are sometimes referred to as fixed point.
• This is because the radix point (binary point) is fixed and assumed to be to
the right of the rightmost digit.
• If we assume the radix point is fixed at the rightmost position, the number 11001010
can be interpreted as an integer.
• The binary number 11001010 is 1×27+1×26+0×25+0×24+1×23+0×22+1×21+0×20
• Calculating this gives: 128+64+0+0+8+0+2+0 =202.
• The programmer can use the same representation for binary fractions by
scaling the numbers so that the binary point is implicitly positioned at
some other location.
• Suppose we want to use the same 8-bit representation for a binary fraction. If we
assume the radix point is 4 positions from the right (i.e., 1100.1010), the
interpretation changes.
• The number now becomes 1×23+1×22+0×21+0×20+1×2−1+0×2−2+1×2−3+0×2−4
• Calculating this gives: 8+4+0+0+0.5+0+0.125+0 =12.625

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Integer Arithmetic
Negation
• In sign-magnitude representation, the rule for forming the negation
of an integer is simple: invert the sign bit.
• In twos complement notation, the negation of an integer can be
formed with the following rules:
• Take the Boolean complement of each bit of the integer (including the sign
bit). That is, set each 1 to 0 and each 0 to 1.
• Treating the result as an unsigned binary integer, add 1.
• This two-step process is referred to as the twos complement
operation, or the taking of the twos complement of an integer.

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Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

• Example:

• There are two special cases to be considered:


• Consider A = 0, in that case, for 8-bit representaion:

• There is a carry out of the most significant bit position, which is ignored. The result is that the
negation of 0 is 0, as it should be.

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• The second special case is more of a problem. If we take the negation of the bit pattern
of 1 followed by n - 1 zeros, we get back the same number. For example, for 8-bit words,

• Some such anomaly is unavoidable. The number of different bit patterns in an n-bit word
is 2n, which is an even number.
• We wish to represent positive and negative integers and 0. If an equal number of positive
and negative integers are represented (sign magnitude), then there are two
representations for 0.
• If there is only one representation of 0 (twos complement), then there must be an
unequal number of negative and positive numbers represented.
• In the case of twos complement, for an n-bit length, there is a representation for - 2n - 1
but not for + 2n - 1

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Addition
• Addition proceeds as if the two numbers were unsigned integers.
• If the result of the operation is positive,
• we get a positive number in twos complement form, which is the same as in
unsigned-integer form.
• If the result of the operation is negative,
• we get a negative number in twos complement form.
• On any addition, the result may be larger than can be held in the word size
being used. This condition is called overflow.
• When overflow occurs, the ALU must signal this fact so that no attempt is made to
use the result. To detect overflow, the following rule is observed:
If two numbers are added, and they are both positive or both negative, then overflow
occurs if and only if the result has the opposite sign.
For example in case of addition of -4 and -5 the result of addition 1100 and 1011 is 0111 with overflow bit
1. In such case we need to consider 1 as sign bit to get result.

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Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

Substraction:
• To subtract one number (subtrahend) from another (minuend), take the twos
complement (negation) of the subtrahend and add it to the minuend.

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Hardware for Addition and Subtraction

OF = Overflow bit
SW = Switch (select
addition or subtraction)

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Multiplication
• Multiplication of unsigned binary numbers:
• Multiplication involves the generation of partial products, one for each digit in the
multiplier. These partial products are then summed to produce the final product.
• The partial products are easily defined. When
• the multiplier bit is 0, the partial product is 0.
• When the multiplier is 1, the partial product is
• the multiplicand.
• The total product is produced by summing the
• partial products. For this operation, each successive
• partial product is shifted one position to the left
• relative to the preceding partial product.
• The multiplication of two n-bit binary integers results in a product of up to 2n bits in
length (e.g., 11 * 11 = 1001).

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Multiplication of unsigned binary numbers


• To make computerized
multiplication more efficient.
• First, we can perform a running
addition on the partial products
rather than waiting until the end. This
eliminates the need for storage of all
the partial products; fewer registers
are needed.
• Second, we can save some time on
the generation of partial products.
For each 1 on the multiplier, an add
and a shift operation are required;
but for each 0, only a shift is required.

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Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

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Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

• Question: Multiply 16*2 using unsigned binary multiplication.


• 16 = 10000
• 2 = 00010
C A Q M Count Remarks
0 00000 00010 10000 5 Initialization
0 00000 00001 4 Logical right shift
Count--
0 10000 00001 3 A ß A+M
0 01000 00000 Logical right shift
Count--
0 00100 00000 2 Logical right shift
Count--
0 00010 00000 1 Logical right shift
Count--
0 00001 00000 0 Logical right shift
Count--

1024*0+512*0+128*0+64*0+32*1+16*0+8*0+4*0+2*0+1*0 = (32)10

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• Question: Multiply 15*11 using unsigned binary multiplication.


• 15 = 1111
• 2 = 1011
C A Q M Count Remarks
0 0000 1011 1111 4 Initialization
0 1111 1011 3 A ß A+M
0 0111 1101 Logical right shift
Count--
1 0110 1101 2 A ß A+M
0 1011 0110 Logical right shift
Count--
0 0101 1011 1 Logical right shift
Count--
1 0100 1011 0 A ß A+M
0 1010 0101 Logical right shift
Count--

512*0+128*1+64*0+32*1+16*0+8*0+4*1+2*0+1*1 = (165)10

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BECE-PU 13
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Multiplication of signed binary numbers


• Straight-forward multiplication will not work if both the multiplicand and
multiplier are negative, even if either the multiplicand or the multiplier is
negative.
• To demonstrate that straight forward multiplication will not work if the
multiplicand is negative.
• The problem is that each contribution of the negative multiplicand as a partial
product must be a negative number on a 2n-bit field;
• The sign bits of the partial products must line up.
• This is demonstrated in Figure, which shows that multiplication of 1001 by 0011.
• If these are treated as unsigned integers, the multiplication of 9 * 3 = 27 proceeds
simply.
• However, if 1001 is interpreted as the twos complement value - 7, then each partial
product must be a negative twos complement number of 2n (8) bits.

27

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Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

• If the multiplier is negative, straightforward multiplication also will not


work.
• The reason is that the bits of the multiplier no longer correspond to the shifts or
multiplications that must take place.
• For example, the 4-bit decimal number - 3 is written 1101 in twos complement. If we
simply took partial products based on each bit position, we would have the following
correspondence:
• 1101 à -(1*23 +1*22 +0*21 +1*20)= -(23 +22 +20)
• In fact, what is desired is -(21 + 20). So this multiplier cannot be used directly in the
manner we have been describing.
• There are a number of ways out of this dilemma.
• One would be to convert both multiplier and multiplicand to positive numbers,
perform the multiplication, and then take the twos complement of the result if and
only if the sign of the two original numbers differed.
• Implementers have preferred to use techniques that do not require this final
transformation step.
• One of the most common of these is Booth’s algorithm . This algorithm also has the
benefit of speeding up the multiplication process, relative to a more straightforward
approach.

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Booth’s Algorithm
• Multiplier and multiplicand are placed in Q and M register respectively.
• There is also one bit register placed logically to the right of the least
significant bit 𝑄0of the Q register and designated as 𝑄−1.
• The result of multiplication will appear in A and Q resister.
• A and 𝑄−1 are initialized to zero if two bits (Q0 and 𝑄−1) are the same (11 or
00) then all the bits of A, Q and 𝑄−1 registers are shifted to the right 1 bit.
• If the two bits differ then the multiplicand is added to or subtracted from
the A register depending on weather the two bits are 01 or 10.
• Following the addition or subtraction the arithmetic right shift occurs.
• When count reaches to zero, result resides into AQ in the form of signed
integer [−2𝑛−1 × 𝑎𝑛−1+2𝑛−2 × an-2+ … … … … 21 × 𝑎1 + 20 × 𝑎0 ].

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• Multiply 9*-3 using booth’s algorithm.


9 = 01001 -9 = 10111 3 = 00011 -3 = 11101
A Q Q-1 M -M Count Remarks
00000 11101 0 01001 10111 5 Initialization
10111 11101 0 AßA-M as Q0Q-1 is 10
11011 11110 1 4 Arithmetic Right Shift A,Q,Q-1, Count--
00100 11110 1 AßA+M as Q0Q-1 is 01
00010 01111 0 3 Arithmetic Right Shift A,Q,Q-1, Count--
11001 01111 0 AßA-M as Q0Q-1 is 10
11100 10111 1 2 Arithmetic Right Shift A,Q,Q-1, Count--
11110 01011 1 1 Q0Q-1 is 11
Arithmetic Right Shift A,Q,Q-1, Count--
11111 00101 1 0 Q0Q-1 is 11
Arithmetic Right Shift A,Q,Q-1, Count--

Result in A,Q = -1*29+ 1*28+ 1*27+ 1*26+ 1*25+ 0*24+ 0*23+ 1*22+ 0*21+ 1*20 =-512+256+128+64+32+4+1 =-27

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Why does booth’s algorithm work?


• Consider first the case of a positive multiplier.
• In particular, consider a positive multiplier consisting of one block of 1s surrounded by 0s
(e.g., 00011110). As we know, multiplication can be achieved by adding appropriately shifted
copies of the multiplicand:

• The number of such operations can be reduced to two if we observe that


2n + 2n-1 + … + 2n-K = 2n+1 -2n-K

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BECE-PU 17
Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

• So the product can be generated by one addition and one subtraction of the
multiplicand. This scheme extends to any number of blocks of 1s in a
multiplier, including the case in which a single 1 is treated as a block.

• Booth’s algorithm conforms to this scheme by performing a subtraction when


the first 1 of the block is encountered (1–0) and an addition when the end of
the block is encountered (0–1).
• To show that the same scheme works for a negative multiplier,
• Let X be a negative number in twos complement notation:
Representation of X = {1xn-2xn-3…x1x0}
• Then the value of X can be expressed as follows:
X= -2n-1 +(xn-2*2n-2)+(xn-3 *2n-3)+ … +(x1 *21)+(x0 *20)

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• Assume that the leftmost 0 is in the kth position. Thus, X is of the


form
Representation of X = {111…10xk-1xk-2…x1x0}
• Then the value of X is:
X= -2n-1 +2n-2 + … +2k+1 +(xk-1 *2k-1)+ … +(x0 *20)
But we have, 2n-2 +2n-3 + … +2k-1 =2n-1 -2k-1
Rearranging, -2n-1 + 2n-2 + 2n-3 + … + 2k+1 = -2k+1
Now, X = -2k+1 +(xk-1 *2k-1)+ … +(x0 *20)
• As the algorithm scans over the leftmost 0 and encounters the next 1
(2k + 1), a 1–0 transition occurs and a subtraction takes place ( - 2k + 1).

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BECE-PU 18
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Division of binary numbers


• The basis for the algorithm is, the operation involved repetitive shifting and
addition or subtraction.
• First, the bits of the dividend are examined from left to right, until the set of bits
examined represents a number greater than or equal to the divisor; this is
referred to as the divisor being able to divide the number.
• Until this event occurs, 0s are placed in the quotient from left to right.
• When the event occurs, a 1 is placed in the quotient and the divisor is subtracted from the
partial dividend.
• The result is referred to as a partial remainder.
• From this point on, the division follows a cyclic pattern.
• At each cycle, additional bits from the dividend are appended to the partial remainder until
the result is greater than or equal to the divisor.
• As before, the divisor is subtracted from this number to produce a new partial remainder.
• The process continues until all the bits of the dividend are exhausted.

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Division of binary numbers

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BECE-PU 19
Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

Restoring two’s complement division


• The algorithm assumes that the divisor V and the dividend D are positive
and that |V| < |D|. If |V| = |D|, then the quotient Q = 1 and the
remainder R = 0.If |V| > |D|, then Q = 0 and R = D. The algorithm can be
summarized as follows:
• Load the twos complement of the divisor into the M register; that is, the M register
contains the negative of the divisor. Load the dividend into the A, Q registers. The
dividend must be expressed as a 2n-bit positive number. Thus, for example, the 4-bit
0111 becomes 00000111.
• Shift A, Q left 1 bit position.
• Perform A d A - M. This operation subtracts the divisor from the contents of A.
• If the result is nonnegative (most significant bit of A = 0), then set Q0 d 1.
• If the result is negative (most significant bit of A = 1), then set Q0 d 0. and restore the
previous value of A.
• Repeat steps 2 through 4 as many times as there are bit positions in Q.
• The remainder is in A and the quotient is in Q.

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• Question: Divide 15 by 4 using restoring algorithm.


15 = 1111 4 = 0100 -4 = 11100
A Q M M’+1 Count Remarks
00000 1111 00100 11100 4 Initialization
00001 111_ Shift left A,Q
11101 111_ AßA-M
00001 1110 3 Q0=0, AßA+M, Count--
00011 110_ Shift left A,Q
11111 110_ AßA-M
00011 1100 2 Q0=0, AßA+M, Count--
00111 100_ Shift left A,Q
00011 100_ AßA-M
00011 1001 1 Q0=1, Count--
00111 001_ Shift left A,Q
00011 001_ AßA-M
00011 0011 Q0=1, Count--

Quotient(Q) = 0011 = 3
Remainder(A) = 00011 = 3

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• Question: Divide 19 by 3 using restoring algorithm.


19 = 10011 3 = 000011 -3 = 111101
A Q M M’+1 Count Remarks
000000 10011 000011 111101 5 Initialization
000001 0011_ Shift left A,Q
111110 0011_ AßA-M
000001 00110 4 Q0=0, AßA+M, Count--
000010 0110_ Shift left A,Q
111111 0110_ AßA-M
000010 01100 3 Q0=0, AßA+M, Count--
000100 1100_ Shift left A,Q
000001 1100_ AßA-M
000001 11001 2 Q0=1, Count--
000011 1001_ Shift left A,Q
000000 1001_ AßA-M
000000 10011 1 Q0=1, Count—
000001 0011_ Shift left A,Q
111110 0011_ AßA-M
000001 00110 0 Q0=0, AßA+M, Count--

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• To deal with negative numbers, we recognize that the remainder is defined by D=Q*V+R
• That is, the remainder is the value of R needed for the preceding equation to be valid.
Consider the following examples of integer division with all possible combinations of
signs of D and V:
D=7 V=3 à Q=2 R=1
D=7 V=-3 à Q=-2 R=1
D=-7 V=3 à Q=-2 R=-1
D=-7 V=-3 à Q=2 R=-1
• Note that (-7)/(3) and (7)/(-3) produce different remainders. We see that the magnitudes
of Q and R are unaffected by the input signs and that the signs of Q and R are easily
derivable from the signs of D and V.
• Specifically, sign(R) = sign(D) and sign(Q) = sign(D) * sign(V).
• Hence, one way to do twos complement division is to convert the operands into
unsigned values and, at the end, to account for the signs by complementation where
needed.
• This is the method of choice for the restoring division algorithm

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Floating point representation


• With a fixed-point notation (e.g., twos complement) it is possible to
represent a range of positive and negative integers centered on or near 0.
By assuming a fixed binary or radix point, this format allows the
representation of numbers with a fractional component as well.
(0110.1010)2 =0*23+1*22+1*21+0*20+1*2-1+0*2-2+1*2-3+0*2-4
= 6.62510
• This approach has limitations. Very large numbers cannot be represented,
nor can very small fractions. Furthermore, the fractional part of the
quotient in a division of two large numbers could be lost.
• For decimal numbers, we get around this limitation by using scientific
notation.
• 976,000,000,000,000 can be represented as 9.76 * 1014, and
• 0.0000000000000976 can be represented as 9.76 * 10-14

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• The same approach can be taken with binary numbers. We can represent a
number in the form
±S * B±E
• This number can be stored in a binary word with three fields:
• Sign: plus or minus
• Significand S
• Exponent E

Figure: Typical 32-Bit Floating-Point Format


Add 127 for 8 bit (2K-1-1) while storing.

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• The leftmost bit stores the sign of the number (0 = positive, 1 = negative).
• The exponent value is stored in the next 8 bits. The representation used is
known as a biased representation.
• A fixed value, called the bias, is subtracted from the field to get the true
exponent value. Typically, the bias equals (2k- 1 - 1), where k is the number
of bits in the binary exponent.
• In 8-bit field, it yields the numbers 0 through 255. With a bias of 127 (27 - 1), the true
exponent values are in the range - 127 to + 128. The base is assumed to be 2.
• The final portion of the word (23 bits in this case) is the significand.
• To simplify operations on floating-point numbers, it is typically required
that they be normalized.
• A normal number is one in which the most significant digit of the significand is
nonzero. For base 2 representation, a normal number is therefore one in which the
most significant bit of the significand is one.
±1.bbb…b* 2±E

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• Using twos complement integer representation, all of the integers from - 231 to
231 - 1 can be represented, for a total of 232 different numbers.
• With floating-point format, the following ranges of numbers are possible:
• Negative numbers between - (2 - 2-23) * 2128 and - 2-127
• Positive numbers between 2-127 and (2 - 2-23) * 2128

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Floating point arithmetic


• There are four basic operations for floating point arithmetic.

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Floating point arithmetic


• For addition and subtraction, it is necessary to ensure that both operands have
the same exponent values.
• This may require shifting the radix point on one of the operands to achieve alignment.
• Multiplication and division are straighter forward. Which include multiplication or
division of significand and addition or subtraction of exponent value.
• A floating point operation may produce one of these conditions:
• Exponent Overflow: A positive exponent exceeds the maximum possible exponent value.
• Exponent Underflow: A negative exponent which is less than the minimum possible value.
• Significand Overflow: The addition of two significands of the same sign may carry in a carry
out of the most significant bit.
• Significand underflow: In the process of aligning significands, digits may flow off the right end
of the significand.

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BECE-PU 25
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BCD Adder
• BCD stand for binary coded decimal.
• Suppose, we have two 4-bit numbers A and B. The value of A and B
can varies from 0(0000 in binary) to 9(1001 in binary) because we are
considering decimal numbers.
• The output will varies from 0 to 18,
• if we are not considering the carry from the previous sum.
• But if we are considering the carry, then the maximum value of output will be
19 (i.e. 9+9+1 = 19).
• When we are simply adding A and B, then we get the binary sum.
Here, to get the output in BCD form, we will use BCD Adder.

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Example-01
Input
• A = 0111 and B = 1000
Output
• Y = 1 0101
Explanation: We are adding A(=7) and B(=8).
• The value of binary sum will be 1111(=15).
• But, the BCD sum will be 1 0101, where 1 is 0001 in binary and 5 is 0101 in
binary.
Note – If sum of two numbers is less than or equal to 9, then the value of BCD sum
and binary sum will be same otherwise they will differ by 6(0110 in binary).

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Example-02
Input
• A = 0101 and B = 1001
Output
• Y = 1 0100
Explanation: We are adding A(=5) and B(=9).
• The value of binary sum will be 1110(=14).
• But, the BCD sum will be 1 0001, where 1 is 0001 in binary and 5 is
0001 in binary.

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Inputs Output
S3 S2 S1 S0 Y
Let’s move to the table and find out 0 0 0 0 0
the logic when we are going to add 0 0 0 1 0
“0110” 0 0 1 0 0
0 0 1 1 0

S1S0 0 1 0 0 0
00 01 11 10
S3S2 0 1 0 1 0
00 0 0 0 0 0 1 1 0 0
01 0 0 0 0 0 1 1 1 0
11 1 1 1 1 1 0 0 0 0
10 0 0 1 1 1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
From K-Map: 𝑌 = 𝑆3𝑆2 + 𝑆3𝑆1 1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

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Computer Architecture - Harimohan Khatri Saturday, June 8, 2024

Hardware implementation

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END OF CHAPTER - 05
References:
§ Computer Organization and Architecture – William Stallings
§ Compiled lecture notes from Pokhara University Constituent/Affiliated colleges.
§ Different internet sources for diagrams and figures.

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