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CH-05
CH-05
Computer Architecture
Harimohan Khatri
Computer Arithmatic
• Integer representation
• Integer arithmetic
• Unsigned binary addition and subtraction
• Unsigned binary multiplication algorithm
• Booth’s algorithm
• Unsigned binary division algorithm
• Floating point representation
• BCD arithmetic unit
• BCD adder
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Integer representation
• In the binary number system, arbitrary numbers can be represented
with just the digits zero and one, the minus sign (for negative
numbers), and the period, or radix point (for numbers with a
fractional component).
• -1101.01012 = - (1*23 + 1*22 + 0*21 + 1*20+ 0*2-1 + 1*2-2 + 0*2-3 *1-4)
=-13.312510
• For purposes of computer storage and processing, we do not have the
benefit of special symbols for the minus sign and radix point. Only
binary digits (0 and 1) may be used to represent numbers.
Integer representation
• If we are limited to nonnegative integers, the representation is straight
forward.
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Range extension
• It is sometimes desirable to take an n-bit integer and store it in m bits, where m >
n. This expansion of bit length is referred to as range extension, because the
range of numbers that can be expressed is extended by increasing the bit length.
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• This procedure will not work for twos complement negative integers. Using the
same example,
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Integer Arithmetic
Negation
• In sign-magnitude representation, the rule for forming the negation
of an integer is simple: invert the sign bit.
• In twos complement notation, the negation of an integer can be
formed with the following rules:
• Take the Boolean complement of each bit of the integer (including the sign
bit). That is, set each 1 to 0 and each 0 to 1.
• Treating the result as an unsigned binary integer, add 1.
• This two-step process is referred to as the twos complement
operation, or the taking of the twos complement of an integer.
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• Example:
• There is a carry out of the most significant bit position, which is ignored. The result is that the
negation of 0 is 0, as it should be.
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• The second special case is more of a problem. If we take the negation of the bit pattern
of 1 followed by n - 1 zeros, we get back the same number. For example, for 8-bit words,
• Some such anomaly is unavoidable. The number of different bit patterns in an n-bit word
is 2n, which is an even number.
• We wish to represent positive and negative integers and 0. If an equal number of positive
and negative integers are represented (sign magnitude), then there are two
representations for 0.
• If there is only one representation of 0 (twos complement), then there must be an
unequal number of negative and positive numbers represented.
• In the case of twos complement, for an n-bit length, there is a representation for - 2n - 1
but not for + 2n - 1
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Addition
• Addition proceeds as if the two numbers were unsigned integers.
• If the result of the operation is positive,
• we get a positive number in twos complement form, which is the same as in
unsigned-integer form.
• If the result of the operation is negative,
• we get a negative number in twos complement form.
• On any addition, the result may be larger than can be held in the word size
being used. This condition is called overflow.
• When overflow occurs, the ALU must signal this fact so that no attempt is made to
use the result. To detect overflow, the following rule is observed:
If two numbers are added, and they are both positive or both negative, then overflow
occurs if and only if the result has the opposite sign.
For example in case of addition of -4 and -5 the result of addition 1100 and 1011 is 0111 with overflow bit
1. In such case we need to consider 1 as sign bit to get result.
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Substraction:
• To subtract one number (subtrahend) from another (minuend), take the twos
complement (negation) of the subtrahend and add it to the minuend.
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OF = Overflow bit
SW = Switch (select
addition or subtraction)
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Multiplication
• Multiplication of unsigned binary numbers:
• Multiplication involves the generation of partial products, one for each digit in the
multiplier. These partial products are then summed to produce the final product.
• The partial products are easily defined. When
• the multiplier bit is 0, the partial product is 0.
• When the multiplier is 1, the partial product is
• the multiplicand.
• The total product is produced by summing the
• partial products. For this operation, each successive
• partial product is shifted one position to the left
• relative to the preceding partial product.
• The multiplication of two n-bit binary integers results in a product of up to 2n bits in
length (e.g., 11 * 11 = 1001).
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1024*0+512*0+128*0+64*0+32*1+16*0+8*0+4*0+2*0+1*0 = (32)10
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512*0+128*1+64*0+32*1+16*0+8*0+4*1+2*0+1*1 = (165)10
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Booth’s Algorithm
• Multiplier and multiplicand are placed in Q and M register respectively.
• There is also one bit register placed logically to the right of the least
significant bit 𝑄0of the Q register and designated as 𝑄−1.
• The result of multiplication will appear in A and Q resister.
• A and 𝑄−1 are initialized to zero if two bits (Q0 and 𝑄−1) are the same (11 or
00) then all the bits of A, Q and 𝑄−1 registers are shifted to the right 1 bit.
• If the two bits differ then the multiplicand is added to or subtracted from
the A register depending on weather the two bits are 01 or 10.
• Following the addition or subtraction the arithmetic right shift occurs.
• When count reaches to zero, result resides into AQ in the form of signed
integer [−2𝑛−1 × 𝑎𝑛−1+2𝑛−2 × an-2+ … … … … 21 × 𝑎1 + 20 × 𝑎0 ].
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Result in A,Q = -1*29+ 1*28+ 1*27+ 1*26+ 1*25+ 0*24+ 0*23+ 1*22+ 0*21+ 1*20 =-512+256+128+64+32+4+1 =-27
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• So the product can be generated by one addition and one subtraction of the
multiplicand. This scheme extends to any number of blocks of 1s in a
multiplier, including the case in which a single 1 is treated as a block.
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Quotient(Q) = 0011 = 3
Remainder(A) = 00011 = 3
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• To deal with negative numbers, we recognize that the remainder is defined by D=Q*V+R
• That is, the remainder is the value of R needed for the preceding equation to be valid.
Consider the following examples of integer division with all possible combinations of
signs of D and V:
D=7 V=3 à Q=2 R=1
D=7 V=-3 à Q=-2 R=1
D=-7 V=3 à Q=-2 R=-1
D=-7 V=-3 à Q=2 R=-1
• Note that (-7)/(3) and (7)/(-3) produce different remainders. We see that the magnitudes
of Q and R are unaffected by the input signs and that the signs of Q and R are easily
derivable from the signs of D and V.
• Specifically, sign(R) = sign(D) and sign(Q) = sign(D) * sign(V).
• Hence, one way to do twos complement division is to convert the operands into
unsigned values and, at the end, to account for the signs by complementation where
needed.
• This is the method of choice for the restoring division algorithm
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• The same approach can be taken with binary numbers. We can represent a
number in the form
±S * B±E
• This number can be stored in a binary word with three fields:
• Sign: plus or minus
• Significand S
• Exponent E
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• The leftmost bit stores the sign of the number (0 = positive, 1 = negative).
• The exponent value is stored in the next 8 bits. The representation used is
known as a biased representation.
• A fixed value, called the bias, is subtracted from the field to get the true
exponent value. Typically, the bias equals (2k- 1 - 1), where k is the number
of bits in the binary exponent.
• In 8-bit field, it yields the numbers 0 through 255. With a bias of 127 (27 - 1), the true
exponent values are in the range - 127 to + 128. The base is assumed to be 2.
• The final portion of the word (23 bits in this case) is the significand.
• To simplify operations on floating-point numbers, it is typically required
that they be normalized.
• A normal number is one in which the most significant digit of the significand is
nonzero. For base 2 representation, a normal number is therefore one in which the
most significant bit of the significand is one.
±1.bbb…b* 2±E
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• Using twos complement integer representation, all of the integers from - 231 to
231 - 1 can be represented, for a total of 232 different numbers.
• With floating-point format, the following ranges of numbers are possible:
• Negative numbers between - (2 - 2-23) * 2128 and - 2-127
• Positive numbers between 2-127 and (2 - 2-23) * 2128
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BCD Adder
• BCD stand for binary coded decimal.
• Suppose, we have two 4-bit numbers A and B. The value of A and B
can varies from 0(0000 in binary) to 9(1001 in binary) because we are
considering decimal numbers.
• The output will varies from 0 to 18,
• if we are not considering the carry from the previous sum.
• But if we are considering the carry, then the maximum value of output will be
19 (i.e. 9+9+1 = 19).
• When we are simply adding A and B, then we get the binary sum.
Here, to get the output in BCD form, we will use BCD Adder.
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Example-01
Input
• A = 0111 and B = 1000
Output
• Y = 1 0101
Explanation: We are adding A(=7) and B(=8).
• The value of binary sum will be 1111(=15).
• But, the BCD sum will be 1 0101, where 1 is 0001 in binary and 5 is 0101 in
binary.
Note – If sum of two numbers is less than or equal to 9, then the value of BCD sum
and binary sum will be same otherwise they will differ by 6(0110 in binary).
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Example-02
Input
• A = 0101 and B = 1001
Output
• Y = 1 0100
Explanation: We are adding A(=5) and B(=9).
• The value of binary sum will be 1110(=14).
• But, the BCD sum will be 1 0001, where 1 is 0001 in binary and 5 is
0001 in binary.
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Inputs Output
S3 S2 S1 S0 Y
Let’s move to the table and find out 0 0 0 0 0
the logic when we are going to add 0 0 0 1 0
“0110” 0 0 1 0 0
0 0 1 1 0
S1S0 0 1 0 0 0
00 01 11 10
S3S2 0 1 0 1 0
00 0 0 0 0 0 1 1 0 0
01 0 0 0 0 0 1 1 1 0
11 1 1 1 1 1 0 0 0 0
10 0 0 1 1 1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
From K-Map: 𝑌 = 𝑆3𝑆2 + 𝑆3𝑆1 1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
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Hardware implementation
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END OF CHAPTER - 05
References:
§ Computer Organization and Architecture – William Stallings
§ Compiled lecture notes from Pokhara University Constituent/Affiliated colleges.
§ Different internet sources for diagrams and figures.
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