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Next-Generation_DC_Power_Flow_Controller_Toward_Future_DC_Grids_A_Disruptive_Module-Based_Design
Next-Generation_DC_Power_Flow_Controller_Toward_Future_DC_Grids_A_Disruptive_Module-Based_Design
Next-Generation_DC_Power_Flow_Controller_Toward_Future_DC_Grids_A_Disruptive_Module-Based_Design
1
China Electric Power Research Institute Co.,Ltd
2
School of Eletronic Information and Electrical Engineering, Shanghai Jiao Tong University, 200240, China
*E-mail: zhanghongyi@sjtu.edu.cn
979-8-3503-0963-8/24/$31.00 ©2024
Authorized licensed use limited IEEE
to: UNIVERSIDADE 296
FEDERAL DO PIAUI. Downloaded on July 03,2024 at 14:10:07 UTC from IEEE Xplore. Restrictions apply.
control, while AC components are used to excite circulation line topologies, interfacing ports of different lines are supposed
currents for power balancing of MMC arms. to independent of each other.
Given the diverse variety of topologies that have been 2) An internal energy buffer. This module functions as an
proposed to date, the concept of developing a generalized internal hub to balance the power of each port. It could also be
paradigm for topology construction has garnered significant regarded as an intermediate medium for the transfer of currents
attention from researchers. As such, in [14], a modular between multiple lines.
topology architecture is proposed and verified. To derive this
architecture, firstly, the module-based interpretation of pre- The aforementioned points serve as the foundation of
existed topologies is conducted. This is realized by classifying dividing n-line DCPFCs into functional modules. Building on
and separating basic topology units based on their circuit this, the modular topology architecture for MDCPFCs could be
functions. Subsequently, a modular extension methodology is established as depicted in Fig.3. The interface unit i is
designed for these units to derive multi-line IDCPFC connected in series between the pi and ci terminals of line i.
topologies. Following these two steps, the modular architecture The bus a and bus b inside the device provide the power flow
is developed. IDCPFCs based on this architecture are denoted path between each interface unit and the energy buffer.
as modular DCPFCs (MDCPFC) in this paper. The concept
Bus0
Busb
Busa
and technology of MDCPFC, although in the early stage of its
development, has already demonstrated disruptive potential for a0 Energy
industry applications. On the one hand, it offers a top-level I1 a1 b0 Buffer
design compliance, allowing topologies with distinctive energy Line1 p1 Part1 b1 c0
transfer mechanisms could be standardized into a uniform form. c1
On the other hand, it has the potential to disrupt the previous I2 a2 p0
application-oriented design of IDCPFCs, where topologies are Part2
Line2 p2 b2
tailored to a specific application scenario. Instead, through its c2
module-based architecture, the flexibility of IDCPFC topology
could be significantly enhanced to accommodate DC grids of
arbitrary topologies.
In an
In this paper, efforts are devoted to this disruptive
Line n pn Part n bn
technology. First the principle of module-based topology is
cn
detailed. Then, other than the inductor-based MDCPFC which
has been elaborated in [14], the topology and operation Fig.3 Generalized topology structure of MDCPFC.
principles of its capacitor-based counterpart is given and
elaborated. Additionally, future trends in the development of III. ANALYSES AND VALIDATION OF CAPACITOR-BASED
MDCPFCs are discussed. MDCPFC
P1
V1 V3
P3
Based on the topology architecture shown in Fig.3, in this
VSC3
section, a detailed topology, the capacitor-based full-bridge
VSC1
MDCPFC, is given, as is depicted in Fig.4. Steady-state
Bus1 Bus3
IDCPFC
modelling and simulation verifications are elaborated.
P2 V2 V4 P4
Bus2 Bus4
II. MODULAR TOPOLOGY ARCHITECTURE Fig.4 Detailed topology of capacitor-based full-bridge MDCPFC
To elucidate the modular topology of MDCPFC, it is A. Operation Principles
essential to first analyze and deconstruct each key functional
unit. An MDCPFC connected in series between n lines is This topology features a full-bridge based interfacing port.
equivalent to n adjustable voltage sources with energy coupling. The combination of the interfacing port and the capacitor-
By controlling the port voltage of each adjustable voltage based energy buffer could realize bidirectional control over
source, the MDCPFC could actively regulate the voltage drop bidirectional power flows, namely, the four-quadrant operation.
across its series-connected lines, thereby achieving the Three typical working modes are defined hereby:
objective of current regulation. 1) Increase of power flow. In this case, the output voltage
As a result, in the n-line MIDCPFC, there shall exist: value of the H-bridge is negative relative to the capacitor
voltage;
1) An interfacing port. This module is directly connected in
series with the line, controlling its current by superimposing an 2) Decrease of power flow. In this case, the output volage of
adjustable DC voltage. In order to construct expandable multi- the H-bridge is positive to the capacitor voltage.
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3) Bypass state. In this case, the output voltage of the H- from Line 1 to the capacitor. The remaining lines do not
bridge is zero and the capacitor is bypassed from the DC line. participate in the energy exchange by bypassing the energy
buffer.
A particular case is chosen to elucidate the principles of the
capacitor-based full-bridge MDCPFC in detail. In this case, Sub-mode 2 (Refer to Fig.5(b)): QB2 and QC2 conduct and
both I1, I2 and I3 are positive. The control objective is to Line 2 is selected to exchange energy with the energy buffer.
decrease the power flows of Line 1 and Line 2. Consequently, The output voltage of port 2 (between nodes p2 and c2) is
the power flow of Line 3 will be increased to realize the overall positive relative to the capacitor voltage. Energy is transferred
power balance of the device. The operation of the capacitor- from Line 2 to the capacitor. The remaining lines do not
based full-bridge MDCPFC adopts the same multi-mode participate in the energy
mechanism as elaborated in [12]. In an entire switching period,
there are three sub-modes operating in complementary with Sub-mode 3 (Refer to Fig.5(c)): QA3 and QD3 conduct and
each other. Line 3 is selected to exchange energy with the energy buffer.,
capacitor C is connected to Line 3 with positive voltage,
Va Vb V4
Va Vb V4 Energy is transferred from the capacitor to Line 3. The
母线 b
母线 a
母线4
母线 b
母线 a
母线4
a0
+ iC a0
VC - C iC
B. Analyses of power flow control ability
+
VC - C
b0
a1
b0 In this section, the power flow control ability of the
QA1 QC1 b1
QA1 QC1
a1
b1 capacitor-based full-bridge MDCPFC is analyzed within the
I1 Vp1 DA1 DC1 I1 Vp1
framework of a 4-terminal DC grid as depicted in Fig.6. The
Line1 p1 QB1 QD1 c1 DA1
Line1 p1 QB1
DC1
QD1 c1 MDCPFC is installed in Line 1, Line 2, and Line 3. Three
DB1 DD1 equivalent series-connected voltages are VC1, VC2 and VC3,
respectively.
DB1 DD1
a2
b2 a2
QA2 QC2 I4 b2
QA2 QC2 I4 V1 R14 L14
I2 Vp2 DA2 DC2 I2 Vp2 DA2 DC2
Line2 p2 QB2 QD2 c2
c2 VSC1 I1
Line2 p2 QB2
Line1
QD2
DB2 DD2 R12 V4
DB2 DD2
a3
b3 a3 L12
QA3 QC3
QA3 QC3 b3 V2 VC1
I3 Vp3 DA3 DC3 R24 L24
I3 Vp3
Line3 p3 QB3 c3 DA3 DC3 VSC2 VSC4
QD3
Line3 p3 QB3 c3 Line2
QD3 I2 VC2
DB3 DD3
DB3 DD3 R23
母线4
+
a0
iC I3
VC - C
Fig.6 The 4-terminal DC grid with 3-line MDCPFC
b0
a1 There are 6 equations for the DC grid:
QA1 QC1 b1
I1 Vp1 1 1 1 V2 V4 + Vc1
P1 V12
DA1 DC1
Line1 p1 QB1 QD1 c1 = + + − V1 + (1)
DB1 DD1
R14 R24 R34 R12 R14
a2 1 1 V1 V4 + Vc 2
QA2 QC2 b2 I4 = P2 V22 + − V2 + (2)
I2 Vp2 DA2 DC2 R24 R23 R12 R14
Line2 p2 QB2 QD2 c2
1 1 V2 V4 + Vc3
DB2 DD2 = P3 V32 + − V3 + (3)
a3
b3
R23 R34 R23 R34
QA3 QC3
V1 − Vc1 − V4
I3 Vp3 DA3 DC3 I1 = (4)
Line3 p3 QB3 QD3 c3
R14
DB3 DD3 V − Vc 2 − V4
I2 = 2 (5)
(c) R24
Fig.5 Example of operation of 3-line shared inductor-based MDCPFC V −V −V
I3 = 3 c3 4 (6)
Sub-mode 1 (Refer to Fig.5(a)): QB1 and QC1 conduct and R34
Line 1 is selected to exchange energy with the energy buffer. Furthermore, consider the constraints within the capacitor-
The output voltage of port 1 (between nodes p1 and c1) is based MDCPFC: The energy center C needs to satisfy the volt-
positive relative to the capacitor voltage. Energy is transferred ampere balance. Hence we have:
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0
− I1 D1 − I 2 D2 + I 3 D3 = (7)
The equivalent series voltage for each line can be obtained
by averaging the switching cycles
I/A
VC1 = − D1VC
VC 2 = − D2VC (8)
V = D V
C3 3 C
Combining (7)(8) gives: (a) Waveforms of line currents
0
I1Vc1 + I 2Vc 2 + I 3Vc 3 = (9)
Voltage/V
Equation (9) is a complementary equation to (1)-(6).
Combine these 7 equations, the steady state model for the
entire system could be derived. In total, there are 7 equations
and 9 variables (V1, V2, V3, I12, I1, I2, I23, I34, VC1, VC2, VC3) in
the entire system. In order to determine the unique solution of
the system, it is necessary to set the values of two variables.
(b) Waveforms of capacitor voltages
Therefore, this three-line inter-capacitor-based full bridge Fig.7 Simulation waveforms of capacitor-based full bridge MDCPFC.
MDCPFC could provide two control degrees of freedom of
power flow control for the system. IV. FUTURE TERNDS OF DEVELOPMENT OF MDCPFCS
C. Simulation verification In this section, key technical challenges and future trends
In order to verify the feasibility of the topology, a 4- of development of MDCPFCs are discussed from three aspects:
terminal DC grid model is built in MATLAB/Simulink, where topology design, modelling and control, and systematic
the triple-line capacitor-based full bridge MDCPFC is optimized operation strategy.
embedded. The system configuration is the same as shown in A. Formation of topology family
Fig.6. Reference directions of electrical quantities are also
given in Fig.6. System parameters are shown in Table I. The topology design serves as the cornerstone for the
application of MDCPFCs. Currently, DC grids are expected to
TABLE I PARAMETERS OF THE 4-TERMINAL DC GRID have a significant share in future power systems at all stages
FOR SIMULATION from electricity generation to consumption. Therefore, from the
application-driven design perspective, there is an urgent need
VSCi 1 2 3 4
to form a topology family of MDCPFCs which cover a wide
P/MW 300 120 200 - range of voltage ratings. However, at present, the majority of
V/kV - - - 200 existed literatures are dedicated to the design of simple switch-
Line i 1 2 3 4 5
mode topologies, whose scalability towards high-voltage
applications is not sufficiently ideal. To boost the voltage
R/Ω 2 1.5 2 1 1 ratings of MDCPFCs, it is necessary to introduce high-voltage
L/mH 2 1.5 2 1 1 topology techniques such as the clamped multi-level technique,
the modular multi-level techniques.
As for the 4-terminal DC grid without the installation of Meanwhile, as a device connected in series with the DC
MDCPFC, the power flow of each line at steady state is shown line, the topology of DCPFC must ensure high reliability,
in Table II. In the simulation, MDCPFC is put into operation at which is primarily reflected in two aspects: Firstly, the
t=1s. Refence values are set for currents of Line 1 and Line 2 topology should be capable of sustaining high DC transmission
as I1=1.2kA and I1=1.3kA respectively. At t=2s, a step change currents over an extended period and should also withstand the
is introduced to the system, where the output power of VSC3 is high transient currents caused by faults for short durations. To
jumped from 200 MW to 240 MW. enhance the reliability of topology in this aspect, parallel
TABLE II POWER FLOW OF THE SYSTEM WITHOUT MDCPFC
connection of modules or the introduction of interleaving
technology could be considered. Second, the topology of
Line i 1 2 3 4 5 MDCPFC is supposed to possess the capability to cut DC
I/kA 1.056 1.123 0.891 -0.428 -0.1 faults. Given that MDCPFC is connected in series with the DC
line, its system wiring method is analogous to that of a DC
circuit breaker. Therefore, by integrating the functions of
Simulation waveforms are shown in Fig. 7. As can be seen,
power flow control and fault protection, the operational
the capacitor-based full-bridge MDCPFC could track reference
reliability of the power flow controller can be further enhanced.
values with zero steady-state error. After the step change is
introduced into the system, currents of Line 1 and Line 2 could B. High-performance dynamic control design
maintain their reference values due to the control of MDCPFC. As a typical multi-input multi-output (MIMO) system, the
However, since the current of Line 3 is passively determined, it control of a multi-line DC power flow controller (MDCPFC) is
will vary to a new steady-state value. inherently complex. The power flows between lines are
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dynamically coupled, exhibiting intricate dynamic behaviors. ACKNOWLEDGMENT
Therefore, it is necessary to design a decoupled control method This work is supported by the Science and Technology
to improve the dynamic performance of MDCPFC. So far, few Project of State Grid Power Company Limited (Research on
research has focused on this issue. What is more, since the the significant impact of potentially disruptive technologies on
MDCPFC is supposed to operate flexibly between multiple the mature form of new power systems) (Project No. 1400-
working conditions, there is an emerging need to develop a 202255271A-2-0-XG, Contract No.
high-performance control strategy to realize seamless transition SGSHDK00HZJS2200482).
between these conditions.
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