Shared-Inductor Based Modular Interline DC Power
Flow Controller with Bi-Directional Regulation
Capability
2023 IEEE 18th Conference on Industrial Electronics and Applications (ICIEA) | 979-8-3503-1220-1/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICIEA58696.2023.10241542
Hongyi ZHANG1, Miao ZHU1*, Pengfeng LIN1, Xiaohong WANG2, Linping WU2
1
School of Eletronic Information and Electrical Engineering, Shanghai Jiao Tong University, 200240, China
2
State Grid Electric Power Research Institute, Nari Group Corporation, 211000, China
*E-mail: miaozhu@sjtu.edu.cn
Abstract—Interline DC power flow controller (IDCPFC) has
emerged as a promising solution to introducing extra control
degrees of freedom of power flow in meshed DC grids. So far,
although several topologies of IDCPFC are able to control bi-
directional power flow, their ripple characteristic or efficiency is
often compromised. In order to mitigate this challenge, in this
paper, a shared-inductor based modular IDCPFC is proposed. In
this topology, only one inductor is utilized to achieve the
controllability over bi-directional power flow, which is by virtue
of a symmetrical design of switching devices. Steady-state analysis
and the respective control design are addressed for the proposed
topology. Furthermore, the ripple analysis is conducted where an
analytical expression of DC current ripples induced by the
topology is derived. Finally, the feasibility of the proposed shared-
inductor based modular IDCPFC and its control scheme are
verified via both simulations and experiments.
Keywords—dc power flow controller, HVDC grid, power
inversion, multi-port dc-dc conversion
I. INTRODUCTION
With the rapid development of renewable power generation,
the DC transmission technique has been selected for its higher
efficiency and enhanced operational flexibility. By means of DC
transmissions, the consumption of intermittent and
indeterminate renewable power generations can be realized in a
more elegant way[1]. As of now, several high-voltage DC
transmission (HVDC) projects have already been implemented,
and there are numerous similar projects that are ongoing for
further investigations of HVDC developments.
The accurate power flow control of transmission lines is
critical for the planning and operations of meshed HVDC grids.
In this case of multiple voltage source converter enabled sources
interlinked, the power flow across the entire transmission
network is naturally formed[2-3]. However, an unbalanced
distribution of power flow is more than likely to happen, where
some lines are prone to be overloaded while others may only be
loaded in a minor fraction of their transmission capacity. In this
sense, DC Power Flow Controller (DCPFC) is highly in need
and has been introduced as an auxiliary equipment for DC grids
This work was supported by Joint Fund of the National Natural Science
Foundation of China (U2166216).
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to bring extra control degrees of freedom of power flow
regulations[4-5].
Over the past decade, academia has been dedicated to the
topology studies of DCPFCs. There are mainly four types of
DCPFCs, i.e., variable-resistor type (VR)[4], series adjustable
voltage source type (SAV)[5-6], DC-transformer type (DCT)[7]
and interline DC power flow controller (IDCPFC)[8],[14].
Compared to its counterparts, IDCPFC possesses the advantages
of higher level of circuit integration, the elimination of external
power supply, and the potential of modular scalability. It is vital
to mention that IDCPFC can be serially connected with
transmission lines, the power flow controller only needs to
withstand a small portion of nominal system voltage. Therefore,
its volume and cost can be considerably reduced, which makes
it increasingly popular in various actual applications.
Furthermore, a modular design methodology for the IDCPFC is
proposed in [12] The design endows modular expansion of the
IDCPFC so as to accommodate more complicated system
configurations. Control over bi-directional power flow is
essential for DCPFCs to increase its operational range and
flexibility, especially in case of contingencies (e.g., the outage
of VSC, the DC grid fault, etc.) where the power flow of a
certain line would be arbitrarily inversed. In topologies proposed
in pre-existed literatures, generally, this function can be realized
via two methods. The first approach is to adopt a capacitor-based
topology which serially connects the transmission line via an H-
bridge. Due to the symmetrical structure of H-bridge, the four-
quadrant operation of IDCPFC can be realized[10],[11],[14].
However, the connection and bypass of a capacitor in a high
frequency will induce large current ripples into transmission
lines and aggravate the Electro Magnetic Interference(EMI). As
for the second method, the bi-directional regulation capability is
achieved via a coupled inductor. Either of its two windings is
activated for power conversion to realize a certain direction of
the power flow[8],[12]. However, the introduction of a magnetic
coupling component is somehow undesired due to its
compromise in efficiency caused by its leakage inductance.
To address the above issue, in this paper, an improved design
is implemented, where a single inductor is adopted to form a
shared-inductor based modular IDCPFC. Meanwhile, in order to
preserve its bi-directional regulation capability, switching
components are designed in a symmetrical way. The topology,
365
 along with its control scheme, is detailed in this paper. Both
simulations and experiments are carried out to verify its
feasibility.
II. TOPOLOGICAL ANALYSIS
A. System configuration
Fig. 1shows an illustrative system of a four-terminal meshed
DC grid. Relevant parameters are shown in Table I. VSC1,
VSC2, VSC3 work under constant power control mode, while
VSC4 functions as a slack bus, whose voltage is regulated as
constant. A three-line shared-inductor based IDCPFC is
embedded within the system to facilitate[12]. In Fig. 1: Three
capacitors (equivalent voltage sources) are serially connected to
transmission lines in order to adjust the power flow, while the
shared-inductor functions as an energy buffer for power transfer
between capacitors. The reference directions of currents and Fig. 2. Topology of shared-inductor based modular IDCPFC. (a) Topological
voltages in the system are denoted as in Fig. 1. architecture. (b) Detailed topology for each unit.

Fig. 2 deliberates the topology of the proposed shared- B. Operation Principle

inductor based modular IDCPFC. As seen in Fig. 2(b), the
interface adopts the symmetrical design of switches, which can The proposed shared-inductor based modular IDCPFC
be divided into the positive group and the negative group. The adopts multi-mode operation principle. Specifically, a single
mechanical switch Si is utilized for bypassing the IDCPFC. If Si switching period is composed of multiple sub-modes. For each
is turned on, the interface will be shorted from the line and the sub-mode, a specific interface is selected to exchange power
power flow control of the very line is deactivated. with the energy buffer. During a single switching period, the
power can be transferred between the energy buffer and all the
interfaces in a sequential way. To better understand the principle,
two scenarios are analyzed as follows.
z Scenario 1: Control over positive power flow
This scenario shows how positive line flow can be managed
by the proposed topology. In Fig. 3, I14, I24 and I34 are positive
as referred to the reference current directions |I14| and |I24|
decrease and |I34| increases. Three sub-modes in this scenario are
expounded as follows:
Mode 1 (see Fig. 3(a)): Interface 1 is activated to exchange
power with the energy buffer L. In order for |I14| to decrease, a
positive Vc1 is inserted in Line 14 to realize a reduced voltage
drop. The energy is transferred from C1 to L to discharge Line
Fig. 1. Configuration of a four-terminal DC grid embedd with DCPFC 14. In this regard, Qa1 and Qd1, which correspond to the positive
group, are switched on to form power path.
TABLE I. PARAMETERS OF THE FOUR-TERMIANL DC GRID
Mode 2 (see Fig. 3(b)): Interface 2 is activated to exchange
Line Parameters power with the energy buffer L. In order for |I24| to decrease, a
positive Vc2 is inserted in Line 24 to reduce voltage drop, and
Line 14 Line 24 Line 34 Line 12 Line 23
power is transferred from C2 to L to charge the inductor. In this
Length/km 200 150 200 100 100 scenario, Qa2 and Qd2, which corresponds to the positive group,
:
Resistance/: 2 1.5 2 1 1 are switched on to form the power path.
Inductance/mH 2 1.5 2 1 1 Mode 3 (see Fig. 3(c)): Interface 3 is activated to exchange
VSC Parameters power with the energy buffer L. In order for |I34| to increase, a
negative Vc3 is inserted in Line 34 to realize an increased voltage
VSC 1 VSC 2 VSC 3 VSC 4 drop, and the charged power in L obtained from C1 and C2 is
Power/MW 300 120 200 - released to C3. In this regard, Qa3 and Qd3, which corresponds to
Voltage/kV - - - 200 the positive group, are switched on to form the power path.

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 Fig. 3. Cicuit diagram in Scenario 1. (a) Mode 1. (b) Mode 2. (c) Mode 3.

Fig. 4. Cicuit diagram in Scenario 2. (a) Mode 1. (b) Mode 2. (c) Mode 3.

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 z Scenario 2: Control over inversed power flow D. Current ripple analysis
In this scenario, I24 and I34 are positive, whereas I14 is
controlled to be negative. |I24| decreases and |I14| increases. Three
sub-modes are expounded as follows:
Mode 1 (see Fig. 4(a)): Interface 1 is activated to exchange
power with the energy buffer L. In order for |I14| to inverse, a
positive Vc1 is inserted in Line 14 to realize an inversed voltage
drop, and the line flow is discharging C1. In order to effectuate
the power balance of C1, in mode 1, the power is transferred
from L to C1 to charge the capacitor. In this regard, Qb1 and Qc1,
which corresponds to the negative group, is switched on.
Since Mode 2 and Mode 3 resemble to those in Scenario 1,
detailed analysis is omitted here for simplicity, only with their
circuit diagrams shown in Fig. 4(b) and Fig. 4(c) respectively.
C. Steady-state analysis and control scheme design
The steady-state equations of the system are as follows:

­ 2§ 1 1 1 · § V2 V4  Vc1 ·
° P1 V1 ¨   ¸  V1 ¨  ¸
° R
© 14 R 24 R34 ¹ © R12 R14 ¹
°
° P V 2 §¨ 1  1 ·¸  V §¨ V1  V4  Vc 2 ·¸
° 2 2
© R24 R23 ¹
2
© R12 R14 ¹
° Fig. 6. Current ripple analysis of Line 14 under Scenario 1. (a) Equivalent
° 2§ 1 1 · § V2 V4  Vc 3 · circuit model. (b) Waveforms of electrical quantities.
° P3 V3 ¨ R  R ¸  V3 ¨ R  R ¸
° © 23 34 ¹ © 23 34 ¹ The charging and discharging process of interfaces will
°° inherently induce current ripples into transmission lines. In this
®Vc1 I14  Vc 2 I 24  Vc 3 I 34 0   section, analytical expressions of these ripples are studied.
° Scenario 1 is chosen as an example, where 'I14 is derived. The
° equivalent circuit model of Line 14 is shown in Fig. 6(a).
°I V1  Vc1  V4
° 14 Referring to the operational principle, in mode 1, C1 is
R14
° discharged by the inductor L, where its voltage drops. In mode
° V2  Vc 2  V4 2 and 3, C1 is charged by the power flow of Line 14 to attain a
° I 24 R24
balanced ampere-second product, which can be shown in Fig.
° 6(b). Therefore, the voltage ripple of C1 can be calculated as:
° V3  Vc 3  V4
° I 34 t  D1Ts
°̄ R34
'Vc1
'Q ³
t
(i14  iL )dt ( I 24  I 34 ) I14Ts
 
There are 7 equations and 9 variables (V1, V2, V3, Vc1, Vc2, Vc3, C1 C1 C1 ( I14  I 24  I 34 )
I14, I24, I34) existing in (1). In order to solely determine the
operating point of the system, two variables need to be specified
by . in controller design, I14 and I24 are configured to track their The voltage ripple of C1 will affect the voltage across L14.
respective references and the tracking error are regulated via PI As shown in Fig. 6(b), when vC1 is under its mean value, which
controllers, as is shown in Fig. 5. Signals of duty cycles further is when vL14 is greater than its mean value (zero), the inductor
go through a set of logical operations in order to generate three will be magnetized, and its current will increase, vice versa.
complementary PWM signals, driving corresponding switches. Therefore, the volt-second product of 'vc1 is equivalent to the
increased flux of L14, leading to the expression of 'I14:

1 1 1
˜ Ts ˜ 'Vc1
'\ 2 2 2 ( I 24  I 34 ) I14Ts2
'I14 | 
L14 L14 8 L14 C1 ( I14  I 24  I 34 )

TABLE II. PARAMETERS OF SHARED-INDUCTOR BASED DCPFC

C1/mF C2/mF C3/mF L/mH fs/kHz

1 1 1 1 2
Fig. 5. Control scheme of shared-inductor based DCPFC.

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 A simple verification of the derived expression is carried out. B. Scenario 2
Parameters of the shared-inductor based modular IDCPFC are In scenario 2, reference values of I14 and I24 are set as -500A
shown in Table II. In this case, I14 and I24 are set as 700A and and 1500A. At t=2s, the DCPFC is put into operation.
800A. Solve the steady-state operating point of the system Waveforms of the simulation are shown in Fig. 8. As illustrated
according to (1), substitute (3) with solved values, and we have: in Fig. 8(a), I14 is reversed to track its reference value accurately
'VC1=539.99A'I14=33.75A. This is basically consistent with after a transient state of about 0.15s. This verifies the ability of
the simulation results shown in Fig. 6. The current ripples of the shared-inductor based modular IDCPFC to control over
other transmissions lines can be calculated in the same method. inversed power flow. Accordingly, Vc1, Vc2 and Vc3 are
To be added, it can be verified from the analysis that, the current established in capacitors C1, C2 and C3, as shown in Fig. 8(b),
ripples induced by the proposed topology is relatively small forming equivalent voltage sources in their inserted lines.
(about 4% of line current), which is one of its major advantages.
III. SIMULATION VERIFICATION
In order to verify the feasibility of the proposed shared-
inductor based modular IDCPFC, simulations are built.
Parameters of the system are shown in TABLE I and II.
A. Scenario 1
In scenario 1, reference values for I14 are I24 are set to be 700A
and 800A. The DCPFC is put into operation at t=2s. At t=2.5s,
a step change of PVSC1, from 300MW to 150MW is to check the
dynamic performance of the topology. Simulation waveforms
are shown in Fig. 7. As demonstrated in Fig. 7(a), at t=2s, with
the control of the DCPFC, I14 and I24 are kept under reference
values after a transient state of approximately 0.3s. I34 reaches a
new steady-state value, which is passively determined by the
topology and parameters of the entire system. After the step
change of PVSC1, I14 and I24 can still maintain their reference
values after a short transient state. Therefore, the designed
topology along with its control scheme can track the reference
value of power flow with zero steady-state error in an ideal Fig. 8. Simulation waveforms under Scenario 2. (a) Line Currents. (b)
dynamic performance. As is illustrated in Fig. 7(b), at t=2s, Capacitor voltages. (c) VSC voltages. (d) Driving sginals.
voltages are established in the three capacitors, formulating
equivalent voltage sources in their inserted lines. Vc1 and Vc2 are IV. EXPERIMENTAL VERIFICATION
positive, while Vc3 is negative, which abides by the theoretical A donwscaled prototype is built in the laboratory to verfity
analysis in Section II. Driving signals for mode 1, mode 2, and the feasibility of the shared-inductor based modular IDCPFC .
mode 3 are plotted in Fig. 7(d). The three complementary sub- The electrical diagram of the test prototype is the same as the
modes together form one entire switching cycle. one in Fig. 1. Its parameters are shown in Table III.

TABLE III. PARAMETERS OF THE TEST PROTOTYPE

Line Parameters
Line 14 Line 24 Line 34 Line 12 Line 23
:
Resistance/: 1 1 1 1 1
Inductance/mH 1 1 1 1 1
VSC Parameters
VSC 1 VSC 2 VSC 3 VSC 4
Injected
4.5 2.5 5 -
Current /A
Voltage/V - - - 25
DCPFC Parameters
C1/uF C2/uF C3/uF L/mH fs/kHz
880 880 880 0.1 10

In the experiment, the scenario is set to reduce the power

Fig. 7. Simulation waveforms under Scenario 1. (a) Line Currents. (b) flow of Line 14 and Line 34 while increasing the power flow of
Capacitor voltage. (c) VSC voltage. (d) Driving sginals. Line 24. Therefore, positve voltages should be inserted in Line

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369
 14 and Line 34 to reduce the voltage drop, and a negative
voltage is to be inserted in Line 24.
Fig. 9. Simulation waveforms. (a) Line currents (b) Cpacitor voltages. (c)
Driving signals and the inductor current.
Experimental waveforms are shown in Fig. 9. Fig. 9(a)
depicts the waveforms of line currents, showing that the
proposed DCPFC can correctly respond to the power flow
control requirements. Fig. 9(b) shows the waveforms of
capacitor voltages. As illustrated in Fig. 9(b), the voltages of C1
and C3 are controlled to be positive, while that of capacitor C2
is negative, which is consistent with theoretical analyses. Fig.
9(c) presents the driving signals and current of the shared
inductor. When Interface 1 is activated, capacitor C1 charges
the shared inductor, causing its current to rise. When Interface
2 is activated, the shared inductor charges capacitor C2,
resulting in a decrease in its current. When Interface 3 is
activated, capacitor C3 charges the shared inductor, causing the
inductor current to rise. The waveforms fall in line with
theoretical analyses, verifing the correctness and feasibility of
the proposed topology and its control schemes.
V. CONCLUSION
In this paper, a shared-inductor based modular IDCPFC is
proposed. Key Conclusions are summarized as follows:
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z The symmetrical design of switching devices make it
capable of controlling over inversed power flow using only
one shared-inductor.
z The proposed topology holds the merit of low current
ripples induced into transmission lines.
z Simulations and the experiment have validated the
effectiveness of this topology under different operating
conditions. This proposed topology is capable of
addressing various power flow scenarios in a flexible way.
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