module clk_check_1 (

input string name,

input stable_clock,
real exp_freq,
input stable_lock_signal
);

// Variable declarations
logic flag = 0;
string hdl_path = $psprintf("%m.");

// Always block to monitor stable_lock_signal

always @(posedge stable_lock_signal) begin
flag = 1;
`uvm_info("CLK_CHECK_SAMPLE", $sformatf("HDL_PATH = %s exp_freq = %d ,flag=%d
Harshit CLK ALL CHECKING STARTED", hdl_path, exp_freq, flag), UVM_LOW);
end
int diff;
real t0;
real t1;
real tp;
real freq, tON, tOFF;
bit print_info_once = 0;
bit print_err_once = 0;
bit print_err_once_tON = 0;
bit print_tol_once = 0;
bit print_tol_once_tON = 0;

// Fork block for different checks

always @(posedge stable_lock_signal) begin
fork
// Frequency Checking block
begin
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK FREQ CHECKING
STARTED HDL_PATH = %s", name, hdl_path), UVM_LOW);
forever begin
// Frequency checking logic
real t0, t1, tp, freq, tON, tOFF;
int diff;

@ (posedge stable_clock) t0 = $realtime;

@ (negedge stable_clock) tp = $realtime;
@ (posedge stable_clock) t1 = $realtime;

freq = 1.0e6 / (t1 - t0);

tON = tp - t0;
tOFF = t1 - tp;

diff = int'(exp_freq - freq);

if (diff != 0) begin
if (freq inside {[0.99*exp_freq : 1.01*exp_freq]}) begin
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit frequency
matches expected value with 1 percent tolerance. Actual = %0d MHz, Expected = %0d
MHz, HDL_PATH = %s", name, freq, exp_freq, hdl_path), UVM_LOW);
end
else begin
if(!($test$plusargs("NO_POR_CHKS_NOW"))) begin
`uvm_error("FREQ_CHECK", $sformatf("%0s Harshit
frequency doesn't match expected value. Actual = %7.4f MHz, Expected = %7.4f MHz,
HDL_PATH = %s", name, freq, exp_freq, hdl_path));
end
end
end
else begin
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit frequency
exactly matches with expected value. Actual = %0d MHz, Expected = %0d MHz, HDL_PATH
= %s", name, freq, exp_freq, hdl_path), UVM_LOW);
end

if (tON != tOFF) begin

if (tON inside {[0.99*tOFF : 1.01*tOFF]}) begin
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit ton and toff
value matching with 1 percent tolerance tON = %0t, tOFF = %0t @ start = %0t,
end = %0t,HDL_PATH = %s", name, tON, tOFF, t0, t1, hdl_path), UVM_LOW);
end
else begin
if(!($test$plusargs("NO_POR_CHKS_NOW"))) begin
`uvm_error("FREQ_CHECK", $sformatf("%0s Harshit ton and
toff value not matching tON = %0t, tOFF = %0t @ start = %0t, end = %0t,HDL_PATH
= %s", name, tON, tOFF, t0, t1, hdl_path));
end
end
end
end
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK FREQ CHECKING ENDED
HDL_PATH = %s ", name, hdl_path), UVM_LOW);
end

// X/Z Propagation Checking block

begin
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK X/Z PROP CHECKING
STARTED", name), UVM_LOW);
forever begin
// X/Z propagation checking logic
@(posedge stable_clock);
if ($isunknown(stable_clock))
`uvm_error("FREQ_CHECK", $sformatf("%0s Harshit Clk has X/Z
running @ %0t", name, $realtime));
end
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK X/Z PROP CHECKING
ENDED", name), UVM_LOW);
end

// Toggling Checking block

begin
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK TOGGLING CHECKING
STARTED", name), UVM_LOW);
forever begin
// Toggling checking logic
@(posedge stable_clock);
@(posedge stable_clock);
if($time > 250) begin
`uvm_error("FREQ_CHECK", $sformatf("%0s Harshit Clk Stuck at
0/1, NOT toggling @ %0t", name, $realtime));
disable;
end
end
 `uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK TOGGLING CHECKING
ENDED", name), UVM_LOW);
end

// Delay Checking block

begin
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK DELAY CHECKING
STARTED", name), UVM_LOW);
forever begin
// Delay checking logic
@(posedge stable_clock);
if($time > 250) begin
`uvm_error("FREQ_CHECK", $sformatf("%0s Harshit Clk Delayed @
%0t", name, $realtime));
disable;
end
end
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK DELAY CHECKING
ENDED", name), UVM_LOW);
end
join_any
disable fork;
end

// Rest of the module...

endmodule