module clk_check_1 (

input string name,

input stable_clock,
real exp_freq,
input stable_lock_signal
);

logic flag = 0;
string hdl_path = $psprintf("%m.");

always @(posedge stable_lock_signal) begin

flag = 1;
`uvm_info("CLK_CHECK_SAMPLE", $sformatf("HDL_PATH = %s exp_freq =
%d ,flag=%d Harshit CLK ALL CHECKING STARTED", hdl_path, exp_freq, flag), UVM_LOW);
end

int diff;
real t0;
real t1;
real tp;
real freq, tON, tOFF;
bit print_info_once = 0;
bit print_err_once = 0;
bit print_err_once_tON = 0;
bit print_tol_once = 0;
bit print_tol_once_tON = 0;

initial begin
$display("%s CLK ALL CHECKING STARTED", name);

integer freq_check_cycles = 0;
integer xz_prop_check_cycles = 0;
integer toggling_check_cycles = 0;
integer delay_check_cycles = 0;

parameter MAX_FREQ_CHECK_CYCLES = 1000;

parameter MAX_XZ_PROP_CHECK_CYCLES = 500;
parameter MAX_TOGGLING_CHECK_CYCLES = 200;
parameter MAX_DELAY_CHECK_CYCLES = 300;

fork
@(posedge stable_lock_signal) begin
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK FREQ CHECKING
STARTED HDL_PATH = %s", name, hdl_path), UVM_LOW);
forever begin
@ (posedge stable_clock) t0 = $realtime;
@ (negedge stable_clock) tp = $realtime;
@ (posedge stable_clock) t1 = $realtime;
freq = 1.0e6 / (t1 - t0);
tON = tp - t0;
tOFF = t1 - tp;

diff = int'(exp_freq - freq);

if (diff != 0) begin
if ((freq inside {[0.99*exp_freq : 1.01*exp_freq]})) begin
if (print_tol_once == 0) begin
`uvm_info("FREQ_CHECK", $psprintf("%0s Harshit
frequency matches expected value with 1 percent tolerance. Actual = %0d MHz,
Expected = %0d MHz, HDL_PATH = %s", name, freq, exp_freq,hdl_path), UVM_LOW);
print_tol_once = 1;
end
end
else begin
if (print_err_once == 0) begin
if (!($test$plusargs("NO_POR_CHKS_NOW"))) begin
`uvm_error("FREQ_CHECK", $psprintf("%0s Harshit
frequency doesn't match expected value. Actual = %7.4f MHz, Expected = %7.4f MHz,
HDL_PATH = %s", name, freq, exp_freq,hdl_path));
print_err_once = 1;
end
end
end
end
else begin
if (print_info_once == 0) begin
`uvm_info("FREQ_CHECK", $psprintf("%0s Harshit
frequency exactly matches with expected value. Actual = %0d MHz, Expected = %0d
MHz, HDL_PATH = %s", name, freq, exp_freq,hdl_path), UVM_LOW);
print_info_once = 1;
end
end

tON = tp - t0;
tOFF = t1 - tp;

if ((tON) != (tOFF)) begin

if ((tON inside {[0.99*tOFF : 1.01*tOFF]})) begin
if (print_tol_once_tON == 0) begin
`uvm_info("FREQ_CHECK", $psprintf("%0s Harshit ton
and toff value matching with 1 percent tolerance tON = %0t, tOFF = %0t @ start =
%0t, end = %0t,HDL_PATH = %s", name, tON, tOFF, t0, t1,hdl_path), UVM_LOW);
print_tol_once_tON = 1;
end
end
else begin
if (!($test$plusargs("NO_POR_CHKS_NOW"))) begin
if (print_err_once_tON == 0) begin
`uvm_error("FREQ_CHECK", $sformatf("%0s Harshit
ton and toff value not matching tON = %0t, tOFF = %0t @ start = %0t, end =
%0t,HDL_PATH = %s", name, tON, tOFF, t0, t1,hdl_path));
print_err_once_tON = 1;
end
end
end
end

freq_check_cycles = freq_check_cycles + 1;
if (freq_check_cycles == MAX_FREQ_CHECK_CYCLES) begin
// Exit condition met, break out of the frequency checking
loop
break;
end
end
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK FREQ CHECKING
ENDED HDL_PATH = %s ", name, hdl_path), UVM_LOW);
end
 begin
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK X/Z PROP
CHECKING STARTED", name), UVM_LOW);
forever begin
@(stable_clock)
if ($isunknown(stable_clock))
`uvm_error("FREQ_CHECK", $sformatf("%0s Harshit Clk has X/Z
running @ %0t", name, $realtime));

xz_prop_check_cycles = xz_prop_check_cycles + 1;
if (xz_prop_check_cycles == MAX_XZ_PROP_CHECK_CYCLES) begin
// Exit condition met, break out of the X/Z propagation
checking loop
break;
end
end
`uvm_info("FREQ_CHECK", $psprintf("%0s Harshit CLK X/Z PROP
CHECKING ENDED", name), UVM_LOW);
end

begin
fork : TOGGLING
begin
@(stable_clock);
@(stable_clock);
@(stable_clock);
@(stable_clock);
@(stable_clock);
end
begin
#250ns;
`uvm_error("FREQ_CHECK", $sformatf("%0s Harshit Clk Stuck
at 0/1, NOT toggling @ %0t", name, $realtime));
end
join_any
disable fork;
if ($test$plusargs("POR_CLK_CHKS_LONGRUN")) begin
#30us; // Extra 90us
end
#1us;

toggling_check_cycles = toggling_check_cycles + 1;
if (toggling_check_cycles == MAX_TOGGLING_CHECK_CYCLES) begin
// Exit condition met, break out of the toggling checking loop
break;
end
end

begin
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK DELAY CHECKING
STARTED", name), UVM_LOW);
// Clock delay checking code here...
`uvm_info("FREQ_CHECK", $sformatf("%0s Harshit CLK DELAY CHECKING
ENDED", name), UVM_LOW);

delay_check_cycles = delay_check_cycles + 1;
if (delay_check_cycles == MAX_DELAY_CHECK_CYCLES) begin
// Exit condition met, break out of the delay checking loop
break;
 end
end
join_any
disable fork;

$display("%s Harshit CLK ALL CHECKING ENDED", name);

end
endmodule