Synopsys EDA Tool Flow for

Back-End Digital IC Design

Professor: Sci.D., Professor

Vazgen Melikyan

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Synopsys EDA Tool Flow for Back-End Digital IC Design
Lecture - 1
1 Developed By: Vazgen Melikyan
Course Overview

 Back End EDA Tools

 2 lectures
 Floorplanning and Partitioning
 4 lectures
 Placement
 4 lectures
 Clock-tree Synthesis (CTS)
 3 lectures
 Routing
 2 lectures
 Physical Verification
 4 lectures
 Static timing analysis (STA)
 4 lectures

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Developed By: Vazgen Melikyan
2
Back End EDA Tools

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Digital Design Flow
Specification

System Level Design

System Level

High-level synthesis (HLS)

RTL

Logic Synthesis

Gate

Physical Synthesis
Back End
Layout

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Back End Design Flow

Physical Design Gate level Timing

design constraints Logical and
Constraints
physical libraries

Floorplanning

Placement

Clock tree synthesis

Routing
Physical Verification
Signoff
Static Timing Analysis
Completed
design

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Developed By: Vazgen Melikyan
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Floorplanning

 During the floorplanning step the overall cell is

defined, including: cell size, supply network, etc.

Floorplan Power Planning

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Placement

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Clock Tree Synthesis (CTS)

FF FF FF FF FF FF

FF FF FF FF FF FF

FF FF FF FF FF FF
Clock

FF FF FF FF FF FF

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Clock Tree Synthesis (CTS) (2)
FF FF FF FF FF FF

FF FF FF FF FF FF

FF FF FF FF FF FF
Clock

FF FF FF FF FF FF

 A buffer tree is built to balance the loads and minimize the skew

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Developed By: Vazgen Melikyan
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Routing

 Routing creates physical connections to all clock

and signal pins through metal interconnects

• Routed paths must meet setup and

hold timing, max cap/trans, power
and clock skew requirements
• Metal traces must meet physical
DRC requirements

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Physical Verification: Design Rule
Check

Layout

DRC Output Summary files

(IC Validator) (Error database)

DRC Rules

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Physical Verification: Layout Versus
Schematic

Layout

LVS Output Summary files

(IC Validator) (Error database)

LVS Rules

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Static Timing Analysis (STA)
Net Parasitics (.spef,
.sdf)
AIR_GAP_SMAX=2.0 }
Layout Parasitic Extraction DIELECTRIC d1 {
THICKNESS=0.725 ER=3.9 }
CONDUCTOR poly {
THICKNESS=0.125 WMIN=0.3
SMIN=0.3 RPSQ=10.0 }
DIELECTRIC d0 {
THICKNESS=0.375 ER=3.9 }
VIA sub_tie { FROM=SUBSTRATE
Netlist (.v) TO=m1 AREA=0.25 RPV=5 }
VIA poly_cont { FROM=poly
TO=m1 AREA=0.25 RPV=4 }
module CONTROL …. VIA via { FROM=m1 TO=m2
input A, B, C; AREA=0.36 RPV=4 }

output reg X;
….. Static Timing Analysis
and2 U1 (.I0(B), .I1(C), .Z(T1); (PrimeTime)
or2 U2 (.I0(B), .I1(C), .Z(T2);
mux2 U3 (.S(A),.I1(T1),.I2(T2),
.Z(X); Design Library
.db
Timing Report

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Parasitic Extraction

Layout Parasitic Extraction Extraction

(StarRC) deck
Parasitics
(.spef, .sdf)
AIR_GAP_SMAX=2.0 }
DIELECTRIC d1 { THICKNESS=0.725 ER=3.9 }
CONDUCTOR poly { THICKNESS=0.125 WMIN=0.3
SMIN=0.3 RPSQ=10.0 }
DIELECTRIC d0 { THICKNESS=0.375 ER=3.9 }
VIA sub_tie { FROM=SUBSTRATE TO=m1 AREA=0.25
RPV=5 }
VIA poly_cont { FROM=poly TO=m1 AREA=0.25
RPV=4 }
VIA via { FROM=m1 TO=m2 AREA=0.36 RPV=4 }

Parasitics
(.spef, .sdf)

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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Back End EDA Tools

 Physical Design (Synthesis)

 IC Compiler II

 Signoff
 IC Validator – Physical Verification
 StarRC- Parasitics extraction
 Prime Time – STA

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Synopsys EDA Tool Flow for Back-End Digital IC Design
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