synopsys_eda_tool_flow_back-end_lecture_2

Synopsys EDA Tool Flow for
Back-End Digital IC Design
Professor: Sci.D., Professor

Vazgen Melikyan
Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
Synopsys EDA Tool Flow for Back-End Digital IC Design
Lecture - 2
1 Developed By: Vazgen Melikyan
Course Overview
 Back End EDA Tools

 2 lectures
 Floorplanning and Partitioning
 4 lectures
 Placement
 4 lectures
 Clock-tree Synthesis (CTS)
 3 lectures
 Routing
 2 lectures
 Physical Verification
 4 lectures
 Static timing analysis (STA)
 4 lectures

Lecture - 2
Developed By: Vazgen Melikyan
2
Floorplanning and Partitioning

Lecture - 2
3 Developed By: Vazgen Melikyan
Floorplanning
 During the floorplanning step the overall cell

is defined, including: cell size, supply
network, etc.
Floorplan
Lecture - 2
4
Floorplanning: Aspect Ratio
 Aspect ratio is the height to width ratio of a block

 Defines the block shape
 Default aspect ratio is 1
width width
height
height

Lecture - 2
5
Floorplanning: Area Utilization
 Utilization dictates how densely user wants cells to be placed within the
block
 The remaining space is needed for ease of routing
Increasing utilization will reduce the core area

(Default Utilization is 0.7)
core_utilization 0.6 core_utilization 0.85

Lecture - 2
6
Floorplanning: Space for Power
Rings
 A fixed space is required to be available around
core for power supply rings
Core

Lecture - 2
7
Floorplanning: Pin Locations
 Pins can be spread automatically by IC Compiler around the boundary

 The exact side and/or location, layers, size for pins can be set by a designer
Pins
Core
set_individual_pin_constraints -pin_name "mypin" \

-layers {M2 M3 M4 M5} \
-width 0.28 -side 1 -offset 5

Lecture - 2
8
Floorplanning: I/O Placement
Periphery Core
(I/O) area

Lecture - 2
9
Floorplanning: Creation of Site
Rows
 Placement requires grid in which cells will be placed
 Floorplanning uses ‘unit tile’ cell to build this grid
 It is defined by a library developer and library cells are designed to be
multiple of unit tile
Creation of sites for

FF detailed placement
NOR BUF
INV
unit tile
(site)

Lecture - 2
10
Floorplanning: Required Actions
Creation of core area

for rough placement
Creation of sites for

detailed placement
Periphery
(I/O) area
Set port’s XY
coordinates

Lecture - 2
11
Floorplanning: ICC II Dialog
1. Core utilization
2. Aspect ratio 1
2

Lecture - 2
12
Floorplanning: Possibilities
Set preferable XY
location of ports
RAM
Setting XY location of IPs
Creation of routing or placement

obstruction / blockage

Lecture - 2
13
Design Planning
Design Floorplan I/O

Library Constraints constraints
Design prototyping
Analyze timing, routability

and power integrity
Detailed floorplanning

Lecture - 2
14
Cell Types
IP I/O Pad Flip Chip Bump
Ring IP
VS VS
Standard
Core
I/O Ring cells

Lecture - 2
15
I/O Cell Placement
Wire Bond Flip-Chip

Underfill IC
Dielectric
http://ffden-2.phys.uaf.edu/212_spring2005.web.dir/george_walker/uses.htm http://blog.daum.net/dourira/6824688

Lecture - 2
16
Wire Bond
Wire Bonding Example

 Most widespread
method
 IC is connected with
package pins with thin
wires
http://www.era.co.uk/case-studies/improving-the-reliability-of-chip-on-board-assembly/

Lecture - 2
17
Flip-Chip
Flip Chip Cross Section
 Modern method of I/O Underfill IC
Dielectric
connection
 IC is connected with
Solder Ball Rigid
Laminate
package using solder

balls
http://www.izm.fraunhofer.de/en/abteilungen/high_density_interconnec
twaferlevelpackaging/arbeitsgebiete/arbeitsgebiet1.html

Lecture - 2
18
Wire Bond Placement
Wire Bond
I/O driver
core area
wide
wire
route
bond
pad

Lecture - 2
19
Flip Chip Placement
IO
Driver
core area core area
wide wire pins
Bump Cells Flip Chip Driver Cells Placed bump

Overlaying the Chip around Perimeter of Chip

Lecture - 2
20
Flip-Chip Routed Example

Lecture - 2
21
Power Planning
Power straps
(in Red)
Power pads (VDD, VSS)
(VDD, VSS)
Power trunks
(VDD, VSS)
Power rings
(VDD, VSS)

Lecture - 2
22
Power Grid Planning
 Steps in Power Grid Planning

 Determine the number of power pads
 Determine which metal layers will be used for
power routing
 Define the width of the top-level power bus
 Determine the structure for block and macro-
level power routing
 Power Network Analysis (PNA)
Lecture - 2
23
Top-level Power Network
 User can specify

 Number of straps: Min,
max
 Width of straps: Min,
Max
 Width of ring
 Layers

Lecture - 2
24
Block Level Power Network
IP1 IP2

Lecture - 2
25
Power Network Synthesis
 PNS
 Power network creation
 Definition of the topology
 Calculation of the width and the number of power straps to
meet IR constraints
 Performance of detail connections and placement of vias
 Validation with PNA
 PNS automates these tasks

Lecture - 2
26
Power Network Synthesis Flow
Defining power nets
Logically connect PG nets
Specifying PNS constraints
Running PNS
Preroute the PG nets
Verify the PG nets
Checking IR-drop/EM maps
OK?
Committing power plan
done

Lecture - 2
27
Logically Connect PG Nets
Defining power nets

 Logically Connect the
P/G Nets
Running PNS
 Specify global PG net
name
Verify the PG nets
 Specify instance port
Checking IR-drop/EM maps names that will be
connected to this net
OK?
 Specify instances to be
Committing power plan connected
done

Lecture - 2
28
Logically Connecting Cells
 Define global power and ground

P/G assignments
signals
 Make ‘logical’ connections between VDD
VDD
VDD
tie hi/lo ports and global P/G netlist
VSS
VSS VSS
P/G connections
VDD
VSS

Lecture - 2
29
Specifying PNS Constraints
Defining power nets

 Ring and Straps Power Network
Specifying PNS constraints Constraints
 Generate rings?
Running PNS
 Layer selection
Preroute the PG nets  Ring width
 Ring spacing
Verify the PG nets  Ring offset from region
 Strap extension
 Block Rings Power Network
Constraints
OK?
 Which plan groups, voltage areas,
or hard macros?
Committing power plan  Layer constraints
 Spacing
done
Lecture - 2
30
Specifying PNS Constraints (2)
Defining power nets

 Global Power Network Constraints
Specifying PNS constraints  Stacked vias
 Routing over hard macros or plan
Running PNS groups
 Track usage optimization
Preroute the PG nets  Floating segment removal
 Same width sizing
Verify the PG nets
 Straps Power Network Constraints
Checking IR-drop/EM maps  Direction
 Density
 By strap number
OK?  By pitch
 Width
 Spacing
done

Lecture - 2
31
Running PNS
Defining power nets

 Specify settings for
the following:
Running PNS
 Power and ground nets
 Power budget
Verify the PG nets
 Supply voltage
 Target IR-drop
OK?  PG pad information
 Power Information
done  Run PNS

Lecture - 2
32
PNS Preview and Final Commit
Preview Power Plan and IR-drop Map
Run PNS
Commit Power Plan

Lecture - 2
33
Preroute the PG Nets
Defining power nets

 Creates connections to
Specifying PNS constraints main PG ports on all cells
Running PNS  First step is to legalize
Preroute the PG nets placement for all cells
Verify the PG nets  Options:
 Select cells
 Select nets
OK?  Select layers
done

Lecture - 2
34
Standard cell PG preroute
VDD VDD VDD
DFFSR1
AOI221
JKFF
VSS VSS VSS
VDD VDD
MUX21 VDD VDD VDD
NOR3
XOR2
BUF2B
NA21
VSS VSS VSS VSS VSS

Lecture - 2
35
Standard cell PG preroute
VDD VDD VDD
DFFSR1
AOI221
JKFF
VSS VSS VSS
VDD VDD
MUX21 VDD VDD VDD
NOR3
XOR2
BUF2B
NA21
VSS VSS VSS VSS VSS

Lecture - 2
36
Verify the PG Nets
Defining power nets

 Final step in PNS
Specifying PNS constraints  Check that the PG connections
Running PNS
are correct
 To standard cells
 To macros
Verify the PG nets  To pads
 For macro and pad PGs
 Can verify that all PG pins are
OK?
connected
 Can verify that at least one PG
pin is connected
 Can ignore
done

Lecture - 2
37
PNA IR-drop Analysis
Defining power nets

Power Network Analysis
During Floorplanning
Running PNS
Verify the PG nets
OK?
Committing power plan Metal 5 and Metal 4 power trunks only, no straps
IR-drop = 378mv
done

Lecture - 2
38
Committing Power Plan
VDD VDD VDD
DFFSR1
AOI221
JKFF
VSS VSS VSS
VDD VDD
MUX21 VDD VDD VDD
NOR3
XOR2
BUF2B
NA21
VSS VSS VSS VSS VSS
VDD VSS

Lecture - 2
39
Committing Power Plan
VDD VDD VDD
DFFSR1
AOI221
JKFF
VSS VSS VSS
VDD VDD
MUX21 VDD VDD VDD
NOR3
XOR2
BUF2B
NA21
VSS VSS VSS VSS VSS
VDD VSS

Lecture - 2
40
Soft Macros
 Soft macros is a Plan Group, isolated from logic hierarchy, which

belongs to a certain physical hierarchy but lacks certain shape.
 Soft macros will allow better Global Optimization.
 Final assembly may solve shape, pin, and global timing problems
Soft macros before parameterization Soft macros after parameterization

Lecture - 2
41
Layout Examples
Intel Core i7-3960X

Lecture - 2
42
Macros and Standard Cells
Placement Challenges
RAM 1 RAM 2 RAM 3
RAM 4 RAM 5 RAM 6
Avoid
constrictive
channels
Avoid many pins
in the narrow RAM 8
RAM 7
channel. Rotate Use blockage
for pin to improve pin
accessibility accessibility

Lecture - 2
43
Macros and Standard Cells
RAMS out of
Single
the way in the
large
RAM corner
partition
Standard cells area
RAM
Large
RAM
routing
channels
PLL MY_SUB_BLOCK
Pins away
from corners

Lecture - 2
44
Macro Placement Constraints
 Basic constraints
 Alignment of macros by edges
 Grouping macros in a way that for standard cells rectangular area
should be left as much as possible
 Alignment of macros with core boundary
 Goals of Macros Placement
 Routability
 Timing
 Wire length
 Area for standard cells

Lecture - 2
45
Placement Blockages
 Placement blockages are areas that leaf cells must avoid

during placement and legalization, including overlapping
any part of the placement blockage
Placement
Blockage

Lecture - 2
46
Global Placement Blockages
RAM1 RAM2 RAM3
Hard blockage
always created on
all four sides
Soft blockage
created only for the
channels between RAM4 RAM5
the macros or
between the macro
and the core
boundary

Lecture - 2
47
Macro Keepout Margin (Padding)
 A keepout margin is a region around the boundary of fixed macros in

the design in which no other cells are placed.
Pins are on
left and
Keepout margin right
Keepout margin
Top
Fixed Cells RAM5

Left Right
Bottom

Lecture - 2
48
Routing Blockage (Route Guide)
 Routing blockage – areas where routing is not allowed
(75,95)
Routing
blockage RAM4
(20,20)

Lecture - 2
49
Placing and Optimizing the Design:
Relative Macro Placement
Minimum width is macro limited:
Starting outline and Maintains relative Smallest possible width
macro locations macro placement - no overlaps
Sees edges in adjacent macro rows:

Starting outline and Maintains relative Smallest possible width
macro locations macro locations - no overlaps

Lecture - 2
50
Relative Placement is Flexible
 Relative Placement Is Flexible Relative Placement Control

 Always tries to keep relative Relative placement of fixed macros is a
placement of macros hard requirement
 For fixed macros

 For un-fixed macros
 May be able to achieve better
sizing if some macros can
move
Unfixed macros can move, if necessary
 We assume original locations
are desirable
 Not recommended to allow all
macros to move

Lecture - 2
51
Controlling Space Between Macros
 Controlling Space Recommended Spacing Control

Between Macros Existing spacing that is equal to or
smaller than sliver size is maintained
 Sliver size is set in
microns
 Honors keepout margin
settings Non-overlapping keepout margin canno
 Set on reference or overlap after size reduction
instance, all sides or
specific sides
 Like a halo around
macro
Lecture - 2
52
Relative Placement of IOs
Full Chip:
Starting outline and IO pad Maintains relative placement Smallest possible height – no
locations IO pad overlaps
Rectangular or rectilinear blocks:

Starting outline and IO pin Maintains relative pin Smallest possible
locations locations

Lecture - 2
53
Placing Optimizing Physical
Datapath (PD)
Free Placement Physical Datapath

Lecture - 2
54

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Synopsys EDA Tool Flow for

Back-End Digital IC Design

Professor: Sci.D., Professor

Synopsys University Courseware

 Back End EDA Tools

Synopsys University Courseware

Synopsys University Courseware

 During the floorplanning step the overall cell

 Aspect ratio is the height to width ratio of a block

Synopsys University Courseware

Increasing utilization will reduce the core area

core_utilization 0.6 core_utilization 0.85

Synopsys University Courseware

Synopsys University Courseware

 Pins can be spread automatically by IC Compiler around the boundary

set_individual_pin_constraints -pin_name "mypin" \

Synopsys University Courseware

Synopsys University Courseware

Creation of sites for

Synopsys University Courseware

Creation of core area

Creation of sites for

Synopsys University Courseware

Synopsys University Courseware

Setting XY location of IPs

Creation of routing or placement

Synopsys University Courseware

Design Floorplan I/O

Analyze timing, routability

Synopsys University Courseware

IP I/O Pad Flip Chip Bump

Synopsys University Courseware

Wire Bond Flip-Chip

Synopsys University Courseware

Wire Bonding Example

Synopsys University Courseware

package using solder

Synopsys University Courseware

Synopsys University Courseware

core area core area

wide wire pins

Bump Cells Flip Chip Driver Cells Placed bump

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

 Steps in Power Grid Planning

 User can specify

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

Logically connect PG nets

Specifying PNS constraints

Preroute the PG nets

Verify the PG nets

Checking IR-drop/EM maps

Committing power plan

Synopsys University Courseware

Logically connect PG nets

Synopsys University Courseware