PREV UP NEXT

XSCHEM - CIRCUIT SCHEMATIC EDITOR

FOR VLSI - ASIC - PCB DESIGN

Submitted to F-si.org - Free Silicon Foundation Conference 2022

• Hierarchical representation of circuits.

• Generate circuit netlists for SPICE, Verilog, VHDL,
tEDAx (pcb-rnd interchange format)
• Components can be primitives, behavioral blocks, subcircuit blocks.
• True mixed mode circuit description: Analog, Behavioral, Transistor-
level, Gate-level.
• Designed from ground-up to handle Very large designs as efficiently
as possible, no scripting language is used for intensive
computations.
• Core is written in C89 for max portability, GUI and scripting language
implemented with Tcl-Tk.
• XSCHEM understands vector instances and bus notations like
DATA[15:0,31:16].
• TCL API for forward / backward annotation to / from 3rd party EDA
software.
• Works on most unix-likes.
• Native Windows port available.
• Xschem is the schematic editor used for the skywater PDK open
source analog hardware design.

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT

XSCHEM SCHEMATIC EDITOR PRESENTATION OUTLINE

• Why Xschem?
• Xschem History
• Xschem is / is not
• Feature List
• Hierarchy, symbols and
component instances
• Instance attributes and
parametrized subcircuits
• Simulation
• Wave viewing
• Skywater 130nm PDK integration
• Roadmap
• Conclusions
• Contacts

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT

WHY XSCHEM?

Have been a Cadence Virtuoso user for many years, in different companies.
• Long startup time
• Creating new components way too complicated (you need a CDF, ask your CAD support and file
a ticket).
• Memory Hog, keeps growing until all Virtual memory exhausted, then crash.
• One process handles all design windows. Process crashes, all work on all windows lost.
• Netlist extraction and many other functions are slow since all is implemented in skill language.
• Proprietary file format.

Most Open source schematic editors are not for VLSI

• Gschem (or its fork, lepton-schematic) and Kicad's eeschema, can not handle complex VLSI
designs.
• Xcircuit is one of the very few Open Source tools i found that is good for VLSI design. Has very
accurate graphics rendering, allows arbitrary rotations, uses postscript as schematic save
format. This makes scripted generation of schematic files a bit complex. Certainly one of the
best tools from graphic quality standpoint.

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT

XSCHEM HISTORY

• Started in 1998 as a hobby home project when i was working at STM.

• First versions were developed on Solaris Sparc, then on linux.
• Subversion local repository in 2007.
• Sourceforge svn repository in December 2016.
• Development boost happened in 2018 to present:
1. More graphic primitives (polygons, arcs, circles).
2. Automatic 'configure' configuration.
3. standard location of installed files / docs / rcfiles.
4. Lot of improvements and bug fixes.
• Some small startups start using Xschem in 2019, getting feedbacks, bug reports and requests
for improvements.
• Succesfully simulated designs (even complete systems) on NGSPICE, Xyce, HSPICE, Icarus
Verilog, ModelSim, GHDL. Generic interface to simulation engines added in 2019.
• Bindings for Gtkwave, Gaw (Gwave improvement) for waveforms in 2019.
• Adding bindings to other simulators (free/proprietary) and viewers is extremely simple (edit
simrc file).
• In 2020 created github repository, Joined the Skywater Free and Open source Silicon Initiative
(FOSSi), created symbol libraries for the 130nm process node, get lot of user feedback.

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT
XSCHEM IS
• A Free OSS small project, follows the UNIX
KISS philosophy. ~65K SLOC.
• A Digital / Analog / Mixed mode circuit
schematic editor.
• A hierarchical design tool: wrap (parametric)
sub-blocks into symbols and use them
multiple times.
• Has syntax for vector nets (bus notation)
like DATA[7:0], WORD[7:0,15:8] as well as
vector instance placements like Xinv[7:0], to
handle repetitive components.
• Fast: Performance is important. Editing a
schematic with 100K instances MUST not be
a problem. Netlist extraction must be instant
(<500ms) on small to medium designs.
• Xschem knows the connectivity. Netlist
build is embedded in the core.
• Verilog, VHDL, Spice, tEDAx netlist
backends. Adding another backend is not
difficult.
• Intensive and time consuming computations
all done in pure C.
• Tcl-tk used for GUI and scripting language.
Direct Xlib drawing.
Xschem Documentation
XSCHEM IS NOT
• Huge. Depends on a very limited number of
libraries. 63k SLOC
• Using binary formats for storing data.
Everything is ASCII and in documented
format.
• A Gtk or Qt project. Xschem will not bitrot
over time due to changed library APIs.
• A layout tool, although the graphical engine
was designed to support layout as well.
• A circuit simulator.
• Easy to use: there is a learning curve.
• A memory hog: XSCHEM with a medium
design loaded requires 54M virtual memory,
24M resident set. A full chip design can be
handled with a 1GB RAM system and low
end processor.
• A C++, C99, C11 project: all code is ANSI-C
C89, works on old Solaris, Irix machines,
compiles on 32bit, 64 bit and on armhf.
Copyright(C) 1998 - 2022 Stefan Schippers
 PREV UP NEXT

FEATURE LIST

FEATURE DESCRIPTION FEATURE DESCRIPTION

File format for Bus notation for nets and
Yes.
schematic and symbol ASCII components.
files. All UNIX systems with Tcl and X11,
Portability.
Each handled by 1 XSCHEM instance. A crash Windows with VS and Active-Tcl.
Multiple schematic of one instance does not crash all others. Extremely fast, Complex system
/symbol windows. Tabbed and multi-windows interface has been with 59 sub blocks netlisted in
added. Netlisting performance.
VHDL in < 1 second on a Linux
Clipboard copy / paste laptop.
(ctrl-c ctrl-v), across Yes, between different windows too. Primitive component creation
hierarchy levels. Works out of the box with very
with arbitrary code for
simple property strings.
Memory footprint. Very low, data purged on hierarchy traversal. VHDL/SPICE/verilog.
Undo buffer. Yes. Single / split file netlisting. Yes, any supported netlist formats.
Scripting language / Mixed mode netlisting, symbol
Tcl / Tk. Yes, in split netlisting mode.
GUI toolkit based.
SPICE, Verilog, VHDL, tEDAx, embedded into Automatic symbol creation from
Schematic netlisting. Yes.
XSCHEM and using Awk post processors. schematic and vice-versa.
Wire snap to pin. Yes. Property editing on multiple
Instance pin auto instances, changing only
Yes. Yes.
wiring. modified token/value pairs, even
Net auto-router engine. No. on different symbol sets.
Parametric symbols Yes. Yes, net names can be changed to
Pin creation from schematic pins and vice-versa, function to
nets. automatically generate pins for nets
that are undriven.

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT

HIERARCHY, SYMBOLS AND COMPONENT INSTANCES

• Describe complex circuits by using symbols.

• A component placed in a schematic is an
instance of a symbol.
• A symbol hides the underlying circuit, showing
only the interface (pins) to the parent
schematic.
• Repetitive blocks (registers, amplifiers,
comparators, logic gates, ...) can be used
multiple times in a design.
• When creating a netlist the circuit is traversed
all the way from the top level down to the
lowest level leaves.
• At the lowest level we have primitive symbols,
these have attributes telling the netlister how
to describe them.
• A symbol definition is stored in a .sym file
(inv.sym), while the circuit implementation is in
a .sch file (inv.sch).

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT

SYMBOL CREATION

1. Start XSCHEM with a new

symbol name
(mynand.sym).
2. Draw symbol shape.
3. Add pins.
4. Set global properties.
5. Add some text
Symbol name, instance
name.
6. If symbol is a subcircuit
draw schematic
(mynand.sch).

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT

INSTANCE ATTRIBUTES, PARAMETRIZED SUBCIRCUITS

• A symbol may have any sort of parameters

that can be specified when placing an instance
of it in a schematic.
• Example: inverter with variable W/L
dimensions for p and n transistors.
• Parameters enable circuit reuse (think of
variable width registers, variable size RAMs,
variable strength buffers).
• Symbol may show parameters using the
@param notation, @param is then expanded
with the actual 'param' value set as attribute in
the component instance.
• Attributes may be used in multiple level
hierarchies. No single-level restriction.

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

 PREV UP NEXT

LOCAL CUSTOM CELLS: SCHEMATIC USED AS COMPONENT INSTANCE

• It is possible to place a schematic instead of a symbol into a parent

schematic
• Example on the right shows one instance of a bus keeper that itself
instantiates 2 parametric inverters, all using the schematic views.
• Of course as with symbols it is possible to have parametric schematics,
as an example the sizing of the feedback inverter is different from the
forward inverter. This is all done with instance attributes.

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT

SIMULATION

• In XSCHEM a schematic usually contains all the details

needed to run a simulation.
• When a schematic is correctly drawn just generate the
netlist pushing the Netlist button, and then start simulation
by pressing the Simulate button.
• XSCHEM has bindings to waveform viewers as well as
simulators. Press the Waves button after simulation is
completed to view the results.
XSCHEM XSCHEM
TOOL TYPE TOOL TYPE
SUPPORT SUPPORT

ngspice Simulator Works Proprietary

Hspice Works
Simulator
Parallel
Xyce Works
Simulator Proprietary
Finesim Works
Simulator
Icarus Verilog Simulator Works
Gtkwave Viewer Works
GHDL Simulator Works
Gaw Viewer Works
Proprietary
ModelSim Works
Simulator Proprietary
Waveview Works
Viewer
Proprietary
NcSim Works
Simulator

• With proper netlisting attributes on leaf cells the same

design can be simulated unchanged in Spice, Verilog,
VHDL.
• DC Operating point information back-annotation into the
schematic is possible.

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT

SIMULATION - 2

• External tools are configured via a

'simconf' widget. This needs to be
tuned for the host system. Config
is then saved in a simrc file, which
can be edited directly to add /
remove / configure tools.
• Tools can be run in the
background. Xschem optionally
shows exit status, stderr and
stdout messages from batch jobs
without blocking.
• Multiple Simulator / viewing tools
can be configured for each
simulation mode (spice, VHDL,
Verilog), a radio button sets the
active tool.
• Additional tools (logic synthesis,
etc) can easily be added in the
future.
• No information about external
tools is hard coded in Xschem.

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

 PREV UP NEXT

SIMULATION - 3

Example of a complex system simulation with

NGSPICE

• 8KW (16KB) Synchronous ROM Macro cell, 16 I/O, 1KB data

fully programmed in array.
• 14287 MOS transistors, 16 sense amplifiers, row / column
decoders, timing circuits, 5.3ns access time.
• 16 read accesses simulated in 12 minutes with ngspice.
• ldq[15:0] data output matches expected data from ROM array.

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

 PREV UP NEXT

WAVE VIEWING

Spice simulation data can be viewed directly in

Xschem.

• Overlayed and stacked analog / digital waveforms, cross-

probing of nodes into graph
• Simple RPN notation for entering waveform expressions
(average, power, derivative,...)
• Cursors for time / delay / amplitude measurements
• Graph configuration (zoom, waveforms, colors) is saved
with the schematic

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT

SKYWATER 130nm PDK INTEGRATION

Use Xschem for (Analog) chip design and

interoperate with other open source EDA
tools using the Skywater open source 130nm
process PDK

• Develop symbols for primitive devices (MOS,

capacitors, resistors, BJTs, ...).
• Primitive silicon devices take geometrical parameters
and produce a valid simulation-ready spice (Ngspice,
Xyce) netlist.
• Develop symbols for the digital standard cell library.

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT

ROADMAP

• Contribute to a Free silicon EDA ecosystem.

• Integration (Forward, Backward annotation) with backend
tools (Klayout, ngspice, Xyce).
• Input filters for more schematic formats as done for
GSCHEM / Lepton-Eda (see right picture).
• Native Windows port improvements.
• Allow changing simulator (Ngspice / Xyce) with minimal / no
schematic changes.
• Mixed mode simulation: Leverage Xyce / Icarus Verilog
(XyceCInterface-VPI)?
• Documentation improvements considering problems /
issues encountered by new users.
• Other improvements driven by users. Your feedback is
Welcome!

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP NEXT

CONCLUSIONS

• A Free and Open Source (GNU GPL

v2) solution for VLSI and complex
circuit descriptions.
• Designed to be efficient, fast and
small.
• Complex mixed mode (digital /
analog) systems have been
succesfully created and simulated.
• True hierarchic schematic
description, with parametric
components.
• Full support for vector buses, bus
rippers and vector instances.
• ASCII output file format, simple and
documented.

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers

PREV UP

THANK YOU FOR WATCHING

Contacts and links

• My email: stefan 'dot' schippers 'at' gmail 'dot' com

• Download Stable XSCHEM releases: http://repo.hu/projects/xschem/releases
• Development source files: https://github.com/StefanSchippers/xschem
• XSCHEM manual and docs: "https://xschem.sourceforge.io/stefan/index.html

Xschem Documentation Copyright(C) 1998 - 2022 Stefan Schippers