03 PLL02

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TRAINERS Since 23 Years

PLL AS FREQUENCY MULTIPLIER AND SYNTHESIZER TRAINER MODEL-PLL02

More than 2000 Trainers

SIGMA TRAINERS AHMEDABAD (INDIA)

INTRODUCTION
This board has been designed with a view to provide practical &s experimental knowledge of Frequency Synthesizer.

SPECIFICATIONS
1. 2. 3. 4. 5. 6. 7. 8. 9. 1 0. 1 1. The complete circuit is printed on a single P.C.B. All parts are soldered on single pin tag for easy replacement. Explanation, Observation, Alignment and adjustment of Internal and external controls is possible due to Single P.C.B. Easy identification of different parts is possible at a glance. Easy measurement of voltages and observation of waveforms at any point. Test Points are provided on P.C.B. A manual having practical detail is provided with the board. Built-in Power supply: + 9VDC at 200mA IC Regulated & short circuit protected Built in 1KHz TTL signal for frequency input. IC 4046 and 4017 - 1 No each. Power requirement Standard Accessories : 230V, 50Hz AC. : 1. A manual having practical details. 2. Patch Cords.

CHAPTER-1 THEORY OF FREQUENCY SYNTHESIS

EXPERIMENT 1
AIM: To observe Frequency Synthesis phenomenon. PROCEDURE:(See connection diagram CN1) 1. 2. 3. 4. 5. 6. 7. 8. Connect output of pulse generator at input terminals. Connect CRO Channel 1 at input terminals. Also connect frequency counter at these terminals. Connect CRO Channel 2 at output terminals. Also connect another frequency counter at these terminals. Connect 1KHz output of Pulse generator to input of synthesizer circuit by jumper link. Connect connector wire between Keep 1KHz-9KHz socket to X1 position. Observe input and output waveforms on CRO. Also observe input and output frequencies on frequency counters. Both input and output frequencies will be 1KHz frequency. Now change position of jumper link to X2 position. The output frequency will be double of input frequency. Similarly observe other multiple frequencies at output from 1KHz to 9KHz by changing jumper link switch position to C3 to X9 positions. In this circuit divide by 10 counter is used in PLL feedback path. Hence X1 to X9 outputs are available. We can use any series of devider circuits in feedback path of PLL to get any output frequency. This explains frequency synthesis phenomenon. ************

TEST POINT WAVEFORM


T1.: Input Frequency (1KHz)

1KHz

T2.: Output Frequency X 2 = (2KHz)

X 2 = 2KHz

T3.: Output Frequency X 3 = (3KHz)

X 3 = 3KHz

Connection diagram CN1

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