EVL62XX-MAIN,EVL62XX-PLUG

Data brief

Evaluation kit environment for L62xx family of dual brush DC and stepper motor
drivers based on STM32 Nucleo

Features
• Voltage range from 8 V to 52 V
• Phase current up to 2.8 A r.m.s (with L6205, L6206, L6207 and L6208 devices)
or 1.4 A r.m.s. (with L6225, L6226, L6227 and L6228 devices)
• Easy interchangeable plug-in boards for quick evaluation of the whole stepper
and brush DC drivers of the L62xx family
• Programmable high-side overcurrent protection (L6206 and L6226 devices)
• Programmable OFF-time of the PWM current control (L6207, L6227, L6208 and
L6228 devices)
• Compatible with Arduino UNO R3 connector
• RoHS compliant

Description
The EVL62XX-MAIN is an expansion board that can host small EVL62XX-PLUG
plug-in boards for quick and easy evaluation of brush DC and stepper motor drivers
of the L62xx family.
These boards provide an affordable and easy-to-use solution to drive dual brush
DC and bipolar stepper motors in association with the evaluation software STSPIN
Studio.
The EVL62XX-MAIN is compatible with the Arduino UNO R3 connector.

Product status link

EVL62XX-MAIN
EVL6205-PLUG
EVL6206-PLUG
EVL6207-PLUG
EVL6208-PLUG
EVL6225-PLUG
EVL6226-PLUG
EVL6227-PLUG
EVL6228-PLUG

DB4485 - Rev 1 - July 2021 www.st.com

For further information contact your local STMicroelectronics sales office.
 EVL62XX-MAIN,EVL62XX-PLUG
Schematic diagrams

1 Schematic diagrams

Figure 1. EVL62XX-MAIN
FID1

FID40RD_80RD
FID2

VDD VDD

ST FID40RD_80RD
FID3
R31 R32

2
VS

2
Q2 Q1
NUCLEO & LOGO NP FDV302P NP FDV302P FID40RD_80RD

2
FAULTA 1 FAULTB
FOR EVALUATION PURPOSE ONLY 1
D5
ROHS COMPLIANT 2002/95/IEC & LOGO Gre e n

3
R15

1
R16
330R 330R
R17
10k

2
D7 D6
CN6 Re d Re d TP 1 GND
VDD
1

1
2
3 Vin
4 TP 2
VS
5
6
7
J1
8
1 2
CON-1x8 3 4 8-50V
S TRIP 254P -F-8 5 6 C2 + C1
OUT2A
7 8
OUT2A GND 1 Vin
100UF TP 3
9 10 100NF 63V
CN8 2 GND
11 12
PA0_TIM2_CH1 13 14
1 IN1A CN3
R18 0R PA1_TIM2_CH2 RES ET 15 16 R7 10K FAULTA
2 IN2A
R19 0R PA4_ADC1_4 VREFA R3 17 18 P ROGCLA 100K R1 CN1
3 ADC-4_S ENS EB ENA
R20 0R 4.7K 19 20
4 R21 0R
VREFB PB0_TIM3_CH3 21 22
5 C9 C3 1
R4 C5
IN1A IN1A/CLOCK 23 24 IN2A/CW _CCW
IN2A 5.6NF
OUT2A A-
6 NP 25 26 RCA
68NF ADC-6_S ENS EA 2
2.2K 27 28 OUT1A A+
CON-1x6 29 30
OUT1A OUT1A 3
S TRIP 254P -F-6 31 32 OUT1B B+
33 34 PROGCLA
4
35 36 C7
OUT2B B-
CN9 37 38 R9
820P F
39 40 200K
1 RCA
2 BS E-020-01-F-D-A-TR
3 ENA PA10
R23 0R FAULTA PB3 CN2
4
5
R22 0R IN2B PB5_TIM3_CH2 RS 805-1699 2.1/2.5mm
6
R24 0R IN1B PB4_TIM3_CH1 1
7
R25 0R VREFA PB10_TIM2_CH3 2 Vin
R26 0R 3
8
GND
CON-1x8
VS
CN5

2
YELLOW YELLOW YELLOW YELLOW
RES ET PA9 D1 D2 D3 D4
1 R27 0R J2
2
3 FAULTB PB6 2 1
R28 0R ENB PA7
4

1
R29 0R 4 3
5 ADC-6_S ENS EA PA6_ADC1_6 6 5
R30 0R OUT2B OUT2B
6 8 7 R11 R12 R13 R14
7 C10 10 9
8 10K 10K 10K 10K
NP 12 11
9 14 13
10 16 15 R8 10K FAULTB
VREFB R5 18 17 P ROGCLB 100K R2
CON-1x10 4.7K 20 19 ENB
22 21 C4
R6 C11 IN1B/CONTROL 24 23 IN2B/HALF_FULL
IN1B IN2B 5.6NF
ADC-4_S ENS EB 26 25 RCB
2.2K 68NF 28 27
OUT1B 30 29 OUT1B PROGCLB
32 31
34 33
36 35 C8
38 37 R10 820P F
40 39 200K
RCB
BS E-020-01-F-D-A-TR

Figure 2. EVL6205-PLUG
VS

C3 220NF J1
1 2
3 4
D1 BAR43 5 6
2 1 OUT2A OUT2A
7 8
9 10
11 12
3

13 14
15 16 ENA
C1 17 18
10NF 19 20
21 22
R19 IN1A 23 24 IN2A
S ENS EA 25 26
100R
VS 27 28
OUT1A 29 30 OUT1A
31 32
ENA 33 34
C2100NF 35 36
ENB U1
17

19
4
2

IN1A L6205P D 37 38
TP 4 39 40
IN2A OUT1ATP 5
VS A
VBOOT

VS B
VCP

5 9
1

ENA OUT1A OUT1B

16 12 BTE-020-01-F-D-A-TR
1

J5 ENB OUT1B 3
OUT2A OUT2A
J8 J7 6 18
7 IN1A OUT2B
2

IN2A TP 7 OUT2B TP 6
14 8
2

IN1B IN1B S ENS EA

IN2B 15 13
VS
GND
GND
GND
GND
GND
1

IN2B S ENS EB R3 R4
J6 R1 R2 0R NP
0R NP J2
1
10
11
20
21

2 1
2

S ENS EA
4 3
C5 OUT2B 6 5 OUT2B
C4 8 7
NP NP 10 9
12 11
14 13
S ENS EB 16 15 ENB
18 17
20 19
22 21
IN1B 24 23 IN2B
S ENS EB 26 25
28 27
OUT1B 30 29 OUT1B
FID1 32 31
34 33
36 35
FID40RD_80RD 38 37
40 39
FID2
BTE-020-01-F-D-A-TR

FID40RD_80RD
FID3

FID40RD_80RD

DB4485 - Rev 1 page 2/8

 EVL62XX-MAIN,EVL62XX-PLUG
Schematic diagrams

Figure 3. EVL6206-PLUG
VS

J1
1 2
3 4
OUT2A 5 6 OUT2A
7 8
C3 220NF 9 10
11 12
13 14
D1 BAR43 ENA_RS T ENA_RS T
R9 NP 15 16 R5 0R
2 1 VREFA_P CA R8 VREFA_P CA FID1
NP 17 18 R6 0R
19 20
21 22

3
IN1A_CLOCK 23 24 IN2A_C/CCW
FID40RD_80RD
S ENS EA 25 26 R7 NP OCDA_RCA
C1 FID2
27 28
10NF OUT1A 29 30 OUT1A
31 32
33 34 FID40RD_80RD
R19
35 36
100R 37 38 FID3
VS 39 40
C6
NP FID40RD_80RD
ENA_RS T C2 BTE-020-01-F-D-A-TR
ENB_ENABLE

30

33
100NF

4
IN1A_CLOCK FID4
IN2A_C/CCW

VS A
VS B
VBOOT

VCP
8 TP 4
1

29 ENA 15 OUT1A
1

J5 ENB OUT1A FID40RD_80RD

1
1

TP 5
J8 J7 10 5 OUT2A VS
J 10 J9 IN1A OUT2A FID5
11 TP 6
2

IN1B_VREFB 26 IN2A 22 OUT1B J2

2

IN1B OUT1B
2
2

IN2B_HALFFULL 27 U1 TP 7 2 1
1

IN2B L6206P D 32 OUT2B FID40RD_80RD

OUT2B 4 3
VREFA_P CA 9
J6 PROGCLA OUT2B 6 5 OUT2B FID6
VREFB_CTRL_P CB28 12
PROGCLB SENSEA 8 7
10 9
2

OCDA_RCA 13 25 R4
OCDA SENSEB 12 11
OCDB_RCB 24 R3 FID40RD_80RD
OCDB NP 14 13
R2 0R IN1B_VREFB R15 NP 16 15 ENB_ENABLE

NC#14
NC#16
NC#17
NC#20
NC#21
NC#23
NC#31
NC#34
NC#35
NC#37
NC#2 R1 VREFB_CTRL_P CB R14 NP VREFB_CTRL_P CB
NC#3
NC#6
NP S ENS EA 18 17 R10 0R
GND
GND
GND
GND

0R 20 19
IN1B_VREFB R13 0R 22 21
VREFA_P CA VREFB_CTRL_P CB IN1B_VREFB S ENS EB
C5 VREFB_CTRL_P CB R12 NP 24 23 IN2B_HALFFULL
1
18
19
36

2
3
6
14
16
17
20
21
23
31
34
35
37
NP S ENS EB 26 25 R11 NP OCDB_RCB
R16 R17 R18 C4 28 27
NP NP NP NP OUT1B 30 29 OUT1B
32 31
34 33
36 35
38 37
40 39

BTE-020-01-F-D-A-TR

Figure 4. EVL6207-PLUG
VS

J1
1 2
3 4
OUT2A 5 6 OUT2A
C3 220NF 7 8
9 10
11 12
D1 BAR43 13 14
2 1 ENA_RS T R9 NP 15 16 R5 0R ENA_RS T
VREFA_P CA R8 0R 17 18 R6 NP VREFA_P CA
19 20
3

21 22
IN1A_CLOCK 23 24 IN2A_C/CCW
C1 S ENS EA 25 26 R7 0R OCDA_RCA
10NF 27 28
OUT1A 29 30 OUT1A
31 32
R19 33 34
100R 35 36
37 38
VS 39 40
C6
NP
ENA_RS T C2 BTE-020-01-F-D-A-TR
ENB_ENABLE
30

33

100NF
7

IN1A_CLOCK
IN2A_C/CCW
VS A
VS B
VBOOT

VCP

8 TP 4
1

29 ENA 15 OUT1A
1

J5 ENB OUT1A
1
1

TP 5
J8 J7 10 5 OUT2A VS
J 10 J9 IN1A OUT2A TP 6
11
2

IN1B_VREFB 26 IN2A 22 OUT1B J2 FID1

2

IN1B OUT1B
2
2

IN2B_HALFFULL 27 U1 TP 7 2 1
1

IN2B L6207P D 32 OUT2B

OUT2B 4 3
J6 VREFA_P CA 9
VREFA OUT2B 6 5 OUT2B FID40RD_80RD
VREFB_CTRL_P CB28 12
VREFB SENSEA 8 7
10 9 FID2
2

OCDA_RCA 13 25 R4
RCA SENSEB 12 11
OCDB_RCB 24 R3 0R
RCB 14 13
R2 0R2 IN1B_VREFB R15 NP 16 15 ENB_ENABLE
FID40RD_80RD
NC#14
NC#16
NC#17
NC#20
NC#21
NC#23
NC#31
NC#34
NC#35
NC#37

R1 VREFB_CTRL_P CB R14 0R VREFB_CTRL_P CB

NC#2
NC#3
NC#6

0R S ENS EA 18 17 R10 NP
GND
GND
GND
GND

0R2 20 19 FID3
IN1B_VREFB R13 0R 22 21
VREFA_P CA VREFB_CTRL_P CB IN1B_VREFB S ENS EB
C5 VREFB_CTRL_P CB R12 NP 24 23 IN2B_HALFFULL
1
18
19
36

2
3
6
14
16
17
20
21
23
31
34
35
37

NP S ENS EB 26 25 R11 0R OCDB_RCB

R16 R18 FID40RD_80RD
R17 C4 28 27
NP NP NP NP OUT1B 30 29 OUT1B
32 31
34 33
36 35
38 37
40 39

BTE-020-01-F-D-A-TR

Figure 5. EVL6208-PLUG
VS

J1
1 2
3 4
OUT2A 5 6 OUT2A
C3 220NF 7 8
9 10
11 12
D1 BAR43 FID1
13 14
2 1 ENA_RS T ENA_RS T
R9 0R 15 16 R5 NP
VREFA_P CA R8 0R 17 18 R6 NP VREFA_P CA
19 20 FID40RD_80RD
3

21 22
IN1A_CLOCK 23 24 IN2A_C/CCW FID2
C1 OCDA_RCA
S ENS EA 25 26 R7 0R
10NF 27 28
OUT1A 29 30 OUT1A FID40RD_80RD
31 32
33 34 FID3
R19
100R 35 36
37 38
VS 39 40 FID40RD_80RD
C6
100NF
ENA_RS T C2 BTE-020-01-F-D-A-TR
ENB_ENABLE
30

33

100NF
7

IN1A_CLOCK
IN2A_C/CCW
VS A
VS B
VBOOT

VCP

8 TP 4
1

29 RESET 15 OUT1A
1

J5 EN OUT1A
1
1

TP 5
J8 J7 10 5 OUT2A VS
J 10 J9 CLOCK OUT2A TP 6
11
2

VREFB_CTRL_P CB 28 CW/CCW 22 OUT1B J2

2

CONTROL OUT1B
2
2

IN2B_HALFFULL 27 U1 TP 7 2 1
1

HALF/FULL L6208P D 32 OUT2B

OUT2B 4 3
J6 VREFA_P CA 9
VREFA OUT2B 6 5 OUT2B
IN1B_VREFB 26 12
VREFB SENSEA 8 7
10 9
2

OCDA_RCA 13 25 R4
RCA SENSEB 12 11
OCDB_RCB 24 R3 0R
RCB 14 13
R2 0R2 IN1B_VREFB R15 0R 16 15 ENB_ENABLE
NC#14
NC#16
NC#17
NC#20
NC#21
NC#23
NC#31
NC#34
NC#35
NC#37

R1 VREFB_CTRL_P CB R14 NP VREFB_CTRL_P CB

NC#2
NC#3
NC#6

0R S ENS EA 18 17 R10 NP
GND
GND
GND
GND

0R2 20 19
IN1B_VREFB R13 NP 22 21
VREFA_P CA VREFB_CTRL_P CB IN1B_VREFB S ENS EB
C5 VREFB_CTRL_P CB R12 0R 24 23 IN2B_HALFFULL
1
18
19
36

2
3
6
14
16
17
20
21
23
31
34
35
37

NP S ENS EB 26 25 R11 0R OCDB_RCB

R16 R17 R18 C4 28 27
NP NP NP NP OUT1B 30 29 OUT1B
32 31
34 33
36 35
38 37
40 39

BTE-020-01-F-D-A-TR

DB4485 - Rev 1 page 3/8

 EVL62XX-MAIN,EVL62XX-PLUG
Schematic diagrams

Figure 6. EVL6225-PLUG
VS

C3 220NF J1
1 2
3 4
D1 BAR43 5 6
2 1 OUT2A OUT2A
7 8
9 10
11 12

3
13 14
15 16 ENA
C1 17 18
10NF 19 20
21 22
IN1A 23 24 IN2A
R19
S ENS EA 25 26
0R 27 28
VS 29 30
OUT1A OUT1A
31 32
33 34
ENA C2 35 36
ENB U1

17

19
100NF 37 38

4
2
IN1A L6225P D 39 40
IN2A TP 4
OUT1A

VS A
VBOOT

VS B
VCP
5 9 TP 5
1

16 ENA OUT1A 12 BTE-020-01-F-D-A-TR

1

J5 ENB OUT1B OUT1B

3 OUT2A
J8 J7 6 OUT2A 18
7 IN1A OUT2B TP 6
2

14 IN2A 8 TP 7OUT2B
2

IN1B IN1B S ENS EA

IN2B 15 13 VS
GND
GND
GND
GND
GND
1

IN2B S ENS EB R3 R4
J6 R1 R2 0R NP J2
0R NP
2 1
1
10
11
20
21
2

S ENS EA 4 3
OUT2B 6 5 OUT2B
C4 C5 8 7
NP NP 10 9
12 11
14 13
S ENS EB 16 15 ENB
18 17
20 19
22 21
IN1B 24 23 IN2B
S ENS EB 26 25
FID1 28 27
OUT1B 30 29 OUT1B
32 31
34 33
FID40RD_80RD 36 35
FID2 38 37
40 39

BTE-020-01-F-D-A-TR
FID40RD_80RD
FID3

FID40RD_80RD

Figure 7. EVL6226-PLUG
VS

J1
1 2
3 4
OUT2A 5 6 OUT2A
C3 220NF 7 8
9 10
11 12
D1 BAR43 13 14
2 1 ENA_RS T R9 NP 15 16 R5 0R ENA_RS T
VREFA_P CA R8 NP 17 18 R6 0R VREFA_P CA
19 20
3

21 22
IN1A_CLOCK 23 24 IN2A_C/CCW
C1 S ENS EA 25 26 R7 NP OCDA_RCA
10NF 27 28
OUT1A 29 30 OUT1A
31 32 FID1
R19 33 34
35 36
0R
37 38
VS FID40RD_80RD
39 40
C6
FID2
NP
ENA_RS T C2 BTE-020-01-F-D-A-TR
ENB_ENABLE
30

33

100NF
7

IN1A_CLOCK FID40RD_80RD
IN2A_C/CCW
VS A
VS B
VBOOT

VCP

8 TP 4 FID3
1

29 ENA 15 OUT1A
1

J5 ENB OUT1A
1
1

TP 5
J8 J7 10 5 OUT2A VS
J 10 J9 FID40RD_80RD
11 IN1A OUT2A TP 6
2

IN1B_VREFB 26 IN2A 22 OUT1B J2

2

IN1B OUT1B
2
2

IN2B_HALFFULL 27 U1 TP 7 2 1
1

IN2B L6226P D 32 OUT2B

OUT2B 4 3
J6 VREFA_P CA 9
PROGCLA OUT2B 6 5 OUT2B
VREFB_CTRL_P CB28 12
PROGCLB SENSEA 8 7
10 9
2

OCDA_RCA 13 25 R4
OCDA SENSEB 12 11
OCDB_RCB 24 R3 NP
OCDB 14 13
R2 0R IN1B_VREFB R15 NP 16 15 ENB_ENABLE
NC#14
NC#16
NC#17
NC#20
NC#21
NC#23
NC#31
NC#34
NC#35
NC#37

R1 VREFB_CTRL_P CB R14 NP VREFB_CTRL_P CB

NC#2
NC#3
NC#6

NP S ENS EA 18 17 R10 0R
GND
GND
GND
GND

0R 20 19
IN1B_VREFB R13 0R 22 21
VREFA_P CA VREFB_CTRL_P CB IN1B_VREFB S ENS EB
C5 VREFB_CTRL_P CB R12 NP 24 23 IN2B_HALFFULL
1
18
19
36

2
3
6
14
16
17
20
21
23
31
34
35
37

NP S ENS EB 26 25 R11 NP OCDB_RCB

R16 R17 R18 C4 28 27
NP NP NP NP OUT1B 30 29 OUT1B
32 31
34 33
36 35
38 37
40 39

BTE-020-01-F-D-A-TR

DB4485 - Rev 1 page 4/8

 EVL62XX-MAIN,EVL62XX-PLUG
Schematic diagrams

Figure 8. EVL6227-PLUG
VS

J1
1 2
3 4
OUT2A 5 6 OUT2A
C3 220NF 7 8
9 10
11 12
D1 BAR43 13 14
2 1 ENA_RS T R9 NP 15 16 R5 0R ENA_RS T
VREFA_P CA R8 0R 17 18 R6 NP VREFA_P CA
19 20

3
21 22
IN1A_CLOCK 23 24 IN2A_C/CCW
C1 S ENS EA 25 26 R7 0R OCDA_RCA
10NF 27 28 FID1
OUT1A 29 30 OUT1A
31 32
33 34
R19 FID40RD_80RD
35 36
0R 37 38
VS FID2
39 40
C6
NP
ENA_RS T C2 BTE-020-01-F-D-A-TR FID40RD_80RD
ENB_ENABLE

30

33
100NF

4
FID3
IN1A_CLOCK
IN2A_C/CCW

VS A
VS B
VBOOT

VCP
8 TP 4
1

29 ENA 15 OUT1A FID40RD_80RD

1

J5 ENB OUT1A
1
1

TP 5
J8 J7 10 5 OUT2A VS
J 10 J9 IN1A OUT2A TP 6
11
2

IN1B_VREFB 26 IN2A 22 OUT1B J2

2

IN1B OUT1B
2
2

IN2B_HALFFULL 27 U1 TP 7 2 1
1

IN2B L6227P D 32 OUT2B

OUT2B 4 3
J6 VREFA_P CA 9
VREFA OUT2B 6 5 OUT2B
VREFB_CTRL_P CB28 12
VREFB SENSEA 8 7
10 9
2

OCDA_RCA 13 25 R4
RCA SENSEB 12 11
OCDB_RCB 24 R3 0R
RCB 14 13
R2 0R2 IN1B_VREFB R15 NP 16 15 ENB_ENABLE

NC#14
NC#16
NC#17
NC#20
NC#21
NC#23
NC#31
NC#34
NC#35
NC#37
NC#2 R1 VREFB_CTRL_P CB R14 0R VREFB_CTRL_P CB
NC#3
NC#6
0R S ENS EA 18 17 R10 NP
GND
GND
GND
GND

0R2 20 19
IN1B_VREFB R13 0R 22 21
VREFA_P CA VREFB_CTRL_P CB IN1B_VREFB S ENS EB
C5 VREFB_CTRL_P CB R12 NP 24 23 IN2B_HALFFULL
1
18
19
36

2
3
6
14
16
17
20
21
23
31
34
35
37
NP S ENS EB 26 25 R11 0R OCDB_RCB
R16 R17 R18 C4 28 27
2.2K 2.2K NP NP OUT1B 30 29 OUT1B
32 31
34 33
36 35
38 37
40 39

BTE-020-01-F-D-A-TR

Figure 9. EVL6228-PLUG
VS

J1
1 2
3 4
C3 220NF OUT2A 5 6 OUT2A
7 8
9 10
D1 BAR43 11 12
2 1 13 14
ENA_RS T R9 0R 15 16 R5 NP ENA_RS T
VREFA_P CA R8 0R 17 18 R6 NP VREFA_P CA
19 20
3

21 22
IN1A_CLOCK 23 24 IN2A_C/CCW
C1
S ENS EA 25 26 R7 0R OCDA_RCA
10NF FID1
27 28
OUT1A 29 30 OUT1A
31 32
R19 33 34 FID40RD_80RD
0R 35 36
37 38 FID2
VS 39 40
C6
100NF FID40RD_80RD
ENA_RS T C2 BTE-020-01-F-D-A-TR
ENB_ENABLE FID3
30

33

100NF
7

IN1A_CLOCK
IN2A_C/CCW
VS A
VS B
VBOOT

VCP

8 TP 4
1

29 RESET 15 OUT1A FID40RD_80RD

1

J5 EN OUT1A
1
1

TP 5
J8 J7 10 5 OUT2A VS
J 10 J9 CLOCK OUT2A TP 6
11
2

VREFB_CTRL_P CB 28 CW/CCW 22 OUT1B J2

2

CONTROL OUT1B
2
2

IN2B_HALFFULL 27 U1 TP 7 2 1
1

HALF/FULL L6228P D 32 OUT2B

OUT2B 4 3
J6 VREFA_P CA 9
VREFA OUT2B 6 5 OUT2B
IN1B_VREFB 26 12
VREFB SENSEA 8 7
10 9
2

OCDA_RCA 13 25 R4
RCA SENSEB 12 11
OCDB_RCB 24 R3 0R
RCB 14 13
R2 0R2 IN1B_VREFB R15 0R 16 15 ENB_ENABLE
NC#14
NC#16
NC#17
NC#20
NC#21
NC#23
NC#31
NC#34
NC#35
NC#37

R1 VREFB_CTRL_P CB R14 NP VREFB_CTRL_P CB

NC#2
NC#3
NC#6

0R S ENS EA 18 17 R10 NP
GND
GND
GND
GND

0R2 20 19
IN1B_VREFB R13 NP 22 21
VREFA_P CA VREFB_CTRL_P CB IN1B_VREFB S ENS EB
C5 VREFB_CTRL_P CB R12 0R 24 23 IN2B_HALFFULL
1
18
19
36

2
3
6
14
16
17
20
21
23
31
34
35
37

NP S ENS EB 26 25 R11 0R OCDB_RCB

R16 R17 R18 C4 28 27
2.2K NP 2.2K NP OUT1B 30 29 OUT1B
32 31
34 33
36 35
38 37
40 39

BTE-020-01-F-D-A-TR

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Revision history

Table 1. Document revision history

Date Version Changes

01-Jul-2021 1 Initial release.

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Contents

Contents
1 Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

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IMPORTANT NOTICE – PLEASE READ CAREFULLY

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