2021 7th International Conference on Advanced Computing & Communication Systems (ICACCS)

Design and Analysis of 8-bit ripple Carry Adder

using nine Transistor Full Adder
2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS) | 978-1-6654-0521-8/20/$31.00 ©2021 IEEE | DOI: 10.1109/ICACCS51430.2021.9441928

'G. R. Padmini, 2O. Rajesh, 3K. Raghu, 4N. Megha Sree, 5C. Apurva, 6K saikumar,
1Dept. o f ECE, Vasavi College o f Engineering, India.
2Dept o f ECE, Vasavi College o f Engineering, India.
3ECE Department, Mahatma Gandhi Institute o f Technology, Hyderabad, India.
4Dept. o f ECE, Vasavi College o f Engineering, India.
5Dept. o f ECE, Vasavi College o f Engineering,India.
6Dept o f ECE, Koneru Lakshmaiah Education Foundation, India.
grpadminil23@rediffmail.com, orajesh@gmail.com, raghukasula@mgit.ac.in, meghsree@gmail.com,
apurvac@gmail.com, saikumarkayam4@ieee.org

Abstract—This paper uses a nine-transistor full adder model
to design an eight-bit ripple carry adder for less power
consumption. The conventional full adder design consists of 28
transistors which constitute high power consumption. Decreasing
the transistor count decreases the power consumption in the
circuit. A single bit full adder using a nine-transistor is
implemented and using this adder, an eight-bit ripple carries
adder is designed. A conventional CMOS adder, both single bit
and 8-bit ripple carry adder remain also designed to compare the
power outputs. Microwind-2.6a and DSCH 2.6 are used to
acquire the power outputs of each circuit. To conclude, power
comparisons for both single and eight-bit adders using the 9-
transistor and conventional CMOS models are made.
Keywords— Adder, Ripple carry adder, Conventional CMOS,
multiplexer
I. In t r o d u c t io n
Consequently, optimizing the Complete adder cell (the
adder's building block) is the main objective [8]. Power
usage has become a significant design consideration as the
market for compact, and mobile computing solutions
grows [9]. Power supply reduction, clock gating, and
other circuit design strategies have effectively reduced
power consumption in digital circuits [10].
II. CONVENTIONAL FULL ADDER
The conventional full adder model consists of twenty-
eight transistors for its design [11]. The number of PM 0 s
and NMOS are equal. Figure 1 explains the CMOS single
bit full adder [12]. It is based on a standard CMOS
architecture [13].

In recent VLSI trends, there has been an increasing

prominence of portable systems and the need to limit power
consumption and heat dissipation in digital circuits. Most
applications require low power dissipation for better
performance, like in computers, portable communication
devices etc [1]. Due to these reasons, there has been a rapid
development in designing low power CMOS circuits. Most of
the digital circuits use full adder as a basic component for
arithmetic calculations [2]. This paper focuses on designing a
ripple carry adder utilizing a 9-transistor full adder to reduce
power [3].
The low voltage and low power regime have been
emerging in CMOS VLSI architecture [4]. The main goal of
the VLSI is to boost the microprocessor's and system's
efficiency. The market for low-power, high-speed, and low-
delay solutions is rising by the day [5]. To satisfy these
criteria, modern processing systems rely heavily on arithmetic
operations. One of the most basic arithmetic operations also. Fig-1: CMOS single bit full adder
It's found in some VLSI systems, including microprocessors
& application-specific DSP constructions. Its primary Above mentioned single transistor is converted into a
function of combining two numbers also performs subtraction, symbol and connected as a ripple carry adder for an eight-
multiplication, division, and address measurement [6]. In bit adder [14]. Figure 2 explains about 8-bit ripple carry
every one of these frameworks, the viper is put the basic way, adder using conventional CMOS added [15].
which characterizes the framework's general speed [7].

978-1-6654-0521-8/21/$31.00 ©2021 IEEE

1982

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 2021 7th International Conference on Advanced Computing & Communication Systems (ICACCS)

III. NINE TRANSISTOR FULL ADDER MODEL

Fig-4: 2x1 multiplexer using two transistors. Gate terminal is
3.1 BASIC BLOCKS: a select line
3.1.1 exclusive-or gate: 3.1.3 Inverter:
The Ex-or entryway is comprised of three semiconductors: The inverter is constructed using two transistors, one NMOS
two PMOS and one n M o S. The PMOS pass semiconductor is and one PMOS and is as shown in fig 5
utilized. The yield is the supplement of the information A
when B is huge. When the contribution to rationale B stays
low, at that point, the pass semiconductor remains
empowered, and the yield is equivalent to include A rationale.
These are two logic gates called Exclusive- OR gate and
Exclusive -NO R gate. Figure 3 explains about exclusive OR
gate by using three transistors with pass transistor logic.

77/7

Fig-5: Inverter

Conventional equations of full adder can be given as

Sum = A xor B xor C

Carry = AB + BC + CA

The 9-transistor model full adder is designed using the

above three mentioned blocks in table 1.

Fig-3: Exclusive or gate using three transistors with pass

transistor logic Table-1

3.1.2 Multiplexer 2x1: Block Transistor count Block Count No.of transistors
The design of a 2x1 multiplexer is done using 2 Exor 3 1 3*1=3
transistors, one PMOS & one NMOS and the gate endpoints
Mux 2 2 2*2=4
remain controlled by a single input, a select line. The input
Invertor 2 1 2*1=2
source terminals of both the transistors are 2 inputs. Figure 4
explains about 2x1 multiplexer using two transistors, and the Total number of transistors 9
gate terminal is a select line.

1983

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 2021 7th International Conference on Advanced Computing & Communication Systems (ICACCS)
Fig-6: Block diagram of single bit 9-transistor full adder
Arithmetic and logic circuits are used in the majority of
necessary applications of integrated circuits. Figure 6
describes the block diagram of the single-bit 9-transistor full
adder.
Fig-7: schematic diagram of single bit 9-transistor full adder
CMOS circuits are widely used as building blocks of
digital integrated circuits. Power consumption has become a
major concern in VLSI architecture owing to the ongoing
shrinking of CMOS circuit function sizes and the resulting
rise in chip density and operating frequency. Figure 7 explains
about schematic diagram of single bit 9- full transistor adder.
IV. RIPPLE CARRY ADDER USING 9-TRANSISTOR
MODEL
The 9-transistor model of the full adder mentioned in fig-7
is used to connect a ripple carry adder. A block of fig-7 is
generated and connected in series.
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Fig-8: 8-bit Ripple carry adder using 9-transistor model
The first block's carry is given to the second, and it
continues as per the required design. The implementation
is done in DSCH, and a Verilog code is generated. The
Verilog code generated from DSCH is compiled in the
Micro wind tool. There is a facility for selecting CMOS
fabrication technology in Micro wind. The simulation is
then done to obtain the power values of the adders. In
figure 8
V. LAYOUTS AND SIMULATION
Fig-9: Layout of 9 transistor single bit adder in 22nm tech
Figure 9 describes the layout of 9 transistor single bit
adder in 22nm tech. in the proposed 9T single bit adder by
using 22nm tech
ff1yy\
Fig-10: 22nm technology single bit 9-transistor full adder
output
Figure 10 describes the 22nm technology single bit 9-
transistor full adder output. In the proposed 22nm single
bit by using 9-bit transistor full adder.
1984
 2021 7th International Conference on Advanced Computing & Communication Systems (ICACCS)

r t

D.D
pHing
r VinW®;
■™
»

0.0!
É
pirar r rZrI \
I

pv-
bW " 1
Û0
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x™>. 1
*
1

J w > > w
Í* > i :r: L >W >i

0.0
m « 1 50 0-0 1 :o m ' 14.0 IBJ 10.0

Fig-14: 22nm technology 1-bit conventional CMOS full

Fig-11: 22nm layout of 9-transistor 8-bit RCA
Figure 11 describes the layout of the 9-transistor 8-bit
RCA. In the proposed method, 22nm is designed layouts by
using a 9-bit transistor and 8-bit RCA.
adder output
Figure 14 explains the 22nm technology 1-bit
conventional CMOS full adder output. In this proposed
method, 22nm technology by using 1-bit conventional
CMOS full adder output.

Fig-12: 22nm technology 8-bit RCA full adder output

Figure 12 describes the 22nm technology 8-bit RCA full

adder output. The proposed method is designed 22nm
technology by using 8-bit RCA full adder output.
Fig-15: 22nm layout of 8-bit conventional CMOS RC adder

Figure 15 explains the 22nm layout of an 8-bit

conventional CMOS RC adder. In this proposed method,
22nm layout by using 8-bit conventional CMOS RC
adder.

Fig-16: 22nm technology 8-bit conventional CMOS RCA

Fug-13: 22nm layout of conventional CMOS 1-bit full adder
Figure 13 describes the 22nm layout of the conventional
CMOS 1-bit full adder. The proposed approach uses a
traditional CMOS complete adder to build a 22nm layout.
output
Figure 16 describes the 22nm technology 8-bit
conventional CMOS RCA output. In the proposed
method, 22nm technology by using 8-bit conventional
CMOS RCA output.

1985

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 2021 7th International Conference on Advanced Computing & Communication Systems (ICACCS)
VI. ANALYSIS
Table-2 CMOS address Power values of adders for
Pow er values o f conventional CM O S adders
22nm technology
N um ber o f bits 22nm 45nm 90nm
Versus
Technology 3.906
1-bit 3.906 pW 6.490 pW 14.768 pW
8-bit RCA 23.430 pW 36.518 pW 82.240 pW 0.471

full adder w ith pass Conventional Cmos

o tran sisto r exor full adder
Table-3 1 bit 9 transistor Q.
a d d 22nm >e
Pow er values o f different 1bit nine transistor adder
Nine transistor 1bit 22nm 45nm 90nm
adder model

Full adder with 0.471 pW 0.815 pW 1.471 pW

Fig-18: Power outputs of single bit adders for 22nm tech
Pass transistor exor

Figure 18 explains the Power outputs of single bit

Table 2 and Table 3 describe CMOS adders' power values adders for 22nm tech.
and the power values of different 1 bit nine transistors adder.

,Power values of adders for

POWER ANALAYSIS OF 45nm tech
6
NINE TRANSISTOR
4

22 nmtech ÆmDdihR £
C 2
0.815
0
fu ü a d d e r with pafionraesiitBtorai cmros full adder
— 45nm
a d d e r ty p e

Fig-19: Power outputs of single bit adders for 45nm tech

Figure 19 describes the Power outputs of single bit

adders for 45nm tech. In the proposed Power outputs by
using single-bit adders for 45nm tech.
FULL A D D E R WITH PASS T R A N S IST O R EXOR
addertype
Fig-17: Power variations of the 9-transistor adder for different f5ower values of adders for
technologies
90nm technology
Figure 17 describes the Power variations of the 9- CO
20
transistor adder for different technologies. In the proposed are 15 14.768
designed Power variations by using 9-transistor adder for
different technologies. u
10

5
1.471
0
5
5
O full adder with pass Conventional Cm os
Q .
tran sisto r exor
• 90nm
a d d e r ty p e

Fig-20: Power outputs of single bit adders for 90nm tech

Figure 20 explains the Power outputs of single bit

adders for 90nm tech.

1986

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 2021 7th International Conference on Advanced Computing & Communication Systems (ICACCS)
Table 2 and 3 explain the 8-bit ripple carry adder's power [8] A. Haldorai and A. Ramu, “Canonical Correlation Analysis Based
analysis by using pass transistor exor. Hyper Basis Feedforward Neural Network Classification for Urban
Sustainability,” Neural Processing Letters, Aug. 2020.
Table-4 Power analysis of 8-bit ripple carry adder using pass doi:10.1007/s11063-020-10327-3
transistor exor [9] D. Devikanniga, A. Ramu, and A. Haldorai, “Efficient Diagnosis
of Liver Disease using Support Vector Machine Optimized with
Pow er analysis o f 8-bit ripple carry adder using pass transistor exor
Crows Search Algorithm,” EAI Endorsed Transactions on Energy
Web, p. 164177, Jul. 2018. doi:10.4108/eai.13-7-2018.164177
22nm 45nm 90nm [10] H. Anandakumar and K. Umamaheswari, “A bio-inspired swarm
5.965 ^W 11.325 ^W 19.227 ^W intelligence technique for social aware cognitive radio handovers,”
Computers & Electrical Engineering, vol. 71, pp. 925-937, Oct.
2018. doi:10.1016/j.compeleceng.2017.09.016
P o w e r v a lu e s o f r ip p le c a r r y [11] Ahammad, Sk, V. Rajesh, K. Saikumar, SrideviJalakam, and G. N.
S. Kumar. "Statistical analysis of spinal cord injury severity
25 a d d e r w ith p a s s tr a n s is to r detection on high dimensional MRI data." International Journal of
Electrical & Computer Engineering (2088-8708) 9 (2019).
EXOR 1Q
[12] Padmini, G.R., Odela, R., Sampath Kumar, P., Saikumar,
K. "Implementation of ultra low power VLSI design and its
participation with Br4-reversible logics"SSRG International
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[13] Saba, S.S., Sreelakshmi, D., Sampath Kumar, P., Sai Kumar, K.,
Saba, S.R."Logistic regression machine learning algorithm on MRI
brain image for fast and accurate diagnosis"International Journal of
Scientific and Technology Research, 2020, 9(3), pp. 7076-7081
■ Full adder with pass transistor Exor [14] Sharath Kumar, D.R.V.A., Srinivas Kumar, Ch., Ragamayi, S.,.Sai
1-bit 8-bit 16-bit Kumar, K., Ahammad, S.H."A test architecture design for SoCs
using atam method"International Journal of Electrical and
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Fig-21: Power outputs of 8-bit RCA using 9-transistor full adder

Figure 21 explains the Power outputs of 8-bit RCA using a

9-transistor full adder. In the figure, we show the comparison
of 1-bit, 8-bit, 16-bit power in microwaves.
VII. CONCLUSION
As the technology scales down, the Absolute circuit
leakage power dissipation increases, which affects the circuit
performance. We have provided an effective method for
reducing power in VLSI architecture in this article. The
design was implemented using Microwind and DSCH 2.6a
tool at 22nm,45nm and 90nm technology for validation. The
output power values have depicted a considerable reduction in
power for the ripple carry adder.

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1987

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