CSE 2011: Computer Organization and Architecture

ASSIGNMENT 1:
Performance assessment of system, coding and decoding of Machine Language instruction, MIPS
programming with respect to Arithmetic, Logical and Data transfer instructions.
Due date: 6.2.2016(Saturday)
This assignment is designed to give you practice with:
1. Different performance assessment criterias.
2. Translating assembly language instructions to machine language instructions and
vice versa.
3. Writing asembly language programming using MIPS Arithmetic, Logical and Data
transfer instructions.

(You are allowed to use only those concepts which are covered in the lecture class till date.)
Plagiarized assignments will be given a zero mark.

1. The following table shows the execution time of five routines of a program running on
different numbers of processors.

Routine A Routine B Routine C Routine D Routine E

(ms) (ms) (ms) (ms) (ms)
4 14 2 12 2

i. Find the total execution time, and how much it is reduced if the time of routines A,
C, & E is improved by 15%.
ii. By how much is the total time reduced if routine B is improved by 10%?
iii. Can the total time be reduced by 30% by reducing only the time of routine D by
30 %?
2. Consider two different implementations, P1 and P2, of the same instruction set. There
are five classes of instructions (A, B, C, D, and E) in the instruction set. The clock
rate and CPI of each class is given below.

Processor Clock CPI (A) CPI (B) CPI (C) CPI (D) CPI (E)
Rate
P1 1Ghz 1 2 3 4 3
P2 1.5 GHz 2 2 2 4 4
 If the number of instructions executed in a certain program is divided equally among the
classes of instructions except for class A, which occurs twice as often as each of the others:
Which computer is faster? How much faster is it?
3. The table below shows instruction-type breakdown for different programs.

Programs Compute Load Store Branch Total

P1 1000 400 100 50 1550
P2 1500 300 100 100 1750

Assuming that computes take 1 cycle, loads and store instructions take 2 cycles, and
branches take 3 cycles, find the execution time of each program on a 4 GHz MIPS
processor.
4. Suppose we have developed new versions of a processor with the following
characteristics.

Version Voltage Clock rate

Version 1 5V 0.5 GHz
Version 2 3.3 V 1 GHz
i. How much has the capacitive load varied between versions if the dynamic power
has been reduced by 10%?
ii. How much has the dynamic power been reduced if the capacitive load does not
change?
iii. Assuming that the capacitive load of version 2 is 80% the capacitive load of
version 1, find the voltage for version 2 if the dynamic power of version 2 is
reduced by 40% from version 1.
5. Consider the following machine language instructions given in hexadecimal
representation:
( 01095020 ) x
( 00095880 ) x
( 218c0005 ) x
( 03e00008 ) x
i. What instruction do they represent?
ii. What type (I-type, R-type, J-type) instruction do the above instruction represent?
iii. Write the corresponding pseudo instruction.
6. The data table contains the values of various fields of MIPS instructions.
op=0, rs=8, rt=9, rd=12, shamt=0, funct=34
op=0x23, rs=8, rt=9, const=0x4

i. What type (I-type, R-type) instruction do the instructions above

represent?
ii. What is the MIPS assembly instruction described above?
iii. What is the binary representation of the instructions above?
7. Consider the following code segment :
a=8;
b=3;
a=a-b;
a=(a-1)>>1;
c=a*b;
Assume that the value of a, b, c are stored in three registers t0, t1 and t2 respectively.
i. Write the minimal set of MIPS instructions using only the three registers to
implement the above code.
ii. Write the output of registers after execution of each MIPS instruction.
iii. For each pseudo instruction write the corresponding bare instruction.
iv. Convert each bare instruction to machine language instruction in bainary and
hexadecimal format.
8. Write an assembly language program to find the gray code of an integer number stored in
a register.
For example: if number entered is 5, in register it will be stored as:
0000 0000 0000 0000 0000 0000 0000 0101 in binary format, and displaed as (5)x,
according to Gray code representation it will be converted to:
0000 0000 0000 0000 0000 0000 0000 0111 in binary format, and displaed as (7)x.
9. Write an assembly language program to enter a three digit decimal number through
console and store the BCD representation of the number in a memory word.
For example: if number entered is 128, in a memory word it will be stored as:
0000 0000 0000 0000 0000 0000 1000 0000 in binary format
and displaed in data segment as (80)x,
according to BCD representation it will be stored as:
0000 0000 0000 0000 0000 0001 0010 1000 in binary format
and displaed in data segment as (128)x.
10. For these problems, the table holds some logical operations that are not included in
the MIPS instruction set. How can these instructions be implemented?
a. not $t1, $t2 // bit-wise invert
b. orn $t1, $t2, $t3 // bit-wise OR of $t2, !$t3
i. The logical instructions above are not included in the MIPS instruction set, but are
described above. If the value of $t2 = 0x00FFA5A5 and the value of $t3 =
0xFFFF003C, what is the result in $t1 ?
ii. The logical instructions above are not included in the MIPS instruction set, but can
be synthesized using one or more MIPS assembly instructions. Provide a minimal
set of MIPS instructions that may be used in place of the instructions in the table
above.

Submission and Grading:

Submit your hard copy assignment by the due date, i.e. 6.2.2016(Saturday).

Part of your assignment grade comes from its "external correctness." This is based on
correct output on various sample inputs (like you have seen in the laboratory classes).
Your output should match the format of the sample run exactly.

The rest of your assignment's score comes from "internal correctness." Internal
correctness includes:
1. Use of minimal MIPS instructions and registers in your program.
2. Appropriate use of the theoretical concepts and suitable diagrams to enhance
readability of your responses.