Digital Electronics-Lecture5-Latches, Flip Flops, Registers[2024]Revised

Digital Electronics
Sequential Logic Circuits
1
Determine the truth tables
https://tinyurl.com/yhcy8cyf https://tinyurl.com/yd9gwzhb
(A) (B)
SET RES Q Q’ SET RES Q Q’
ET ET
Sequential Logic vs. Combinational Logic
➢ In digital circuit theory, sequential logic is a type of logic circuit

whose output depends not only on the present input but also on
the history of the input.
➢ This is in contrast to combinational logic, whose output is a
function of, and only of, the present input. In other words,
sequential logic has storage (memory) while combinational logic
does not.
3
➢ A latches and Flipflops are temporary storage devices that have two
stable states (bistable). They are basic forms of memory.
➢ A trigger
The state of a latch or flip-flop is
switched by a change of the
control input.
➢ Level triggered – Latches
➢ Edge triggered – Flip-Flops
Storage elements What: memory elements, such as latches,
Flip flops
How: logic gates with feedback
Why: required to store states
symbol
Active high SR Latch
Rising Edge Triggered JK Flip Flop 5

SR latch operation
S R State Qnext
0 0 Hold (No Previous
Change) state
1 0 Set 1
0 1 Reset 0
1 1 Invalid Invalid
6
Symbols
7
Latches with the enable signal
Why: to synchronize or enable stages →

Enable signal/Clock signal
8
Example Show the Q output with
relation to the input signals.
Assume Q starts LOW.
Solution Keep in mind that S and R are only active when EN is HIGH.
S
R
EN
Q
Invalid state: both S and R are simultaneously HIGH and EN is also HIGH.
9
Do it yourself: determine the truth table https://tinyurl.com/ydkyznrs
ENB A B Q
0 X X No change
1
How to eliminate the invalid state in the SR latch?
https://tinyurl.com/ye7b8evd
Determine the truth table ENB D Q Q’

0 X
1
How to avoid the invalid state of SR latch
The Gated D Latch
The D latch is a variation of the S-R latch but combines the
S and R inputs into a single D input as shown:
D D Q
Q
EN EN
Q
Q
A simple rule for the D latch is:

Q follows D when the Enable is active.
12
Latches, Flip Flops and Timers
Latches
The truth table for the D latch summarizes its operation. If
EN is LOW, then there is no change in the output, and it is
latched.
Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change
13
Latches D Q
Example EN
Determine the Q output for the
Q
D latch, given the inputs shown.
EN
Notice that the Enable is not active during these times, so

the output is latched.
14
Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be positive or negative.
D Q D Q
C C
Dynamic Q Q
input
indicator (a) Positive edge-triggered (b) Negative edge-triggered
15
Flip-flops
The truth table for a positive-edge triggered D flip-flop
shows an up arrow to remind you that it is sensitive to its
D input only on the rising edge of the clock; otherwise it is
latched. The truth table for a negative-edge triggered D
flip-flop is identical except for the direction of the arrow.
Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments
1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET
(a) Positive-edge triggered (b) Negative-edge triggered
16
Edge-triggered D Flip-flop
How to generate edge trigger? → 3 basic methods:

 1. Master-slave D flip-flop
◆ Two separate flip-flops
◆ A master flip-flop (positive-level triggered)
◆ A slave flip-flop (negative-level triggered)
17
https://tinyurl.com/yjx9uz2k
Draw the comment:

Active level-triggered of each latch→ positive/negative edge FF?
19
Flip-flop Characteristics
Propagation delay time is specified for the rising and
falling outputs. It is measured between the 50% level of the
clock to the 50% level of the output transition.
50% point on triggering edge
CLK CLK 50% point
Q 50% point on LOW-to- Q 50% point on HIGH-to-

HIGH transition of Q LOW transition of Q
tPLH tPHL
The typical propagation delay time for the 74AHC family (CMOS) is
4 ns. Even faster logic is available for specialized applications.
20
Another propagation delay time specification is the time
required for an asynchronous input to cause a change in the
output. Again it is measured from the 50% levels. The
74AHC family has specified delay times under 5 ns.
PRE 50% point CLR 50% point
Q 50% point Q 50% point
tPHL tPLH
21
Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.
D
Setup time is the minimum
time for the data to be present CLK
before the clock.
Set-up time, ts
Hold time is the minimum time
for the data to remain after the D
clock.
CLK
Hold time, tH
A useful comparison between logic
22
families is the speed-power product.
Extended Slides
23
Latches
A latch is a temporary storage device that has two stable
states (bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds
to active-HIGH inputs; with NAND gates, it responds to active-LOW
inputs.
NOR Active-HIGH Latch NAND Active-LOW Latch 24

Latches
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
0 R 01
Assume the latch is initially RESET Q
(Q = 0) and the inputs are at their Latch
inactive level (0). To SET the latch initially
(Q = 1), a momentary HIGH signal RESET
10
is applied to the S input while the R Q
0 S
remains LOW.
0 R 01
To RESET the latch (Q = 0), a Q
momentary HIGH signal is Latch
applied to the R input while the S initially
remains LOW. SET
01
Q
0 S
25
Latches
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET 1 S 01
Q
(Q = 0) and the inputs are at their
Latch
inactive level (1). To SET the latch initially
(Q = 1), a momentary LOW signal RESET
is applied to the S input while the R 01
1 R Q
remains HIGH.
To RESET the latch a momentary 1 S 01
Q
LOW is applied to the R input
Latch
while S is HIGH. initially
Never apply an active set and reset 01 SET
Q
at the same time (invalid). 1R
26
27
Symbols
Example
28
Latches
The active-LOW S-R latch is available as the 74LS279A IC.
(2)
It features four internal latches with 1S1
(3) (4) 1Q
two having two S inputs. To SET any 1S2
(1)
1R
of the latches, the S line is pulsed low.
(6)
It is available in several packages. 2S (7) 2Q
(5)
S-R latches are frequently used for 2R
switch debounce circuits as shown: (11)
3S1
VCC (12) (9) 3Q
3S2
(10)
3R
(15)
4S (13)
Q 4Q
2 S (14)
S 4R
R R Position Position
1 1 to 2 2 to 1 74LS279A
29
Latches, Flip
Summary
Flops and Timers
The Gated S-R Latch
A gated latch is a variation on the basic latch.
The gated latch has an additional S
Q
input, called enable (EN) that must
be HIGH in order for the latch to
EN
respond to the S and R inputs.
Q
R
Example Show the Q output with
relation to the input signals.
Assume Q starts LOW.
Solution Keep in mind that S and R are only active when EN is HIGH.
S
R
EN
Q
Invalid state: both S and R are simultaneously HIGH and EN is also HIGH.
31
The Gated D Latch
The D latch is a variation of the S-R latch but combines the
S and R inputs into a single D input as shown:
D D Q
Q
EN EN
Q
Q
A simple rule for the D latch is:

Q follows D when the Enable is active.
32
Latches
The truth table for the D latch summarizes its operation. If
EN is LOW, then there is no change in the output, and it is
latched.
Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change
33
Latches D Q
Example EN
Determine the Q output for the
Q
D latch, given the inputs shown.
EN
Notice that the Enable is not active during these times, so

the output is latched.
34
Fixed-Function Device: 7475 Quad Latch
35
Fixed-Function Device: 74373
The 54/74LS373 consists of eight latches with 3-state outputs
for bus organized system applications
36
Flip-Flops
➢ A trigger
The state of a latch or flip-flop is switched by a change of the
control input.
➢ Level triggered – Latches
➢ Edge triggered – Flip-Flops
37
Edge-triggered flip-flop logic symbols
38
Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be positive or negative.
D Q D Q
C C
Dynamic Q Q
input
indicator (a) Positive edge-triggered (b) Negative edge-triggered
39
Flip-flops
The truth table for a positive-edge triggered D flip-flop
shows an up arrow to remind you that it is sensitive to its
D input only on the rising edge of the clock; otherwise it is
latched. The truth table for a negative-edge triggered D
flip-flop is identical except for the direction of the arrow.
Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments
1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET
(a) Positive-edge triggered (b) Negative-edge triggered
40
Why using Flip-flops?
 If level-triggered flip-flops are used

◆ The feedback path may cause instability problem
 Edge-triggered flip-flops
◆ The state transition happens only at the edge
◆ Eliminate the multiple-transition problem

41
How to generate edge trigger? → 3 basic mehods:

 1. Master-slave D flip-flop
◆ Two separate flip-flops
◆ A master flip-flop (positive-level triggered)
◆ A slave flip-flop (negative-level triggered)
42
 2. Edge-triggered flip-flops
◆ The state changes during a clock-pulse transition
43
 3. D-type positive-edge-triggered flip-flop
44
◆ (S, R) = (0, 1): Q = 1
◆
◆
(S, R) = (1, 0): Q = 0
(S, R) = (1, 1): no operation
Operation
◆ (S, R) = (0, 0): should be avoided
D-type positive-edge-triggered flip-flop

Holding data Operation
1
0
1
positive-edge-triggered
Clk=0 Clk=0
1 0 1
Clk=1 Clk=1
Set Reset
1 1 0 1 0 1
1 1 1
0 1 1 0
1
0 1 1 0
46
JK Flip-flop
The J-K flip-flop is more flexible than the D flip flop. In
addition to the clock input, it has two inputs, labeled J and
K. When both J and K = 1, the output changes states
(toggles) on the active clock edge (in this case, the rising
edge).
Inputs Outputs Q
J
J K CLK Q Q Comments
No change CLK
0 0 Q0 Q0
0 1 0 1 RESET
K Q
1 0 1 0 SET
1 1 Q0 Q0 Toggle
47
JK Flip-flop
➢ D=JQ’+K’Q
J K CLK Q(t+1)
– J=0, K=0: D=Q, no change
0 0  Q(t) (No change)
– J=0, K=1: D=0  Q=0
– J=1, K=0: D=1  Q=1 0 1  0 (Reset)
– J=1, K=1: D=Q'  Q=Q' 1 0  1 (Set)

1 1  Q’(t) (Complement, Toggle)
48
Flip-flops Q
J
Example CLK
Determine the Q output for the J-K
flip-flop, given the inputs shown. K Q
Notice that the outputs change on the leading edge of the clock.
Solution
Set Toggle Set Latch
CLK
49
T (toggle) Flip-flop
D = T⊕Q = TQ'+T'Q T CLK Q(t+1)

•T=0: D=Q, no change 0  Q(t) (No change)
•T=1: D=Q'  Q=Q' 1  Q’(t) (Complement)
50
51
How does the output change?
D Q
CLK CLK
52
Flip-flops: Asynchronous inputs
Synchronous inputs are transferred in the triggering edge
of the clock (for example the D or J-K inputs). Most flip-
flops have other inputs that are asynchronous, meaning
they affect the output independent of the clock.
PRE
Two such inputs are normally labeled
preset (PRE) and clear (CLR). These Q
J
inputs are usually active LOW. A J-K
flip flop with active LOW preset and CLK
CLR is shown.
K Q
CLR
53
PRE
Flip-flops
J Q
Example CLK
Determine the Q output for the J-K
flip-flop, given the inputs shown. K Q
Solution
Set Toggle Set Reset Toggle Latch CLR
CLK
K Set
PRE Reset
CLR
54
Fixed-Function Device: 7474 dual D flip-flop
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
55
Fixed-Function Device: 74112 dual JK flip-flop
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
7476A: Dual JK Flip-Flops With Preset And Clear
56
Propagation delay time is specified for the rising and
falling outputs. It is measured between the 50% level of the
clock to the 50% level of the output transition.
50% point on triggering edge
CLK CLK 50% point
Q 50% point on LOW-to- Q 50% point on HIGH-to-

HIGH transition of Q LOW transition of Q
tPLH tPHL
The typical propagation delay time for the 74AHC family (CMOS) is
4 ns. Even faster logic is available for specialized applications.
57
Another propagation delay time specification is the time
required for an asynchronous input to cause a change in the
output. Again it is measured from the 50% levels. The
74AHC family has specified delay times under 5 ns.
PRE 50% point CLR 50% point
Q 50% point Q 50% point
tPHL tPLH
58
Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.
D
Setup time is the minimum
time for the data to be present CLK
before the clock.
Set-up time, ts
Hold time is the minimum time
for the data to remain after the D
clock.
CLK
Hold time, tH
A useful comparison between logic
59
families is the speed-power product.
Flip-flop Applications Output
lines
D Q0
Principal flip-flop applications are for C
temporary data storage, as frequency R
dividers, and in counters. D Q1

C
Q2
Typically, for data storage applications, D
a group of flip-flops are connected to Parallel data

C
parallel data lines and clocked together. input lines R
Data is stored until the next clock pulse. D Q3

Clock C
R
Clear
60
Flip-flop Applications
For frequency division, it is simple to use a flip-flop in

the toggle mode or to chain a series of toggle flip flops to
continue to divide by two. HIGH HIGH
One flip-flop will divide fin

J QA J QB fout
by 2, two flip-flops will
divide fin by 4 (and so on). fin CLK CLK
A side benefit of frequency
division is that the output K K
has an exact 50% duty
fin
cycle.
Waveforms:
fout
61
One-Shots
The one-shot or monostable multivibrator is a device
with only one stable state. When triggered, it goes to
its unstable state for a predetermined length of time,
then returns to its stable state. +V
REXT CEXT
For most one-shots, the length of time Q
CX
in the unstable state (tW) is determined RX/CX
by an external RC circuit. Trigger
Q
Trigger
Q
tW
62
A simple one-shot circuit
63
One-Shots
Nonretriggerable one-shots do not respond to any triggers that
occur during the unstable state.
Retriggerable one-shots respond to any trigger, even if it occurs in
the unstable state. If it occurs during the unstable state, the state is
extended by an amount equal to the pulse width.
Nonretriggerable one-shot:
Retriggerable one-shot:
Trigger
Retriggers
Q
tW 64
One-Shots
An application for a retriggerable one-shot is a power failure
detection circuit. Triggers are derived from the ac power source
and continue to retrigger the one shot. In the event of a power
failure, the one-shot is not triggered and an alarm can be
initiated.
Triggers Missing trigger
derived due to power
from ac failure
Q Retriggers Retriggers Power failure indication

tW
tW
tW
65
One-shot ICs
74121: nonretriggerable
ANSI/IEEE std. 91–1984 logic symbol
RINT =2k 66
74122/74123 RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH CLEAR
The internal resistance (RINT):10 k
67
IC 555 Timer
Supply +Vcc:
4.5V→ 15V
Pin 3. – Output, The

output pin can drive any
TTL circuit and is
capable of sourcing or
sinking up to 200mA of
current. 68
555 Operating modes
+VCC
Setting frequency and duty cycle

(4) (8) (4) (8)
R1 R1
RESET VCC
(7)
(7) RESET VCC DISCH
DISCH
(6) (3)
(6) (3) R2 THRES OUT
THRES OUT
(2) (5)
(2) (5) TRIG CONT
TRIG CONT C1 GND
GND (1)
C1 (1)
Monostable mode Astable mode Bistable mode

tW = 1.1R1C1.
1.44
The trigger is a f =
negative-going pulse. ( R1 + 2R2 ) C1
tW = 1.1R1C1
Nonretriggerable one-shot 69
The 555 timer
Example Determine the pulse width for the circuit shown.
Solution tW = 1.1R1C1 = 1.1(10 k)(2.2 F) = 24.2 ms
+VCC
+15 V
(4) (8)
R1
10 k (7) RESET VCC
DISCH
(6) (3)
THRES OUT
(2) (5) tW = 1.1R1C1
TRIG CONT
C1 GND
(1)
2.2 F
70
Selected Key Terms
Latch A bistable digital circuit used for storing a bit.

Bistable Having two stable states. Latches and flip-flops are
bistable multivibrators.
Clock A triggering input of a flip-flop.
D flip-flop A type of bistable multivibrator in which the output

assumes the state of the D input on the triggering
edge of a clock pulse.
J-K flip-flop A type of flip-flop that can operate in the SET,

RESET, no-change, and toggle modes.
71
Selected Key Terms
Propagation The interval of time required after an input signal

delay time has been applied for the resulting output signal to
change.
Set-up time The time interval required for the input levels to be
on a digital circuit.
Hold time The time interval required for the input levels to
remain steady to a flip-flop after the triggering
edge in order to reliably activate the device.
Timer A circuit that can be used as a one-shot or as an
oscillator.
72
1. The output of a D latch will not change if
a. the output is LOW
b. Enable is not active
c. D is LOW
d. all of the above
73
© 2008 Pearson Education
2. The D flip-flop shown will
D Q
a. set on the next clock pulse
CLK CLK
b. reset on the next clock pulse
c. latch on the next clock pulse Q
d. toggle on the next clock pulse
74
3. For the J-K flip-flop shown, the number of inputs that
are asynchronous is
PRE
a. 1
b. 2 J Q
c. 3 CLK
d. 4 K Q
CLR
75
4. Assume the output is initially HIGH on a leading edge
triggered J-K flip flop. For the inputs shown, the output
will go from HIGH to LOW on which clock pulse?
a. 1
CLK
b. 2 J
c. 3 K
d. 4 1 2 3 4
76
5. The time interval illustrated is called
a. tPHL 50% point on triggering edge
b. tPLH CLK
c. set-up time
Q 50% point on LOW-to-
d. hold time HIGH transition of Q
?
77
6. The time interval illustrated is called
a. tPHL
b. tPLH D
c. set-up time CLK
d. hold time ?
78
7. The application illustrated is a
a. astable multivibrator HIGH HIGH
b. data storage device fout

J QA J QB
c. frequency multiplier
fin CLK CLK
d. frequency divider
K K
79
Output
lines
D Q0
8. The application illustrated is a C
a. astable multivibrator R
D Q1
b. data storage device C
c. frequency multiplier D Q2
d. frequency divider Parallel data

C
input lines R
D Q3
Clock C
R
Clear
80
9. A retriggerable one-shot with an active HIGH output has
a pulse width of 20 ms and is triggered from a 60 Hz line.
The output will be a
a. series of 16.7 ms pulses
b. series of 20 ms pulses
c. constant LOW
d. constant HIGH
81
10. The circuit illustrated is a +VCC
a. astable multivibrator
(4) (8)
R1
b. monostable multivibrator (7)
RESET VCC
DISCH
c. frequency multiplier R2 (6)
THRES OUT
(3)
(2) (5)
d. frequency divider C1
TRIG CONT
GND
(1)
82
Answers:
1. b 6. d
2. d 7. d
3. b 8. b
4. c 9. d
5. b 10. a
83
Shift Registers
Basic Shift Register Operations
A shift register is an arrangement of flip-flops with
important applications in storage and movement of data.
Some basic data movements are illustrated here.
Data in
Data in Data out Data out Data in Data out
Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out
Data in
Data in
Data out Data out

Serial in/parallel out Parallel in/parallel out Rotate right Rotate left
84
Shift Registers
Serial-in/Serial out Shift Register
Shift registers are available in IC form or can be constructed
from discrete flip-flops as is shown here with a five-bit
serial-in serial-out register.
Each clock pulse will move an input bit to the next flip-
flop. For example, a 1 is shown as it moves across.
FF0 FF1 FF2 FF3 FF4

Serial 1 1 1 1 1 1 Serial
data D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 data
input output
C C C C C
CLK
CLK
85
Shift Registers
A Basic Application
An application of shift registers is conversion of serial
data to parallel form.
For example, assume the binary number 1011 is loaded
sequentially, one bit at each clock pulse.
After 4 clock pulses, the data is available at the parallel output.
FF0 FF1 FF2

FF2 FF3
FF3
Serial X
0
1 1
0 0
11 10 11
data D00
D Q00
Q D11
D Q11
Q D22
D Q22
Q D33
D Q33
Q
input
C
C C
C C
C C
C
CLK
CLK
86
Shift Registers
The 74HC164A Shift Register
The 74HC164A is a CMOS 8-bit serial in/parallel out shift
register.
(9)
CLR
(8)
CLK
(1)
Serial A
R R R R R R R R
inputs B (2)
C C C C C C C C
S S S S S S S S
(3) (4) (5) (6) (10) (11) (12) (13)
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
One of the two serial data inputs may be used as an active HIGH
enable to gate the other input. If no enable is needed, the other serial
input can be connected to VCC. The 74HC164A has an active LOW
asynchronous clear. Data is entered on the leading-edge of the clock.
87
Shift Registers
Waveforms for the 74HC164A
Sample waveforms for CLR
the 74HC164A are Serial

A
shown. Notice that B inputs B

acts as an active HIGH CLK
enable for the data on Q0
A as discussed. Q1
As with CMOS Q2
devices, unused inputs Q3
should always be Outputs
Q4
connected to a logic
Q5
level; unused outputs
Q6
should be left open.
Q7
Clear Clear
88
Shift Registers
Parallel in/Serial out Shift Register
Shift registers can be used to convert parallel data to serial
form. A logic diagram for this type of register is shown:
D0 D1 D2 D3
SHIFT/LOAD
G1 G5 G2 G6 G3 G7 G4
Serial
D D D D
Q0 Q1 Q2 Q3 data out
C C C C
FF0 FF1 FF2 FF3

CLK
89
Shift Registers
The 74HC165 Shift Register
The 74HC165 is a CMOS 8-bit parallel in/serial out shift
register. The logic symbol is shown:
D0 D1 D2 D3 D4 D5 D6 D7
(11) (12) (13) (14) (3) (4) (5) (6)
(1) (9)
SH/LD SRG 8 Q7
(10)
SER
(15)
CLK INH (2) (7)
CLK C Q7
The clock (CLK) and clock inhibit (CLK INH) lines are connected to a
common OR gate, so either of these inputs can be used as an active-
LOW clock enable with the other as the clock input. Data is loaded
asynchronously when SH/LD is LOW and moved through the register
synchronously when SH/LD is HIGH and a rising clock pulse occurs.
90
Addition/EDA demos:
Multisim, Digital works,…
Shift Registers
A Multisim simulation of the 74165A is shown. The word generator is
used as a source for the pattern shown in the green probes.
MSB
Q7 is labeled QH
in Multisim
Pattern is loaded
when J1 is LOW
91
Addition/EDA demos:
Shift Registers
The MSB is HIGH and is on the Q7 output as soon as LOAD is LOW.
MSB
Q7
Load
Clk
92
Addition/EDA demos:
Shift Registers
Bidirectional Shift Register
Bidirectional shift registers can shift the data in either
direction using a RIGHT/LEFT input.
The logic analyzer simulation shows a bidirectional shift register
such as the one shown in Figure 9-19 of the text. Notice the HIGH
level from the Serial data in is shifted at first from Q3 toward Q0.
CLK
RIGHT/LEFT Shift left Shift right
Serial data in
Q0
Q1
Q2
Q3
93
Addition/EDA demos:
Shift Registers
Bidirectional Shift Register
Question
How will the pattern change if the RIGHT/LEFT control
signal is inverted?
Answer See display
CLK
RIGHT/LEFT Shift
Shiftleft
right Shift Shift
right left
Serial data in
Q0
Q1
Q2
Q3
94
Shift Registers
Universal Shift Register
A universal shift register has both serial and parallel input
and output capability. The 74HC194 is an example of a 4-
bit bidirectional universal shift register.
D0 D1 D2 D3
(3) (4) (5) (6)

(1)
CLR SRG 4
(9)
S0
(10)
S1
(2)
SR SER
(7)
SL SER
(11)
CLK C
(15) (14) (13) (12)
Q0 Q1 Q2 Q3
Sample waveforms are
on the following slide…
95
Shift Registers
Universal Shift Register
CLK
Mode S0
control
inputs S1
CLR
Serial SR SER
data
inputs SL SER
D0
Parallel D1
data
inputs D2
D3
Q0
Q1
Parallel
outputs
Q2
Q3
Shift right Shift left Inhibit
Clear Load Clear
96
Shift Registers
Shift Register Counters
Shift registers can form useful counters by recirculating
a pattern of 0’s and 1’s. Two important shift register
counters are the Johnson counter and the ring counter.
FF0 FF1 FF2 FF3
The Johnson counter can D0 Q0 D1 Q1 D2 Q2 D3 Q3
be made with a series of D C C C C
flip-flops Q3 Q3
CLK
… or with a series of J-K FF0 FF1 FF2 FF3

Q3
J0 Q0 J1 Q1 J2 Q2 J3 Q3
flip flops. Here Q3 and Q3
C C C C
are fed back to the J and K Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3
inputs with a “twist”.
CLK
97
Shift Registers
Johnson Counter
Redrawing the same Johnson counter (without the clock
shown) illustrates why it is sometimes called as a “twisted-
ring” counter.
FF0
J0 Q0
“twist” C
K0 Q0
Q3
Q3
Q3
Q3
K1
J1
C
FF3
FF1
C
Q1
Q1
J3
K3
Q2 K2
Q2 2 J
2 FF
98
Shift Registers
Johnson Counter
The Johnson counter is useful when you need a sequence
that changes by only one bit at a time, but it has a limited
number of states (2n, where n = number of stages).
The first five counts for a 4-bit Johnson counter that is
initially cleared are: CLK Q 0 Q1 Q 2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
Question 6 0 0 1 1
7 0 0 0 1
What are the remaining 3 states?
99
Shift Registers
Ring Counter
The ring counter can also be implemented with either D
flip-flops or J-K flip-flops.
FF0 FF1 FF2 FF3
Q3
Here is a 4-bit ring counter D0 Q0 D1 Q1 D2 Q2 D3 Q3
constructed from a series C C C C
of D flip-flops. Notice the

feedback. CLK
FF0 FF1 FF2 FF3

Q3
Like the Johnson counter, J0 Q0 J 1 Q1 J 2 Q2 J 3 Q3
it can also be implemented C C C C
with J-K flip flops. K0 Q0 K1 Q1 K2 Q2 K3 Q3

Q3
CLK
100
Shift Registers
Ring Counter
Redrawing the Ring counter (without the clock shown)
shows why it is a “ring”.
FF0
The disadvantage to this counter J0 Q0
is that it must be preloaded with C
the desired pattern (usually a K0 Q0
single 0 or 1) and it has even
Q3
Q3
fewer states than a Johnson
Q3
Q3
K1
J1
C
FF3
FF1
counter (n, where n = number of
Q1
Q1
J3
K3
flip-flops.
On the other hand, it has the Q2 K2
advantage of being self-decoding C
with a unique output for each state. Q2 2 J
2 FF
101
Shift Registers
Ring Counter
A common pattern for a ring counter is to load it with a single 1 or a
single 0. The waveforms shown here are for an 8-bit ring counter
with a single 1.
CLK 1 2 3 4 5 6 7 8 9 10
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
102
Shift Registers
Shift Register Applications
Shift registers can be used to delay a digital signal by a
predetermined amount.
Example
An 8-bit serial in/serial out shift register has a 40 MHz
clock. What is the total delay through the register?
Solution
A SRG 8 Q7
Data in Data out
B
Q7
The delay for each clock CLK
40 MHz
C
is 1/40 MHz = 25 ns
25 ns
The total delay is CLK

8 x 25 ns = 200 ns
Data in
Data out
td = 200 ns
103
Key Terms
Register One or more flip-flops used to store and shift data.

Stage One storage element in a register.
Shift To move binary data from stage to stage within a
shift register or other storage device or to move
binary data into or out of the device.
Load To enter data in a shift register.
Bidirectional Having two directions. In a bidirectional shift
register, the stored data can be shifted right or left.
104
1. The shift register that would be used to delay serial data by
4 clock periods is Data in
a. c.
Data in Data out Data out
Data in
b. Data in
d.
Data out Data out
105
2. The circuit shown is a
a. serial-in/serial-out shift register
b. serial-in/parallel-out shift register
c. parallel-in/serial-out shift register
d. parallel-in/parallel-out shift register
D0 D1 D2 D3
SHIFT/LOAD
G4 G1 G5 G2 G6 G3
Serial
D0 Q0 D1 Q1 D2 Q2 D3 Q3 data
out
C C C C
CLK
106
3. If the SHIFT/LOAD line is HIGH, data
a. is loaded from D0, D1, D2 and D3 immediately
b. is loaded from D0, D1, D2 and D3 on the next CLK
c. shifted from left to right on the next CLK
d. shifted from right to left on the next CLK
D0 D1 D2 D3
SHIFT/LOAD
G4 G1 G5 G2 G6 G3
Serial
D0 Q0 D1 Q1 D2 Q2 D3 Q3 data
out
C C C C
CLK
107
4. A 4-bit parallel-in/parallel-out shift register will store
data for
a. 1 clock period
b. 2 clock periods
c. 3 clock periods
d. 4 clock periods
108
5. The 74HC164 (shown) has two serial inputs. If data is
placed on the A input, the B input
a. could serve as an active LOW enable
b. could serve as an active HIGH enable
c. should be connected to ground
d. should be left open
(9)
CLR
(8)
CLK
(1)
Serial A
R R R R R R R R
inputs B (2)
C C C C C C C C
S S S S S S S S
(3) (4) (5) (6) (10) (11) (12) (13)
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
109
6. An advantage of a ring counter over a Johnson counter is
that the ring counter
a. has more possible states for a given number of flip-flops
b. is cleared after each cycle
c. allows only one bit to change at a time
d. is self-decoding
110
7. A possible sequence for a 4-bit ring counter is
a. … 1111, 1110, 1101 …
b. … 0000, 0001, 0010 …
c. … 0001, 0011, 0111 …
d. … 1000, 0100, 0010 …
111
8. The circuit shown is a
a. serial-in/parallel-out shift register
b. serial-in/serial-out shift register
c. ring counter
d. Johnson counter
FF0 FF1 FF2 FF3
Q3
J0 Q0 J1 Q1 J2 Q2 J3 Q3
C C C C
Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3
CLK
112
9. Assume serial data is applied to the 8-bit shift register
shown. The clock frequency is 20 MHz. The first data bit
will show up at the output in
a. 50 ns
b. 200 ns
c. 400 ns
d. 800 ns
A SRG 8 Q7
Data in Data out
B
CLK Q7
C
20 MHz
113
10. For transmission, data from a UART is sent in
a. asynchronous serial form
b. synchronous parallel form
c. can be either of the above
d. none of the above
114
Answers:
1. a 6. d
2. c 7. d
3. c 8. d
4. a 9. c
5. b 10. a
115

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Digital Electronics

Sequential Logic Circuits

➢ In digital circuit theory, sequential logic is a type of logic circuit

Active high SR Latch

Rising Edge Triggered JK Flip Flop 5

Why: to synchronize or enable stages →

Determine the truth table ENB D Q Q’

A simple rule for the D latch is:

Notice that the Enable is not active during these times, so

Inputs Outputs Inputs Outputs

(a) Positive-edge triggered (b) Negative-edge triggered

How to generate edge trigger? → 3 basic methods:

Draw the comment:

CLK CLK 50% point

Q 50% point on LOW-to- Q 50% point on HIGH-to-

PRE 50% point CLR 50% point

Q 50% point Q 50% point

NOR Active-HIGH Latch NAND Active-LOW Latch 24

A simple rule for the D latch is:

Notice that the Enable is not active during these times, so

Inputs Outputs Inputs Outputs

(a) Positive-edge triggered (b) Negative-edge triggered

 If level-triggered flip-flops are used

◆ Eliminate the multiple-transition problem

How to generate edge trigger? → 3 basic mehods:

 3. D-type positive-edge-triggered flip-flop

D-type positive-edge-triggered flip-flop

– J=1, K=1: D=Q'  Q=Q' 1 0  1 (Set)

D = T⊕Q = TQ'+T'Q T CLK Q(t+1)

•T=1: D=Q'  Q=Q' 1  Q’(t) (Complement)

7476A: Dual JK Flip-Flops With Preset And Clear

CLK CLK 50% point

Q 50% point on LOW-to- Q 50% point on HIGH-to-

PRE 50% point CLR 50% point

Q 50% point Q 50% point

temporary data storage, as frequency R

dividers, and in counters. D Q1

a group of flip-flops are connected to Parallel data

parallel data lines and clocked together. input lines R

Data is stored until the next clock pulse. D Q3

For frequency division, it is simple to use a flip-flop in

One flip-flop will divide fin

Q Retriggers Retriggers Power failure indication

ANSI/IEEE std. 91–1984 logic symbol

The internal resistance (RINT):10 k

Pin 3. – Output, The

Setting frequency and duty cycle

Monostable mode Astable mode Bistable mode

Latch A bistable digital circuit used for storing a bit.

D flip-flop A type of bistable multivibrator in which the output

J-K flip-flop A type of flip-flop that can operate in the SET,

Propagation The interval of time required after an input signal

d. toggle on the next clock pulse

c. set-up time CLK

b. data storage device fout

d. frequency divider Parallel data

Data in Data out Data out Data in Data out

Data out Data out

FF0 FF1 FF2 FF3 FF4