Name: [] SID: [] Homework 02

Homework 04: 20 pts

1. Consider a proposed new instruction named rpt. This instruction combines a loop’s condition check and counter
decrement into a single instruction. For example rpt x29, loop would do the following:
if (x29 > 0) {
x29 = x29 −1;
goto loop;
}
(1) If this instruction were to be added to the RISC-V instruction set, what is the most appropriate instruction format? [2 pts]
(2) What is the shortest sequence of RISC-V instructions that performs the same operation? [2 pts]
Solution:
(1)

(2)

2. Write down the binary representation of the decimal number 13.25 assuming (1) the IEEE 754 single precision format
[2pts] and (2) the IEEE 754 double precision format [2pts].
Solution:
(1)

(2)
Name: [] SID: [] Homework 02

3. Assume that the logic blocks used to implement a processor’s datapath have the following latencies:
I-Mem/D-Mem Register File Mux ALU Adder Single gate Register Read Sign extend Control
250 ps 150 ps 25 ps 170 ps 150 ps 5 ps 30 ps 50 ps 50 ps

Note here“Register read” is the time needed after the rising clock edge for the new register value to appear on the output.
This value applies to the PC only.
(1) What is the latency of an R-type instruction? [2 pts]
(2) What is the latency of ld? [2 pts]
(3) What is the maximum clock rate for this CPU? [2 pts]
Solution:

4. For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache

Bit Tag Index Offset

Width 63-10 9-5 4-0

(1) What is the cache block size (in words)? [1 pts]

(2) How many blocks does the cache have? [1 pts]
(3) What is the ratio between total bits required for such a cache implementation over the data storage bits? [1 pts]
Solution:
Name: [] SID: [] Homework 02

5. In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time is
proportional to capacity. Assume that main memory accesses take 70 ns and that 36% of all instructions access data
memory.
The following table shows data for L1 caches attached to each of two processors P1 and P2. Assuming that the L1 hit time

Processor L1 Size L1 Miss Rate L1 Hit Time

P1 2KiB 8% 0.5ns
P2 4KiB 5% 0.8ns

determines the clock cycle times for P1 and P2.

(1) Calculate the clock rates of P1 and P2? [1 pts]
(2) What is the Average Memory Access Time for P1 and P2 (in clock cycles)? [1 pts]
(3) Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster?
(When we say a “base CPI of 1.0”, we mean that instructions complete in one cycle, unless either the instruction access or
the data access causes a cache miss.) [1 pts]
*hint: consider both instruction cache and data cache.
Solution: