This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2021.3072291, IEEE
Transactions on Power Electronics

New Dual-Input Zero-Voltage Switching DC-DC Boost

Converter for Low Power Clean Energy Applications

Saeed Danyali1, Amin Moradkhani1, Rahmat Aazami1, Mostafa Haghi2, Member, IEEE
1
Faculty of Engineering, Ilam University, Ilam, Iran
2
Peter L. Reichertz Institute for Medical Informatics of TU Braunschweig
and Hannover Medical School Braunschweig, DE

*Corresponding author: Saeed danyali

E-mail address: s.danyali90@gmail.com, s.danyali@ilam.ac.ir

Abstract- This paper introduces a new dual-input non-isolated
zero-voltage switching (ZVS) dc-dc boost converter. The proposed
converter hybridizes two bidirectional and unidirectional boost
converters, to harvest energy from a rechargeable energy storage
element and a clean energy dc generator, respectively. Hence, the
proposed circuit utilizes three power switches, one power diode,
two inductors and an output filtering capacitor. The ZVS of the all
power switches and ZCS for the power diode is realized without
any auxiliary circuit. The soft-switching performance is designed
to be valid for the whole power ranges of the converter input
sources and the output load. The converter power switches are
switched in PWM manner with two individual duty ratios,
allowing to regulate the converter output voltage and control the
extracted power from the input unidirectional port through a
simple and useful control system. Depending on the converter duty
ratios, its basic operation principle is analyzed in two different
operation cases. The proposed converter benefits from simple and
compact structure, minimum numbers of power switches and
magnetic elements and high efficiency. The behavior of the
proposed converter is analytically investigated, and a low-power
laboratory prototype is designed and fabricated to evaluate the
converter performance in different operation conditions.
I. INTRODUCTION
Recently, multi-input converters (MICs) [1]-[2] are
successfully introduced due to the capabilities of integrating
and controlling several power ports simultaneously, low cost,
high power density, high efficiency, and compact structure.
They are basically capable of boosting low input voltages to a
high level output voltage, implementing MPPT approach for
each renewable source individually and providing at least one
input terminal with bidirectional power flow capability for
storage elements. Generally, MICs can be classified into two
categories: isolated/semi-isolated topologies and non-isolated
topologies. In the meantime, and advantageously some MICs
may enjoy soft-switching performances to gain higher
efficiency, lower EMI and higher power density.
Isolated MICs are typically derived by combining full-
bridge, half-bridge, or series-resonant topologies via magnetic
coupling, e.g., utilizing multi-winding transformers [3]-[4]. In
[5], a systematic method for deriving multiport converters from
the full bridge converter and bidirectional dc–dc converters is
proposed by sharing the parasitized switching legs. A new
partly isolated multi-port phase-shift bidirectional dc-dc
converter for hybrid battery and super-capacitor applications is
presented by [6], which can achieve ZVS for all switches in the
whole load range. The paper [7] presents a partly isolated three-
port dc-dc converter for standalone PV systems, based on an
improved Flyback-Forward topology and using two coupled
inductors. In [8], A systematic approach to synthesize a MIC
from four pulsating voltage source cells (PVSC) and three
pulsating current source cells (PCSC) is developed based on the
circuit structure of the five basic isolated dc-dc converters. A
novel full bridge three-port converter (TPC) is proposed in [9]
with the features of PWM secondary-side phase-shift control,
ZVS of both the primary and secondary sides switches and
improved power devices sharing, but still using many power
circuit elements. A novel three-port dc-dc converter with
winding-cross-coupled inductors is derived in [10] for
distributed storage power generation, which offers ZVS
performance for all the power MOSFETs. In [11] a systematic
method for deriving soft-switching TPCs is introduced. A new
integrated TPC dc-dc converter with high step-up ratio for high-
voltage bus based micro grid systems is proposed by [12]. It is
featured with high degree of integration and high power
density. Extended ZVS and ZCS can be achieved in all
MOSFETs and diodes, respectively.
To improve system efficiency and power density, many non-
isolated MICs have been proposed in recent years. Non-isolated
MICs can either be derived by using dc-link or integration
methods. A ZVS series integrated dual-inputs dc-dc converter
is proposed in [13] with high efficiency. As the main drawback,
none of the input ports doesn’t provide bidirectional power
performance. A high step-up three-port dc-dc converter to
integrate solar and battery powers is introduced in [14] by
aiding two coupled inductors as voltage gain extension cells,

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Transactions on Power Electronics
but it doesn’t offer any soft-switching performance for the
converter switches. In [15], a systematic approach is proposed
for the derivation of non-isolated TPC topologies based on
dual-input converters (DIC) and dual-output converters (DOC).
In [16] a high-efficiency dual-input interleaved dc–dc converter
is proposed for rechargeable power sources. The input sources
are integrated at the output common dc-link and all the power
switches are soft-switched. As a negative score, this circuit idea
needs eight power switches and four power inductors. The
paper [17] presented two families of multi-input single-output
(MISO) converter topologies by combining some pulsating
source cells with one output filter. A three-port dc-dc topology
is proposed for simultaneously interfacing a PV source, a
battery storage and the load in [18]. A new non-isolated family
of multi-input converters based on three switches legs is
proposed in [19], which can work in either buck or boost mode.
In [20], a family of integrated multiport converters using three-
switch which can provide single-input dual-output (SIDO) or
dual-input single-output (DISO) with bidirectional power flow
between any two ports. Although these three recent mentioned
circuits seem to be attractive and efficient, they don’t propose
any soft-switching performances for the converters power
switches. A novel topology synthesis methodology is presented
in [21], which can be utilized to derive various integrated SIDO
and DISO dc–dc converters from conventional SISO
converters. In [22], a three-port three-level converter for
hybridizing of renewable energy sources is introduced which
features simple topology, low voltage stress across switches and
ZVS performance for wide load variation. A novel dual-input
ZVS dc-dc converter is presented in [23], however without
providing any bidirectional input port. It can boost two dc
sources to a constant DC output voltage and realize ZVS of both
used MOSFETs without any auxiliary circuit. In [24] a soft-
switching MIC for PV-battery system has been presented. The
PV power optimizer and battery charging and discharging
circuits share the switching device and magnetic components.
Therefore, the overall system becomes efficient. A family of
dual-output/input DC-DC converters is derived in [25] by
simply replacing the input/output inductors in conventional
TPCs with the proposed magnetic coupling branch based.
Although the mentioned circuits may enjoy isolation, soft
switching and high efficiencies they may still suffer from using
additional auxiliary/snubber circuits, many active and passive
circuit elements, complicated driving and control circuitry and
therefore higher circuit size and cost. Also, the proposed ZVS
scheme in some papers should satisfy complex criteria in
addition to that it is not applicable for the whole power ranges
of input sources and output load.
This paper introduces a new non-isolated dual-input zero-
voltage switching dc-dc boost converter. The proposed
topology can be applied to hybrid clean energy applications,
such as PV/FC generators along with battery/ultracapacitor
storage elements. The proposed converter structure hybridizes
two bidirectional and unidirectional boost units. The
bidirectional boost converter is feed from a rechargeable
storage element, while the unidirectional one is supplied by a
clean energy dc generator. Hence, the proposed circuit utilizes
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three power switches, one power diode, two inductors and an
output common filtering capacitor. The ZVS of the converter
power switches is achieved without any snubber or auxiliary
circuit. Also, the converter power diode stops conducting in
ZCS and therefore it achieves low di/dt and mitigated reverse
recovery loss. These soft-switching performances is designed
to be valid for the whole power ranges of the system input and
output load. The converter power switches are switched in
PWM manner and with two individual duty ratios. Considering
a simple and efficient control system, the first duty ratio is
employed to regulate the converter output voltage while the
second one is a controlling variable to control the desired power
from the input unidirectional source. Depending on the
converter duty ratios, its basic operation principle is analyzed
in two different operation cases. The converter operation
principle is analyzed and its validity is confirmed through the
final experiments in different operation conditions. As a result,
the proposed converter offers simple and compact structure,
minimum number of active and passive elements, bidirectional
power flow at the storage element port and high power
efficiency.
II. PROPOSED DUAL-INPUT DC-DC BOOST CONVERTER
The proposed dual-input ZVS dc-dc boost converter is
illustrated in Fig. 1. The proposed converter structure is based
on hybridizing two bidirectional and unidirectional boost units.
The bidirectional boost converter is feed from a rechargeable
storage element i.e. VB, while the unidirectional one is supplied
by a clean energy generator i.e. Vi. The converter is composed
of three active power switches S1, S2 and S3, two inductors L1
and L2, an output diode DO and a common capacitive output
filter CO. The diodes D1, D2 and D3 are the internal diodes of the
switches S1, S2 and S3, respectively. The capacitors Cs1, Cs2 and
Cs3 are the drain-source parasitic capacitances of the converter
power mosfet switches. In the converter, all the power switches
are switched with PWM scheme and by two independent duty
ratios of d1 and d2. The switch S1 and S2 are turned-on and off
complementarily with narrow dead-band and work with the
converter first duty ratio d1. Meanwhile, the switch S3 is
controlled by the converter second duty ratio d2 to regulate the
extracted power from the source Vi and turned-on at the
moment that the switched S1 is turned-off.
DO
ID o
_
VL2 L2
+
S3 CS3 IL2
D3
IS3 Vi
+
_ CS2 +
_
+ VL1 IS2 D2
RO VO
L1 _
IL1
S2
IB
S1 CS1
CO
VB
D1
IS1
Fig. 1: Proposed converter topology.
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Transactions on Power Electronics

III. PROPOSED CONVERTER OPERATION PERFORMANCE S2 S1 S2 S1

The only criterion for the proposed system is that the input
source Vi should have a voltage level lower than the battery S3 S3
voltage (VB>Vi). This criterion is necessary to have ZVS
performance for the switch S3 and is realizable by choosing
max IL1 max IL1
appropriate number for series renewable power cells. Before min min

turning-on of the converter power switches, their body diodes

IL2 IL2
are at on-state so the switches are all turned-on with ZVS. max
max
Meanwhile, the converter power diode (DO) stops conducting
min
in ZCS, alleviating its reverse recovery problem. The converter min

inductors currents IL1 and IL2 are in continuous conduction IB IB

mode (CCM) and take triangle and semi-trapezoidal shapes,
respectively. Depend on the values of the converter duty ratios, IDo
IDo
the proposed converter may operate in two different operation
cases i.e. d1+d2>1 or d1+d2<1. The converter different current IS1
and voltage waveforms are also illustrated by the Fig. 2, for the IS1
both operation cases. Also, the switching cycle of each
operation case composes nine operating modes, which are IS2 IS2
shown by the Fig. 3 and Fig 4 and analyzed as follows.
A) FIRST OPERATION CASE D1+D2>1 IS3
IS3
This operation case is occurred for higher extracted power
levels from the input source Vi. Before starting the first
operating mode at t=0, note that the switch S1 is conducting, the VS1 VS2 VS1 VS2
switches S2 and S3 are turn-off and the body diode of S3 is
conducting the negative currents of IL2. VS3
VS3
Mode I [0, t1): At t=0, the switch S1 is turned-off and the
switch S3 is turned-on with ZVS, as shown in the Fig. 3(a). 0 0
t1 t2 t3 t4 t5 t6 t7 t 8 Ts t1 t2 t3 t4 t5 t6 t7 t8 Ts
From the figure, the positive result current IL1-IL2 charges the
a) For d1+d2>1 b) For d1+d2<1
parasitic capacitance CS1, simultaneously discharges Cs2, till the
Fig. 2: Converter different waveforms.
moment t=t1 that the switch S2 body diode (D2) becomes
forward biased and starts conducting the result current. This Mode VI [t5, t6): At t=t5, the switch S1 is turned-on with ZVS
interval lasts for a short period of time. since its body diode D1 is conducting from the previous
Mode II [t1, t2): In this state, as seen from the Fig. 3(b) the operating mode, as shown in Fig.3 (f). As is clear from the
body diode D2 start conducting the result current I L1-IL2. This circuit, the inductor L1 is charged in the circuit loop containing
interval is short and prepares ZVS for the switch S2 at the its VB, L1 and S1 since VL1=VB>0. c Meanwhile, the new circuit
ahead turning-on moment of t=t2, at which the dead-time loop containing VB, S3, L2, Vi and S1 is provided, which slowly
interval between the switches S1 and S2 is elapsed. discharges the inductor L2 since VL2=Vi-VB<0.
Mode III [t2, t3): This state, as shown in Fig. 3(c), is started Mode VII [t6, t7): At t=t6, as shown in Fig. 3(g), the switch
by turning-on the switch S2 with ZVS and discharges the S3 is turned-off and therefore, the current IL2 charges the
inductor L1 through the circuit loop containing VB, L1, S2 and parasitic capacitance CS3, increasing the anode voltage of DO.
CO, since VL1=VB-VO<0. Meanwhile, the inductor L2 is charged This short interval lasts till t=t7 at which the diode DO is forward
through the circuit loop containing VB, S3, L2, Vi, S2 and CO, biased, IS3 reaches to zero and the next operating mode occurs.
since VL2=VO+Vi-VB>0. At the end of this interval, the inductor Mode VIII [t7, t8): At the time t=t7, the diode DO starts
current IL1 and IL2 reach to the values of IL1min and IL2max, conducting the current IL2 as shown by the circuit in Fig. 3(h).
respectively, so the result current of them (IL2-IL1) becomes As is seen from the circuit, the new circuit loop containing S1,
positive and therefore is carried by the switch S2. Vi, L2, DO and CO is provided, which discharges the inductor L2
Mode IV [t3, t4): This state is started by turning-off the since VL2=Vi-VB<0. Meanwhile, the inductor L1 is still charged
switch S2 at t=t3, and forms the converter circuit as shown in the in the former circuit loop containing VB, L1 and S1 since
Fig. 3(d). The result current of IL2-IL1 charges the parasitic VL1=VB>0. This operating mode lasts for the interval time Δ1Ts
capacitance of the switch S2 (CS2) till the moment t=t4 that the and ends at t=t8 that the current IDO reaches to zero and hence
switch S1 body diode (D1) becomes forward biased and start the diode DO stop conducting with ZCS.
conducting. This interval lasts for a short period of time. Mode IX [t8, Ts): At the beginning of this operating mode,
Mode V [t4, t5): At the beginning of this state, the body diode as shown in Fig. 3(i), the body diode of S3 starts conducting a
of S1 start conducting the result current IL2-IL1, as seen by the low negative current for L2 through the circuit loop containing
Fig. 3(e). This interval is short and prepares ZVS for the ahead VB, D3, L2, Vi and S1, preparing ZVS for S3 in the next operating
turning-on moment of the switch S1 that at which the dead-time mode. Meanwhile, the inductor current IL1 is still increasing
interval between the switches S2 and S1 is elapsed. through the circuit loop of VB, L1 and S1.

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Transactions on Power Electronics

ID o DO ID o DO ID o DO
_ _ _

VL2 L2 VL2 L2 VL2 L2

+ + + + + +
S3 CS3 IL2 S3 CS3 IL2 S3 CS3 IL2
D3 _ D3 _ D3 _
+ _ CS2 + + _ CS2 + + _ CS2 +
IS3 Vi _ + IS3 Vi _ + IS3 Vi _ +
_ _ _
+ VL1 IS2 D2
RO VO + VL1 IS2 D2
RO VO + VL1 IS2 D2
RO VO
IL1 L1 _ IL1 L1 _ IL1 L1 _
S2 IB S2 IB S2
IB + + +
S1 CS1 S1 CS1 CO S1 CS1 CO
D1 _ CO D1 _ D1 _
VB VB VB
IS1 IS1 IS1

a) Converter circuit for 0 < t < t1 b) Converter circuit for t1 < t < t2 c) Converter circuit for t2 < t < t3
ID o DO ID o DO ID o DO
_ _ _

VL2 L2 VL2 L2 VL2 L2

+ + + + + +
S3 CS3 IL2 S3 CS3 IL2 S3 CS3 IL2
D3 _ D3 _ D3 _
+ _ CS2 + + _ CS2 + + _ CS2 +
IS3 Vi _ + IS3 Vi _ + IS3 Vi _ +
_ _ _
+ VL1 IS2 D2
RO VO + VL1 IS2 D2
RO VO + VL1 IS2 D2
RO VO
IL1 L1 _ IL1 L1 _ IL1 L1 _
IB S2 S2 IB S2
+ IB + +
S1 CS1 CO S1 CS1 CO S1 CS1 CO
D1 _ D1 _ D1 _
VB VB VB
IS1 IS1 IS1

d) Converter circuit for t3 < t < t4 e) Converter circuit for t4 < t < t5 f) Converter circuit for t5 < t < t6
ID o DO ID o DO ID o DO
_ _ _

VL2 L2 VL2 L2 VL2 L2

+ + + + + +
S3 CS3 IL2 S3 CS3 IL2 S3 CS3 IL2
D3 _ D3 _ D3 _
+ _ CS2 + + _ CS2 + + _ CS2 +
IS3 Vi _ + IS3 Vi _ + IS3 Vi _ +
_ _ _
+ VL1 IS2 D2
RO VO + VL1 IS2 D2
RO VO + VL1 IS2 D2
RO VO
IL1 L1 _ IL1 L1 _ IL1 L1 _
IB + S2 IB + S2 IB + S2
S1 CS1 CO S1 CS1 CO S1 CS1 CO
D1 _ D1 _ D1 _
VB VB VB
IS1 IS1 IS1

g) Converter circuit for t6 < t < t7 h) Converter circuit for t7 < t < t8 i) Converter circuit for t8 < t < Ts
Fig. 3: Proposed converter different operating modes for d1+d2>1.

B) SECOND OPERATION CASE D1+D2<1 the end of this interval, the result current I L2-IL1 becomes
positive and is conducted by the switch S2.
This operation case occurs for the lower power levels
Mode IV [t3, t4): At the time t=t3, as shown in Fig. 4(d), the
extracted from the source Vi. Before starting the first operating
switch S3 is turned-off and therefore, the current I L2 charges the
mode at t=0, the switch S1 is conducting, the switches S2 and S3
parasitic capacitance CS3, increasing the anode voltage of the
are turn-off and the body diode of S3 is conducting IL2.
diode DO. This interval is short and lasts till t=t4 at which the
Mode I [0, t1): At the time t=0, the switch S1 is turned-off
diode DO becomes forward biased, IS3 reaches to zero, and then
and the switch S3 is turned-on with ZVS, as shown in the Fig.
the next operating state is started.
4(a). From the figure, the positive result current of IL1-IL2
Mode V [t4, t5): At the time t4 the diode DO starts conducting
charges the parasitic capacitance CS1, simultaneously
the current IL2 in the circuit loop containing Vi, L2, DO and S2,
discharges Cs2, till the moment t=t1 that the switch S2 body
as seen in the Fig. 4(e). Also, the previous circuit loop
diode (D2) becomes forward biased and starts conducting the
containing VB, L1, S2 and CO is still valid. So, the inductors
result current. This interval lasts for a short period of time.
voltages of VL1=VB-VO>0 and VL2=-Vi<0 are recognized,
Mode II [t1, t2): In this state, as seen from the Fig. 4(b) the
denoting the same discharging state for L1 and a lower rate
body diode D2 start conducting the result current I L1-IL2. This
charging state for L2, compared to those in Mode III.
interval is short and prepares ZVS for the switch S2 at the its
Mode VI [t5, t6): This state is started by turning-off the
ahead turning-on moment of t=t2, at which the dead-time
switch S2 at t=t5, forming the converter circuit as shown in the
interval between the switches S1 and S2 is elapsed.
Fig. 4(f). The result current of IL2-IL1 charges the switch S2
Mode III [t2, t3): This state, as shown in Fig. 4(c), starts by
parasitic capacitance (CS2) till the moment t=t4 that the switch
turning-on the switch S2 with ZVS and provides the circuit loop
S1 body diode (D1) becomes forward biased and start
containing VB, L1, S2 and CO, which discharges L1 since
conducting. This interval lasts for a short period of time.
VL1=VB-VO<0. Meanwhile, the circuit loop of VB, S3, L2, Vi, S2
and CO is also formed, charging L2 since VL2=VO+Vi-VB>0. At

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Transactions on Power Electronics

ID o DO ID o DO ID o DO
_ _ _

VL2 L2 VL2 L2 VL2 L2

+ + + + + +
S3 CS3 IL2 S3 CS3 IL2 S3 CS3 IL2
D3 _ D3 _ D3 _
+ _ CS2 + + _ CS2 + + _ CS2 +
IS3 Vi _ + IS3 Vi _ + IS3 Vi _ +
_ _ _
+ VL1 IS2 D2
RO VO + VL1 IS2 D2
RO VO + VL1 IS2 D2
RO VO
IL1 L1 _ IL1 L1 _ IL1 L1 _
S2 IB S2 IB S2
IB + + +
S1 CS1 S1 CS1 CO S1 CS1 CO
D1 _ CO D1 _ D1 _
VB VB VB
IS1 IS1 IS1

a) Converter circuit for 0 < t < t1 b) Converter circuit for t1 < t < t2 c) Converter circuit for t2 < t < t3
ID o DO DO DO
ID o ID o
_ _ _

VL2 L2 VL2 L2 VL2 L2

+ + + + +
IL2 +
S3 CS3 S3 CS3 IL2 S3 CS3 IL2
D3 _ D3 _ D3 _
+ _ CS2 + + _ CS2 + + _ CS2 +
IS3 Vi _ + IS3 Vi _ + IS3 Vi _ +
_ _
+ VL1 IS2 D2
RO VO + VL1
_ IS2 D2
RO VO + VL1 IS2 D2
RO VO
IL1 L1 _ L1 _ IL1 L1 _
IL1
IB + S2 S2 IB S2
IB + +
S1 CS1 CO S1 CS1 S1 CS1 CO
D1 _ _ CO D1 _
D1
VB VB VB
IS1 IS1 IS1

d) Converter Circuit for t3 < t < t4 e) Converter Circuit for t4 < t < t5 f) Converter circuit for t5 < t < t6
DO ID o DO ID o DO
ID o
_ _ _

VL2 L2 VL2 L2 VL2 L2

+ + + + +
+ IL2
S3 CS3 IL2 S3 CS3 IL2 S3 CS3
D3 _ D3 _ D3 _
+ _ CS2 + + _ CS2 + + _ CS2 +
IS3 Vi _ + IS3 Vi _ + IS3 Vi _ +
_ _ _
+ VL1 IS2 D2
RO VO + VL1 IS2 D2
RO VO + VL1 IS2 D2
RO VO
IL1 L1 _ IL1 L1 _ IL1 L1 _
IB + S2 IB S2 IB + S2
+
S1 CS1 CO S1 CS1 CO S1 CS1 CO
D1 _ D1 _ D1 _
VB VB VB
IS1 IS1 IS1

g) Converter circuit for t6 < t < t7 h) Converter circuit for t7 < t < t8 i) Converter circuit for t8 < t < Ts
Fig. 4: Proposed converter different operating modes for d1+d2<1.

Mode VII [t6, t7): The converter circuit is shown by the Fig.
V. PROPOSED CONVERTER VOLTAGE GAIN
4(g) in this state. At the beginning of this state, the body diode
of S1 (D1) start conducting the positive result current of IL2-IL1. From the converter waveforms in Fig. 2 and its operating
This interval is short and prepares ZVS for the switch S1 at the modes analysis for the both operation cases, the first inductor
its ahead turning-on moment of t=t7 that at which the dead-time volt-second balance over a switching cycle and the converter
interval between the switches S2 and S1 is elapsed. voltage relation is written:
Mode VIII [t7, t8): At t=t7, the switch S1 is turned-on with VB
VB d1  (VB  VO )(1  d1 )  0  VO  (1)
ZVS since its body diode D1 is conducting from the previous 1  d1
operating mode, as shown in Fig. 4(h). As is clear from the This voltage gain is the same as that of the classic boost
circuit, the new circuit loop containing S1, Vi, L2, DO and CO is converter and implies that the output voltage is directly
provided, which discharges the inductor L2 since VL2=Vi-VB<0. regulated by only the two parameters of V B and d1 and does not
Meanwhile, the inductor L1 is charged in the circuit loop theoretically accept any impacts from Vi or d2. Meanwhile, the
containing VB, L1 and S1 since VL1=VB>0. This operating mode Vi and d2 values show direct impacts on the delivered power
lasts for the interval time Δ2Ts and ends at the moment t8 that from the input source Vi (Pi), discussed in the next section.
the current IDO reaches to zero and therefore the diode DO stop
conducting with ZCS. VI. VOLTAGE AND CURRENT STRESSES ANALYSIS
Mode IX [t8, Ts): At the beginning of this operating mode, For the both operation cases of the proposed converter, the
as shown in Fig. 4(i), the body diode of S3 starts conducting a block voltage across the power switches and reverse voltage
low negative current for L2 through the circuit loop containing across the power diodes during their turn off intervals are found
VB, D3, L2, Vi and S1, preparing ZVS for S3 in the next operating as follows:
mode. Meanwhile, the inductor current IL1 is still increasing
through the circuit loop of VB, L1 and S1.

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Transactions on Power Electronics

VDS1  VO ; VDS2  VO ; I L 2 ( t5 )  I L1 ( t5 )  I L 2 max  I L1min (9)

(2)
VDS 3  VO VB ; VDo  VO VB ; Based on this, the peak current of IL2 max
is formulated as follow
The current stresses of the converter power elements are also for the second operation case:
directly deduced through the converter currents waveforms in Ts
I L 2 max  Vi  VO d 2  VB (d1   2  d 2 )  (10)
Fig. 2, which are found as follows: L
I Sstr1  I L1max  I L 2 min ; I Sstr2  I L 2 max  I L1min ; where, ∆2 is the time interval ratio of the converter operating
(3) Mode VIII in the second operation case, obtained as follow:
I Sstr3  I L 2 max ; I Dstro  I L 2 max
 2  d1  d 2  1  1 (11)
Compared to the classic boost converter and with the same
voltage and power level, the proposed converter switches S1 and Also, the following average, maximum and minimum values
S2 shows the same voltage stresses while they experience lower can also be proven for IL1 in the second operation case:
current stresses than those of the boost converter. Meanwhile, PO  Pi 1
the switch S3 and the diode DO shows lower voltage and current I L1 ave   I L 2 max d 2
VB 2
stresses than those of the classic boost converter.
VB
I L1max  I L1ave  d1Ts (12)
VI. CONVERTER DESIGN CONSIDERATIONS 2 L1
Assuming fixed values for Vi, VB and VO, the converter first VB
duty ratio d1 is solved by (1). The converter second inductor I L1min  I L1ave  d1Ts
2 L1
plays some important roles in the converter circuit performance.
The first one is that it is responsible to form the semi- Considering (9) to (12) gives the following maximum
trapezoidal current waveform of IL2. Neglecting the converter inductance value for L2:
short commutation states, the following average value can be VB Vi  VO d 2  VB (1  1 )  (2  d 2 ) L1Ts
formulated for the converter first operation case (i.e. d1+d2>1): L2 max  (13)
2 L1 ( PO  Pi )  VB 2 d1Ts
Ts
I L 2 ave  [Vi  (VB  Vi ) 1 ]( d 2  1 )( d 2  d1  1) (4)
2L In this relation with the assumption of known values for VO, Vi,
where, ∆1 is the ratio of the time interval of the converter VB, d1, L1 and ∆1, the values of PO, Pi and d2 vary during the
operating Mode VIII in the first operation case (i.e. d1+d2>1), circuit operation and in accordance to the loading and the power
and is obtained as the following fixed value: from Vi, respectively. As can be easily deduced from (13), the
Vi lowest value for L2max is related to Po=Pomax and Pi=Pimin when
1  (5) the converter second duty ratio is chosen in the range of
VO  VB
0<d2<1-d1. Therefore, based on the circuit parameters in the
So, the drawn average power from Vi is calculated: experimental section, the acceptable maximum and minimum
Ts
Pi  Vi I L 2 ave  Vi Vi  (VB  Vi ) 1  (d 2  1 )(d 2  d1  1)
values for the converter second inductance are determined by
(6)
2L (8) and (13) as follows:
The second role of the inductor L2 is to provide ZVS L2
min
 0.09mH , L2 max  0.22mH
(14)
condition for the switch S3. As seen in the Fig. 2(a) for the first
Choosing the converter second inductance value within this
operation case, in the last operating Mode IX [t8, Ts), the current
range ensure ZVS performance for the converter power
IL2 takes negative values, flowing through D3 and preparing
switches S1 and S3 in all power operation conditions.
ZVS condition for the switch S3 which is turned-on at t=Ts. The
time interval of this operating mode is (1-d2-∆1)Ts. In order to VII. CONVERTER POWER LOSSES ANALYSIS
ensure ZVS for the switch S3 the following criterion should be The converter power losses include two components, i.e.
fulfilled: conduction losses and switching losses. The conduction losses
(1  d 2  1 )Ts  0  d 2  1  1  d 2 max  1  1 (7) is formulated as:
Ploss  rL I 1 rms  rL I 2 rms  rDS I S rms  rDS I S rms  rDS I S rms  V FD I D
con 2 2 on 2 on 2 on 2 ave

Considering this value d2max and a maximum value for Pi the 1 2 1 1 2 2 3 3 O

(15)
minimum inductance value of L2 is obtained using (6) and (7): where, rL1, rL2 and rL3 are the associated ESRs of the converter
Vi Ts inductors, rDS1 and rDS2 are the on-state resistances of the
L2
min
 V  (V
i B
 Vi ) 1  ( d 2
max
 1 )( d 2
max
 d1  1) (8) converter power MOSFETs and VFD is the on-state drop voltage
2 Pi max
across the converter power diode. For the intervals that the body
The third role of the inductor L2 is to provide ZVS condition
diode of the converter power MOSFETs are conducting, the
for the switch S1. This performance is realized if the peak on 2 sw ave sw ave
current of L2 (IL2max) be larger than the minimum current of L1 term of rDS I S rms is replaced by V FD I S , where V FD and I
1 1 i i i Si

(IL1min). Refereeing the converter waveforms in Fig. 2, it is
obvious that the peak current of L2 for the second operation case
i.e. IL2max=IL2(t5), is smaller than that in the first operation case
i.e. IL2max=IL2(t3). Therefore, the validity of ZVS for S1 should
be evaluated for the second operation case as follow:
are forward drop voltage and current of the corresponding
switch body diode. Also, Irms and Iave denote the effective and
average values of the corresponding component current over a
switching cycle. Neglecting the converter commutation
switching states, calculating Irms and Iave values in (15) needs to

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Transactions on Power Electronics

know the converter current relation in different non- As seen from the figure, the converter power losses of each
commutation operation states. These currents relations have input power level will increase if the load power increases,
been obtained by means of the converter operating modes which is expectable. Furthermore, for the lower output loads if
analysis in section III. Also, as the converter power diode DO the input generated power is increased the proposed converter
stop conducting in ZCS, thus the converter switching power shows higher power losses. This means that, for fixed load
losses is mainly associated with the power switches as: power as the battery charging power is increased (by means of
increasing Pi) the converter power losses will increase, too.
sw
Ploss
1
2
on  on 
 f s V DS 1 
.I S1 .t on V DSoff  off 
1
.I S1 .t off  (16) VIII. PROPOSED CONVERTER CONTROL SCHEME
1
2
on  on 
 f s V DS 2  off  off 
.I S 2 .t on V DS 2
.I S 2 .t off  The proposed converter control scheme is shown in Fig. 6.
on 
Where, V DS and I Son  are switch Drain-Source voltage before Considering (1), the output voltage is regulated through the first
PI control loop and by using the converter first duty ratio d 1.
turning-on moment and Drain-Source current after turning-on This control process makes the storage source to spontaneously
moment, respectively. Also, V DSoff  and I Soff  are the switch support the load in any attendances of the input power source.
Drain-Source voltage after turning-off moment and Drain- Moreover, the source Vi is a unidirectional renewable power
Source current before turning-off moment, respectively. source, existing in different power levels. This voltage source
Meanwhile, fs, ton and toff denote the switching frequency, should be regulated at Viref that is the voltage of the maximum
switches turning-on and turning-off times, respectively. It is power point (VMPP), calculated by the MPPT control technique.
also obvious that, since the converter power switches enjoy As obtained in (6), the drawn average current from the input
ZVS performance their Drain-Source voltage before turning-on source (IL2ave) directly depends on d2. Therefore, the second
moments is set at zero value. These parameters before and after control loop is formed to regulate power of the input source by
turning-on/off moments are determined for the converter power employing the converter second duty ratio d 2. Also, a SOC
switches as follows: control block is considered which can supervisory analyze the
off  off  converter power flow to remain the SOC of the storage source
VO I
on  on 
V  0 , I 0 ; V DS , IS -I L2min
DS
1
S
1 1 1 L1max
within the allowed band of SOCmin<SOC<SOCmax.
off  off 
VO I (17)
on  on 
V DS
 0 , I S
0 ; V DS , IS L2max
-I L1min + Ii -
1 1 1 1
Vi
off  off  Vi
V I
on  on 
V DS
 0 , I S
0 ; V DS O
-VB , IS L2max Vi
1 1 1 1
MPPT V G3 +
iref - d2
Finally, the converter total power losses and its efficiency can Ii & + PI
Proposed

PWM
SOC G2 VO RO
be estimated as follows: VB
d1 G1
Converter
PI
 Ploss VOref +
- _

Ploss  P P 1  P for PB  0

sw con
loss loss
 i
(18) VO
PB  PO  Pi  Ploss 1  P _
for PB  0
+
loss IB
VB

 Pi  PB Fig. 6: Proposed converter control system.
The curve of converter power losses versus load power
(0<PO<220W) has been estimated and depicted by the Fig. 5 for IX. EXPERIMENTAL VERIFICATION
different input power levels (P i=10W, 50W, 70W, 100W, and In order to verify the proposed converter validity, a low-
130W) and with the experimental circuit specifications: power (200W) laboratory prototype is designed and fabricated
Vi=48V, VB=40V, Ll=300µH, L2=200µH, fs=50kHz, as shown in Fig. 7. The parameters of the prototype are listed in
rL1=rL2=0.1Ω, rS1=rS2=rS3=0.1Ω, VFD=1V, V FD  1.6V and Table I. The Texas Instrument digital signal processor (DSP)
sw

i
TMS320F2812 has been used as the system controller. In the
ton=toff=50nsec. prototype, two isolated voltage sensors NV25-P along with four
isolated current sensors La-55p are employed in the
measurement board to feedback the measured analog signals of
VO, VB, Vi and Ii to the A/D conversion. The DSP executes the
digital process routine of the control system and generates the
system duty ratios. The resulted duty ratios are converted to
3.3V-PWM signals by the DSP digital comparator modules of
the PWM timer (50kHz). Theses PWM signals are employed to
the system MOSFETs using the drive circuits in the PWM
board. A rechargeable battery stack of VB=48V is used at the
bidirectional input port of the proposed converter. Also, a fixed
voltage source of Vi=40V is considered at the converter
unidirectional input port. The output voltage is also desired to
be regulated at 220VDC. In order to validate practical
Fig. 5: Proposed converter estimated power losses.
performances of the proposed converter, a comprehensive

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experiment with the duration of 600msec has been prepared.
Based on this experiment, three different experimental
conditions are scheduled for the system by employing some
step changes in the converter reference values of the second
duty ratio (d2) and the load resistance. Initially, the converter
transient responses toward the applied step changes are
depicted for the load voltage VO in Fig. 8(a) and the inductors
currents IL1, IL2 and the battery current IB in Fig. 8(b).
First experimental stage (0<t<200msec): For the first
experimental condition, the load power is P O=55W (RO≈915Ω)
and the converter second duty ratio is set at d2=0.7. This setting
cause to draw average current and power from the
unidirectional input source about IL2ave=2.5A and Pi=100W,
respectively. Meanwhile, the first control loop of the converter
control system regulates the load voltage by the first duty ratio.
As a consequence, the average current of IBave=-0.84A is
measured to the battery source, which indicates its charging
power about PB=-40W. This situation reveals the converter
power losses of 5W and therefore its power efficiency about
95%. The different currents and voltages waveforms of the
converter inductors, power MOSFETs and the diode are shown
in Fig. 9(a)-(b). As is clearly seen from the figures, they comply
with to the converter waveforms in Fig. 2(a) of the first
operation case since d1+d2>1. Also, Fig. 9(c) demonstrates the
ZVS of the converter power switches S1, S2 and S3,
respectively. As seen from the figure, before turning on
moments of each power switch, its drain-source voltage has
dropped to zero.
IL2(2A/div)
IL1(2A/div)

IB(5A/div)

5µsec/div
(a)

Fig. 7: Proposed converter experimental setup.

IS1(2A/div)
IS2(2A/div)
Table I: Experimental parameters values
Battery voltage VB=50V
Input source voltage Vi=40V
Switching frequency Fs=50kHz
Power mosfets IRFP460
Power diode MUR15560
IS3(2A/div)
Inductors L1=0.3mH, L2=0.2mH
ID4(2A/div)
Output capacitor CO=100µF

50msec/div
Vo(50V/div) ZCS for D4 5µsec/div
(b)
Vds1(100V/div)
1st Operation Stage 2nd Operation Stage 3rd Operation Stage Vgs1(10V/div)

ZVS for S1
5µsec/div
(a)
Vds2(100V/div)
Vgs2(10V/div)
IL1(2A/div) IL1(2A/div)

IL2(2A/div)
ZVS for S2 5µsec/div

Vds3(100V/div) Vgs3(10V/div)

IB(5A/div)

50msec/div ZVS for S3

5µsec/div
(b) (c)
Fig. 8: Converter output voltage and inductors currents during all the Fig. 9: Different waveforms of the converter first experimental stage.
experiment stages.

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Second experimental stage (200msec<t<400msec): In this
stage, the load power step changes to P O=145W by changing
the load resistance to RO≈334Ω. Meanwhile, the converter
second duty ratio is set at d2=0.57, which results in drawing
average current and power from the unidirectional input source
about IL2ave=2A and Pi=80W, respectively. Meanwhile, as the
control system regulates the output voltage via the first control
loop and d1, the average current and power of IBave=+1.56A and
PB=+75W are measured for the battery source, respectively.
Considering these values reveals the converter power losses of
10W and denoting its power efficiency about 94%.
For this experimental stage, the different currents and voltages
waveforms of the converter inductors, power MOSFETs and
the diode are shown in Figs. 10(a)-(b). Again as seen from the
figures, since d1+d2>1 the converter experimental waveforms
comply with those in Fig. 2(a) of the first operation case. Also,
Fig. 10(c) demonstrates the ZVS of the converter power
switches S1, S2 and S3, respectively. As seen from the figure,
before turning on moments of each power switch, its drain-
source voltage has dropped to zero.

IL1(2A/div)
IL2(2A/div) IL1(2A/div)

IL2(2A/div)

IB(5A/div)
IB(5A/div)

5µsec/div 5µsec/div
(a) (a)

IS1(2A/div)
IS1(2A/div)

IS2(2A/div)

IS2(2A/div)
IS3(2A/div)
ID4(2A/div)
ID4(2A/div)
IS3(2A/div)

ZCS for D4 5µsec/div ZCS for D4 5µsec/div

(b) (b)
Vds1(100V/div) Vds1(100V/div)
Vgs1(10V/div) Vgs1(10V/div)

ZVS for S1 ZVS for S1

5µsec/div 5µsec/div
Vds2(100V/div) Vds2(100V/div)
Vgs2(10V/div) Vgs2(10V/div)

ZVS for S2 5µsec/div ZVS for S2 5µsec/div

Vds3(100V/div) V (10V/div) Vds3(100V/div) Vgs3(10V/div)

gs3

ZVS for S3 5µsec/div ZVS for S3 5µsec/div

(c) (c)
Fig. 10: Different waveforms of the converter second experimental stage. Fig. 11: Different waveforms of the converter third experimental stage.

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Table II: Proposed converter comparison with state of the art dual-input converters.
Ref. Voltage Gain
[12] V O  6nV B / d
[13] V O  2V B / (1  d )
[14] V O  (1  n1d )V B / (1  d )
[22] V O  2V B / (1  d )
[24] V O  dV B / n (1  d )
[26] V O  nV B / (1  d )
Proposed V O V B / (1  d )
converter
Third experimental stage (400msec<t<600msec): For the last
experimental stage, the load power does not change and
remains constant at its previous stage value (P O=145W), while
the converter second duty ratio is changed to d 2=0.12. This
settings result in drawing the low average current and power
from the unidirectional input source about IL2ave=0.15A and
Pi=6W, respectively. So, the converter control system tries to
regulate the output voltage through the first control loop, which
results in drawing average current and power of IBave=+3A and
PB=+145W from the battery source, respectively. This power
values gives the converter power losses of 6W and denotes its
power efficiency about 96%. For this experimental stage, the
different currents and voltages waveforms of the converter
inductors, power MOSFETs and the diode are shown in Figs.
11(a)-(b). These waveforms comply with those in Fig. 2(b) of
the converter second operation case since d 1+d2<1. Also, Fig.
11(c), (d) and (e) demonstrate the ZVS of the converter power
switches S1, S2 and S3, respectively. As seen from the figures,
before turning on moments of each power switch, its drain-
source voltage has dropped to zero.
In addition, the proposed converter is successfully employed
to operate in different operation conditions for variable input
and output powers and both charge and discharge operation
modes of the battery. The proposed converter efficiency curve
is measured and illustrated by the Fig. 12. Also, some dual-
input structures as simple as the proposed converter and with
soft-switching operation, presented in [12], [13], [14], [22], [24]
and [24] are found and compared in terms of voltage gain,
numbers of capacitors and inductors, numbers of switching
devices and converter efficiency in Table II. This table shows
that the proposed converter employs classic voltage gain,
minimum number of passive and active power elements, while
achieving a good high efficiency.
Fig. 12. Proposed converter measured efficiency curves.
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Transactions on Power Electronics
Capacitors Inductors Switches Diodes Rated Power Efficiency
6 3 6 2 500W 92-98%With ZVS
2 2 3 1 400W 88-95% With ZVS
2 2 5 0 200W 88-91% With ZVS
3 2 4 0 900W 96-98% With ZVS
1 2 3 1 175W 94-96% With ZVS
2 1 8 0 1000W 89-95% With ZVS
1 2 3 1 200W 93-96% With ZVS
X. CONCLUSION
A new dual-input ZVS dc-dc boost converter is proposed to
harvest and manage powers from a clean energy source and an
energy storage element. The proposed converter basic operation
principle is analyzed in two operation cases. A low-power
laboratory prototype is designed and fabricated to evaluate the
converter performance in the different operation conditions. As
is clear from the experimental results, the converter provides
ZVS performance for all the power switches and ZCS for the
only power diode without any additional auxiliary circuit, and
also for the whole ranges of the system input and output powers.
Considering a simple and useful control scheme, the converter
first duty ratio is employed to regulate the load voltage while
the second duty ratio controls the drawn power from the input
source. As a result, the proposed converter offers simple and
compact structure, minimum number of active and passive
power switches and high power efficiency.
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