AppNote 10961

A P P N O T E S SM

Setting up IBIS Models Compliant with DDRx Wizard and JEDEC

Specifications

By: Tomoyuki Ueda

Last Modified: December 16, 2011

Table of contents
Introduction.................................................................................................................................................... 1
1. IBIS model descriptions used in DDRx Wizard ....................................................................................... 1
1.1. [Diff pin] ........................................................................................................................................ 2
1.2. [Model Selector] ........................................................................................................................... 2
1.3. Timing_location Die (as necessary) ............................................................................................. 3
1.4. [Receiver Thresholds] .................................................................................................................. 3
1.4.1. Offset voltage Vth, Vth_min and Vth_max ....................................................................... 4
1.4.2. AC threshold voltage Vinh_ac and Vinl_ac ...................................................................... 7
1.4.3. DC threshold voltage Vinh_dc and Vinl_dc ...................................................................... 7
1.4.4. Crosspoint voltage Vcross_low and Vcross_high for differential Pos/Neg signals .......... 8
1.4.5. Threshold voltage Vdiff_ac Vdiff_dc for differential composite signals ............................ 8
1.5. [Pin] signal_name ........................................................................................................................ 9
2. Procedures and notes on editing an IBIS model ................................................................................... 10
2.1. Separating [Receiver Thresholds] for single-ended and differential signals .............................. 10
2.2. Adding and Editing [Model Selector] .......................................................................................... 10
2.3. Golden IBIS model ..................................................................................................................... 10

Introduction
Some of the IBIS model descriptions used in DDRx Batch Wizard are not required in the IBIS
specifications, and may not be included in the IBIS model supplied by the vendor. These
undefined specifications can affect the timing analysis results. This AppNote discusses these
optional IBIS model descriptions that may be influential to the outcome of the DDRx Batch
Wizard simulation. We will also look at the thresholds defined in IBIS models for simulation and
their corresponding JEDEC standard. Use this document when adding thresholds to an IBIS
model.

1. IBIS model descriptions used in DDRx Wizard

This section discusses the descriptions not required by the IBIS specifications. If needed, refer to
the device specifications and JEDEC standards and add appropriate descriptions.

December 16, 2011 Page 1 of 11

Copyright © 2011 Mentor Graphics Corporation

Trademarks that appear in Mentor Graphics product publications that are not owned by Mentor Graphics are
trademarks of their respective owners.
Setting up IBIS Models to Be Compliant with DDRx Wizard and JEDEC Specifications

1.1. [Diff pin]

This description defines a differential signal and a pair of pins. It is required for defining
clock (CK), strobe (DQS) and signal pins. HyperLynx uses the description to determine if the
net is a differential signal. In most cases descriptions are included in differential signal pins.
If not, add the description using the below syntax.

[Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max

|Pos Pin Neg Pin Differential Threshold Skew Typ Skew Min Skew Max
|number number Pos/Neg
1 2 200mV 0ns NA NA

When the [Receiver Thresholds] described later in this AppNote for differential signal is not
included, vdiff will be used as the threshold for the differential waveform. In the above
example, timing will be measured with Vdiff_ac = ±200mV.The vdiff thresholds are just
used for measure DQS slew rate, SI measurement delay and overshoot/undershoot in this
case.
1.2. [Model Selector]
Use this description to switch ODTs and specify one of the pin characteristics for use in
simulation. DDRx Wizard allows you to select them under the ODT section. Please be aware
that ODT characteristics must be listed in [Model Selector] in order to use this functionality.

[Model Selector] sample description

[Pin] signal_name model_name R_pin L_pin C_pin
|
1 DQ0 Model Selector name 44.3m 1.99nH0.59pF
・・・
[Model Selector] Model Selector name
DQ_FULL Comments
DQ_ODT50 Comments
DQ_ODT75 Comments
DQ_ODT150 Comments

The Model Selector name is the name of the model defined in the [Pin] section. You can
select the pin’s characteristics from DQ_FULL, DQ_ODT50, DQ_ODT75 or DQODT150
and run simulation.

December 16, 2011 Page 2 of 11

Setting up IBIS Models to Be Compliant with DDRx Wizard and JEDEC Specifications

1.3. Timing_location Die (as necessary)

The measurement is done on the pin by default when there is no specific definition within the
IBIS model. To make a measurement on the die, you need to add “Timing_location Die”
immediately after the [Component] section as shown below. (This information is current as
of HyperLynx8.1.1 Update2.)

[Component] GOLDEN_MODEL
Timing_location Die

[Driver Model]

[Receiver Model]

1.4. [Receiver Thresholds]

Use this description to define AC/DC thresholds for timing analysis of the DDR interface.
IBIS models have three kinds of threshold definition as shown in the example below. In
HyperLynx simulation, they are used in order of [Receiver Thresholds] > [Model Spec] >
[Model].
[Model] DQ_FULL_ODT50
・・・
Vinl = 650.000mV
Vinh = 1.150V
[Model Spec]
Vinl 0.650V 0.600V 0.700V
Vinh 1.150V 1.100V 1.200V
Vref 1.1V 1V 0.9V
December 16, 2011 Page 3 of 11
Setting up IBIS Models to Be Compliant with DDRx Wizard and JEDEC Specifications

[Receiver Thresholds] | for single-ended signals

Vth = 0.900V
Vth_min = 0.882V
Vth_max = 0.918V
Vinh_ac = 0.250V
Vinh_dc = 0.125V
Vinl_ac = -0.250V
Vinl_dc = -0.125V
Threshold_sensitivity = 0.50
Reference_supply Pullup_ref
・・・
[Pullup Reference] 1.800V 1.700V 1.900V
[Receiver Thresholds] | for differential signals
Vcross_low = 0.725V
Vcross_high = 1.075V
Vdiff_ac = 500mV
Vdiff_dc = 250mV

If there is no definition for [Receiver Thresholds], the simulator uses the definition for
[Model Spec] or [Model]. In this case, Setup and Hold timing simulation are run with the
same threshold, since the thresholds for AC and DC are the same. After you run the DDR
Batch Wizard, the log file DDR_log*.txt reports as follows:

** Warning **: DC thresholds are not defined! Using AC thresholds instead!

This section discusses each [Receiver Thresholds] and their corresponding JEDEC standard.
You can use the standard to edit undefined [Receiver Thresholds] by adding them under the
[Model Spec] description.

1.4.1. Offset voltage Vth, Vth_min and Vth_max

[Referenced JEDEC standard]

December 16, 2011 Page 4 of 11

Setting up IBIS Models to Be Compliant with DDRx Wizard and JEDEC Specifications

Use VREF as offset voltage Vth. (For DDR2, Vth = 0.5×1.8V = 0.9 V)
There are no corresponding JEDEC standards for Vth_min and Vth_max.
However, some vendors specify the values as shown below.

In the above example, Vth_min and Vth_max can be calculated as follows (for
DDR2).
Vth_min = 0.49 × 1.8V = 0.882V
Vth_max = 0.51 × 1.8V = 0.918V
The reference offset voltage varies in cornercase analysis. Now, we will take an
example of the [Receiver Thresholds] for single-ended signals on the previous
page and see the offset voltage Vth_Typ, Vth_Fast and Vth_Slow that are used
for Typical, Fast-Strong and Slow-Weak.

Vth_Typ, Vth_Fast and Vth_Slow will take different values in the DDRx Batch
Wizard depending on the presence or absence of the below definitions.
- Threshold_sensitivity
- Reference_supply
[When Threshold_sensitivity and Reference_supply are defined]
Vth_typ, Vth_max and Vth_min will be calculated according to the IBIS standard
below.
(IBIS standard)
Vth(min/max) = Vth* + [(Threshold_sensitivity) * (change in supply voltage)]
 Vth in Fast-Strong
- Vth_max is used for calculation.

December 16, 2011 Page 5 of 11

Setting up IBIS Models to Be Compliant with DDRx Wizard and JEDEC Specifications

Vth_Fast = Vth_max + [0.5 * (Pullup_ref_max - Pullup_ref_typ)] = 0.918V+

[0.5 * (1.9V - 1.8V)] = 0.968V
AC high = 0.968V + 0.25V = 1.218V
AC low = 0.968V - 0.25V = 0.718V
DC high = 0.968V + 0.125V = 1.093V
DC low = 0.968V - 0.125V = 0.843V
 Vth in Typical
- Vth is used for calculation.
Vth_Typ = Vth + [0.5 * (Pullup_ref_typ - Pullup_ref_typ)] = 0.900V + [0.5 *
(1.8V - 1.8V)] = 0.900V
AC high = 0.900V + 0.25V = 1.15V
AC low = 0.900V - 0.25V = 0.65V
DC high = 0.900V + 0.125V = 1.025V
DC low = 0.900V - 0.125V = 0.775V
 Vth in Slow-Weak
- Vth_min is used for calculation.
Vth_Slow = Vth_min + [0.5 * (Pullup_ref_min - Pullup_ref_typ)] = 0.882V +
[0.5 * (1.7V -1.8V)] = 0.832V
AC high = 0.832V + 0.25V = 1.082V
AC low = 0.832V - 0.25V = 0.582V
DC high = 0.832V + 0.125V = 0.957V
DC low = 0.832V - 0.125V = 0.707V

[When Threshold_sensitivity and Reference_supply are not defined]

 Vth in Fast-Strong
- Vth_max is used for calculation.
Vth_Fast = V_max = 0.918V
AC high = 0.918V + 0.25V = 1.168V
AC low = 0.918V - 0.25V = 0.668V
DC high = 0.918V + 0.125V = 1.043V
DC low = 0.918V - 0.125V = 0.793V
 Vth in Typical
- Vth is used for calculation.
Vth_Typ = Vth = 0.900V
AC high = 0.900V + 0.25V = 1.15V
AC low = 0.900V - 0.25V = 0.65V
DC high = 0.900V + 0.125V = 1.025V
DC low = 0.900V - 0.125V = 0.775V
 Vth in Slow-Weak
- Vth_min is used for calculation.
Vth_Slow = Vth_min = 0.882V
AC high = 0.882V + 0.25V = 1.132V
AC low = 0.882V - 0.25V = 0.632V
DC high = 0.882V + 0.125V = 1.007V
DC low = 0.882V - 0.125V = 0.757V

December 16, 2011 Page 6 of 11

Setting up IBIS Models to Be Compliant with DDRx Wizard and JEDEC Specifications

1.4.2. AC threshold voltage Vinh_ac and Vinl_ac

[Referenced JEDEC standard]

Vinh_ac defines the Min characteristics of VIH(ac), and Vinl_ac defines the Max
characteristics of VIL(ac) stipulated by JEDEC, respectively. IBIS model thresholds are
determined by offset voltage. Thus, in the above example, they are calculated as follows.
Vinh_ac = 0.25V(DDR2-400, DDR2-533), 0.2V(DDR-667, DDR-800)
Vinl_ac = -0.25V(DDR2-400, DDR2-533), 0.2V(DDR-667, DDR-800).

1.4.3.DC threshold voltage Vinh_dc and Vinl_dc

[Referenced JEDEC standard]

Vinh_dc defines the Min characteristics of VIH(ac), and Vinl_dc defines the Max
characteristics of VIL(ac) stipulated by JEDEC, respectively. IBIS model thresholds are
determined by offset voltage. Thus, in the above example, they are calculated as follows.
Vinh_dc = 0.125V
Vinl_dc = -0.125V

December 16, 2011 Page 7 of 11

Setting up IBIS Models to Be Compliant with DDRx Wizard and JEDEC Specifications

1.4.4.Crosspoint voltage Vcross_low and Vcross_high for differential Pos/Neg signals

[Referenced JEDEC standard]

Vcross_low defines Min characteristics of VIX(ac), and Vcross_high defines Max

characteristics of VIX(ac) stipulated by JEDEC, respectively. For the above example,
IBIS model thresholds will be calculated as follows (for DDR2).
Vcross_low = 0.5 × 1.8V – 0.175V = 0.725V
Vcross_high = 0.5 × 1.8V + 0.175V = 1.075V

1.4.5.Threshold voltage Vdiff_ac、Vdiff_dc for differential composite signals

[Referenced JEDEC standard]

Vdiff_ac defines Min characteristics of VID(ac) stipulated by JEDEC. In the above

example, an IBIS model threshold will be calculated as Vdiff_ac = 0.5V.
There is no corresponding JEDEC standard for Vdiff_dc. However, some vendors specify
the values as shown below.

December 16, 2011 Page 8 of 11

Setting up IBIS Models to Be Compliant with DDRx Wizard and JEDEC Specifications

Vdiff_dc defines Min characteristics of VID(DC) stipulated by JEDEC. In the above

example, an IBIS model threshold will be calculated as Vdiff_dc = 0.25V.
1.5. [Pin] signal_name
The [Pin] section is defined as in the following example.

Note: A REF file is used to assign models to each component. Therefore, pin names J7 and
K2 must match the component pin numbers laid out in BoardSim.

[Pin] signal_name model_name R_pin L_pin C_pin

J7 DQS0 DQ NA NA NA
K2 DQ1 DQ NA NA NA

Signal_name in this section is referenced when DDR interface signals are automatically
assigned with Perform Automatic Net Mapping functionality enabled under the DRAM
Signals section in the DDR Batch Wizard. The automatic assignment algorithm has typical
signal name used in the DDR interface as the key. Automatic Net Mapping may fail when an
unusual signal name is defined in the IBIS model.

[Clock net]
*CK*
[Strobe net]
*DQS*
[Data net]
*DQ*
[Mask net]
*DM*
[Address net]
A*, BA*
[Command net]
CAS*, RAS*, *WE*
[Control net]
CKE*, ODT*, S*

Change any IBIS model signal name not listed above to the one including the above names.
For example, when pin J7 is strobe signal and pin K2 is data signal as shown below:

December 16, 2011 Page 9 of 11

Setting up IBIS Models to Be Compliant with DDRx Wizard and JEDEC Specifications

[Pin] signal_name model_name R_pin L_pin C_pin

J7 STB0 DQ NA NA NA
K2 DATA1 DQ NA NA NA

Change the signal names as follows (and avoid name conflict with other pins).

[Pin] signal_name model_name R_pin L_pin C_pin

J7 DQS0 DQ NA NA NA
K2 DQ1 DQ NA NA NA

2. Procedures and notes on editing an IBIS model

2.1. Separating [Receiver Thresholds] for single-ended and differential signals
An IBIS model for the DDR interface must have the same [Model] defined for the
characteristics of the data signal DQ and the strobe signal DQS. The DDRx Batch Wizard
simulation also assumes the characteristics for DQ and DQS to be identical. However, we
must make separate definitions of thresholds for single-ended signals (DQ) and deferential
signals (DQ) in the [Receiver Thresholds] created for DDR simulation. It is not possible to
define both in the same [Model] section. See the TechNote below for separating the
thresholds for single-ended and differential signals [Receiver Thresholds].

TechNote mg545826 - Editing DDRx IBIS Model to Use Separate [Receiver Thresholds] for
Single-ended and Differential Signals
2.2. Adding and Editing [Model Selector]
DDRx Batch Wizard allows you to select an ODT model under the ODT section. However,
this is not available when there are individual IBIS model files for each ODT characteristics.
In this case, you have to switch model file assignment using a REF file for every simulation
run. See the TechNote below for how to add the [Model Selector] section to an IBIS model
so that an ODT model can be selected under the ODT section.

TechNote mg545824 - Merging Multiple IBIS Models for Each ODT Characteristics into a
Single IBIS File
2.3. Golden IBIS model
DDRx Batch Wizard simulation references necessary parameters in an IBIS model for
analysis as described above. The TechNote below has a link to download a sample IBIS
model for DDRx Batch Wizard simulation. See the descriptions required for a simulation.
Please note that the characteristics in this golden model are arbitrary and cannot be used for
actual simulation.

TechNote mg548944 - Downloading Sample IBIS Model with Necessary Parameters for
DDRx Wizard Simulations

December 16, 2011 Page 10 of 11

Setting up IBIS Models to Be Compliant with DDRx Wizard and JEDEC Specifications

December 16, 2011 Page 11 of 11

Copyright © 2011 Mentor Graphics Corporation

Trademarks that appear in Mentor Graphics product publications that are not owned by Mentor Graphics are trademarks
of their respective owners.