Regulation – 2019 Academic Year 2023-2024

IFET COLLEGE OF ENGINEERING

(An Autonomous Institution)
DEPARTMENT OF ECE
SUBJECT CODE: 19UECPC401 SEM : IV
SUBJECT NAME: LINEAR INTEGRATED CIRCUITS YEAR: II
Application Question -Solved

UNIT 4- REGULATORS AND PLL

IC Voltage regulators – Three terminal fixed and adjustable voltage regulators – IC 723
general purpose regulator. PLL: Operation of the basic PLL, Voltage controlled oscillator,
Monolithic PLL IC 565 & PLL Applications.

14 Enlist any four applications of NE565 PLL. A

• Frequency Modulation (FM) stereo decoders, FM Demodulation networks
for FM operation.
• Frequency synthesis that provides multiple of a reference signal frequency.
• Used in motor speed controls, tracking filters.
• Used in frequency shift keying (FSK) decodes for demodulation carrier
frequencies.
15 The free running frequency of a PLL is 300 kHz and the bandwidth of low A
pass filter is 10 kHz. Will the PLL acquire the lock for the input signal of
320 kHz. Also, what happens if the cut-off frequency of the LPF is 25 kHz.
Solution: The phase detector output will be
fs + fo = 320 kHz + 300 kHz
= 620 kHz
fs - fo = 320 kHz - 300 kHz
= 20 kHz
If the bandwidth of the LPF is 10 kHz, then the PLL will not lock. However, for
25 kHz bandwidth, PLL will lock.
16 Illustrate how frequency stability is obtained in a PLL by use of a VCO. A
PLL is an electronic circuit that is used to lock the output frequency of
the voltage-controlled oscillator with the desired input frequency by constantly
comparing the phase of the input frequency with that of the output frequency of
the VCO. The PLL is used to generate a signal, modulate, or demodulate it.
20 Predict when does PLL circuit gets locked. A
The process of acquiring of a lock of frequency with an input signal is called
capturing and capturing continues till the output frequency of VCO is same as
the input signal frequency.
➢ Once the two frequencies are same the circuit is said to be locked.
➢ In locked condition, phase detector generates a constant dc level which is
required to shift the output frequency of VCO from center frequency to the
input frequency. Once locked, PLL tracks the frequency changes of the
input signal.
25 PLL is both linear and Non-linear in nature-Justify the answer. A
➢ PLL consist of a Gilbert type phase detector, a temperature-compensated
VCO and facility for connecting an external RC circuit to perform the loop-
filter function
➢ Under locked conditions a linear relationship can exist between the output
voltage of the phase detector and the phase difference between the VCO and
the input signal.
➢ The non-linearity of the phase detector makes the PLL nonlinear.
Regulation – 2019 Academic Year 2023-2024

So, PLL acts both in linear and non-linear in nature.

26 Express the close loop transfer function for a PLL system in terms of Loop A
Bandwidth.
The close loop transfer function for a PLL system is given by
Vf K F (s) A
=
S s + K Kv AF (s)
if loop-filter is not used, and F(s)=1 then,
Vf K A KL 1
= =( )
S s + K Kv A s + K L Kv
where KL = KφKvA and it is known as loop bandwidth. In terms of loop
parameters, KL is simply the product of the phase detector gain Kφ, VCO transfer
coefficient and the electrical gain provided by the amplifier.
27 A PLL has free running frequency of 500 kHz and bandwidth of the low A
pass filter is 10 kHz. Will the loop acquire lock for an input signal of 600
kHz?
Justify the answer. Assume that the phase detector produces sum and
difference frequency components.
Solution: The phase detector will produce
fi + fc = 600 kHz + 500 kHz = 1100 kHz
fi - fc = 600 kHz - 500 kHz = 100 kHz
both sum and different frequency components are outside the passband of the
low pass filter. Hence, the loop will not acquire lock.
31 Illustrate the limitations of three terminal regulators and how it is overcome A
by IC723 regulator?
The general three terminal regulators have the following limitations
i) No short circuit protection
ii) Output voltage is fixed.
These limitations have been overcome in the 723 general purpose regulator,
which can be adjusted over a wide range of both positive or negative regulated
voltage.
34 In a VCO if input signal frequency fs = 20 kHz, free running, frequency f0 = A
21 kHz/V, voltage to frequency conversion factor Kv is 4kHz/V, find the
change in the dc control Vc during lock
Solution: The voltage to frequency conversion factor
f
Kv = o
VC
f o
VC =
Kv
Frequency shift
f o = 21 kHz − 20 kHz
=1 kHz
1 X 103
V = V
Therefore, 4 X 103
= 0.25V
38 Construct the circuit diagram of PLL circuit used in FM detection. A
FM signal can be demodulated using PLL. When the PLL is locked in on the
FM signal, the VCO frequency follows the instantaneous frequency of the FM
Regulation – 2019 Academic Year 2023-2024

signal, and the error voltage or VCO control voltage is proportional to the
deviation of the input frequency from the center frequency.

39 Can FM signal be demodulated using PLL? If yes, sketch the circuit. A

Yes, FM signal can be demodulated using PLL. The faithful reproduction of
modulating voltage depends on the linearity between the instantaneous
frequency deviation and the control voltage of VCO.

40 Mention the need for frequency synthesizer. Relate how PLL is acting as a A
Clock synchronizer.
A frequency synthesizer allows the designer to generate a variety of
output frequencies as multiples of a single reference frequency. The main
application is in generating local oscillator (LO) signals for the up- and down-
conversion of RF signals. The phase-locked loop can track an input frequency,
or it can generate a frequency that is a multiple of the input frequency. These
properties are used for computer clock synchronization.

Part B
2 ii) Design a regulator using IC723 to meet the following specifications:VO = A
5 V, IO = 100 mA, Vin = 15 ±20 % , ISC = 150 mA, Vsense = 0.7 V. (8)
Solution: The given specifications are
VO = 5 V, IO = 100 mA
Vin = 15 ±20 %
ISC = 150 mA
Vsense = 0.7 V
V 0.7
Now Rsc = sense = = 4.67 
I sc 150 X 10−3
Neglecting input bias current of an error amplifier we can write,
Regulation – 2019 Academic Year 2023-2024

Vref − Vo
R1 =
ID
where I D = Potential divider current = 1 mA
and Vref = 7.15 V for IC 723
7.15 − 5
 R1 = = 2.15 k 
1X 10−3
Use 2.2 k  s tan dard resis tan ce.
R2
Now Vo = Vref .
R1 + R2
R2
 5 = 7.15.
(2.2 + R2 )
 2.2 + R2 = 1.43 R2
 R2 = 5.11 k 
Use 5.1 k  s tan dard resis tan ce
R3 = R1 || R2
2.2 X 5.1
= = 1.536 k 
2.2 + 5.1
Use1.5 k  s tan dard resis t or.
The design of the regulator is shown in figure.

5 i) The free running frequency of a 565 PLL is 100 kHz, the filter capacitor A
is 2 µF and supply voltage is ±6V. Compute the lock-in range and capture
range frequency and the value of external components RT and CT. (8)
Solution: Given fo = 100 kHz,
C = 2µF and
VCC = 6V.
The lock-in range is given by
7.8 f o
f L = 
V
7.8 f o
=
VCC − (−VCC ) (3)
7.8 X 100
=
6 − (−6)V
=  65 kHz
Regulation – 2019 Academic Year 2023-2024

Thus lock-in range = ±65 kHz

The capture range, 2ΔfC is given by
f L
2fC = 
2 X (3.6 X 103 )C
Putting the value and solving, we get
2Δfc = 2.397 kHz (3)
The free running frequency, fo is
0.25
fo =
RT CT
Assuming RT = 10KΩ,
CT = 250 pF (2)
6 (i) Compute the free running frequency fo, lock-in range and capture range A
of PLL 565. Assume RT=20 KΩ, CT=0.01 µF, C=1 µF and supply voltage is
±6V. (8)
Solution:
The free running frequency of VCO is
0.25
fo =
RT CT
0.25
=
10 X 10 X 0.01X 10−6
3
(2)
= 2.5 kHz

The lock in range is given by

7.8 f o
f L = 
V
7.8 X 2.5 X 103
= (3)
12
= 1.62 kHz

The capture range is given by

f L
2f C =
2 X (3.6 X 103 )C
2 X 1.62 X 103
= (3)
2 X (3.6 X 103 ) X 1X 10−6
= 378 Hz
8 (i) Demonstrate the application of PLL as AM detector and FM A
Demodulator. (8)
AM detection: In an AM detector, the PLL is locked to the carrier frequency
of the incoming AM signal. The output frequency of VCO is same as the carrier
frequency, but unmodulated is fed to the multiplier. Since VCO output is always
90˚ out of phase with the incoming AM signal under the locked condition, the
AM input signal is also shifted in phase by 90˚ before being fed to the multiplier.
This makes both the signals applied to the multiplier in same phase. The output
of the multiplier contains both the sum and difference signals, the demodulated
output is obtained after filtering high frequency components by the LPF. Since
the PLL responds only to the carrier frequencies which are very close to the
VCO output, a PLL AM detector exhibits a high degree of selectivity and noise
Regulation – 2019 Academic Year 2023-2024

immunity which is not possible with conventional peak detector type AM

modulators. (2)

(2)
FM demodulator: (2)
FM signal can be demodulated using PLL. When the PLL is locked in on
the FM signal, the VCO frequency follows the instantaneous frequency of the
FM signal, and the error voltage or VCO control voltage is proportional to the
deviation of the input frequency from the centre frequency. Therefore, the a-c
component of error voltage or control voltage of VCO will represent a true
replica of the modulating voltage that is applied to the FM carrier at the
transmitter. The faithful reproduction of modulating voltage depends on the
linearity between the instantaneous frequency deviation and the control voltage
of VCO.
It is also important to note that the FM frequency deviation and the
modulating frequency should remain in the locking range of PLL to get the
faithful replica of the modulating signal. If the product of the modulation
frequency fm and the frequency deviation exceeds the (Δ fc)2 , the VCO will not
be able to follow the instantaneous frequency variations of the FM signal.

(2)

(ii)Demonstrate the application of PLL as FSK Demodulator and Frequency A

synthesizer. (8)
FSK demodulator: (2)
A PLL can be used as a FSK demodulator, as shown in figure. It is
similar to the PLL demodulated for analog FM signals except for the addition of
a comparator to produce a reconstructed digital output signal.
Let us consider that there are two frequencies, one frequency (f1) is represented
as “0” and other frequency (f2) is represented as “1”. If the PLL remain locked
Regulation – 2019 Academic Year 2023-2024

into the FSK signal at both f1 and f2, the VCO control voltage is also supplied to
the comparator will be given as
VC1 = (f1 – f0) / kV
VC2 = (f2 – f0) / kV , respectively.
Where is the voltage to frequency transfer coefficient of the VCO.
The difference between the two control voltage levels will be Δ VC = (f2 – f1) /
kV.
The reference voltage for the comparator is derived from the additional low pass
filter and it is adjusted midway between VC1 and VC2. Therefore, for VC1 and
VC2, comparator gives output ‘0’ and ‘1’, respectively.

(2)
Frequency synthesizer: (2)
The frequency synthesizer is similar to a frequency multiplier circuit except that
divided by M network is added at the input of phase locked loop. The frequency
of the crystal controlled oscillator is divided by an integer factor M by divider
network to produce a frequency fosc/M, where fosc is the frequency of the crystal
controlled oscillator.
The VCO frequency fVCO is similarly derived by factor N by divider network to
give frequency equal to fVCO/N. When the PLL is locked in on the divided-down
oscillator frequency, we have fosc/M= fVCO/N, so that fVCO= (N/M) fosc
By adjusting divider counts to desired values large number of frequencies can be
produced, all derived from the crystal controlled oscillator.

(2)