Digital Logi

Logic Design Unit 1
Unit 1 Number Systems

Structure:
1.1 Introduction
Objectives
1.2 Decimal Number System
1.3 Binary Number Systems
1.4 Octal number systems
1.5 Hexadecimal Number systems
1.6 Negative Number Representation
Signed Magnitude Representation
1’s Complement
2’s Complement
1.7 Conversion from one number system to other number system
1.8 Complements Arithmetic
1.9 Summary
1.10 Terminal Questions
1.11 Answers
1.1 Introduction
The number system is a collection of number to represent the quantifiable
information. Most of the computations in the number systems are addition,
subtraction, multiplication, division, etc. we usually perform all calculation
using the decimal number system.
In decimal number system we have ten different digits or symbols i.e. 0, 1, 2,
3, 4, 5, 6, 7, 8 and 9. The combination of this number gives quantifiable
values. To represent these values in the electronics world, we don’t have
the hardware, so there was need for the hardware which can represent the
any one number system. The invention of transistor, have triggered the
engineers to make use of the binary number system. The binary numbers
system have only two values i.e., 0, 1. With the help of the transistor we can
represent the two states (0, 1) of the number.
The invention of transistor made a remarkable change in the electronic
world especially in computer science. The transistor acted as a switch, able
to represent the binary number. In computer, the computations are not
Manipal University Jaipur B0948 Page No. 1

Logic Design Unit 1
carried similar to the normal day to day computation. Enormous numbers of

algorithms are developed to carry out the computation operations.
There is a need of human computer interpretation requirement because
human requires the value must be represented in the decimal systems
whereas the computer computes internal value in binary systems. So there
was a need of binary to decimal interpretation representation system and it
is called Binary Coded Decimal (BCD). All decimal numbersare converted
into the binary and then computation is performed and later is converted
back into the decimal system.
The encoding of data in digital system is common. Since we know that the
computer can only understand binary, there is a need for the conversion of
alphabets and other special characters also into the binary. The different
encoding and decoding has designed to suite the requirements. In this unit,
we will discuss the different numbering system and their conversion
between across the different numbering system.
Objectives:
By the end of Unit 1 the learners are able to:
 list and explain the different numbering systems.
 explain the negative number representation
 explain conversion techniques in number systems
 perform complements arithmetic
1.2 Decimal Number Systems

From the kindergarten to nowadays, we are exposed only to the decimal
number systems.
A decimal number system has ten different digits or symbols. They are 0, 1,
2, 3, 4, 5, 6, 7, 8 and 9. The base (or radix) of a number system is the
number of different symbols available to represent any digit within that
system. For example, the base or radix of decimal number system is 10 as
there are ten different digits.We represent the value with base i.e. 2510 here
the number 25 represent the quantifiable value and the number 10
represent the base of the decimal numbering system.
Example 1.1: How do you represent decimal number 456710?

Logic Design Unit 1
This number is represented as

4 x 103 + 5 x 102 + 6 x 101 + 7 x 100
The number position always starts from Zero. Here if you observe
7 is in 0th position it give value 7
6 is in 1st position it gives value 60
5 is in 2nd position it gives value 500
4 is in 3rd position it gives value 4000
Summing all together we get the value is 456710.
All decimal number is split into two parts. The value before dot and the
value after dot. The value before dot is an absolute vale and the value after
dot is a fractional value.
Example 1.2: How do you represent decimal number 4567.890110?
This number can represented as
4 x 103 + 5 x 102 + 6 x 101 + 7 x 100 . 8 x 10-1 + 9 x 10-2 + 0 x 10-3 + 1 x 10-4
The number is position is given as
The value before dot
7 is in 0th position it give value 7
6 is in 1st position it gives value 60
5 is in 2nd position it gives value 500
4 is in 3rd position it gives value 4000
The value after dot
8 is in -1st position it give value 0.8
9 is in -2nd position it gives value 0.09
0 is in -3rd position it gives value 0.000
1 is in -4th position it gives value 0.0001
Summing all together we get the value 4567.890110
1.3 Binary Number Systems

The word bi means two.Binary number system has only two digits or
symbols. They are 0 and 1. Hence the base of this number system is 2.
Numbers represented in this system are commonly called binary numbers.
The digit 0 or 1 is called binary digit (Bit).The use of binary number system
came to existence because of the computer. The transistor can represent
the value ‘0’ by off state and the value “1” by on state.

Logic Design Unit 1
Example 1.3: How to represent the binary value “1010” in decimal format?
1 x 23 + 0 x 22 + 1 x 21 + 0 x 20
The decimal representation is
8 + 0 + 2 + 0 = 1010
Example 1.4: How do you represent the binary value 1010.101 in decimal
format?
1 x 23 + 0 x 22 + 1 x 21 + 0 x 20. 1 x 2-1 + 0 x 2-2 + 1 x 2-3
The binary representation is
8 + 0 + 2 + 0 . 0.5 + 0.0 + 0.125 = 10.62510
1.4 Octal Number Systems

In octal number system, there are eight different digits or symbols. They are
0, 1, 2, 3, 4, 5, 6 and 7. Since there are eight digits, the base of the octal
number system is 8.
Example 1.5: How do to represent the octal value “1760” in decimal format?
1 x 83 + 7 x 82 + 6 x 81 + 0 x 80
512 + 448 + 48 + 0 = 100810
Example 1.6: How do you represent the octal value 1760.154 in decimal
format?
1 x 83 + 7 x 82 + 6 x 81 + 0 x 80. 1 x 8-1 + 5 x 8-2 + 4 x 8-3
512 + 448 + 48 +0+0.125 + 0.078125 + 0.0078125 = 1008.210937510
1.5 Hexadecimal Number Systems

The base of Hexadecimal number system is 16, means there are sixteen
different symbols or digits. They are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,
E, F.
Where A = (10)10, B = (11)10 , C = (12)10 , D = (13)10, E=(14)10 and F = (15)10

Logic Design Unit 1
Example 1.7: How to represent the Hexadecimal value “1A3F” in decimal

format?
1 x 163 + A x 162 + 3 x 161 + F x 160
1 x 163+ 10x 162+ 3 x 161 + 15x 160
4096 + 2560 + 48 + 15 = 671910
Example 1.8: How do you represent the hexadecimal value “1A3F.C0E” in
decimal format?
1 x 163 + A x 162 + 3 x 161 + F x 160.C x 16-1 + 0 x 16-2 + E x 16-3
4096 + 2560 + 48 + 15+0.75 +0 +0.0034179= 6719.753417910
The table 1.1 says about the collection of the binary number as
Table 1.1: Acronyms
4 bits Nibble
8 bits Byte
16 bits Half Word
32 bit Word
The binary presented in two ways little endian and big endian method are as
shown in the tables 1.2 and 1.3 respectively. Most of computer architecture
has been designed based on either of this format to transfer the data across
the system. The Least Significant Bit (LSB) where the value has least place
holder value. The Most Significant Value (MSB), where the value has
highest place holder value.
Table 1.2: Big Endian Method
1 0 1 0 1
MSB LSB

Logic Design Unit 1
Table 1.3: Little Endian Method

1 0 1 0 1
LSB MSB
1.6 Negative Number Representation

The negative number has represented in many ways, they are
 Signed magnitude
 1’s complement
 2’s complement
1.6.1 Signed Magnitude Representation
The signed magnitude representation is one of the methods to represent the
negative and positive number in binary system. It is a regular binary
representation with addition of one more bit in the MSB side represent the
number is negative or positive. The MSB “0” represent the positive value
and MSB “1” represent the negative value.
The range for this representation is: - 2n-1 -1 to + 2n-1 -1
The drawbacks of this representation are: It has both positive and negative
zero, and complex architecture required for computation.
1.6.2 1’s Complement
The 1’s complement is slightly different from the signed magnitude number.
All binary bits are complemented and represented along with the sign bit. As
shown in table 1.4
The range function for this representation is: - 2n-1 -1 to + 2n-1 -1
The drawbacks of this representation are: It has both positive and negative
zero and complex architecture required for computation.
1.6.3 2’s Complement
The 2’s Complement is asymmetric system with additional bit is required to
represent any numbers. The binary bits are complemented and added 1
with it.The range function for this representation is: - 2n-1 to + 2n-1 -1.The
addition and subtraction can be performed using same hardware. The table
1.4 shows the comparison of negative number systems.

Logic Design Unit 1
Table 1.4: Comparisons of Negative Number Systems

Signed 1’s 2’s
Decimal
Magnitude Complement Complement
-8 – – 1000
-7 1111 1000 1001
-6 1110 1001 1010
-5 1101 1010 1011
-4 1100 1011 1100
-3 1011 1100 1101
-2 1010 1101 1110
-1 1001 1110 1111
-0 1000 1111 –
+0 0000 0000 0000
+1 0001 0001 0001
+2 0010 0010 0010
+3 0011 0011 0011
+4 0100 0100 0100
+5 0101 0101 0101
+6 0110 0110 0110
+7 0111 0111 0111
1.7 Conversion from one number system to other number

system
From the earlier example from 1.1 to 1.8 was showing how to convert from
all number system to decimal. From here onwards, we will see how to
convert the number from decimal to all other number systems.
The decimal number must be divided by the base of the other number
systems to convert decimal number (i.e. Integer part) to other numbering
system. For example, if we want to convert the decimal number to binary
number system, we must divide the decimal number by 2 repeatedly till our
quotient becomes zero as shown in example 1.9. The reminder moving from
the bottom to top will be our binary number. It is similar for all other number
system.

Logic Design Unit 1
Example 1.9: How to convert 10010 into binary, octal and hexadecimal?
So far we have studied the decimal number to other number system without
fraction. Now we will concentrate on the fractional conversion.
The fractional decimal number must be multiplied by the base of the other
number system to convert it into other number systems as shown in
example 1.10. For example decimal number is to be converted into the
binary. Fractional part has to be multiplied by 2 repeatedly till we will make
the fractional part zero. If the fractional part goes on and on, we can
terminate in between.
Example 1.10: How to convert 100.26510 into binary, octal and
hexadecimal?
Let us take the integer part first and convert it to other number systems.

Logic Design Unit 1
Now for the fractional part, we follow the multiplication process as shown
below:
Therefore,
100.26510= (1100100.0100)2 ; 100.26510=(144.20753)8 ;
100.26510= (64.43D70)16
Now before we convert number from octal to binary and vice versa, one has
to know the equivalent numbers for both the systems. The table 1.5 shows
the octal numbers with its equivalent the binary numbers.
Table 1.5: Octal numbers with equivalent binary number formats
Octal Binary
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
From the table 1.5, it is clear that any octal digit can be represented by a
group of three binary digits (or Bits)
To covert any hexadecimal number to binary and vice versa, refer the table
1.6 which shows the binary equivalent for the hexadecimal numbers. The
table 1.6 also gives the comparison of all the four number systems

Logic Design Unit 1
Table 1.6: Comparison of decimal values with other number formats

Decimal Binary Octal Hexadecimal
0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F
From the table 1.6, it is clear that any hexadecimal digit can be represented
by a group of four binary digits (or Bits)
Example 1.11: Convert the 61358 into binary value
In this example, we can replace all independent value into equivalent 3-bit
binary value as shown below to get our answer.
6 1 3 58
110 001 011 1012
Example 1.12: Convert (6135.2478)8 into binary value
Similar with the example 1.11, here we will replace equivalent 3 bit binary
value to represent the octal value.
6 1 3 5 . 2 4 78
110 001 011 101 . 010 100 1112
Example 1.13: Convert 1A2C16 into Binary Value.
In this example, we can replace all independent value into 4-bit binary
equivalent as shown below to get our answer.
1 A 2 C16
0001 1010 0010 11002
Logic Design Unit 1
Example 1.14: Convert 1A2C.3B4D16 into Binary Value.

In this example, we can replace all independent value into 4-bit binary
equivalent as shown below to get our answer irrespective of its position.
1 A 2 C . 3 B 4 D16
0001 1010 0010 1100 . 0011 1011 0100 11012
1.8 Complements Arithmetic

This is a powerful yet simple technique which minimizes the hardware
implementation of signed arithmetic operations in a digital machine. In
practice, when using complement arithmetic, the process of subtraction
becomes one of addition.
In any number system, complements are available. In the binary system
they are
a) 2's complement or radix complement
b) 1's complement or diminished radix complement.
For the decimal number system, they are:
a) 10's complement or radix complement
b) 9's complement or diminished radix complement.
The tables 1.7 and 1.8 show the rules for binary addition and subtraction
respectively.
Table 1.7: Addition
Value 1 Value 2 Carry Sum

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Table 1.8: Subtraction
Value 1 Value 2 Borrow Difference

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

Logic Design Unit 1
It is worth noting that the use of the 1's complement in the binary system
raises certain hardware implementation difficulties so that signed arithmetic
processes are invariably performedusing 2's complement notation.
The major advantage of 2's complement over 1's complement is that 2's
complement has only one value for zero. One's complement has a "positive"
zero and a "negative" zero which is the disadvantage of 1's complement.
Also note that there is no addition of end around carry in 2’s complement
method.
Example 1.15: Compute binary arithmetic operation for 9 – 5 using 2’s
Complement.
Note: Refer table 1.4 for the equivalent values.
Here keep the binary equivalent of 9 (1001) as it is and keep the 2’s
complement equivalent of 5 (1011) and add both vales to get the result 4,
ignore carry generated MSB bit.
1001
1011
10100
Discarding the carry (i.e. 1), we get the answer 0100 which is equal to 4 in
decimal.
Example 1.16: Compute Binary arithmetic Operation for 9 – 5 using 1’s
Complement.
Note: Refer table 1.4 for the equivalent values.
Here keep the binary equivalent of 9 (1001) as it is and keep the 1’s
complement equivalent of 5(1010) and add both vales to get the partial
result and add the carry value in the LSB to get the result 4.
1001
1010
10011
+1
0100
Excess Notation
The excess notation is a means of representing both negative and positive
numbers in a manner in which the order of the bit patterns is maintained.
Logic Design Unit 1
The algorithm for computing the excess notation bit pattern is as follows:
1. Add the excess value 2N-1, (where N is the number of bits used to
represent the number) to the number.
2. Convert the resulting number into binary format.
The 2N–1 is often referred to as the Magic Number for computing the excess
representation of the number (except that there is no magic in it). Table 1.9
presents all the numbers that can be represented using the excess-8
notation.
Table 1.9: Numbers using the Excess-8 representation
Number Excess Number Bit Pattern

7 15 1111
6 14 1110
5 13 1101
4 12 1100
3 11 1011
2 10 1010
1 9 1001
0 8 1000
-1 7 0111
-2 6 0110
-3 5 0101
-4 4 0100
-5 3 0011
-6 2 0010
-7 1 0001
-8 0 0000
The number of bits used to represent a code in excess-8 is 4 bits. Also, the
bit patterns are in sequence (the largest number that can be represented
has the bit pattern 1111).
Example 1.17: Consider the following operation 7 – 2. Substituting the bit
patterns from the table:
The result of the addition operation is the bit-pattern used for 5 in binary.

Logic Design Unit 1
The excess notation representation however takes longer to compute than

the 2’s complement notation. The excess notation will however play an
important part in computing floating-point representations.
Bias Notation
The excess notation is a special case of the biased notation. For instance,
excess-8 is biased around 8 (i.e.0 has the bit pattern associated with
decimal 8). Instead of using the magic number, any number (bias) can be
used.
Note: This concept becomes important when we address the IEEE Single
Precision Floating-Point standard.
Floating-Point Notation
The floating-point notation is used:
a. To represent integers that are larger than the maximum value that can
be held by a bit-pattern (the maximum value that can be held by 8 bits is
255).
b. To represent real numbers.
Large Integers
Consider a really large number 1,234,567. The number requires seven
places to represent the value. If the number of places available to represent
the number is limited to say four places, certain digits have to be dropped.
The selection of digits to be dropped is based on the value associated with
the digit. In this case, we will drop the last three digits ‘567’.
The resulting number is:
1,234,000
The loss of ‘567’ is a loss of precision but if the most significant digits were
to be eliminated, says ‘123’, and then the resulting number is 4,567, which
presents an even greater loss of precision.
Rules for determining significance (integers):
1. A nonzero digit is always significant
2. The digit '0' is significant if it lies between other significant digits
3. The digit '0' is never significant if it precedes all the nonzero digits
Self Assessment Questions
1. Decimal means base __________.
2. The decimal value of the bit pattern 11111111 is _________.
Logic Design Unit 1
3. The range of values represented by an 8-bit binary number is _____.

4. The binary equivalent of 228 is _________.
5. The result of 7 – 2 using 1’s complement notation is ____________.
6. The bit pattern 1011 in 1’s complement notation is __________.
7. The result of 7 – 2 using 2’s complement notation is __________.
8. The bit pattern 1110 in 2’s complement notation is ___________.
9. The 2N–1 is often referred to as the ______________ for computing the
excess representation of the number.
10. The significant digits of 0012340 are _______.
11. The bit pattern 1101 Excess Number converted value is ________.
1.9 Summary
Let us recapitulate the important concepts discussed in this unit:
 In decimal number system, we have ten different digits or symbols
i.e. 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.
 The base of octal number system is 8, means the number system has
eight different digits 0, 1, 2, 3, 4, 5, 6 and 7.
 Any octal digit can be represented by a group of three binary digits (or
Bits)
 In Hexadecimal number system, we have sixteen different digits or
symbols i.e. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and A, B, C, D, E and F.
 The negative number can be represented in many ways. They are
Signed magnitude, 1’s complement and 2’s complement.
 2’s complement is obtained by complementing the binary digits i.e. bits
and then 1 is added to it.
 The major advantage of 2's complement over 1's complement is that 2's
complement has only one value for zero.

1. Convert the following binary numbers to base 10:
a. 10101101
b. 110110.1
2. Convert the following octal numbers to base 10:
a. 273
b. 1021
Logic Design Unit 1
3. Convert the following hexadecimal numbers to base 10:

a. 145
b. A2C1
4. Convert the following decimal numbers to base 2:
a. 122
b. 98
5. Convert the following decimal numbers to hexadecimal:
a. 1145
b. 2421
6. Perform the following binary arithmetic operations
a. 101011 + 10111
b. 1101 + 1110 + 1001
c. 11101 –10110
d. 1100.010 – 1000.111
7. Write the 8-bit signed magnitude, 2's complement and 1's complement
form of the following decimal numbers:
a. + 119
b. – 77
c. – 3
8. Perform the following arithmetic operations using 2's complement
a. 9 – 8
b. 10 - 6
1.11 Answers
1. 10
2. 255
3. 0 to 255.
4. 11100100
5. (0101)
6. (0100)2
7. (0101)
8. 0010
9. Magic Number

Logic Design Unit 1
10. 0012340
11. 13
Terminal Questions
1. Refer to Section 1.3 for conversion method
2. Refer to Section 1.4 forconversion method
7. Refer to Section 1.6 for method
8. Refer to Section 1.8 for 2’s complement subtraction method

Logic Design Unit 2
Unit 2 Boolean Algebra

Structure:
2.1 Introduction
Objectives
2.2 Rules & Laws of Boolean Algebra with Derivations
2.3 Basic Gates (NOT, AND & OR)
2.4 Universal Gates (NAND & NOR)
2.5 Exclusive-OR & Exclusive-NOR Gates
2.6 Exercises on Realizing Circuits with Universal Gates
2.7 Summary
2.9 Answers
2.1 Introduction
In the last unit, you studied about the different types of number systems and
their conversion from one number system to other. You also studied the
methods of representing negative numbers. The components in computer
accept set of inputs and produce outputs depending upon their functionality.
Any basic 2 state (state-1 & state-0) units can be used to construct the
digital circuits. These basic units can be represented as a switch based on
their state (ON or OFF). In this unit, you will study about the Boolean
algebra, basics of logic gates and realization of other gates or logic function
using universal gates.
Objectives:
By the end of Unit 2, the learners are able to:
 list rules & laws of Boolean algebra
 explain basic gates
 explain universal gates
 explain exclusive OR gate and exclusive NOR gate
 exercise on realizing circuits with universal gates

Logic Design Unit 2
2.2 Rules & Laws of Boolean Algebra with Derivations

Boolean Operators
Boolean operators include sum, product and complement. The complement
operator is represented by a single quote. The complement operations are
the following:
0' = 1
1' = 0
The Boolean sum operator is represented by “+” or “OR”. The sum
operations are the following:
0 + 0 = 0 (or) 0 OR 0 = 0
0 + 1 = 1 (or) 0 OR 1 = 1
1 + 0 = 1 (or) 1 OR 0 = 1
1 + 1 = 1 (or) 1 OR 1 = 1
The Boolean product operator is represented by “•” or “AND”. The product
operations are the following:
0 • 0 = 0 (or) 0 AND 0 = 0
0 • 1 = 0 (or) 0 AND 1 = 0
1• 0 = 0 (or) 1 AND 0 = 0
1 • 1 = 1 (or) 1 AND 1 = 1
In product operations, the • operator can be dropped while using the
algebraic expression, i.e., “x • y” can be represented as “xy” (because x • y
= xy). The precedence rules for these Boolean operators are: complement,
product, and sum.
Example:
1 • 1 + (0 + 1)’ = 1 • 1 + 1’
=1•1+0
=1+0
=1
Boolean Identities
Identity Name
(a')' = a Involution Law
a + a' = 1 Complementarity
a • a' = 0

Logic Design Unit 2
a + a = a Idempotent Laws
a•a=a
a + 0 = a Identity Laws
a•1=a
a+1=1 Dominance Laws

a•0=0
a + b = b + a Commutative Laws
ab = ba
a + (b + c) = (a + b) + c Associative Laws
a(bc) = (ab)c
a + bc = (a + b)(a + c) Distributive Laws

a(b + c) = ab + ac
(ab)' = a' + b' DeMorgans Laws

(a + b)' = a'b'
a + (ab) = a Absorption Laws

a(a + b) = a
a + a'b = a + b Redundancy Laws

a(a' + b) = ab
ab + a'c + bc = ab + a'c Consensus Laws

(a+b)(a'+c)(a+c) = (a+b)(a'+c)
In Boolean algebra, the duality principle will be applicable to all the Boolean
identities. The difference between the given identity and its dual is “•”
interchanged with “+”, and “0” interchanged with “1”. Any Boolean theorem
which has been proved will be true for the dual of the theorem.
Truth tables or other identities can be used to prove the Boolean identities.
For example, the distributive law is proven true by the last two columns of
the table 2.1.
Logic Design Unit 2
Table 2.1: Distributive law
A proof of the absorption law x (x + y) = x using identities:

X (x + y) = (x + 0) (x + y) identity law
= x + 0 • y distributive law
= x + y • 0 commutative law
= x + 0 dominance law
= x identity law
In building digital circuits by using Boolean algebra, the following two basic
problems need to be solved.
1) How the Boolean expression can be derived from a given table of values
for a Boolean function?
2) Can the Boolean function be represented with an optimum set of
operators?
First, question, How the Boolean expression can be derived from a given
table 2.2 of values for a Boolean function?

Logic Design Unit 2
Table 2.2: Boolean expression
From the above table of values, the function F is 1 when y = z = 1 and x = 0.

And hence, we get the expression x’yz i.e., the value of the function F will
be 1 if and only if x’ = y = z = 1.
The function G will have value 1 in two cases: y = z = 1, x =0, and x = y = 0,
z = 1. From the above information, the expression for G can be represented
in the sum of two product terms: x’yz + x’y’z
The above method explains the way to construct a Boolean expression from
the values of a Boolean function. A Boolean product m1, m2, m3…mn is
said to be a minterm of Boolean variables x1, x2, x3,…xn if mi = xi or mi =
xi’. Only if all the variables of minterm are 1, the minterm product will result
in 1. For the 1st scenario discussed above, x’yz will only be the minterm that
has the value 1. In other words, a Boolean expression for a Boolean
function can be quoted as the sum of the minterms. Minterms referred here
are those with value 1 for a given combination.
Boolean sum discussed above is also referred to as sum of products (SOP)
expansion or disjunctive normal form.
Maxterm is the dual of Minterm. It is also referred to as product of sums
(POS) or conjunctive normal form. Duality can be observed from the
table 2.3.

Logic Design Unit 2
Table 2.3: Duality

x y z minterm maxterm
0 0 0 a'b'c' a+b+c
0 0 1 a'b'c a+b+c'
0 1 0 a'bc' a+b'+c
0 1 1 a'bc a+b'+c'
1 0 0 ab'c' a'+b+c
1 0 1 ab'c a'+b+c'
1 1 0 abc' a'+b'+c
1 1 1 abc a'+b'+c'
Now for the Boolean function F(x,y,z) = xy + zI , refer the table 2.4.
Table 2.4: F(x,y,z) = xy + zI
Here the minterm expression will be xyz + xyz’ + x y’z’ + x’yz’ + x’ y’z’ and
the max term expression will be (x’+y+z’)( x+y’+z’) (x+y+z’ )
2.3 Basic Gates (NOT, AND & OR)

Boolean algebra is a deductive mathematical system closed over the values
zero and one (false and true). A binary operator “°” defined over this set of
values for a given set of Boolean inputs, output results in a single Boolean
value. For example, the Boolean AND operator output results in a single
Boolean for any combination of two Boolean inputs.
In algebra systems, there are basic set of postulates and initial assumptions
which system follows. Using the basic set of postulates of algebra system,
the additional set of properties, rules and other theorems can be deduced.
Boolean algebra systems often employ the following postulates:

Logic Design Unit 2
 Closure. The Boolean system is said to be closed with respect to a

given binary operator if, a Boolean result has been obtained for every
pair of Boolean input values, For example, logical OR is said to be
closed in the Boolean system because it produces a Boolean result for
the accepted input Boolean operands..
 Commutativity. A binary operator “°” is said to be commutative if
X°Y = Y°X for all possible Boolean values X and Y.
 Associativity. A binary operator “°” is said to be associative if (X ° Y) ° Z
= X ° (Y ° Z) for all Boolean values X, Y, and Z.
 Distribution. Two binary operators “°” and “%” are distributive if X ° (Y %
Z) = (X ° Y) % (X ° Z) for all Boolean values X, Y, and Z.
 Identity. A Boolean value I is said to be the identity element with respect
to some binary operator “ °” if X ° I = Y.
 Inverse. A Boolean value I is said to be the inverse element with respect
to some binary operator “°” if A ° I = B and BA (i.e., B is the opposite
value of A in a Boolean system).
0 and 1 are only possible values in the Boolean system, which are often
called as false and true respectively.
The logical AND operation is represented by the symbol “•”; e.g., for
Boolean values A and B logical AND result is obtained using A • B
expression. The symbol “•” is dropped when the single letter variable names
are used; Therefore, logical AND of the variables can be represented as AB.
ANDing of variables A and B is also called as the product of variables A
and B.
The logical OR operation is represented using the symbol “+”; e.g., for
Boolean variables A and B the logical OR operation can be represented as
A + B. ORing of Boolean variables A and B is also called as sum of
variables A and B.
The unary operator’s in digital system are Logical complement, negation, or
not. The logical negation is denoted by (‘). For example, logical NOT of A is
denoted by A’.
If a single Boolean expression has many different operators, the result of
that expression depends on the precedence of the operators. In Boolean
algebra, the following precedence (from lowest to highest) for the Boolean
Logic Design Unit 2
operators are used: logical OR, logical AND, logical NOT, parenthesis. The
logical OR and logical AND operators are left associative. In a single
expression, if there two operators adjacent to each other with the same
precedence, the expression must be evaluated from left to right. The logical
NOT operation is right associative. As logical NOT is unary operator, the
results of both left associativity and right associativity will result in same
value.
The following sets of postulates are used in digital systems:
Postulate 1: Boolean algebra is closed under the AND, OR, and NOT
operations.
Postulate 2: The identity element with respect to • is one and + is zero.
There is no identity element with respect to logical NOT.
Postulate 3: The • and + Boolean operators are commutative.
Postulate 4: • and + Boolean operators are distributive with respect to one
another. That is,
X • (Y + Z) = (X • Y) + (X • Z) and
X + (Y • Z) = (X + Y) • (X + Z).
Postulate 5: For every value X there exists a value X’ such that
X•X’ = 0 and
X+X’ = 1. X’ value is the logical complement (or NOT) of X.
Postulate 6: • and + Boolean operators are both associative. That is,
(X•Y)•Z = X•(Y•Z) and
(X+Y)+Z = X+(Y+Z).
Using the above postulates any theorem in Boolean algebra can be proved.
Following are the some important theorems in Boolean algebra using which
a digital system can be constructed.
Theorem-1: X + X = X
Theorem-2: X • X = X
Theorem-3: X + 0 = X
Theorem-4: X • 1 = X
Theorem-5: X • 0 = 0
Theorem-6: X + 1 = 1

Logic Design Unit 2
Theorem-7: (X + Y)’ = X’ • Y’
Theorem-8: (X • Y)’ = X’ + Y’
Theorem-9: X + X•Y = X
Theorem-10: X •(X + Y) = X
Theorem-11: X + X’Y = X+Y
Theorem-12: X’ • (X + Y’) = X’Y’
Theorem-13: XY + XY’ = X
Theorem-14: (X’+Y’) • (X’ + Y) = Y’
Theorem-15: X + X’ = 1
Theorem-16: X • X’ = 0
A Boolean expression is a combination of ones, zeros, and literals which are
separated by Boolean operators. A literal is an unprimed or primed
(negated) variable name. In further discussion, we consider that a single
alphabetic character for all variable names. A specific Boolean expression is
considered as Boolean function; In general the name of Boolean functions
can be any alphabetic character with a possible superscript. For example:
F = A + BC
The Boolean function F first computes the logical AND operation of B and C
and then performs logical OR operation with A. If A=1, B=0, and C=1, then
value one is returned by the function F (1+0•1 = 1). Table 2.5 can be used
as alternate way to represent a Boolean function.
Table 2.5: AND Truth Table
AND 0 1
0 0 0
1 0 1
Truth tables will be more convenient and natural for any binary operators
with two input variables. However, when the Boolean function F mentioned
above is considered, we can observe that the function F has 3 input
variables. For such conditions the above mentioned truth table (for two input
variables) cannot be used, instead a truth table for three input variables can
be used. Truth table for any number of input variables can be constructed
easily. One of the methods to construct the truth table for three or four
variables is explained in the following example:

Logic Design Unit 2
In the table 2.6 for input variables A & B, the possible combinations of zeros
and ones are given in four different columns of the table.
Table 2.6
A B
0 0
0 1
1 0
1 1
The table 2.7 shows the truth table for OR function.

Table 2.7: Truth Table for OR function
OR 0 1
0 0 1
1 1 1
From the truth table 2.9 it can be observed that the possible combinations of
zeros and ones for variables C and D are given in the four different rows of
the truth table. Alternate method to construct the truth tables is shown in
table 2.10. The current method provides a compact representation when
compared to the method explained above; also using this method it is easier
to fill in the rows and columns of the table. In digital systems one can create
many unique Boolean functions. By using the theorems which have been
mentioned above, we can show that two or more Boolean functions can be
equivalent, i.e., for any set of input combinations, Boolean functions
produces same outputs. For example, F=(A+B)’ and F=A’B’ are two different
Boolean functions. By theorem seven, it can be easily proved that the two
Boolean functions are equivalent. If the number of input variables are fixed,
then only finite number of unique Boolean functions possible. For example,
for two input variables there will be only 16 possible Boolean functions and
for three input variables there will be only 256 unique Boolean functions. For
n input variables, the number of unique Boolean functions are 2^(2n) (i.e.
two raised to the two raised to the nth power). For example for three input
variable, number of unique Boolean functions are 2^(23) = 256.

Logic Design Unit 2
Tables 2.8 and 2.9 show truth tables for three variables and four variables
respectively.
Table 2.8: Truth Table for a Function with Three Variables
Table 2.9: Truth Table for a Function with Four Variables
The table 2.10 shows the another format for truth tables
Table 2.10: Another Format for Truth Table
From the above discussion, it is clear that we have only three basic logic
operations: OR, AND and NOT. So we have three basic gates to produce
basic logic operations. These are OR gate, AND gate and NOT gate. Before
we study these basic gates let us see what a logic gate is.
A logic gate is an electronic circuit which has one or more inputs but only
one output. Logic gate produces logical operation on binary numbers.
Now let us study basic logic gates.
OR gate: OR gate has two or more inputs and only one output. The
operation of this gate is such that it produces a high output (i.e. logic 1)

Logic Design Unit 2
when one or more of inputs are high and it produces a low output (i.e. logic
0) when all the inputs are low.
The logic symbol, truth table and Boolean expression for 2-input OR gate is
shown in figure 2.1.
Figure 2.1: OR gate (a) Logic symbol (b) Boolean expression (c) Truth table
Note that A and B are the inputs and Y is the output. The Boolean
expression Y = A + B is read as Y equals A OR B.
AND gate: AND gate has two or more inputs and only one output. This gate
produces a high output (i.e. logic 1) when all of inputs are high and it
produces a low output (i.e. logic 0) when one or more of its inputs are low.
The logic symbol, truth table and Boolean expression for 2-input OR gate is
Figure 2.2: AND gate (a) Logic symbol (b) Boolean expression (c) Truth table
Note that A and B are the inputs and Y is the output. The Boolean
expression Y = A .B is read as Y equals A AND B.
NOT gate: A NOT gate has only one input and only one output. This gate
produces the output which is the inversion (i.e. complement) of the input.
Suppose if the input is 1(HIGH), then its output is 0 i.e. logic 0 (LOW). NOT
gate is also known as an inverter. If the input variable is A, the inverted

Logic Design Unit 2
output is known as NOT A. This can also be shown as A', or A with a bar
over the top i.e. A .
The logic symbol, truth table and Boolean expression for NOT gate is shown
in figure 2.3.
Figure 2.3: NOT gate (a) Logic symbol (b) Boolean expression (c) Truth table
Note that A is the input and Y is the output. The Boolean expression Y = A
is read as Y equals NOT A. This can also be read as Y equals A bar.
2.4 Universal Gates (NAND & NOR)

The NAND gate is a digital logic gate that behaves in a manner that
corresponds to the truth table to the left. When both the inputs to NAND
gate are high, then output of the gate will be LOW. The output of gate will be
HIGH when one or both the inputs of NAND gate are LOW. As any type of
gate or Boolean function can be implemented using NAND gates, they are
also known as Universal gates.
The functional completeness of the NAND gate has to be taken as
advantage while constructing logic circuits in digital systems. Constructing
the complicated logic circuits using NAND gates yields more compact
results and cost saving when compared to the logic circuits constructed
using AND, OR and NOT gates.
An n-input NAND gates can also be constructed. When all the inputs to
NAND gate are high, then output of the gate will be LOW. The output of
gate will be HIGH when one or all the inputs of NAND gate are LOW. N-
input NAND gates instead of operating as simple binary operator, they
operate as n-ary operators. Algebraically, these can be expressed as the
function NAND (a, b,..., n), which is logically equivalent to NOT
(a AND b AND ... AND n).

Logic Design Unit 2
There are two symbols for NAND gates: the 'distinctive' symbol (refer figure
2.4) and the 'rectangular' symbol (refer figure 2.5).
Figure 2.4: Distinctive NAND Symbol
Figure 2.5: Rectangular NAND symbol
NAND operator "|" as follows:

x y x|y
0 0 1
0 1 1
1 0 1
1 1 0
The NOR gate is a digital logic gate and it behaves such that when both the
inputs of NOR gate are LOW, the output of the gate will be HIGH. A LOW
output results when one or both inputs of the NOR gate are HIGH. Negation
of OR gate output results in NOR. NOR is a functionally complete operation
– As any type of gate or Boolean function can be implemented using NOR
gates, they are also known as Universal gates. As the OR operator can
change LOW to HIGH but not vice versa, it is said to be monotonic
In most of the circuit implementations including CMOS (Complementary
Metal Oxide semiconductor) and TTL (Transistor-Transistor Logic), the
negation is not freely available in such logic families, NOR gate followed by
an inverter can be used to implement OR gate. A significant exception is
some forms of the domino logic family. The figure 2.6 shows the NOR
symbol.
Figure 2.6: American NOR symbol

Logic Design Unit 2
The figure 2.7 shows the IEC NOR symbol.
Figure 2.7: IEC NOR symbol
NOR operator: ?
x y x?y
0 0 1
0 1 0
1 0 0
1 1 0
Now to prove that we can construct any Boolean function using only NAND
gates, we need only show how to build an inverter (NOT), AND gate, and
OR gate from a NAND (since we can create any Boolean function using
only AND, NOT, and OR). Building an inverter is easy; just connect the two
inputs together. Once we build an inverter, building an AND gate is easy –
just invert the output of a NAND gate. After all, NOT (NOT (A AND B)) is
equivalent to A. AND B. Of course, it takes two NAND gates to construct a
single AND. We have already discussed about AND, OR and NOT Gates.
Let us once again look at their logic symbols shown in figure 2.8 as these
are taken as references while constructing the these gates using universal
gates i.e using NOR and NAND gates.
Figure 2.8: AND, OR and Inverted NOT Gates
Using DeMorgan’s theorems, an OR gate can be easily constructed from

NAND gates.
DeMorgan’s Theorem 1 : (X OR Y) I = XI AND YI. i.e. (X + Y)I = XI . YI
Demorgan’s Theorem 2: (X AND Y)I = XI OR YI. i.e. (X . Y)I = XI + YI
Now you might be wondering why we would even bother with this. After all,
why not just use logical AND, OR, and inverter gates directly? Following are
the reasons for this.
Logic Design Unit 2
NAND gate and NOR gates are called universal gates because any logic
function or any logic gate can be realized using either only NAND gates or
only NOR gates. For example, we can construct or realize the operation of
OR, AND, and NOT gates using only NAND gates or only NOR gates.
First, when compared to other gates NAND gates are less expensive to
construct. Second, constructing complex digital systems using same
building blocks will be easier than constructing the digital systems using
different basic blocks. The correspondence between NAND and NOR logic
is orthogonal to the correspondence between the two canonical forms
appearing in this unit (sum of minterms vs. product of maxterms). While
NOR logic is useful for many circuits, most electronic designs use NAND
logic.
16 possible Boolean functions of two variables are shown in table 2.11.
Table 2.11: 16 possible Boolean functions of two variables

Logic Design Unit 2
2.5 Exclusive-OR and Exclusive-NOR Gates

The XOR gate (sometimes EOR gate) is a digital logic gate that implements
exclusive disjunction – it behaves according to the truth table to the right. If
either one of the input is HIGH, then the output will be HIGH. The output of
the gate results a LOW value when either the inputs of the gate are LOW or
both are HIGH.
This function is called addition modulo 2. In digital systems, the binary adder
are implemented using XOR gate. A half adder consists of an XOR gate and
an AND gate. The table 2.12 shows the truth table of XOR gate.
Table 2.12: Truth table of XOR gate
INPUT OUTPUT
A B A XOR B
0 0 0
0 1 1
1 0 1
1 1 0
The figure 2.9 shows the logic symbol of two input XOR gate and figure 2.10
shows its rectangular symbol.
Figure 2.9: Logic Symbol of XOR gate
.
Figure 2.10: Rectangular XOR symbol
X-NOR Gate
The XNOR gate is a digital logic gate whose function is the inverse of the
exclusive OR (XOR) gate. The two-input version implements logical equality,
behaving according to the truth table to the right. If the inputs to XOR gate
are same, then the output will be HIGH. A LOW output will result if both the
inputs to the XOR gate are not same. The table 2.13 shows the truth table
of XNOR gate.
Logic Design Unit 2
Table 2.13: Truth table of XNOR gate
INPUT OUTPUT
A B A XNOR B
0 0 1
0 1 0
1 0 0
1 1 1
The figure 2.11 shows the logic symbol of two input XOR gate and figure
2.12 shows its rectangular symbol.
Figure 2.11: X-NOR symbol
Figure 2.12: Rectangular X-NOR symbol
The XOR or Mod-2 addition operation is defined by the equation
An alternative way of expressing this relationship is
The laws of Association, Commutation and Distribution are also valid for the
XOR operation. They are
If Boolean algebraic equations are written in terms of the XOR function, the
following identities may prove useful:

Logic Design Unit 2
Which is sometimes referred to as the coincidence function and is written as
Now we can construct any circuit for any given Boolean expression using
logic gates. Let see the example 1.
Example 1: Draw a logic circuit for (A + B) C.
Solution: The logic circuit for (A + B) C. is shown in figure 2.12
Figure 2.12: logic circuit for the expression (A + B)C.
2.6 Exercise on Realizing Circuits with Universal Gates

Now let see the realization of other circuits or gates using only NOR gate/s.
Realizing Circuits with NOR Gates:
The figure 2.13 shows the construction of NOT gate using NOR Gate.
Figure 2.13: NOT Gate Construction using NOR Gate

Logic Design Unit 2
The figure 2.14 shows the construction of OR gate using NOR Gates only.
Figure 2.14: OR Gate Construction using NOR Gates
The figure 2.15 shows the construction of AND Gate using NOR Gates only.
Figure 2.15: AND Gate Construction using NOR Gates
The figure 2.16 shows the construction of NAND Gate using NOR Gates
only.
Figure 2.16: NAND Gate Construction using NOR Gates
The figures 2.17 and 2.18 show the construction of XNOR and XOR gates
using NOR Gates only.
Figure 2.17: XNOR Gate Construction using NOR Gates

Logic Design Unit 2
Figure 2.18: XOR Gate Construction using NOR Gates
Realizing Circuits with NAND Gates: The figures 2.19 through 2.24 shows
the various gates realized using NAND gates only.
Figure 2.19: NOT Gate construction using NAND Gate
Figure 2.20: OR Gate construction using NAND Gate
Figure 2.21: AND construction using NAND Gate
Figure 2.22: NOR construction using only NAND Gates

Logic Design Unit 2
Figure 2.23: XOR Gate construction using NAND Gate
Figure 2.24: XNOR Gate construction using NAND gate

1. If x,y,z contains values 0,1,1 then (x+z) y is _______.
2. x+y.0 is ____________ Law.
3. x+1 =1 is __________ Law.
4. Boolean product for 1 and 0 in AND has ____ value.
5. Boolean sum for 1 and 0 in OR has _____ value.
6. A Boolean expression is a combination of ones, zeros, twos and literals
which are separated connected by Boolean operators. (True or
False ?)
7. The NAND Gate output for input values 0 and 1 is _______.
8. The NOR Gate output for input values 1 and 0 is _______.
9. The XNOR gate is a digital logic gate whose function is the inverse of
the exclusive OR (XOR) gate. (State True or False?).
10. Draw a logic circuit for AB + AC
11. Draw a logic circuit for ( A  B) (C + D) C .

12. The XOR or Mod-2 addition operation is defined by the equation is
_________.
13. Exclusive NOR is defined as __________.

Logic Design Unit 2
2.7 Summary
A logic gate is an electronic circuit which has one or more inputs but only
one output. Logic gate produces logical operation on binary numbers.
 A logic gate is an elementary building block of a digital circuit.
 There are three fundamental logic gates namely, AND, OR and NOT.
 We have other logic gates like NAND, NOR, XOR and XNOR.
 NAND and NOR gates are called the universal gates.

1. What is a logic gate?
2. List the fundamental logical gates.
3. Why NAND and NOR gates are called as universal gates?
4. How AND gate can be realized using NOR gate?
5. How OR gate can be realized using NAND gate?
6. Give the truth table of XOR gates for two inputs.
7. Draw a logic circuit for (A + B) C.
8. Draw a logic circuit for A + BC + D .
9. Draw a logic circuit for AB + AC.
10. Draw a logic circuit for (A + B)(C + D) C .
2.9 Answers
1. 1
2. Commutative
3. Dominance
4. 0
5. 1
6. False
7. 1
8. 0
9. True

Logic Design Unit 2
10.
11.
12. A  B  AB  AB
13. NOT of ( A XOR B)
Terminal Questions
1. Refer to section 2.3
7. Refer to section 2.5 for method

Logic Design Unit 3
Unit 3 Techniques for Simplifying Boolean

Expressions
Structure:
3.1 Introduction
Objectives
3.2 Boolean Algebra
Boolean Expressions and Functions
More on Boolean Functions
Functional Completeness
Simplification of Boolean Functions
3.3 Karnaugh Maps
3.4 Quine-McCluskey Method
3.5 Exercises
3.6 Summary
3.8 Answers
3.1 Introduction
In the last unit, you studied about rules and laws of Boolean algebra, basic
gates, universal gates and realization of other gates using universal gates.
In a digital system, there are two voltage levels of electrical signals i.e., 0v
and 5v. If the supply to the system is maintained, the electrical devices can
exist in one of the two voltage levels indefinitely. For example, a bipolar
transistor that is non-conducting in a 5 volt system will have approximately 5
volts between collector and emitter. However, when the transistor is turned
on and is conducting, the voltage between collector and emitter can be
made zero by connecting a suitable load to the transistor. Among the two
voltage levels, logic zero is assigned to 0v and logic one is assigned to 5v.
The presence or absence of a particular condition can be indicated by the
two states logic 0 and logic 1. An algebra developed in the nineteenth
century by George Boole (1815-1864), an English mathematician, is well
suited for representing the situation above. This branch of mathematics,
called Boolean algebra, is a discrete algebra in which the variables can
have one of two values, either 0 or 1. Associated with the algebra is a
number of theorems which allow the manipulation and simplification of
Boolean equations.
Logic Design Unit 3
Shannon, who was the first to develop information theory, became aware
that Boolean algebra was useful in the design of switching networks. Initially,
the algebra was used in the design of relay networks. More recently
switching circuits were implemented using discrete components but rapid
technological advances have seen the introduction of MSI, LSI and VLSI
devices and because of the sophisticated and versatile nature of these
components there have been significant changes in the design techniques
used by engineers. In spite of these changes it is still essential for engineers
to have a good working knowledge of traditional switching theory.
In digital system designing, one of the main objectives to implement a
Boolean function using minimum number of discrete gates. The cost of the
circuit will be low when the number of gates used in implementing a
Boolean function is smaller. Simplification of Boolean function can be
performed using a purely algebraic process. Simplification using algebraic
process can be tedious, and at the end of process designer is not always
sure whether the simplest solution is obtained or not.
Instead of using algebraic process, Boolean function can be simplified easily
by plotting the function to Karnaugh map and simple rules to reduce the
Boolean function. Upto six variables simplification of Boolean function using
karnaugh maps will be very straightforward. Tabulation method which has
been developed by Quine and McCluskey will be better method to simplify
the Boolean function which has more than six variables. So in this unit we
will study about Boolean expressions and functions and simplification of
Boolean expressions using Karnaugh map and Quine-McCluskey Methods.
Objectives:
By the end of Unit 3 the learners are able to
 define Boolean variable and Boolean function
 simplify the expressions using Boolean algebra
 explain Karnaugh maps
 explain Quine-McCluskey method
3.2 Boolean Algebra

3.2.1 Boolean Expressions and Functions
Boolean variable is a variable which can have either 0 or 1 as its value. A
Boolean function is an expression formed with binary variables, the two
binary operators AND and OR, one unary operator NOT, parentheses and
Logic Design Unit 3
equal sign.Truth tables are used to display the values of a given Boolean
function. A Boolean expression is an expression using Boolean variables
{X1, X2,….Xn} and the operations of a Boolean algebra.
Boolean functions in digital systems are defined by Boolean expression.
The Boolean function value is evaluated by applying 0’s and 1’s to the
variables in the Boolean expression. For example, the Boolean function
F(A,B) is defined by the Boolean expression A’B’ + AB’ i.e., F(A,B) = A’B’ +
AB’. The truth table for the function F(A,B) is given in the table 3.1.
Table 3.1: Truth table for F(A,B) = A’B’ + AB’
The domain in this function is the 2-tuple which represents the values of
x and y. The range is {0, 1} in the last column. The possible value of the
variables in the Boolean expression represents the n-tuple of a Boolean
function. If two or more Boolean expressions represent the same function,
then those Boolean expressions are said to be equivalent. (i.e., have the
same truth table).
3.2.2 More on Boolean Functions
In order to use the above information to construct the digital circuits, the
following basic problems need to solve:
1) how the Boolean expression is derived from the given truth table for a
Boolean function?
2) Can the Boolean function be represented with an optimum set of
operators?
First, question 1. How the Boolean expression can be derived from a given
table (for example table 3.2) of values for a Boolean function?

Logic Design Unit 3
Table 3.2: Deriving Boolean expression
From the above table 3.2, the function F is 1 when y = z = 1 and x =0. And
hence we get the expression x’yz i.e., the value of the function F will be 1 if
and only if x’ = y = z = 1. The function G will have value 1 in two cases: y = z
= 1, x =0, and x = y = 0, z = 1. From the above information the expression
for G can be represented in the sum of two product terms: x’yz + x’y’z
The above method explains the way to construct a Boolean expression from
the values of a Boolean function. A Boolean product m1, m2, m3…mn is
said to be a minterm of Boolean variables x1, x2, x3,…xn if mi = xi or mi =
xi’. Only if all the variables of minterm are 1, the minterm product will result
in 1. For the 1st scenario discussed above, x’yz will only be the minterm that
has the value 1. In other words, a Boolean expression for a Boolean
function can be quoted as the sum of the minterms. Minterms referred here
are those with value 1 for a given combination.
Boolean sum discussed above is also referred to as sum of products (SOP)
expansion or disjunctive normal form. Maxterm is the dual of minterm. It is
also referred to as product of sums (POS) or conjunctive normal form.
Duality can be observed from the table 3.3 below:
Table 3.3: Duality

Logic Design Unit 3
3.2.3 Functional Completeness

The other question posed in the previous section was: In order to express a
Boolean, is it required to all the three operators? From the above discussion,
using the operators {' + •} it is easy to construct any Boolean function. As
these three operators used to express the every Boolean function, set of
three operators is considered as functionally complete. Is there a smaller
set of functionally complete operators? If one of three operators in a set can
be expressed in terms of other two operators, then a smaller set which is
functionally complete can be determined. One way to determine the smaller
set is by using DeMorgan’s law. For example:
x + y = (x'y')'
From the above expression we can observe that the + operator has been
expressed in terms of {' •}. So, the set of {' •} is functionally complete. In a
similar way Boolean products can be eliminated:
xy = (x' + y')'
Is the set {+ •} functionally complete? No, there is no way to represent the
Boolean function F(x) = x' using these two operators, so this set is not
functionally complete.
Finally, is there a set of one operator that is functionally complete? Only if
we define a new operator. We could define a NAND operator "|" as shown
in the table 3.4.
Table 3.4: NAND operator
This set is functionally complete. In order to prove that operator | is

functionally complete, the operators {• '} has to be expressed using |:
x' = x | x
xy = (x | y) | (x | y)

Logic Design Unit 3
A similar operator that is functionally complete is the NOR operator. This is

shown in table 3.5.
Table 3.5: NOR operator
3.2.4 Simplification of Boolean Functions

From the above discussion, it can be observed that any Boolean function
can be constructed using NOTs, ANDs, and ORs using minterm expansion.
As minterm expansion requires more number of gates than necessary, a
design engineer will rarely satisfied with it. A minterm expansion can be
simplified using the identities and laws of Boolean algebra. For example, the
minterm expansion for a Boolean function f of three variables might be
represented as follows.
f = x'y'z' + x'y'z + x'yz' + x'yz + xyz' + xyz
The maximum gates required to implement above Boolean function are: 12
AND gates, 5 OR gates and 9 NOT gates. Above minterm expansion can be
reduced by using the laws and identities of Boolean algebra:
f = x'y'z' + x'y'z + x'yz' + x'yz + xyz' + xyz
= x'y'(z' + z) + x'y(z' + z) + xy(z' + z) distributive law
= x'y' + x'y + xy complementarity & identity
= x'(y' + y) + xy distributive law
= x' + xy complementarity & identity
= x' + y redundancy
From the above example, it can be observed that the long minterm has
been reduced down to expression x’+y, which can construct using single
NOT gate and OR gate. But to reduce the given minterm expansion,
Engineer should be able to choose the appropriate laws and identities of
Boolean algebra and apply them in the right step. Therefore, we will look at
a very simple technique that usually leads to a significant simplification of

Logic Design Unit 3
minterms. It won't always produce the simplest form, but it's close enough
for most engineers considering the difficulty of the alternative method.
3.3 Karnaugh Maps

Maurice Karnaugh a telecommunication engineer has invented Karnaugh
Maps. In 1953, the Karnaugh map has been developed in Bell Labs while
studying the application of digital logic to design of telephone circuits. This
method is also known as K-maps. A Karnaugh map (K-map) is a visual
representation of a Boolean functions. The plan is to recognize patterns in
the visual representation and thus find a minimized circuit for the Boolean
function K-maps are generally used in simplification of two, three or four
variables Boolean function. For the Boolean functions with 5 variables or
more, K-maps get cumbersome and other techniques like Tabular Method is
used. A Karnaugh map is a 2-dimensional representation of the truth table
for a Boolean function. For example, consider the table 3.6.
Table 3.6: Truth Table for the function f (x,y,z)
The figure 3.1 shows the template for 3 variable Karnaugh maps
Figure 3.1: Karnaugh map for three variables

Logic Design Unit 3
For three variables, there are eight possible combinations and each cell in
K-map corresponds to one of the combination. The templates for 2 and 4
variable Karnaugh maps are given in figure 3.2(a) and 3.2(b) respectively.
(a) (b)
Figure 3.2: (a) Karnaugh map for 2 variables (b) Karnaugh map for 4
variables
Once we have placed the 1's in the map, there is a simple procedure that
we apply.
Before analyzing the procedure, understanding the basis for the procedure
is necessary. As there are many simple functions in Boolean functions, K-
maps are useful. The simple functions in Boolean function are known as
product function; product functions can be product of few variables or all
variables. The product terms can have both normal variable and its
complements. For example, A, A'B and ABC are all product functions but
A + B' and AB + CD are not product functions.
Consider the Boolean function f(A,B,C) = AC. For inputs equal to 101 and
111, the value of the Boolean function will be 1. Its Karnaugh map is shown
in figure 3.3.
Figure 3.3: Karnaugh map for f(A,B,C)=AC

Logic Design Unit 3
The minterms of the Boolean function lie in 1x2 rectangular block.

Consider another Boolean function g(A,B,C) = B'. For input values equal to
000, 001, 100, 101, the Boolean function g will be 1. Its Karnaugh map is
Figure 3.4: Karnaugh map for g(A,B,C)=B'
Notice that 1’s lie in a 2x2 rectangular block. From the above example, it
can be observed that for every product function there will be corresponding
K-map whose minterms can lie in a block of 1, 2, or 4 cells long. Thus,
recognizing the product function which represented by a K-map has highest
priority.
In order to recognize the product function represented by k-map, the truth
set of the Boolean functions is written down. Truth set is the set of
combinations for which Boolean function will be 1. For example consider the
k-map shown in figure 3.5.
Figure 3.5: k-map for Boolean function with output 1
From the above k-map, it can be observed that values 011 and 111 will form
the truth set. Next, the truth set values are analyzed. If the variables of the
Boolean function are A, B, and C, it can be observed that value of A can be
either 0 or 1; while the values of B and C has to be 1. The above analysis
can be characterized as follows: {*11}. A particular value for x will only be
accepted if A is involved in unknown product function. From the above truth
set it can be observed that value of A can be either 0 or 1, thus it can be
Logic Design Unit 3
concluded that A is not involved. From the truth set it is observed that value
of B is 1 for all inputs, thus B must be involved but not B’. The same is
applicable for C. From the above discussion, we can say that BC is the
product function. For the K-maps given in figure 3.6, derive the product
functions associated with it.
Figure 3.6: k-map Examples
1) Truth set for the first k-map is: {011, 010, 111, 110} = {*1*}. It can be
observed that B should be involved in the product function, but A and C
are not necessary to be involved. Thus the product function is B.
2) Truth set for the second k-map is: {010} as there is only one value in the
truth set, the Boolean function for the k-map will be A'BC'.
3) Truth set for the third k-map is: {000, 100, 010, 110} = {**0} = z'. It can
be observed that complement of C should be involved in the product
function, but A and B are not necessary to be involved. From the k-map
it can be noticed that there is a wraparound of rectangular block.
Finally, try some 2 and 4 variable maps as shown in figure 3.7.
Figure 3.7: 2 and 4 variable k-maps
1) Truth set = {00, 10} = {*0} = y'

2) (variables are wxyz): truth set = {0001, 0011, 1001, 1011} = {*0*1} = x'z.
Using K-map, the same expression can be used to represent any Boolean
function. Another expression with the same Karnaugh map as the two-
variable one above: x'y' + xy' + x'yxy; therefore, we can represent this as y'
and build a circuit as such.
Logic Design Unit 3
But sometimes the Boolean expressions will not be equivalent to the k-maps
product function. The first example we looked at did not break down into a 1,
2, or 4 cell rectangular blocks. Now consider the figure 3.8.
Figure 3.8.: K-maps for 3 variables with “x” representation
Blocks in the above k-map can be broken down into two separate product
blocks. x’ is represented by one product block and the other product
represents y. The Boolean function which has been derived from the k-map
is x' + y, in the present method, the two product functions are determined
and ORed together. It can be observed that the blocks has been determined
directly without using any truth sets and same can be applied to any
Boolean function. The main idea is to use only minimum blocks to cover the
terms and the Boolean function is derived by summing all the product blocks.
The simple Boolean expression can be derived when the large sized blocks
are used. For example, in the k-map above, one horizontal and two vertical
blocks could be used: the first two ones form one horizontal block, ones in
column 3 forms first vertical block, and ones in column 4 forms the other
vertical block. By using above method the following Boolean expression is
derived: x’y’+yz+yz’.
In the above k-map, if the first two ones form a block and the four ones
forms another block, then the Boolean expression cab be reduced to x’y’+y.
But the Boolean expression derived using second method is not that simple
as the Boolean expression which is derived using the first method. By using
Boolean identities and theorems, the Boolean expression x’y’+y can be
further reduced to x’y. From the above discussion, it can be observed that a
simple Boolean expression can be derived by choosing the blocks carefully.
An implicant of a function is a product term that is included in the function.

Logic Design Unit 3
In the Boolean expression above implicants are x'y', yz and yz'. A prime
implicant of a function is an implicant of the function that is not included in
any other implicant of the function. Therefore, only few prime implicants
should be used to cover the minterms of the Boolean function.
As additional practice, simplify the following functions represented by
Karnaugh maps shown in figure 3.9.
(a) (b)
Figure 3.9: K-maps for (a) 3 variable and (b) 4 variables
1) x'z' + yz'
2) w'x + xyz' + wx'z x'y'z'
Notice that you can overlap the blocks if necessary as shown in figure 3.10.
(a) (b)
Figure 3.10: Over lapping in K-maps for (a) 3 variable and (b) 4 variables
Instead of using identities for simplification of Boolean functions, it can be

done easily by using k-maps. The main important thing is to determine the
simple Boolean expression, a right set of blocks need to be chosen.

Logic Design Unit 3
There are no rules to choose the right set of blocks to determine the simple
expression, it comes with practice.
Now let us see some examples
Example 1: Simplify f (a, b, c, d)=∑m(0, 2, 4, 6, 7, 8, 9, 11, 12, 14).
Solution: Write the karnaugh Map and enter 1’s as shown in figure 3.11 in
the corresponding cells.
Figure 3.11: Karnaugh Map for example 1.
Now group the 1’s staring from groups of eight 1’s, then four 1’s, two 1’s as
Figure 3.12: Karnaugh Map simplification for example 1.
Finally we get,
f = aIdI + bdI+ aIbc+abId + cIdI

Logic Design Unit 3
Example 2: Simplify the following expression using K-Map.
Solution: The K-map and its simplification is shown in figure 3.13.
Figure 3.13: Karnaugh Map for example 2.
Therefore,
3.4 Quine-McCluskey Method

When a Boolean expression contains more than six variables, then it
becomes very difficult to solve the expression using Karnaugh map method.
In such cases the Quine–McCluskey method can be used to solve these
types of Boolean equations. This method was developed by W.V. Quine and
Edward J. McCluskey. This method is sometimes referred to as the method
of prime implicants or the tabulation method.
The following steps are followed to simplify the given Boolean expression
using Quine-McCluskey method.
Step 1: If the function is not given in minterm form, then translate the
decimal values to minterms.
F(A,B,C,D) = ∑m(0, 2, 3, 6, 7, 8, 9, 10, 13)

Logic Design Unit 3
Step 2: If the function is not given in binary minterm form, then translate the
decimal values to binary notation of minterms.
F(A,B,C,D) = ∑m(0000, 0010, 0011, 0110, 0111, 1000, 1001, 1010, 1101)
Step 3: Minterms are grouped depending upon number of one’s they have
and entered in table form as shown in the table 3.7.
Table 3.7: Quine-McCluskey Method
Step 4: The minterms in the adjacent blocks are compared to determine the
minterms which are differed by only one bit. Replace the missing literal by –
and place the minterms in the next column. The minterms in the present
column which are combined are placed with a check mark (refer to the
table 3.8).
Table 3.8: Quine-McCluskey Method for Step 4

Logic Design Unit 3
Step 5: The minterms in the adjacent blocks are compared to determine the
minterms which are differed by only one bit. Note -’s must line up. Replace
the missing literal by – and place the minterms in the next column. The
minterms in the present column which are combined are placed with a
check mark. Table 3.9 shows completion of first phase of Q-M method.
Step 6: The prime implicant chart is to be formed with minterms in a row

and prime implicants in column. When there is intersection of minterm and
the prime implicant, the  placed (refer the table 3.10).
Step 7: Select prime implicants for minterms with only one  in a column.
(refer the table 3.11).

Logic Design Unit 3
Step 8: Repeat step 8 for minterms with only two  in a column. (refer the
table 3.12). If the minterms of those colums are already included, then not
required to be considered (refer the table 3.12).
In table 3.12, two  correspond to colums 0010, 1000 and 1001. These can
be dropped since corresponding minterms are already included.
Now the final expression is
F(A,B,C,D) = 1-01 + -0-0 + 0-1-
Step 9: Translate to literal notation
F(A,B,C,D) = AC’D + B’D’ + A’C
Don’t Cares
It is important to note that don’t cares are used to find out prime implicant
but not compulsory to include in the final expression.
Step A: Translate to canonical minterm representation
G(A,B,C,D) = m(2,3,6,8,9,10,13) +d(0,7)
Step B: Form table and find prime implicants. Include minterms and don’t
cares in table. Since G(A,B,C,D) is just F(A,B,C,D) with mintems 0 and 7
changed to don’t cares; this process would be identical to steps 3, through 5
from above. See steps 3 through 5 from above.
Step C: Form table with don’t cares missing. Only include required
minterms. Note 0000 and 0111 columns missing. Check required minterms
covered by each prime implicant (refer the table 3.13).
Table 3.13: Step C

Logic Design Unit 3
Step D: Select column in which a specific minterm is only covered by one

prime implicant (refer the table 3.14).
Table 3.14: Step D
Step E: Extract essential prime implicants (refer the table 3.15).

Table 3.15: Step E
Step F: Translate back to literals.

G(A,B,C,D) = 1-01 + -0-0 + 0-1-
G((A,B,C,D) = AC’D + B’D’ +A’C
3.5 Exercises
Figure 3.14: (c) and (d) independent implementation of f1 and f2 in (a) and (b)

Logic Design Unit 3
Function and product maps for determining multiple output circuits
Figure 3.15: K-maps for determining multiple output circuits

1. If x and y is 0 and 1, the Boolean function xy+xy’ result is __________.
2. A minterm has a value ___ if and only if all the values of its variables
are 1.
3. If x, y, z are 0, 0, 1 the minterm is _______ and maxterm is_________.
4. A Karnaugh map is a _______ representation of the truth table for a
Boolean function.
5. Implicants that cover as many cells of the map as possible are called
__________.
6. A prime implicant of a function is an implicant of the function that is not
included in any other implicant of the function (True or false?).

Logic Design Unit 3
3.6 Summary
Let us recapitulate the important concepts discussed in this unit.
 A Boolean function is an expression formed with binary variables, the two
binary operators AND and OR, one unary operator NOT, parentheses
and equal sign.
 A Boolean product m1, m2, m3…mn is said to be a minterm of Boolean
variables x1, x2, x3,…xn if mi = xi or mi = xi’.
 K-maps are generally used in simplification of two, three or four variables
Boolean function.
 A prime implicant of a function is an implicant of the function that is not
included in any other implicant of the function.
 Quine-McCluskey method is sometimes referred to as the method of
prime implicants or the tabulation method.

1. Simplify the expression algebraically x'y'z' + x'y'z + x'yz' + x'yz + xyz' +
xyz
2. What is a Karnaugh map? Explain.
3. Simplify the following three-variable Boolean functions using Karnaugh
map
4. Find the minimized sum-of-products expressions using Karnaugh map
5. Minimize the following functions using the Quine-McCluskey tabular

method:

Logic Design Unit 3
3.8 Answers
1. 0
2. 1
3. Minterm  x I y I z Maxterm  x+y+z I
4. 2-dimensional
5. Prime implicants
6. True
Terminal Questions
1. Refer to the sub-section 3.2.4
2. Refer to the sub-section 3.3
3. Refer to the section 3.3 for method

Logic Design Unit 4
Unit 4 Combinational Circuits

Structure:
4.1 Introduction
Objectives
4.2 Definition of Combinational Circuits
4.3 Types of Combinational Circuits
Adders
Subtractors
Comparators
Decoders
Encoders
Multiplexers
Demultiplexers
4.4 Gray Code and its Properties
4.5 BCD Code and its Properties
4.6 Excess-3 Code and its Properties
4.7 Summary
4.9 Answers
4.1 Introduction
In the last unit, we studied about Boolean expressions and functions and
simplification of Boolean expressions using Karnaugh map and Quine-
McCluskey Methods. The digital system which drives the modern computer
can be constructed using the basic gates i.e., AND, OR, and NOT gates.
There are two types of digital circuit: Combinational circuits and Sequential
circuits. Circuits whose outputs depend only on the current inputs are known
as Combinational circuits; hence the outputs will be generated by combining
the inputs according to the functionality. Circuits whose outputs depend on
both past and current inputs are known as Sequential circuits. Outputs of
sequential circuits can be determined by using the sequence of inputs over
the time. Memory circuits are considered as sequential circuits and adders
which is constructed using gates is considered as combinational circuits. In
this unit we will study about combinational circuits, and different codes like
Gray code, BCD code, and Excess-3 code.

Logic Design Unit 4
Objectives:
 explain different types of combinational circuits.
 explain Gray code and its conversion
 explain BCD code
 explain Excess-3 code
4.2 Definition of Combinational Circuits

Combinational circuits are those whose outputs depend only on the current
inputs. Here digital circuits generate a set of outputs from set of inputs using
Boolean operations. Usually many Boolean functions are implemented
using combinational circuit and each Boolean function corresponds to a
particular output. In a combinational circuit, it is important to observe that
each Boolean function implemented is represented by an output.
Combinational circuits are used to construct the computer’s Central
Processing Unit (CPU). For example, a set of Boolean functions can be
used to implement an adder circuit. For example, if there are two one bit
numbers X and Y. By using Boolean functions, SUM and CARRY values
can be generated.
SUM (S) = XY’+X’Y= X (XOR) Y.
CARRY (C) = XY = X (AND) Y.
A half-adder can be implemented by using above Boolean functions. As the
adder can add only two input bits but carry from the previous stage cannot
be added, engineers call is as half adder.
The circuit which adds the carry bit from previous stage with two one bit
inputs is known as Full adder. Full adder accepts three one bit inputs and
generates SUM and CARRY outputs. The SUM and CARRY Boolean
functions for a full adder is given below.
S = A’B’Cin + A’BCin’ + AB’Cin’ + ABCin = A (XOR) B (XOR) C
Cout = AB + ACin + BCin
Using 1 bit adders, an n bit adder can be constructed easily by combining
many 1 bit adder circuits. The figure 4.1 shows building an N-Bit Adder
Using Half and Full Adders.

Logic Design Unit 4
Figure 4.1: Building an N-Bit Adder Using Half and Full Adders
From above discussion we can clearly say that Boolean operations and
arithmetic can be implemented using Boolean logic functions.
BCD to Seven segment decoder is the combination circuit which is used
very commonly. Using this circuit, we can determine which Light Emitting
Diode (LED) on seven segment should be displayed. As there are seven
outputs, there will be seven Boolean logic functions (segment 0 through
segment 6). Note that light-emitting diode (LED) is a two-lead
semiconductor light source that resembles a basic pn-junction diode, except
that an LED also emits light.
The four inputs to each of these seven Boolean functions are the four bits
from a binary number in the range 0...9. Let D be the Higher Order bit of this
number and A be the Lower Order bit of this number. Each logic function
should produce a one (segment on) for a given input if that particular
segment should be illuminated.
Counting as we have been taught since kindergarten is based on the
decimal number system. Decimal means base 10 (the prefix dec). In any
number system, given the base (often referred to as radix), the number of
digits that can be used to count is fixed. For example in the base 10 number
system, the digits that can be used to count are 0,1,2,3,4,5,6,7,8,9.

Logic Design Unit 4
Generalizing that for any base b, the first b digits (starting with 0) represent
the digits that are used to count. When a number ≥ b has to be represented,
the place values are used.
4.3 Types of Combinational Circuits

4.3.1 Adders
There are two types of single bit adders. They are Half adder and Full
adder.
A half adder circuits will generate sum (S) and carry (C) from the two of its
inputs A and B. Sum S can be generated by XORing inputs A and B and
Carry C is generated by ANDing A and B . The output of the half adder will
be of 2 bits. The sum is indicated by least significant bit and carry is
indicated by most significant bit.
A full adder circuit adds the carry in C along with the two inputs A and B. A
large adder circuit can be constructed using multiple full adders. In full adder
circuit, carry in is labeled as Ci or Cin and carry out is labeled as Co or Cout,
labeling this way will remove the ambiguity between the output carry and the
input carry..
Half adder
A half adder is a digital circuit which accepts two inputs and performs
addition on them and generates two binary digits known as sum(S) and
carry(C).
As the carry is not included in the addition, this circuit cannot be used to
perform addition of multibit numbers.
The table 4.1 shows the truth table for a half adder:
Table 4.1: Truth Table for Half adder

Logic Design Unit 4
The figure 4.2 shows the logic circuit diagram for Half adder.
Figure 4.2: Circuit diagram for Half adder
Full adder: The figure 4.3 shows the the logic circuit diagram for Full adder
Figure 4.3: Circuit diagram for Half adder
Inputs: {A, B, Cin} Outputs: {Sum, Cout}

The figure 4.4 shows the schematic symbol for a 1-bit full adder.

Logic Design Unit 4
Figure 4.4: Schematic symbol for a 1-bit full adder
A full adder circuit adds the carry in Cin (or Ci) along with the two inputs A
and B. The full adder performs addition on 3 input bits and generates carry
and sum binary outputs. Multiple full adders can be used to perform the
addition of multibit (binary) inputs. The table 4.2 shows the truth table for
Full adder.
Table 4.2: Truth table for Full adder
Two half adder circuits can be used to implement a full adder circuit, the two
inputs A and B are connected to one half adder and its output sum is
connected as input to the second half adder. Carry in will be the other input
to the second half adder and two carry outputs are ORed. The Boolean
function for S can be expressed as XOR of three inputs A, B, Ci and a
majority function of A, B, and Ci can be Carry out equation. Sum of three
one bit numbers will be the output of the full adder circuit.

Logic Design Unit 4
4.3.2 Subtractors
The approach used for designing an adder can be used to design a
subtractor. Following is the summary of the process used for subtracting
binary numbers. For multi-bit numbers during subtraction of each bit,
following three bits will be involved: the subtrahend (Yi), minuend (Xi), and a
borrow in from the previous bit order position (Bi). The difference bit (Di) and
borrow bit Bi+1 are the outputs of the subtractor. Following is the equation
for the difference of two bits.
D i  X i  Yi  B i
4.3.3 Comparators
A digital comparator is a hardware electronic device that compares two
numbers in binary form and generates a one or a zero at its output
depending on whether they are the same (i.e. equal) or not.
Comparators can be used in a central processing unit (CPU) or
microcontroller in branching software. A comparator can be simulated by
subtracting the two values (A & B) in question and checking if the result is
zero. This works because if A = B then A - B = 0.
Many microcontrollers have analog comparators on some of their inputs that
can be read or trigger an interrupt.
The operation of a single bit digital comparator can be expressed as truth
table shown in the table 4.3.
Table 4.3: Truth table for Single Bit Comparator
The operation of a two bit digital comparator can be expressed as a truth

table shown in the table 4.4.

Logic Design Unit 4
Table 4.4: Truth table for Two Bit Comparator
Examples of the comparator include the CMOS 4063 and 4585 and the
TTL 7485 and 74682-'89.
4.3.4 Decoders
A decoder is a digital device which decodes the original information from the
encoded inputs. The functionality of a decoder is exactly the reverse of an
encoder. In order to decode the information from the signals, the method
used to encode the information is reversed.
In digital systems, decoder is a logic circuit with multiple inputs and multiple
outputs that produces a coded output from the coded inputs. In decoder the
input and output codes are different i.e., if there is an n-bit input code then
decoder produces 2n output code. So a decoder is a combinational circuit
that detects the binary information present on n input lines and decodes it
and indicates this decoded output on any one of the 2n output lines.

Logic Design Unit 4
The outputs of a decoder without enable input are assumed as single

“disabled” output code word. In digital circuits, decoders are used in many
applications like 7 segment display, multiplexing of the data and decoding of
the memory address.
When all the input of an AND gates are “high” the output will also be “high”,
therefore the AND gate can be considered as the simple decoder. The
output which goes “high” when the inputs are high is known as “active High
output". If NAND gate is connected instead of AND gate, then when all the
inputs are “high” the output will be "Low" (0). Such output is called as "active
low output". Example: A 2-to-4 Line Decoder. This is shown in figure 4.5.
Figure 4.5: 2-to-4 Line Decoder
A slightly more complex decoder would be the n-to-2n type binary decoders.
With n-to-2n binary decoders, maximum of ‘2n’ outputs are generated from
‘n’ coded inputs which carry information. For ‘n’ bit coded input, if there are
any unused combinations then number of outputs of the decoder can be
less than 2n. From above discussion we can say that a decoder can
produce maximum of 2n outputs. In digital systems various types of
decoders like 3-to-8 decoder, 2-to-4 decoder or 4-to-16 decoder are used.

Logic Design Unit 4
Two 2-to-4 decoders along with enable signal can be used to construct a 3-
to-8 decoders.
In the same way, a 4-to-16 decoder can be constructed by combining
two 3-to-8 decoders. In the above design process, the 4th input which is
given as enable input to both 3-to-8 decoders acts like selector between two
3-to-8 decoders.. The outputs D(0) through D(7) are produced by the first
decoder and D(8) through D(15) are produced by the second decoder, the
4th input in 4-to-16 decoder enables either the first decoder or second
decoder.
This kind of decoders with enable signals is also known as a decoder-
demultiplexer. Thus, we have a 4-to-16 decoder produced by adding a 4th
input shared among both decoders, producing 16 outputs.
4.3.5 Encoders
An encoder is a device used to change a signal (such as a bit stream) or
data into a code. The code may serve any of a number of purposes such as
compressing information for transmission or storage, encrypting or adding
redundancies to the input code, or translating from one code to another.
This is usually done by means of a programmed algorithm, especially if any
part is digital, while most analog encoding is done with analog circuitry.
Single bit 4 to 2 Encoder
An encoder has 2n input lines and n output lines. The output lines generate
a binary code corresponding to the input value. The figure 4.6 shows the
logic symbol of typical encoder.
Figure 4.6: Logic symbol of typical encoder.

Logic Design Unit 4
For example a single bit 4 to 2 encoder takes in 4 bits and outputs 2 bits.
The Gate level circuit diagram of a single bit 4-to-2 line encoder is shown in
figure 4.7 and its truth table shown in the table 4.5.
Figure 4.7: Gate level circuit diagram of a single bit 4-to-2 line encoder
Table 4.5: Truth table of 4-to-2 line Encoder
The encoder has the limitation that only one input can be active at any given
time. If two inputs are simultaneously active, the output produces an
undefined combination. To prevent this we make use of the priority encoder.
Priority encoder
A priority encoder is a digital circuit in which when two or more inputs are
given at the same time, the input having the highest priority will take
precedence. An example of a single bit 4 to 2 priority encoder is shown in
figure 4.8. Its truth table is shown in the table 4.6.

Logic Design Unit 4
Table 4.6: Truth table of 4 to 2 priority encoder
Figure 4.8: 4 to 2 priority encoder
Connecting Priority Encoders

Priority encoders can be easily connected in arrays to make larger
encoders, such as a 16 to 4 encoder made from six 4 to 2 priority encoders
(four encoders having the signal source connected to their inputs, and two
encoders that take the output of the first four as input).
4.3.6 Multiplexers
In electronics, multiplexing of many signals is performed by the device
known as multiplexer or mux. The combination of multiplexer and
demultiplexer is termed as muldex. Many analog or digital signals can be
given as input signals for the multiplexer; those input signals will be
multiplexed into a single output line. An expensive device or any other
resource can be shared with many signals using multiplexer, for example

Logic Design Unit 4
instead of using A/D converter or communication line for every input signal,
a single device can be used along with the multiplexer.
A multiplexer is a switch that has multiple inputs and single output. The
schematic symbol for a multiplexer is an isosceles trapezoid. Inputs are
connected to the multiplexer on the longer parallel side and output is
connected on short parallel side. In the schematic shown in figure 4.9, on
the left is the symbol for 2-to-1 multiplexer and on the right is the equivalent
switch of the multiplexer. The single output line can be connected to the
desired output through the sel wire.
In telecommunications, many communication channels can be carried using
multiplexer which combines many input signals (which carries information)
to a single output signal. A demultiplexer is a device which separates the
input signal to multiple output signals.
Figure 4.9: Schematic of a 2-to-1 Multiplexer
Multiplexer can be equated to a controlled switch.

Digital multiplexers
In digital circuit design, the values given for the selection line will be either
zero or one. In the case of a 2-to-1 multiplexer, input I0 is connected to the
output signal when logic 0 is applied to selection line and input I1 is
connected to output when logic 1 is applied to selection line. In larger
multiplexers, using n selection pins, 2n input signals can be multiplexed.
For example, 4 selection pins are required to multiplex 9 to 16 input signals
and 5 selection pins are required to multiplex 17 to 32 input signals. The
selected input pin can be determined by the binary values on the selection
pins.

Logic Design Unit 4
For a 2-to-1 multiplexer shown in figure 4.10, the Boolean equation in terms
of inputs and output can be as follows:
Where A and B are two input signals, S0 is the selection line, and Z is the
output signal.
Figure 4.10: A 2-to-1 mux
This can be expressed in truth table as shown in the table 4.7.
Table 4.7: Truth table for 2-to-1 Mux
S A B Z
0 0 0
0 1 0
0
1 0 1
1 1 1
0 0 0
0 1 1
1
1 0 0
1 1 1
From the truth table 4.7, it can be observed that output Z will be equal to A
when selection line S is 0 and Z is equal to B when S is 1. In order to realize
the 2-to-1 multiplexer using gates, it requires 2 AND gates, a NOT gate and
an OR gate.
In present day digital systems, large multiplexers are used commonly and,
as stated above, for n input signals [log2 (n)] selection pins are required.
Multiplexers that are used frequently apart from 2-to-1 multiplexer are
16-to-1, 8-to-1 and 4-to-1 multiplexers. Since digital logic uses binary
values, for a given number of selection lines powers of 2 (2, 4, 8, 16) is used

Logic Design Unit 4
to control the number of inputs signals. The figure 4.11 shows the symbol of
4 to1 Mux and figure 4.12 shows the symbol of 8 to1 Mux
Figure 4.11: 4 to1 Mux Figure 4.12: 8 to1 Mux
The truth table of 4 to 1 Mux is shown in the table 4.8.
Table 4.8: Truth table of 4 to 1 Mux
The Boolean equation for a 4-to-1 multiplexer is:
The figure 4.13 shows the logic circuit diagram of 4 to1 Mux.
Figure 4.13: Logic circuit of 4 to1 Mux

Logic Design Unit 4
4.3.7 De-Multiplexers
In electronics, a demultiplexer is a device which separates the input signal
to multiple output signals. At the receiving end demultiplexer can be used as
a complementary to the multiplexer which is at transmitting end. A
demultiplexer can be considered as switch with single input and multiple-
outputs. The figure 4.14 shows schematic of a 1 to 2 demultiplexer. A
demultiplexer can also be equated to a controlled switch.
Figure 4.14: Schematic of a 1 to 2 Demultiplexer
4.4 Gray Code and its Properties

A Gray code is a function G(i) of the integers i, that for each integer N ≥0 is
one-to-one for 0 ≤ i ≤ 2N − 1, and that has the following remarkable property:
There will be only one bit difference between binary representation of
G(i) and binary representation of G(i+1). Gray code is most commonly used
technique in constructing digital systems. An example of a Gray code is, the
sequence 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, 1101,
1111, 1110, 1010, 1011, 1001, and 1000. The bitwise exclusive or (XOR) of
i with i /2(integer part) is performed to generate the Gray code. Think about
how the carries work when you add one to a number in binary, and you will
be able to see why this works. You will also see that G(i) and G(i+1) differ in
the bit position of the rightmost zero bit of i (prefixing a leading zero if
necessary).
The Gray codes are named after Frank Gray who patented the idea of using
Gray codes in shaft encoders. A shaft encoder is a wheel which uses a fixed
conducting brush to read the concentric coded stripes in order to generate a
binary code for position of the wheel. Constructing a shaft encoder having a
stripe conducting on one half of the wheel, insulating on other half; the next
stripe is conducting in quadrants 1 and 3; the next stripe is conducting in
octants 1, 3, 5, and 7; and so on. Then the brushes read a binary code from
concentric coded stripes which describes the angle of the wheel.

Logic Design Unit 4
With the above method, when the wheel is turning there is no guarantee
that all the brushes break or make contact with stripes at the same time. As
different brushes break or make contact, while going from position 7 (0111)
to 8 (1000), one might pass spuriously and transiently through 6 (0110),
14 (1110), and 10 (1010).
One can avoid the transient states between 7 and 8 by using Gray code on
the encoding stripes. An algorithm or a circuit which translates back the
Gray code to integer is required. The Gray code is generated by a cascade
of XOR gates; XOR of all most significant input bits gives an individual
output bit. In a circuit, N-1 steps are required to perform the inversion of N
bit Gray code. In a register with binary word operations, instead of doing N
operations consecutively on ln2N operations are sufficient. The number of
operations can be reduced by using associativity of XOR and hierarchically
grouping the operations. The above step involves the right shits of input bits
by 1, 2, 4, 8, and so on bits till the word length are zero.
Gray codes are not arithmetic codes. 4 bit gray code numbers for binary
numbers are shown in table 4.15.
Table 4.9: 4 bit gray code numbers for Binary numbers
Decimal Binary code Gray code

0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101

Logic Design Unit 4
Binary to Gray Conversion:

Binary to gray conversion employs following rules
o The most significant bit (MSB) in the Gray code is the same as the
corresponding digit in the binary number
o Starting from left to right, perform Ex-OR operation on adjacent pair of
binary bits to get the next Gray code bit.
Example: Compute the Gray code of the Binary number 110010(2)
Binary
1 1 0 0 1 0
Number
↓
Gray
1
Code
Binary
Number
1  1 0 0 1 0
↓
Gray
1 0
Code
Binary
Number
1 1  0 0 1 0
↓
Gray
1 0 1
Code
Binary
Number
1 1 0  0 1 0
↓
Gray
1 0 1 0
Code
Binary
Number
1 1 0 0  1 0
↓
Gray
1 0 1 0 1
Code
Binary
Number
1 1 0 0 1  0
↓
Gray
1 0 1 0 1 1
Code
Thus Binary number 110010 has a Gray code 101011

Logic Design Unit 4
A combinational logic circuit to implement binary to gray code conversion is

shown in figure 4.15 which employs Ex-OR logic gates.
Figure 4.15: Logic circuitry for 5 bit Binary to Gray Conversion
Gray code to Binary Conversion

To convert from Gray code to binary, a similar method is used with the
following rules
o The most significant bit (MSB) in the binary code is the same as the
corresponding digit in the Gray code
o Perform Ex-OR operation with each binary bit generated to the next
Gray code bit to get new binary bit.

Logic Design Unit 4
Example: Convert the Gray code 101011 to Binary

Gray
1 0 1 0 1 1
Code
↓
Binary
1
Number
Gray
1 0 1 0 1 1
Code
 ↓
Binary
1 1
Number
Gray
1 0 1 0 1 1
Code
 ↓
Binary
1 1 0
Number
Gray
1 0 1 0 1 1
Code
 ↓
Binary
1 1 0 0
Number
Gray
1 0 1 0 1 1
Code
 ↓
Binary
1 1 0 0 1
Number
Gray
1 0 1 0 1 1
Code
 ↓
Binary
1 1 0 0 1 0
Number
Thus Gray code 101011 has a Binary number 110010

A combinational logic circuit to implement binary to gray code conversion is
shown in figure 4.16 which employs Ex-OR logic gates.

Logic Design Unit 4
Figure 4.16: Logic circuitry for 5 bit Gray to Binary Conversion
4.5 BCD Code and its properties

In digital system, decimal numbers are encoded to binary sequence using
binary coded decimal (BCD) technique. The advantage of the BCD
encoding is that the conversion of binary sequence to decimal digits for
printing or display is easier and also the decimal calculations will be faster.
The drawbacks of the BCD encoding are the complexity of the digital circuits
which are used to implement the mathematical operations increases and
because of a relative inefficient encoding than a pure binary representation
BCD requires more space.
For financial, industrial and commercial computing, decimal fixed point and
floating point are used frequently, but BCD is not used widely as it was
once. Instead of using BCD encodings, base 10 exponents are used to
represent modern floating point. In BCD, four bits are used to represent a
digit. In general these fours bits represent the values/digits/characters 0-9.
For sign or other indications, other bit combinations are used.
To BCD-encode a decimal number using the common encoding, each
decimal digit is stored in a four-bit nibble.
Decimal: 0 1 2 3 4 5 6 7 8 9
BCD: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

Logic Design Unit 4
Thus, the BCD encoding for the number 256 would be:
0010 0101 0110
As the data in most of the computers are stored in eight bit bytes, the four
bit BCD digits can be stored in those bytes using two ways:
In a byte, BCD digit is stored in one nibble, and other nibble of a byte is set
to all zeros or all ones (as in the EBCDIC code), or to 0011 (as in the ASCII
code) two digits are stored in each byte.
By mapping each nibble to a different character, BCD encoded numbers
can be easily displayed. Generally, integer multiplication or division
operation are involved in conversion of binary coded number to decimal,
because of above reason the display of binary coded number is harder. In
electronic systems which have only digital logic but no microprocessor, BCD
is used to display the numeric values. In BCD each digit has been treated
as a single sub circuit, because of that the manipulation of numerical values
for display can be simplified to great extent. This matches much more
closely the physical reality of display hardware. For example, a designer can
develop a metering circuit by choosing a series of identical 7-segment
displays. A complex circuitry would be required to interface a display device
if the numeric data is manipulated and stored in the form of pure binary.
Therefore, using BCD a simple digital system can be developed than
converting to pure binary, and also calculations are relatively simple. Even
the digital system which has embedded microcontroller or small processor
will hold the same argument. On limited processors the process of
converting numeric’s to or from binary representation can be expensive,
less expensive systems can be developed by representing numeric’s in
BCD format and often it results in smaller code. For these applications,
some small processors feature BCD arithmetic modes, which assist when
writing routines that manipulate BCD quantities.
Packed BCD
In packed BCD encoding two digits are placed in a single byte. Packed BCD
encoding is also known as simply packed decimal. Decimal integers are
stored in all upper bytes plus upper four bits of the lowest byte of a multi
byte word. The lower four bits of the lowest byte are used as the sign flag.
As an example, in a word of 32 bits which contains 8 nibbles or 4 bytes

Logic Design Unit 4
lowest nibble is used stores sign flag of the decimal value and integers are
stored in upper 7 nibbles.
Standard sign values are 1100 (Hex C i.e Ch) for positive (+) and 1101 (Dh)
for negative (–). Other allowed signs are 1010 (Ah) and 1110 (Eh) for
positive and 1011 (Bh) for negative. Some implementations also provide
unsigned BCD values with a sign nibble of 1111 (Fh). In packed BCD, the
number 127 is represented by "0001 0010 0111 1100" (127Ch) and -127 is
represented by "0001 0010 0111 1101 (127Dh).
Sign BCD
Digit 8 4 2 1 Sign Notes
A 1010 +
B 1011 −
C 1100 + Preferred
D 1101 − Preferred
E 1110 +
F 1111 + Unsigned
As two digits are stored in a byte, the number of nibbles is always even
irrespective of size of the word. Therefore there can be (2n)-1 decimal digits
in a n bytes word. The number of decimal digit is always odd. A decimal
number with d digits requires ½(d+1) bytes of storage space.
For example, a four-byte (32bit) word can hold seven decimal digits plus a
sign, and can represent values ranging from ±9,999,999. Thus the number
-1,234,567 is 7 digits wide and is encoded as:
0001 0010 0011 0100 0101 0110 0111 1101
1 2 3 4 5 6 7 -
(Note that, like character strings, irrespective to endianness of the digital
system – lowest address space in memory is used to store the first byte of
the packed decimal).
In contrast, a four-byte binary two's complement integer can represent
values from −2,147,483,648 to +2,147,483,647.
While packed BCD does not make optimal use of storage (about 1/6 of the
memory used is wasted), conversion to ASCII, EBCDIC, or the various
encodings of Unicode is still trivial, as no arithmetic operations are required.

Logic Design Unit 4
The extra storage requirements are usually offset by the need for the
accuracy that fixed-point decimal arithmetic provides. More dense packings
of BCD exist which avoid the storage penalty and also need no arithmetic
operations for common conversions.
Fixed-point packed decimal
Programming languages such as COBOL and PL/I support fixed point
decimal numbers, and a decimal point has to be provided in front of one of
the digits. For example, the fixed point value +1234.567 can be represented
by 12 34 56 7C (a packed decimal value) if the decimal point is placed
between 4th and 5th digits.
12 34 56 7C
12 34.56 7+
Higher-density encodings
Totally 12 bits are required for a three decimal digits if each digit is
represented using four bits. However, since 210 (1,024) is greater than 103
(1,000), only 10 bits are sufficient if the encoding of all three decimal digits
done together. Two such encodings are Chen-Ho encoding and Densely
Packed Decimal. Densely Packed Decimal encodes two digits in the optimal
7 bits and one digit in 4 bits.
Zoned decimal
An IBM mainframe system uses Zoned decimal numeric representations. In
this encoding, each digit is stored in one byte with lower four bits encoding
the digit in BCD form. The upper bits are called the zone bits; they are set to
a fixed value so that the character value of the digit is stored in the byte.
EBCDIC systems use a zone value of 1111 (hex F); this yields bytes in the
range F0 to F9 (hex), which are the EBCDIC codes for the characters "0"
through "9". Similarly, ASCII systems use a zone value of 0011 (hex 3),
giving character codes 30 to 39 (hex). For signed zoned decimal values, the
sign digit of a numeric is stored in the least significant zone nibble of the
byte. Even for packed decimal, sign bits are stored in the same set of
values. Thus a zoned decimal value encoded as hex bytes F1 F2 D3
represents the signed decimal value −123.
i.e. F1 F2 D3 is the zoned representation of -123.

Logic Design Unit 4
The table 4.10 shows the zoned decimal conversion table

Table 4.10: EBCDIC zoned decimal conversion table
Digit EBCDIC Display EBCDIC Hex
0+ {(*) X'C0'
1+ A X'C1'
2+ B X'C2'
3+ C X'C3'
4+ D X'C4'
5+ E X'C5'
6+ F X'C6'
7+ G X'C7'
8+ H X'C8'
9+ I X'C9'
0− } (*) X'D0'
1− J X'D1'
2− K X'D2'
3− L X'D3'
4− M X'D4'
5− N X'D5'
6− O X'D6'
7− P X'D7'
8− Q X'D8'
9− R X'D9'
(*) Note: These characters vary depending on the local character code page.
Fixed-point zoned decimal

Languages like COBOL and PL/I use fixed point decimal values. The
decimal point will be assigned at some location between the decimal values
of a number. For example, given a seven-byte signed zoned decimal value
with an implied decimal point to the right of the fifth digit, the hex bytes
F3 F2 F1 F6 F8 F4 C0 represent the value +32,178.40:
F3 F2 F1 F6 F8 F4 C0
3 2 1 6 8. 4 +0

Logic Design Unit 4
IBM and BCD

For 6-bit alphanumeric codes that represents special characters, numbers
and upper case letters, IBM uses the terms BCD and binary coded decimal.
In most early IBM computers use some variations of BCD alphanumerics.
These computers include IBM 1400 series, IBM 1620 and non-Decimal
Architecture members of IBM 700/7000 series.
In BCD B, A, 8, 4, 2, 1 is labeled as bit positions. B and A are zero’s while
encoding for digits. The letter A was encoded (B, A, 1).
In IBM 1620 computer, a digit pairs are used to encode the BCD
alphanumerics. In those digit pairs, the “digit” will be the odd digit and the
“zone” will be the even digit. The conversion between external standard 6 bit
BCD codes and the internal digit pairs is done by the input/output translation
hardware.
In the Decimal Architecture 7074, 7070, and 7072, digit pairs of 10-digit
word are used to encode the alphamerics. These digit pairs instead of BCD
digits, use two-out-of-five code in the digits. “Digit” will be in right digit of
digit pair and zone will be in the left of digit pair. The conversion between
external standard 6 bit BCD codes and the internal digit pairs is done by the
input/output translation hardware.
In IBM System/360, the addition of more characters like lowercase letters
are allowed by expanding 6 bit BCD alphanumerics to 8 bit EBCDIC. Also
IBM implemented a variable length Packed BCD numeric data type.
The current IBM databases and processors still use BCD data. BCD in the
IBM processors and databases are usually Packed BCD, zoned BCD as in
ASCII or EBCDIC or “pure” BCD encoding. The software, processing units
and hardware registers uses the above BCD encodings.
Addition with BCD
The addition in BCD can be performed in three steps: 1) Add the numbers in
binary. 2) Check if the number is greater than 9. 3) Then convert the sum of
two numbers to BCD number by adding correction value. The correction
value will be equal to 6 if the sum output in step 1 is greater than 9, else the
correction value will be zero. For example:
8 + 6 = 14 = [1000] + [0110] = [0000 1110] in binary.

Logic Design Unit 4
However, in BCD, per nibble value greater than 9 cannot exist. To correct
the value of first two digits, sum will be added with 6 (0110):
[0000 1110] + [0000 0110] = [0001 0100]
[0001] and [0100] are two nibbles, which correspond to "1" and "4"
respectively. This gives correct result “14” in BCD. The above technique can
be extended to adding multiple digits groups from right to left, the second
digit is propagated as a carry, and always 5 bit result is compared to 9.
Subtraction with BCD
Subtraction is done by adding the nines' complement plus 1, or by adding
the ten's complement of the subtrahend.
4.6 Excess-3 Code and its Properties

Excess-3 binary coded decimal (XS-3), also called biased representation or
Excess-N, is a numeral system used on some older computers that uses a
pre-specified number N as a biasing value. It is a way to represent values
with a balanced number of positive and negative numbers. In XS-3,
numbers are represented as decimal digits, and each digit is represented by
four bits as the BCD value plus 3 (the "excess" amount):
The smallest binary number represents the smallest value. (i.e. 0 - Excess
Value).The greatest binary number represents the largest value.
(i.e. 2N+1 - Excess Value - 1). The table 4.11 shows the XS3 code for
decimal numbers.
Table 4.11: XS3 code for decimal numbers.
Decimal Binary Decimal Binary Decimal Binary Decimal Binary

-3 0000 1 0100 5 1000 9 1100
-2 0001 2 0101 6 1001 10 1101
-1 0010 3 0110 7 1010 11 1110
0 0011 4 0111 8 1011 12 1111
To encode a number such as 127, then, one simply encodes each of the
decimal digits as above, giving (0100, 0101, 1010).
The primary advantage of XS-3 coding over BCD coding is that a decimal
number can be nines' complemented (for subtraction) as easily as a binary
number can be ones' complemented; just invert all bits.

Logic Design Unit 4
Adding Excess-3 works on a different algorithm than BCD coding or regular

binary numbers. When you add two XS-3 numbers together, the result is not
an XS-3 number. For instance, when you add 1 and 0 in XS-3 the answer
seems to be 4 instead of 1. In order to correct this problem, when you are
finished adding each digit, you have to subtract 3 (binary 11) if the digit is
less than decimal 10 and add three if the number is greater than or equal to
decimal 10.
Assessment Questions
1. Circuits whose outputs depend only on the current inputs are called
___________________.
2. The circuit which adds the carry bit from previous stage with two one bit
inputs is known as __________________.
3. A ____________ circuits will generate sum (S) and carry (C) from the
two of its inputs A and B.
4. Comparators can be used in a central processing unit (CPU) or
microcontroller in branching software (True or False?).
5. A ________________ is a digital device which decodes the original
information from the encoded inputs.
6. A __________________ is a digital circuit in which when two or more
inputs are given at the same time, the input having the highest priority
will take precedence.
7. The ________________are named after Frank Gray who patented the
idea of using Gray codes in shaft encoders.
8. The Gray code is generated by a cascade of OR gates (True or False?).
9. In binary to gray code conversion, the most significant bit (MSB) in the
gray code is the same as the corresponding digit in the binary number
(True or False?).
10. An IBM mainframe system uses ______________ decimal numeric
representations.
11. Excess-3 binary coded decimal (XS-3), also called ________________.
12. When you add two XS-3 numbers together, the result is not an XS-3
number (True or False?).

Logic Design Unit 4
4.7 Summary
 A digital circuit which generates a set of outputs from set of inputs using
Boolean operations is known as combinational circuits.
 A half adder is a digital circuit which accepts two inputs and performs
addition on them and generates two binary digits known as sum(S) and
carry(C).
 A digital comparator is a hardware electronic device that compares two
numbers in binary form and generates a one or a zero at its output
depending on whether they are the same (i.e. equal) or not.
 An encoder is a device used to change a signal (such as a bit stream) or
data into a code.
 A decoder is a digital device which decodes the original information from
the encoded inputs.
 Multiplexing of many signals is performed by the device known as
multiplexer or mux.
 In packed BCD encoding two digits are placed in a single byte.
 Excess-3 binary coded decimal (XS-3), also called biased
representation

1. What is a full adder? Explain the operation with a neat logic diagram.
2. What is comparator? Design the combinational circuit that will compare
two bits A and B produce 3 outputs A>B, A=B and A<B.
3. What is the function of decoder? Explain.
4. What is an encoder? Explain priority encoder.
5. What is Multiplexer? Draw the logic diagram of 4 to 1 line multiplexer.
6. Explain Binary to Gray Conversion with an example.
4.9 Answers
1. Combinational
2. Full adder
3. Half adder
4. True
Logic Design Unit 4
5. Decoder
6. Priority encoder
7. Gray codes
8. True
9. True
10. Zoned
11. Biased representation
12. True
Terminal Questions
1. Refer to section 4.3.
2. Refer to section 4.3.3
3. Refer to sub-section 4.3.4

Logic Design Unit 5
Unit 5 Sequential Circuits and Applications

Structure:
5.1 Introduction
Objectives
5.2 Definition of Sequential Circuits
5.3 Latch
5.4 Flip-Flop
S-R Flip Flop
J-K Flip Flop
D-Flip Flop
J-K Master Slave Flip Flop
5.5 Real world Applications of Sequential Circuits
5.6 Summary
5.8 Answers to Self Assessment Questions
5.1 Introduction
In the previous unit we studied about combinational circuits, and different
codes like Gray code, BCD code, and Excess-3 code. In 1918 William
Eccles and F.W. Jordan invented the first flip flop. Initially it was named after
the inventers and was called as Eccles Jordan trigger circuit. The name flip-
flop was later derived from the sound produced on a speaker connected to
one of the back coupled amplifiers outputs during the trigger process within
the circuit. This original electronic flip-flop – a simple two-input bistable
circuit without any dedicated clock (or even gate) signal, was transparent,
and thus a device would be labeled as a "latch" in many circles today.
In digital circuits, combinational circuits don’t have memory to store the
values and its output depends only on the inputs. A powerful model is
required to build a complex digital system. In order to build a powerful
model, a digital circuit which has a memory and its output should depend on
its previous state and also on the input to the circuit is required. So a device
should have following three characteristics to serve as a memory:
 two stable states should exists in the device
 the state of the device should be readable.
 at least once, we should be able to set the state of the device.

Logic Design Unit 5
The concept of feedback should be used to construct a digital circuit with

memory. The digital circuits are said to be acyclic if the logical flow is from
input to output. In this unit, we will study about the definition of sequential
circuit, latches and flip flops and various types of flip-flops and their
operation.
Objectives:
 define sequential circuits
 define Latch
 list and explain different types of Flip-Flops
 discuss on real world applications of sequential circuits
5.2 Definition of Sequential Circuits

Both combinational circuits such as universal gates and memory such as
latches and flip flops are used to construct a digital system. In many
sequential circuits (like counter and shift registers), we can see the
interconnection of both logic gates and memory elements. While designing
the digital systems, the additional variable and timing information of the
memory should be taken care. Sequential logic operations should be
performed, the data is stored in a memory and later combinational operation
uses the data when it is released from the memory. The digital systems
which perform sequential operations are known as sequentially operated
systems. Sequential circuits are those whose outputs depends not only on
the present value of its inputs but also on past history of its inputs. There
are two types of memory elements which are used in sequential circuits,
they are latch and flip flop. Flip flop is a device which changes its state at
the positive edge or negative edge (also known as leading edge and trailing
edge) of the clock signal. Asynchronous latch is a device which changes its
state whenever there is a change in the input signals irrespective of control
signal value. A synchronous latch is device which monitors the input signal
and changes its state whenever the control signal is high.
Events are used to drive both Asynchronous and Synchronous latches. But
the output of the synchronous latch is changed only when the control signal
is active.

Logic Design Unit 5

1. The digital systems which perform sequential operations are known as
sequentially operated systems. (True or False?).
2. ___________ is a device which changes its state at the positive edge
or negative edge of the clock signal.
5.3 Latch
The S-R Latch
The figure 5.1 shows the SR latch constructed using NOR gates. From
figure 5.1, it can be observed that the output of each NOR gate is given as
feedback to the other NOR gate.
Figure 5.1: The S-R Latch. S sets the latch, causing Q to become true.
R resets the latch.
When both the inputs to an NOR gate are low, the output will be high. From
the circuit it can be analyzed that among two NOR gate outputs, only one
output will be high and other will be low. Consider that the output of the
upper NOR gate ( Q ) is high, as this output is connected as input to the
lower NOR gate its output will be low. This circuit is an S-R latch. Where S
stands for set and R stands for reset, because of which it is also known as
set-reset latch.
By examining the circuit we can see that both the inputs of NOR gate should
be low to generate a high output. When the set S button is pressed, the
output of the latch will be high i.e.; output of lower gate and its complement
output will be low. The latch will be set i.e. its output will be high when the
Set S input is high, and the latch will be reset i.e., its output will be low when
the reset R input is high. Even when the inputs are removed the circuit will
be in the stable state. The inputs which generated a particular output and

Logic Design Unit 5
unchanged the output value can be removed. The complementary input

changes the output and the state of the circuit. As the circuit has two stable
states, this kind of circuits are said to be bistable.
The figure 5.2 shows the logic symbol of SR latch.
Figure 5.2: The symbol for the S-R latch
The availability of the complemented output pin depends on the packaging

of the latch and on the availability of an extra pin. Both the outputs of the
circuit will be false if both inputs S and R are equal to 1. This kind of outputs
is inconsistent logically and also the circuit will be in unstable state. The
circuit will come to stable state from unstable state when one of the inputs is
made low and the output also changes. The circuit which stores a single bit
is described by a keyword latch.
Timing Considerations
Before discussing further topics, the scenario like the output of the
combinational circuit formed from the combination of outputs from two or
more gates should also be considered. In the earlier topics, it has been
discussed that in a transistor, switching happens in nanoseconds, but even
this switching time will cause a finite amount of time delay to change in the
output for the given inputs. This time is called gate delay. Causing of wrong
output because of the timing dependencies is known as hazard.
Clocking
A storage element which accepts the input only upon event should be
designed to avoid glitches. The event is given only when the input to the
storage device which is computed by the combinational circuits have a
chance to settle down to the correct value.
One way to do that is to interpose AND gates between the S and R inputs
and the latch circuit. The control signal drives the other input of each AND
gate. When the control signal is false, the output of the two AND gates is
always low and changes to S and R do not affect the bit stored by the latch.

Logic Design Unit 5
When the control signal is true, the S and R signals are propagated through
the AND gates and the stored value can change. Because the control input
is generally driven by a regular train of pulses, it is often called a clock input.
Figure 5.3-A shows the digital circuit of a clocked S-R latch and figure 5.3-B
shows the symbol for the clocked S-R latch.
Figure 5.3-A: Clocked S-R latch. The latch can change only when C is true.
Figure 5.3-B: The symbol for the clocked S-R latch.
First experiment the given digital circuit with different combination of S and
R inputs by giving low to C input. Later a high value is applied to C and
circuit is experimented with different values of S and R inputs. But when
both S and R inputs are high, clocking will not help much. When S and R
values are equal to 1, and C is clocking, it is difficult to predict which value
will be stored in the memory, either true value or complement value. But
latch will settle down to one of the two stable states when both inputs S and
R are removed at the same time.
The Clocked D-Latch
When the idea of clocking is applied to S-R latch, the problem of what
should happen when S=R=1 can be taken care of and the input to the circuit
can also be simplified.
Usually one bit information should be stored in the memory element. The
complexity of the circuit increases when the set and reset of the latch are
explicitly needed.

Logic Design Unit 5
The main intention is to design a circuit which has a data input and data
output. When the clock signal is high, irrespective of the value at data input
D storage device should store the value of D and transfer to the data output
Q.
Figure 5.4-A shows the circuit for clocked D latch and the figure 5.4-B
shows the logic symbol of clocked D latch.
Figure 5.4-A: Cloked D-latch.When C(control) is true,the value at D(data) is

stored
Figure 5.4-B: The symbol for the clocked D latch
The circuit shown in above figure 5.4-A has two inputs. One is control input
and other is data input. An AND gate is used to connect the data input to the
S input of an S-R latch and the data input is connected to R input through
an inverter and an AND gate. The control input C is connected as the
second input to both the AND gates. The state of the latch will not change
when the control input C is applied with low value. When the control input
and the data input are true (i.e. High), the Set input of the latch also will be
true and therefore the true value is stored in the element. When the control
input is true and the data input is false, the Reset input of the latch also will
be true and therefore the false value (i.e low value) is stored in the element.

Logic Design Unit 5
Here is something to think about: The concept of a D latch, where the bit to
be stored is applied to the S input of a latch, and through an inverter to the
R input, can only be made to work when the latch is clocked. Why is that?
When the control input is true, the clocked D latch stores the data input D
value. The correct value of D will be stored in the latch if the control input is
triggered only when the input to the circuit is settled.
The functionality of the circuit is analyzed by asserting the value of C and
changing the values of D. The output of the circuit will be equal to the data
input D if the C input is high. This kind of clocked D latches are said to be
level triggered devices, the level at C says whether to store the data or not.
3. The latch will be set when the Set S input is ________________.
4. Usually one bit information should be stored in the _________element.
5. The control input which is generally driven by a regular train of pulses
is often called a _____________ input.
6. When the control input is true, the clocked D latch stores the data input
D value (True or False?).
5.4 Flip Flop

Usually the master slave devices are implemented using clocked flip flops.
The two basic flip flops in master slave devices make the circuit insensitive
to the noise and spike which are occurred between two clock transitions.
This circuit might have asynchronous reset or set which changes the
present value of the output irrespective of clock signal.
Flip-flops can be further divided into types that have found common
applicability in both asynchronous and clocked sequential systems: the SR
("set-reset"), D ("data" or "delay"), T ("toggle"), and JK types are the
common ones; all of which may be synthesized from (most) other types by a
few logic gates. The behavior of a particular type can be described by what
is termed the characteristic equation, which derives the "next" (i.e., after the
next clock pulse) output, Qnext, in terms of the input signal(s) and/or the
current output, Q. The circuit which is capable of remembering the applied
input is called a flip flop. As the flip flop stores the given values, in a memory
device it can be used as basic storage device. Only one bit information can
be stored in a Flip Flop.
Logic Design Unit 5
Basic flip-flops
Two NOR gates or two NAND gates can be used to construct a flip flop.
Usually flip flop are used in constructing the sequential circuits. As Flip flop
has two stable states, it is also known as bi-state gate. Until the trigger is
received by the flip flop, it maintains its state for indefinite amount of time.
When the trigger is applied according to the predefined rules, the state of
the flip flop changes and the new state will be unchanged till another trigger
is applied.
Flip – Flop circuit using NOR gates
The functionality of the flip flop can be explained using cross coupled two
NOR gates or NAND gates. The cross coupled circuits will have the
feedback paths. The figure 5.5 shows the logic diagram of SR Flip flop using
NOR gates
Figure 5.5: SR Flip flop using NOR gates
Normal value (Q) and the complement value ( Q ) are the two outputs of a
flip flop. Set(S) and Reset (R) are the two inputs for above circuit. The
current state of the output is determined by the feeding back the previous
states. i.e output is feedback to the input as shown in figure 5.5. Flip-flops
which are constructed using NOR gates works normally at input equal to
logic zero.
When the S input is equal to 1 and R input is 0, the output Q is equal to 0.
As this Q value is given again along with R, the output Q will become 1.
Therefore, from the above discussion we can say that when S = 1and R = 0,
outputs Q will be 1 and Q will be 0.
The state of outputs will be unchanged even when the Set input is made 0
and R is also 0. When the S input is equal to 0 and R input is 1, the output
Manipal University of Jaipur B0948 Page No. 100

Logic Design Unit 5
Q is equal to 0. As this Q value is given again along with S, the output Q

will become 1. Therefore, from the above discussion we can say that when
S = 0 and R = 1, outputs Q will be 0 and Q will be 1. The state of outputs
will be unchanged even when the Set input is 0 and R is made 0. The truth
table for S-R flip flop is shown in the table 5.1.
Table 5.1: Truth table for S-R flip flop
The outputs Q and Q are 0’s when inputs S = 1 and R = 1. This violates the
fact that Q and Q are complement to each other. This condition must be
avoided in normal operations.
From the above discussion, it can be observed that the flip flop has two
stable state i.e., set state (Q =1, Q = 0) and reset state (Q = 0, Q = 1).
Flip – Flop Circuit using NAND Gates

By cross coupling the NAND gates a flip flop can also be constructed. This
is shown in figure 5.6.
Figure 5.6: SR Flip flop using NAND gates
The corresponding truth table is given in table 5.2.

Logic Design Unit 5
Table 5.2: Truth table for S-R flip flop using NAND gates
Flip flops which are constructed using NAND gates works normally at input
equal to logic one. When the input S is applied with logic 0, then the outputs
Q will be 1 and Q will be 0. Then flip flop is said to be in set sate. If R input
is applied with logic 0, then outputs Q will be 0 and Q will be 1. Then flip
flop is said to be in reset state. Both the output Q and Q will be 1 if S and R
inputs are applied with logic 0. In normal operation this condition must be
avoided.
R-S, D, J-K and T are the different types of flip flops used in designing
sequential circuits. The digital circuits like memories and microprocessors
can be constructed by interconnecting flip-flops to form the logic gates.
5.4.1 SR flip-Flop
The figure 5.7 shows the logic symbol of Set-Reset flip-flops (SR flip-flop).
Figure 5.7: The symbol for an SR flip flop
Normally, in storage mode, the S and R inputs are both low, and feedback
maintains the Q and Q outputs in a constant state, with Q the complement
of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced
high, and stays high even after S returns low; similarly, if R (Reset) is pulsed
high while S is held low, then the Q output is forced low, and stays low even
after R returns low. The table 5.3 shows the truth table SR flip-flop which
shows the operation of SR flip-flop.

Logic Design Unit 5
Table 5.3: Truth table for the operation of SR flip-flop
SR Flip-Flop operation
Characteristic table Excitation table
S R Action Q(t) Q(t+1) S R Action
0 0 Keep state 0 0 0 X No change
0 1 Q=0 0 1 1 0 Set
1 0 Q=1 1 0 0 1 Reset
1 1 Unstable combination, 1 1 X 0 No change
5.4.2 JK flip-flop
The figure 5.8 shows the timing diagram for JK flip-flop.
Figure 5.8: JK flip-flop timing diagram
The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset)

by interpreting the S = R = 1 condition as a "flip" or toggle command. The
flip flop will be set when J is 1 and K is 0; and flip flop will be reset when J is
0 and K is 1; the output of the flip flop will toggle when both J and K are
1.Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the
current state. The D flip flop can be obtained from JK flip flop by setting
complement of J to K. As JK flip flop can be configured to any of other 3 flip
flops (SR, D, T), it is considered as Universal flip flop. The figure 5.9 shows
the logic symbol of JK flip-flop.
Figure 5.9: The symbol of JK flip flop

Logic Design Unit 5
In the JK flip flop circuit symbol, the clock input is shown as > and data
inputs are J, K. Q and Q are the data outputs. The characteristic equation
of the JK flip-flop is:
And the corresponding truth table is shown n in the table 5.4.

Table 5.4: Truth table for the operation of JK flip-flop
JK Flip Flop operation

Characteristic table Excitation table
J K Qnext Comment Q Qnext J K Comment
0 0 hold state 0 0 0 X No change
0 1 Reset 0 1 1 X Set
1 0 Set 1 0 X 1 Reset
1 1 toggle 1 1 X 0 No change
The origin of the name for the JK flip-flop is detailed by P. L. Lindley, a JPL
engineer, in a letter to EDN, an electronics design magazine. The letter is
dated June 13, 1968, and was published in the August edition of the
newsletter. In the letter, Mr. Lindley explains that he heard the story of the
JK flip-flop from Dr. Eldred Nelson, who was responsible for coining the
term while working at Hughes Aircraft. Flip-flops in use at Hughes at the
time were all of the type that came to be known as J-K. Another theory
holds that the set and reset inputs were given the symbols "J" and "K" after
one of the engineers that helped design the J-K flip-flop, Jack Kilby.
5.4.3 D flip-flop
The symbol of D flip flop is shown in the figure 5.10.
Figure 5.10: Symbol of D flip flop

Logic Design Unit 5
During the positive edge of the clock or negative edge of the clock, the
output of the flip flop will take the value of D. The flip flop output should not
take the values of inputs on both the edges of the clock. As the output of the
flip flop takes the value of input after one clock cycle, it is called the D or
Delay flip flop. The D flip flop can also be used as a memory cell or zero
order hold or a delay line. The table 5.5 shows the truth table of D flip-flop.
Table 5.5: Truth table of D flip-flop

Clock D Q Qprev
Rising edge 0 0 X
Rising edge 1 1 X
Non-Rising X constant
('X' denotes a Don't care condition, meaning the signal is irrelevant)

All the shift registers which are important part of digital system are
constructed using flip flops. When compared to D latch, the advantage of
the D flip flop is that the input is captured only during positive edge or
negative edge of the clock and any changes in input line will not be stored in
flip flop at the high or low level of the clock. A flip flop can have a reset
signal which can be used to reset the output to zero; the reset to the flip flop
can be synchronous or asynchronous.
Master-slave (pulse-triggered) D flip-flop
By connecting two gated D latches in series as shown in figure 5.11, a
master-slave D flip flop can be constructed. In this master-slave D flip flop
one of the two gated is connected to active low enable. As the second flip
flop responds for the changes from first flip flop (master) this circuit is called
master slave. The circuit is said to be pulse triggered if the data is accepted
at the positive edge of the clock and that value is reflected at the output at
the negative edge of the clock.

Logic Design Unit 5
Figure 5.11: Master-slave (pulse-triggered) D flip-flop
Usually a master slave flip flop responds during the negative edge of the
enable input. When the clock input low for a positive edge triggered master
slave D flip flop and enable to the master is high. During the transition of
clock from low to high, the input value will be latched. When the clock is
changed from 0 to 1, the enable to the master will go low and its locks the
value which is at master’s input. At the same time, the enable to the slave
will be changed from low to high and the signal which is captured by the
master is latched by the slave. When the clock signal is changed from high
to low, the output of the slave is locked and holds the value which is seen at
the last positive edge while the master accepts the new value. The figure
5.12 shows the circuit for positive edge triggered master slave D flip flop.
Figure 5.12: Circuit for positive edge triggered master slave D flip flop
A negative edge triggered flip flop can be determined by removing the left
most inverter in the above circuit. This has a truth table as shown in
table 5.6.

Logic Design Unit 5
Table 5.6: Truth table for negative edge triggered D flip- flop
D Q > Qnext
0 X Falling 0
1 X Falling 1
Like SR flip flop, most of the D flip flops in digital systems has set and reset
capability. In D flip flop the illegal condition i.e., S=R=1 in SR flip flop is
resolved (refer to the truth table shown in table 5.7).
Table 5.7: Truth table for D flip-flop with S=R=1 resolved

Inputs Outputs
S R D > Q Q'
0 1 X X 0 1
1 0 X X 1 0
1 1 X X 1 1
By setting S = R = 0, the flip-flop can be used as described above.

Edge-triggered D flip-flop
A more efficient way to make a D flip-flop is not as easy to understand, but it
works the same way. While the master-slave D flip flop is also triggered on
the edge of a clock, its components are each triggered by clock levels. The
"edge-triggered D flip-flop" does not have the master slave properties.
5.4.4 J-K Master Slave Flip Flop
The logic symbol for the master-slave flip-flop shown in figure 5.13 only
indicates the initial inputs to the master and the outputs from the slave.
Master-slave flip flop is designed using two separate flip flops. One acts as
the master and the other as a slave as shown in figure 5.13.

Logic Design Unit 5
Figure 5.13: Symbol for the master-slave JK flip-flop
Let us now examine the operation of the master-slave J-K flip-flop:

When clock signal i.e. Clk=1, the master J-K flip flop gets disabled. The Clk
input of the master input will be the opposite of the slave input. So the
master flip flop output will be recognized by the slave flip flop only when the
Clk value becomes 0. So when the clock pulse makes a transition from 1 to
0, the locked outputs of the master flip flop are fed through to the inputs of
the slave flip-flop making this flip flop edge or pulse-triggered. To
understand this operation, take a look at the timing diagram shown in figure
5.14.
Figure 5.14: Timing Diagram for the master-slave JK flip-flop
From the timing diagram, it is clear the circuit accepts the value in the input
when the clock is HIGH, and passes the data to the output on the falling-
edge of the clock signal (i.e when clock pulse is making transition from 1 to
0). Thus Master-Slave J-K flip flop is a Synchronous device since it only
passes data with the timing of the clock signal.

Logic Design Unit 5
Application of flip-flops
An important application of flip-flops is in the design of digital counters.
These devices generate binary numbers in a specified count sequence
when triggered by an incoming clock waveform. On each trigger, the
counter advances to the next number in the sequence. After reaching the
final state in the sequence, the counter then recycles. Counters may be
used to count up or down, to cycle through memory addresses in
microprocessors applications, to generate waveforms of particular patterns
and frequencies, and to activate other logic circuits in a complex process.
5.5 Real World Applications of Sequential Circuits

Design of Sequential Circuits
The design of a synchronous sequential circuit starts from a set of
specifications and culminates in a logic diagram or a list of Boolean
functions from which a logic diagram can be obtained. In contrast to a
combinational logic, which is fully specified by a truth table, a sequential
circuit requires a state table for its specification. The first step in the design
of sequential circuits is to obtain a state table or an equivalence
representation, such as a state diagram. A synchronous sequential circuit is
made up of flip-flops and combinational gates. The design of the circuit
consists of choosing the flip-flops and then finding the combinational
structure which, together with the flip-flops, produces a circuit that fulfills the
required specifications. The number of flip-flops is determined from the
number of states needed in the circuit. The recommended steps for the
design of sequential circuits are set out as shown in the figure 5.15.

Logic Design Unit 5
Figure 5.15: Steps for the design of sequential circuits
Example 1: We wish to design a synchronous sequential circuit whose

state diagram is shown in figure 5.16. The type of flip-flop to be use is J-K.

Logic Design Unit 5
Figure 5.16: State diagram
From the state diagram, we can generate the state table shown in table 5.8
Note that there is no output section for this circuit. Two flip-flops are needed
to represent the four states and are designated Q0Q1. The input variable is
labeled x.
Table 5.8: State table
Present State Next State
Q0 Q1 x=0 x=1
00 00 01
01 10 01
10 10 11
11 11 00
We shall now derive the excitation table and the combinational structure.
The table is now arranged in a different form as shown in table 5.9, where
the present state and input variables are arranged in the form of a truth
table.
Table 5.9: Excitation table of the circuit
Output Transitions Flip-flop inputs

Q →Q (next) JK
0 → 0 0 X
0 → 1 1 X
1 → 0 X 1
1 → 1 X 0
The Table 5.10 shows the Excitation table with present state and next state.

Logic Design Unit 5
Table 5.10: Excitation table with present state and next state
Present State Next State Input Flip-flop Inputs
Q0 Q1 Q0 Q1 x J0K0 J1K1
00 00 0 0X 0X
00 01 1 0X 1X
01 10 0 1X X1
01 01 1 0X X0
10 10 0 X0 0X
10 11 1 X0 1X
11 11 0 X0 X0
11 00 1 X1 X1
In the first row of table 5.10 we have a transition for flip-flop Q0 from 0 in the
present state to 0 in the next state. In table 5.10 we find that a transition of
states from 0 to 0 requires that input J = 0 and input K = X. So 0 and X are
copied in the first row under J0 and K0 respectively. Since the first row also
shows a transition for the flip-flop Q1 from 0 in the present state to 0 in the
next state, 0 and X are copied in the first row under J1 and K1. This process
is continued for each row of the table and for each flip-flop, with the input
conditions as specified in table 5.10.
The simplified Boolean functions for the combinational circuit can now be
derived. The input variables are Q0, Q1, and x; the outputs are the variables
J0, K0, J1 and K1.The information from the truth table is plotted on the
Karnaugh maps shown in figure 5.17.
Figure 5.17: Karnaugh Maps
The flip-flop input functions are derived:

J0 = Q1*x' K0 = Q1*x
J1 = x K1 = Q0'*x' + Q0*x = Q0x
Logic Design Unit 5
Note: the symbol  is exclusive-NOR.

The logic diagram is drawn in figure 5.18.
Figure 5.18: Logic diagram of the sequential circuit
Example 2: Design a sequential circuit whose state tables are specified in

table 5.11, using D flip-flops.
Table 5.11: State table of a sequential circuit
Present
Next State Output
State
Q0 Q1 X=0 x=1 x=0 x=1
00 00 01 0 0
01 00 10 0 0
10 11 10 0 0
11 00 01 0 1
Table 5.12: Excitation table for a D flip-flop

Output
Flip-flop inputs
Transitions
D
Q→ Q(next)
0 → 0 0
0 → 1 1
1 → 0 0
1 → 1 1

Logic Design Unit 5
The Table 5.12 shows the excitation table for D flip-flop. Next step is to
derive the excitation table for the design circuit, which is shown in table
5.13. The output of the circuit is labeled Z.
Table 5.13: Excitation table
Present State Next State Input Flip-flop Input Output
Q0 Q1 Q0 Q1 x D0 D1 Z
00 00 0 0 0 0
00 01 1 0 1 0
01 00 0 0 0 0
01 10 1 1 0 0
10 11 0 1 1 0
10 10 1 1 0 0
11 00 0 0 0 0
11 01 1 0 1 1
Now plot the flip-flop inputs and output functions on the Karnaugh map to
derive the Boolean expressions, which is shown in figure 5.19.
Figure 5.19: Karnaugh maps
The simplified Boolean expressions are:

D0 = Q0*Q1' + Q0'*Q1*x
D1 = Q0'*Q1'*x + Q0*Q1*x + Q0*Q1'*x'
Z = Q0*Q1*x

Logic Design Unit 5
Finally, draw the logic diagram as shown in the figure 5.20
Figure 5.20: Logic diagram of the sequential circuit

7. As the flip flop stores the given values, in a memory device it can be
used as _____________device.
8. In case of flip flop using NAND gates, both the output Q and Qbar will
be 1 if S and R inputs are applied with logic 0 and in normal operation
this condition must be avoided. (State True or False?)
9. The design of the circuit consists of choosing the flip-flops and then
finding the sequential structure which produces a circuit that fulfills the
required specifications. (True or False?)
10. The master J-K flip flop gets enabled when clock signal i.e._______.
11. A synchronous sequential circuit is made up of ___________and
combinational gates
12. The first step in the design of sequential circuits is to obtain a
________ or an equivalence representation, such as a state diagram.
5.6 Summary
 Flip flop is a device which changes its state at the positive edge or
negative edge (also known as leading edge and trailing edge) of the
clock signal. A synchronous latch is device which monitors the input
signal and changes its state whenever the control signal is high.
 As the flip flop stores the given values, in a memory device it can be
used as basic storage device. Only one bit information can be stored in
a Flip Flop.

Logic Design Unit 5
 Two NOR gates or two NAND gates can be used to construct a basic
flip flop.
 Flip-flops types are: SR ("set-reset"), D ("data" or "delay"), T ("toggle"),
and JK flip flop.
 The output of the flip flop takes the value of input after one clock cycle in
case of D flip flop.
 All the shift registers which are important part of digital system are
constructed using flip flops.
 Master-slave flip flop is designed using two separate flip flops. One acts
as the master and another acts as slave.

1. Define Sequential Circuits.
2. Draw and explain the working of JK, S-R, D Flip-Flops.
3. Write a short note on J-K Master Slave Flip-Flop.
4. What are the steps recommended for the design of sequential circuits?
5.8 Answers
1. True
2. Flip flop
3. High
4. Memory
5. Clock
6. True
7. Basic storage
8. True
9. True
10. Clk=1
11. Flip-flops
12. State table
Terminal Questions

Logic Design Unit 6
Unit 6 Shift Registers and Applications

Structure:
6.1 Introduction
Objectives
6.2 Definition of Shift Registers
6.3 Types of Shift Registers
Serial-In Serial-Out (SISO)
Serial-In Parallel-Out (SIPO)
Parallel-In Serial-Out (PISO)
Parallel-In Parallel-Out (PIPO)
6.4 Case Study IC’s
6.5 Summary
6.7 Answers
6.1 Introduction
In the previous unit, we studied about the definition of sequential circuit,
latches and flip flops and various types of flip-flops. We also studied about
real world applications of sequential circuits. Historically a shift register was
built as early as in 1940’s. It was a code-breaking machine, having
five-stages and was built using vacuum tubes. Shift registers are typically
used as converters between serial and parallel devices. Most of the data
processing logic works on set of bits together. An example can be the CPU
of a computer that works on data bits stored in the registers. Hence
mapping serial stream of data into parallel data bytes is really useful. At the
same time it is easier to implement serial data transmission logic. We can
think of shift registers as delay elements. We can implement stack of a CPU
in hardware using bi-directional shift registers. Unlike mono-shots
(mono-stable multi-vibrators), the accuracy of timing offered by shift
registers is independent of its component values. Hence pulse extenders
can be realized using them. However the timing properties of shift register
are defined and limited by the clock signal supplied to it.
Architectures of old computers involved shift registers in the CPU for holding
and moving the data into the ALU (Arithmetic Logic Unit). The two operands
of addition were first shifted into the shift registers and then shifted out into

Logic Design Unit 6
ALU for performing addition. The answer was again moved back to one of
the shift register, generally known as the Accumulator.
Most of the CPU’s have machine level instructions that can move the bits
stored in a shift register to the left or right in a group. These instructions are
‘shift left’ and ‘shift right’. Higher level languages also provide constructs
that make use of these instructions. As we know from binary arithmetic, left
shifting of data multiplies it by two and right shift of it divides the same by
two.
Historical computers used very large sized shift registers (serial-in – serial-
out type), having sizes of few thousands of bits. These worked like delay
line memory elements. In this unit we study about the definition of shift
registers, its types and their operation. We also study some shift
register ICs.
Objectives:
 define shift registers.
 list and explain different types of Shift Registers
 discuss on IC 74LS395
6.2 Definition of Shift Registers

Shift Register is a set of binary storage elements, typically flip-flops
combined and linked together to facilitate the movement of the data bits
stored, from one to another and in and out of it, whenever desired by
activating control signals.
Inputs to the shift registers can be serial or parallel. Similarly outputs of the
shift registers can be serial or parallel. Thus we can have four types of shift
registers based on the serial or parallel nature of inputs and outputs. They
are listed below.
 Serial Input Serial Output (SISO)
 Serial Input Parallel Output (SIPO)
 Parallel Input Serial Output (PISO)
 Parallel Input Parallel Output (PIPO)
There are bi-directional shift registers that allow shifting of data bits in both
directions, i.e. from left to right and vice versa. If we connect inputs and

Logic Design Unit 6
outputs of a serial-in serial-out shift register, we get so called circular shift

register.
6.3 Types of Shift Registers

Now let us study the different types of shift registers.
6.3.1 Serial-In Serial-Out (SISO)
Operationally this is one of the simple types. As the name suggests, data
bits are stored in serially and in the same way these get out of the shift
register serially. This concept is shown in figure 6.1.
Figure 6.1: Serial-In Serial-Out (SISO)
The string of bits that we want to shift in are given to the input pin named
‘Data In’. Each bit presented at ‘Data In’ is shifted to its right one flip-flop at
a time, every time ‘Data Shift’ signal is enabled. First time, the bit on ‘Data
In’ line is moved into the first ‘flip-flop’s output. The data bit on the rightmost
flip-flop gets shifted out through the output line of the shift register ‘Data
Out’. The bit that goes out through ‘Data Out’ is lost. The figure 6.2 shows
the 4-bit Serial-In Serial-Out (SISO) Shift Register.
Figure 6.2: 4-bit Serial-In Serial-Out (SISO) Shift Register

Logic Design Unit 6
Let us see more clearly how this works. Each row of four bits in the table 6.1
can be imagined to be the outputs of the four flip-flops that make up our
SISO (serial-in serial-out) shift register.
Table 6.1: Truth table of SISO shift register
Clock Pulse Data In Q1 Q2 Q3 Q4

0 0 0 0 0 0
1 1 (LSB) 1 0 0 0
2 0 0 1 0 0
3 1 1 0 1 0
4 1 (MSB) 1 1 0 1
5 0 0 1 1 0
6 0 0 0 1 1
7 0 0 0 0 1
8 0 0 0 0 0
Let the register is reset so that all the flip-flop outputs to 0. We now feed a
stream of bits (LSB) 1, 0, 1 ,1 (MSB) at ‘Data In’ line and at the same time
pulse the ‘Data Shift’ signal for every data bit. We see that data is right
shifted for every pulse and after four pulses the register is filled with 1101
from left to right. If we clock further, the data can be read out from ‘Data Out’
with simultaneous right shift of data bits as shown in the table 6.1. From the
clock pulse 5th onwards, we assumed that the data In takes the 0 as its input
data.
If we collect all the data bits at ‘Data Out’ line after the register is filled with
the serial data input, we get 10110000 as the bit stream. So what we get at
the output is what we had put in through the input. However the output is
delayed by four cycles of clocking or pulsing the ‘Data Shift’ line. The data
movement though SISO shift register resembles a queue implemented in
hardware. To start over again, the register flip-flops can be set to 0 by
asserting the ‘Reset’ input. Since the data bits that are shifted out of ‘Data
Out’ are lost, we call this destructive readout.
Non-destructive readout
It is possible to ensure reading the data out from a SISO shift register is
non-destructive. All we have to do is to connect the ‘Data Out’ line to
Logic Design Unit 6
‘Data In’ line under the control of an additional input line. Let us call this
‘Read/Write (R/W)’ line. When this input is set to 1(or Write), it behaves like
a normal SISO register with destructive readout. When R/W is set to
0 (Read), ‘Data Out’ gets logically connected to ‘Data In’ and the data bits
that get shifted out upon pulsing the ‘Data Shift’ line become the inputs and
get shifted in again. Thus the data is retained in the shift register.
6.3.2 Serial-In Parallel-Out (SIPO)
This is almost similar to SISO shift register discussed in the section 6.3.1
except that the data are readout in parallel at the same time. this means,
We can input the data bits into this shift register serially via ‘Data In’ input
line and data can be read out in parallel from data out lines. The concept of
SIPO is shown in figure 6.3.
Figure 6.3: Serial-In Parallel-Out (SIPO)
Note that we may readout the data in two ways.

In the first method, data is readout in parallel from the flip-flop outputs
Q1 through Q4. Hence the name ‘Parallel Out’. Alternatively we can do
destructive readout serially via ‘Data Out’ or Q4 line and replace it with new
data if presented at ‘Data In’. The figure 6.4 shows the 4-bit Serial-In
Parallel-Out (SIPO) Shift Register and table 6.2 shows its truth table.
Figure 6.4: 4-bit Serial-In Parallel-Out (SIPO) Shift Register

Logic Design Unit 6
Table 6.2: Truth table of SIPO shift register
Clock Pulse Data In Q1 Q2 Q3 Q4

0 0 0 0 0 0
1 1 (LSB) 1 0 0 0
2 0 0 1 0 0
3 1 1 0 1 0
1
4 1 1 0 1
(MSB)
6.3.3 Parallel-In Serial-Out (PISO)

In Parallel-In, Serial-Out (PISO) shift register, the data input is given in
parallel to the input line of each of the flip-flops and outputs are readout
serially from single output line (Data Out) as shown in figure 6.5.
Figure 6.5: Parallel-In Serial-Out (PISO)
The figure 6.6 shows the 4-bit Parallel-In Serial-Out (PISO) Shift Register
and table 6.3 shows its truth table. In this type, the data input can be given
in parallel to the input line of each of the flip-flops, D1 through D4. To switch
between data-input and data-shift mode, we use a signal ‘Write/Shift’ (W/S).

Logic Design Unit 6
Figure 6.6: 4-Bit PISO Shift Register

When we set W/S input to 0, the data bits on D1-D4 lines get loaded to the
outputs of the respective flip-flops, Q1-Q4. For shifting the data out, we set
W/S to 1. Now the shift register works much like a SISO register and D1
acts like ‘Data In’ line. For the first few cycles, the number of which is equal
to number of flip-flops in the register, the data bits readout of Q4 represent
the parallel data that was read in through D1-D4 inputs.
Table 6.3: Truth table of PISO shift register
Parallel Data
Clock Pulse Q1 Q2 Q3 Q4
D1D2D3D4
0 0 0 0 0 0 0 0 0
1 1 0 1 1 1 0 1 1
2 XX XX x 1 0 1
3 XX XX x x 1 0
4 XX XX x x x 1
X= 0 or 1
6.3.4 Parallel-In Parallel-Out (PIPO)
The PIPO register is mainly used to shift a given set of bits and present it to
the next stage as illustrated below. Input for shifting can be loaded into the
register in parallel and the shifted output can be read out of the register in

Logic Design Unit 6
parallel as well. Hence the name PIPO shift register. The concept of PIPO is
Figure 6.7: PIPO Shift Register
In the above schematic diagram of PIPO shift register, we load the data at
D1-D3 inputs. The ‘mode’ input is used to swap between ‘parallel load’ and
‘shift’ operation. Additional control pins may be provided for changing the
direction of the data shift. Once the ‘mode’ input is set to ‘shift’ the loaded
data can be shifted upon supplying the clock signal. The shifted data can be
obtained at the outputs Q1-Q3. The ‘data in’ and ‘data out’ lines can be used
to enable serial input and serial output operation. They can also be used for
cascading additional stages. Shift register shown in figure 6.7 can also be
used to input/output data serially. So we can call this a universal shift
register.
The figure 6.8 shows the 4-bit Parallel-In Parallel-Out (PIPO) Shift Register
and table 6.4 shows its truth table.
Figure 6.8: 4-bit Parallel-In Parallel-Out (PIPO) Shift Register

Logic Design Unit 6
Table 6.4: Truth table of PIPO shift register
Parallel Input Data

Clock Pulse Q1 Q2 Q3 Q4
D1D2D3D4
1 1 0 1 1 1 0 1 1
6.4 Case Study IC’s

The following schematic diagram shown in figure 6.9 depicts the hardware
details of a PIPO shift register. The register shifts the data towards right.
The buffers shown are necessary for real physical IC that is used with other
components.
Figure 6.9: 74LS395 Parallel-In Parallel-Out Shift Register with Tri-state output
The 74LS395 IC resembles very much like our theoretical PIPO shift
register that shifts data right. The schematic diagram shown above is
simplified version of that found in the data sheet. You may refer to the
detailed information.
LD/SH' controls the AND-OR multiplexer at the data input to the FF's. If
LD/SH'=1, the upper four AND gates are enabled allowing application of
parallel inputs DA DB DC DD to the four FF data inputs. Note the inverter
bubble at the clock input of the four FFs. This indicates that the 74LS395
clocks data on the negative going clock, which is the high to low transition.
The four bits of data will be clocked in parallel from DA DB DC DD to QA QB
QC QD at the next negative going clock. In this "real part", OC' must be low if
the data needs to be available at the actual output pins, as opposed to only
on the internal FFs.

Logic Design Unit 6
The previously loaded data may be shifted right by one bit position if
LD/SH'=0 for the succeeding negative going clock edges. Four clocks would
shift the data entirely out of our 4-bit shift register. The data would be lost
unless our device was cascaded from QD' to SER of another device. The
figure 6.10 shows the loading and shifting of parallel data.
Figure 6.10: Parallel-in/ Parallel-out shift register
Above, a data pattern is presented to inputs DA DB DC DD. The pattern is

loaded to QA QB QC QD. Then it is shifted one bit to the right. The incoming
data is indicated by X, meaning that we do no know what it is. If the input
(SER) were grounded, for example, we would know what data (0) was
shifted in. Also shown, is right shifting by two positions, requiring two clocks.
The figure 6.11 serves as a reference for the hardware involved in right
shifting of data.
Figure 6.11: Right shifting

Logic Design Unit 6
Figure 6.12: Right shifting of data.
Right shifting of data is shown in figure 6.12 and is provided for reference to
the previous right shifter shown in figure 6.11.
The figure 6.13 serves as a reference for the hardware involved in left
shifting of data.
Figure 6.13: Left shifting of data.
If we need to shift left, then the FFs need to be rewired. Compare to the
previous right shifter, SI and SO have been reversed. SI shifts to QC. QC
shifts to QB. QB shifts to QA. QA leaves on the SO connection, where it
could cascade to another shifter SI. This left shift is backwards from the
right shift sequence as shown in figure 6.14.
Figure 6.14: Left shift operation

Logic Design Unit 6
Above we shift the same data pattern left by one bit. The issue with the
above arrangement is that, it is not much in demand in the market. Hence it
is hardly manufactured. We can reverse the shifting direction by
appropriately wiring a physical shift register IC externally. Thus the direction
of shift loses significance in a way. However better arrangement would be to
bring the desired direction of shift under the control of an input signal as
Figure 6.15: Left shift /right register, right action
What we have above is a hypothetical shift register capable of shifting either

direction under the control of L'/R. It is setup with L'/R=1 to shift the normal
direction, right. L'/R=1 enables the multiplexer AND gates labeled R. This
allows data to follow the path illustrated by the arrows, when a clock is
applied.
Data shifts in at SR, to QA, to QB, to QC, where it leaves at SR cascade. This
pin could drive SR of another device to the right.
What if we change L'/R to L'/R=0?
With L'/R=0, the multiplexer AND gates labeled L are enabled, yielding a
path, shown by the arrows in figure 6.16.

Logic Design Unit 6
Figure 6.16: Left shift /right register, left action
Data shifts in at SL, to QC, to QB, to QA, where it leaves at SL cascade. This
pin could drive SL of another device to the left.
The prime virtue of the above two figures 6.15 and 6.16 illustrating the "shift
left/ right register" is simplicity. The operation of the left right control L'/R=0
is easy to follow. A commercial part needs the parallel data loading implied
by the section title. This appears in the figure 6.17 shown below.
Figure 6.17: Shift left/right/ the parallel data loading

Logic Design Unit 6
Now that we can shift both left and right via L'/R, let us add SH/LD', shift/
load, and the AND gates labeled "load" to provide for parallel loading of data
from inputs DA DB DC. When SH/LD'=0, AND gates R and L are disabled,
AND gates "load" is enabled to pass data DA DB DC to the FF data inputs.
The next clock CLK will clock the data to QA QB QC. As long as the same
data is present it will be re-loaded on succeeding clocks. However, data
present for only one clock will be lost from the outputs, when it is no longer
present on the data inputs. One solution is to load the data on one clock,
and then proceed to shift on the next four clocks. This problem is remedied
in the 74ALS299 by the addition of another AND gate to the multiplexer.
If SH/LD' is changed to SH/LD'=1, the AND gates labeled "load" are
disabled, allowing the left/ right control L'/R to set the direction of shift on the
L or R AND gates. Shifting is as in the previous figures.
The only thing needed to produce a viable integrated device is to add the
fourth AND gate to the multiplexer as alluded for the 74ALS299.
6.5 Summary
 Shift Register is a set of binary storage elements, typically flip-flops
combined and linked together to facilitate the movement of the data bits
stored, from one to another and in and out of it, whenever desired by
activating control signals.
 Four types of shift registers are: Serial Input Serial Output (SISO), Serial
Input Parallel Output (SIPO), Parallel Input Serial Output (PISO) and
Parallel Input Parallel Output (PIPO).
 In SIPO, we can input the data bits into this shift register serially via
‘Data In’ input line and data can be read out in parallel from data out
lines.
 In Parallel-In, Serial-Out (PISO) shift register, the data input is given in
serially from single output line.
 In Parallel-In, Parallel-Out (PIPO) shift register, the data input is given in
in parallel from all the output lines.

Logic Design Unit 6

1. The storage elements in shift registers are ______________.
2. There are ______________ types of shift registers.
3. When ‘Data Out’ is fed back to ‘Data In’ of a SISO shift register, It
becomes _________________shift register.
4. In __________ shift register, we can input the data bits into this shift
register serially via ‘Data In’ input line and data can be read out in
parallel from data out lines.
5. In______________shift register, input for shifting can be loaded into the
register in parallel and the shifted output can be read out of the register
in parallel as well.
6. ________________ IC is Parallel-In Parallel-Out Shift Register with Tri-
state output.

1. What is a shift register? Mention the types of shift register.
2. Draw and explain 4-bit serial-in-parallel-out shift register.
3. Draw and explain the operation of parallel-in-parallel-out shift register.
4. Discuss on 74LS395 IC
6.7 Answers
Self-Assessment Questions
1. Flip-Flops
2. Four
3. Circular.
4. SIPO ( Serial-In Parallel-out)
5. PIPO ( Parallel-In Parallel-out)
6. 74LS395
Terminal Questions
1. Refer Section 6.3

Logic Design Unit 7
Unit 7 Basics of Counters & Design of Counters

Structure:
7.1 Introduction
Objectives
7.2 Typical Counters
Johnson Counter
Ring Counter
7.3 Design of Modulo-N counters
7.4 Problem on Counter Design
7.5 Summary
7.7 Answers
7.1 Introduction
In the previous unit we studied about shift registers and their types. We also
studied some ICs in relation to shift registers. In electronics, a counter is a
logic device which is capable of counting the number of times an event has
occurred. It can also display the count. The counter for its operation needs a
trigger or prompt which conveys that an event has occurred. This trigger is
usually supplied to a counter in the form of a signal called ‘clock’.
Depending on whether the count value increases/decreases, we have the
following basic types of counters.
 Up counters - Increase count value
 Down counters - Decrease count value
Counters are generally implemented using basic storage elements such as

flip-flops, latches or registers. There are many types of counters with
different designs. They are also used in different applications.
Objectives:
By the end of Unit 7, the learners should be able to:
 explain the function of counters
 differentiate asynchronous and synchronous counters
 explain Johnson and ring counter
 explain the design of Modulo-N counters
 solve problems on counter design

Logic Design Unit 7
7.2 Typical Counters

Counters are digital logic devices and as we know, widely used digital logic
is binary in nature. So binary counters count in terms of binary numbers.
They can even count BCD (Binary Coded Decimal) numbers. There are
many commercially available counter ICs that can be used in electronic
circuit/system design. For example, CMOS IC’s in the 4XXX series
implement different counters.
There are different types of counters which can count binary numbers.
Counters can be classified based on how the clock is applied, number of
flip-flops and sequential states. Some of the counter types are listed below.
 Asynchronous (ripple) counters
 Synchronous counters
 Up-Down counters
 Johnson counters
 Decade counters
In asynchronous or ripple counters, all the flip-flops are not clocked by the
same clock and all flip-flops do not change their state in exact synchronism
with the applied clock pulses. It is because, usually the clock pulse is
applied to the first flip-flop and the output of the first flip flop is connected as
a clock for the next flip-flop. Asynchronous counters are also called ripple
counters because the flip-flops change their state in a ripple fashion i.e.the
clock pulse fed into first flip-flop ripples through the other counters after
propagation delays, like a ripple on water, hence the name Ripple Counter.
In synchronous counters, all the flip-flops are clocked by the same clock and
all flip-flops change their state in exact synchronism with the applied clock
pulses. So a common clock is connected to all the clock inputs of all the flip
flops. The delay involved is equal to the propagation delay of one flip-flop
only, irrespective of the number of flip-flops used to construct the counter.
An up counter is one which counts in upward direction in ascending order.
On the other hand, a down counter counts in downward direction in
descending order.
A counter which counts in both up and down directions is called an
UP/DOWN counter.

Logic Design Unit 7
A Johnson counter is basically a circulating shift register in which the output

of the most significant stage is fed back to the input of the least significant
stage.
The simplest counter circuits can be built using T flip-flops because the
toggle feature is suited for the implementation of the counting operation.
Decade Counter is a type of counters which counts only from 0 through 9.
Hence the modulus of decade counter is 10. This decade counter requires
four flip-flops for its construction.
Modulus of a counter
Modulus of a counter is the number of different states that a counter can go
through before it comes back to initial state to repeat the count sequence.
An n-bit counter that counts through all its natural states and does not skip
any of the states has a modulus of 2n. For example, a 3 stage counter
consists of cascade of 3 flip flops and can count maximum of eight counts.
Hence the Modulus of this counter is 8. If a counter counts all the maximum
possible counts, then it is called natural count and in this case the modulus
of a counter is equal to natural count. Note that a counter with three flip
flops can count maximum of 9 counts from 0 through 8 and suppose if it is
designed to count only from 0 through 5, then modulus of the counter is 6.
So it is called Modulo-6 counter. In this case the modulus of a counter is not
equal to natural count.
Asynchronous Counters:
A counter may count up or count down or count up and down depending on
the input control. The count sequence usually repeats itself. For example,
for a 4- bit counter when counting up, the count sequence goes from 0000,
0001, 0010, ... 1110 , 1111 , 0000, 0001, ... etc. When counting down the
count sequence goes in the opposite manner: 1111, 1110, ... 0010, 0001,
0000, 1111, 1110, ... etc.
3- Bit asynchronous up counter
The figure 7.1 shows a 3 bit asynchronous up counter along with timing
diagram.

Logic Design Unit 7
Figure 7.1: 3 –Bit Asynchronous Up Counter

(a) Circuit diagram
(b) Timing diagram
The table 7.1 shows the truth table of 3-Bit asynchronous Up counters
Table 7.1: Truth table of 3-Bit Asynchronous Up Counter

Logic Design Unit 7
Figure 7.1(a) shows a 3-bit counter implemented using T-flip flops. This
counter can count from 0 to 7 in upward direction (i.e. Count Increases in
ascending order). The T input of each flip-flop is 1(High), so that state of
each flip-flop will be toggled at each positive edge of its clock. The clock
input of the first flip-flop is connected to the Clock line and other two flip-
flops recieve their clock inputs driven by the Q output of the preceding flip-
flop. Therefore, they also toggle their state whenever the preceding flip-flop
changes its state from Q = 1 to Q = 0, which results in a positive edge of the
Q signal.
Figure 7.1(b) shows a timing diagram for the counter. The value of Q0
toggles once after each positive edge of the Clock signal. The second flip-
flop is clocked by Q0, the value of Q1 changes after the negative edge of
the Q0 signal. Similarly, Q2 changes its state after the negative edge of the
Q1 signal. This is also evident from the truth table shown in table 7.1.
If we look at the values Q2Q1Q0 in truth table, counting is in ascending order
in the sequence 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, and so on. This is a modulo-8
counter. Since it counts in the upward direction, it is called an up-counter.
3-Bit asynchronous Down counter
The figure 7.2 shows a 3-bit asynchronous Down counter along with timing
diagram and truth table. The difference between figure 7.1(a) and figure
7.2(a) is that only the clock inputs of the second and third flip-flops are
driven by the Q outputs of the preceding flip-flops, instead of the Q outputs.
The timing diagram shown in 7.2(b) shows how the counter counts during
clock pulse. The truth table shown in table 7.2 clearly indicates the counter
counts in down ward direction and the sequence is 7, 6, 5, 4, 3, 2, 1, 0, 7,
and so on. Since the counter counts in the downward direction, it is called
down-counter.

Logic Design Unit 7
Figure 7.2: 3 –Bit asynchronous Up Counter

(a) Circuit diagram
(b) Timing diagram
Table 7.2: Truth Table of a 3-bit Asynchronous Down Counter

Logic Design Unit 7
Synchronous Counters:
The asynchronous counters above are simple but not very fast. If a counter
with a larger number of bits is constructed in this manner, then the delays
caused by the cascaded clocking scheme may become too long to meet the
desired performance requirements. We can build a faster counter by
clocking all flip-flops at the same time as presented below.
Synchronous Up-Counter with T Flip-Flops
An example of a 3-bit synchronous up-counter is shown in figure 7.3(a) and
the timing diagram is shown in figure 7.3(b).
(a)
(b)
Figure 7.3: 3 –Bit Synchronous Up Counter
(a) Logic circuit diagram
(b) Timing diagram

Logic Design Unit 7
The table 7.3 shows the truth table of a 3-Bit Synchronous Binary Counter.
Table: 7.3: Truth table of a 3-Bit Synchronous Binary Counter
4-bit synchronous up-counter

A 4-bit synchronous up-counter using T flip-flop is shown in figure 7.4.
Figure 7.4: 4-bit synchronous up-counter
The table 7.4 shows the contents of such a 4-bit up-counter for sixteen
consecutive clock cycles, assuming that the counter is initially 0.

Logic Design Unit 7
Table 7.4: Contents of a 4−bit up−counter for 16 consecutive clock cycles
Observing the pattern of bits in each row of the table, it is apparent that bit
Q0 changes on each clock cycle. Bit Q1 changes only when Q0 = 1. Bit Q2
changes only when both Q1 and Q0 are equal to 1. Bit Q3 changes only
when Q2 = Q1 = Q0 = 1. In general, for an n-bit up-counter, a give flip-flop
changes its state only when all the preceding flip-flops are in the state
Q = 1. Therefore, if we use T flip-flops to realize the 4-bit counter, then the T
inputs should be defined as
T0 = 1
T1 = Q0
T2 = Q0Q1
T3 = Q0Q1Q2
In figure 7.4, instead of using AND gates of increased size for each stage,
we use a factored arrangement. This arrangement does not slow down the
response of the counter, because all flip-flops change their states after a
propagation delay from the positive edge of the clock. Note that a change in
the value of Q0 may have to propagate through several AND gates to reach
the flip-flops in the higher stages of the counter, which requires a certain

Logic Design Unit 7
amount of time. This time must not exceed the clock period. Actually, it must
be less than the clock period minus the setup time of the flip-flops.
Figure 7.5 shows an example timing diagram for the 4-bit synchronous up-
counter. It shows that the circuit behaves as a modulo-16 up-counter.
Because all changes take place with the same delay after the active edge of
the Clock signal, the circuit is called a synchronous counter.
Figure 7.5: Timing diagram for a 4−bit synchronous up−counter
Now let see Johnson ring counter and ring counter.

7.2.1 Johnson Counter
A Johnson counter or Johnson Ring Counter or Twisted Ring Counter is
constructed using serial-in and serial-out (SISO) shift register. Here the
output of the last shift register is connected back to the input of the first after
passing it through an inverter or the inverted output Q of the last flip-flop is
connected back to the input of the first flip. Depending on the initial bit
pattern stored in the shift register, the shift register content changes for
every clock pulse and the bit pattern gets repeated after 2n clocks, where n
is the number of bits in the shift register. These counters are also called
“walking ring” counters and have applications like digital-to-analog
converters (DAC) etc. The figure 7.6 shows the 4 bit Johnson Ring Counter
using D flip-flop.

Logic Design Unit 7
Figure 7.6: 4-bit Johnson Ring Counter
Operation:
Initially all the flip-flops are cleared to zero (0) by making asynchronous
input Clear =1 so that the initial value of the outputs QA QB QC QD =0000.
Now make the clear input=0 so that it becomes inactive. Now the operation
of circuit depends only on the clock input. Also note that inverted output is
Q =1. Since the inverted output Q is connected to the input of the first flip
flop, the input D=1. Now when 1st clock pulse is applied, shifting operation
takes place and hence after the 1st clock pulse, QA QB QC QD =1000. The
complete bit patterns of this circuit for the subsequent clock pulses is 1000,
1100, 1110, 1111, 0111, 0011, 0001, 0000... . and is shown in the table
7.5.
Table 7.5: Truth Table for a 4-bit Johnson Ring Counter

Logic Design Unit 7
As the inverted output Q is connected to the input D, 8-bit pattern

continually repeats. For example, “1000″, “1100″, “1110″, “1111″, “0111″,
“0011″, “0001″, “0000″ and this is demonstrated in the table 7.5. The figure
7.7 shows the timing diagram (waveform) of a 4 bit Johnson counter.
Figure 7.7: Waveform of a 4 bit Johnson Counter
From the timing diagram shown in figure 7.7, it is clear that after the 8th
pulse t8 (i.e. after second 0th pulse in the truth table 7.5), the sequence
repeats again with the initial value QA QB QC QD =0000.,
Apart from counting or rotating data around a continuous loop, ring counters
can also be used to detect or recognise various patterns or number values
within a set of data. By connecting simple logic gates such as the AND or
the OR gates to the outputs of the flip-flops the circuit can be made to detect
a set of number or value.
Standard 2, 3 or 4-stage Johnson Ring Counters can also be used to divide
the frequency of the clock signal by varying their feedback connections and
divide-by-3 or divide-by-5 outputs are also available. For example, a 3-stage
Johnson Ring Counter could be used as a 3-phase, 120 degree phase shift
square wave generator by connecting to the data outputs at A, B and NOT-
B. The standard 5-stage Johnson counter such as the commonly available
CD4017 is generally used as a synchronous decade counter/divider circuit.
7.2.2 Ring Counter
A ring counter is a circulating shift register in which the output the last flip
flop is fed back to input of the first flip-flop thus forming a loop. All but one
flip-flop in a ring counter will be in the same state which could be either 0 or
1. Usually a bit “1” for a single flip-flop will be chosen, then the valid states
of the 4 bit ring counter are 1000, 0100, 0010,0001 etc.

Logic Design Unit 7
An example of a 4 bit ring counter constructed using S-R (set-reset) flip-

flops is shown in figure 7.8(a). Output of each stage is fed to the S (set)
input of next stage after AND’ing it with the ‘INPUT’ signal which can be
considered to be a clock. The S input of the next stage is also fed to the R
(reset) input of the current stage. The wave form of flip-flops FF1 through
FF4 in response to the clock signal on ‘INPUT’ is shown in figure 7.8(b) (i.e.
timing diagram).
Figure 7.8: Ring Counter (a) Logic diagram counter (b) Timing diagram
The table 7.6 shows the truth table of 4-Bit ring counter
Table 7.6: Truth table of 4-Bit ring counter

Logic Design Unit 7
Operation:
The operation of the circuit is straight forward. Assume that the initial output
of first flip-flop is 1 and rest of the flip-flops and ‘INPUT’ are at 0. This
means that A will be at 1 and B, C and D will be at 0. We can say that the
counter state now is 1000 i.e. The Q output of first flip-flop is also connected
to the B input of the first AND gate.
Let us apply a logic 1 to the ‘INPUT’ line which is connected to A inputs of
all the AND gates. We know that as outputs (Q) of FF2 to FF4 are low,
outputs of AND gates 2, 3, 4 will be 0. But the output of AND gate 1 is HIGH
(1) as both of its inputs are at 1. This resets Q of FF1 to 0 and sets that of
FF2 to 1. Hence B will be at logic 1 and A, C, D outputs will be at logic 0.
Please note that in this process, the original state of FF1 appears to be
shifted right by one position. The counter state now is 0100. Now if we apply
one more pulse to the ‘INPUT’ line again, the same process repeats and the
counter state would ne 0010.
Ring counter using D-flip flops:
A ring counter can also be constructed using d flip flops. The figure 7.9
shows a 4-Bit ring counter implemented using D-flip flops.
Figure 7.9: 4-Bit Ring counter using D-flip flops.

In the logic diagram shown in figure 7.9 above, the output of the last flip flop
is fed back to the input of a first flip flop thereby forming a loop or a ring.
Hence the name ring counters. A bit “1” will keep on circulating in a ring
fashion when clock pulses are applied. The valid states of the 4 bit ring
counter are 1000, 0100, 0010, 0001 etc. Note that during this operation, the
asynchronous input Clear =0 making it inactive so that the entire operation
will be based on the application of clock pulse.

Logic Design Unit 7
7.3 Design of Modulo-N counters

In a counter, the sequence of states may follow a binary count or any other
sequence of states. As we know counters count the number of occurrences
of an event and are useful for generating timing sequences to control
operations in a digital system. A counter that follows the binary sequence is
called a binary counter. A single flip-flop used gives two states output and is
referred to as mod-2 counter. With two flip-flops four output states can be
counted in ascending or in descending way and is referred to as mod-4 or
mod-22 counter. With ‘n’ flip-flops a mod-2n counting is possible either of
ascending or of descending type. So, an n-bit binary counter consists of n
flip-flops and can count in binary from 0 to 2n - 1.
To design an asynchronous counter to count till mod-N where N is a
modulus of a counter and is not a power of 2, the following procedure is
used.
 Find the number of flip-flops required n = log2 N. calculated value is not
an integer value if the N # 2n then select n by rounding to the next integer
value.
 First write the sequence of counting till N either in ascending or in
descending way.
 Tabulate the value to reset the flip-flops in a mod-N count.
 Find the flip-flop outputs which are to reset from the tabulated value.
 Tap the output from these flip-flops and feed it to a suitable gate whose
output is connected to the clear pin.
To design an synchronous counter, the following procedure can be used.
 Develop a state diagram for a given sequence.
 Develop a next-state table for a specific counter sequence.
 Create a FF transition table. (using JK Flip Flops)
 Use K-map to derive the logic equations. (Optional: Use Truth Table)
 Convert the logic equations to Boolean Algebra
 Implement a counter to produce a specified sequence of states.
Let's look at some examples of counter designs.
7.4 Problem on Counter Design

In this section we study some of the examples which show the design
asynchronous and synchronous conters.

Logic Design Unit 7
Problems on Asynchronous counter design

Problem 1: Design a Mod-6 counter using JK flip flop
Solution: The mod-6 counter counts from 0 through 5 (i.e. 000 to 101 in
binary). After this this counter reset back to initial count 000 and it starts
counting again. Only three flip flops are required, because 23 = 8 and this
number 8 is greater than mod-6.
Now we draw the table 7.7 to represent the desired output of the
combinational circuit to reset FFs as
Table 7.7: The truth table for Mod 6-counter.
From the truth table it observed that we want the counter to count only from
000 to 101 and the count 110 is not required to be count. So the counter
should reset to 000 immediately after the count 101. Observe that count 110
corresponds to Q2=1, Q1=1 and Q0=0. So we give the Q2 and Q1 as inputs
to two input NAND gate so that whenever the value Q2=1 , Q1=1 appears
the NAND gate outputs zero(o) and this out in turn activate the
asynchronous inputs Clear (i.e. CLR) so that the counter resets back to 000
and it starts counting again. This mod-6 counter is shown in the figure 7.10.
Note that J=K=1 so that each flip-flop acts as a Toggle flip-flop (i.e. T-flip
flop).

Logic Design Unit 7
Figure 7.10: Mod-6 counter
2nd method:
We firstly draw the state diagram as shown in the figure 7.11.
Figure 7.11: State diagram for Mod-6 counter
We draw the truth table to represent the desired output of the combinational
circuit to reset FFs as shown in the table 7.8.

Logic Design Unit 7
Table 7.8: The truth table for Mod 6-counter ( for 2nd method).
Note that the output is 1 for required combinations or count and is 0 for the
count 110 onwards.
Now we use k-map to get the simplified circuit as shown in the figure 7.12
Figure 7.12: K-map for mod-6 design using 2nd method
And the equation we get is output = Q1 + Q2 .

= Q1Q2
So, output= NAND(Q1 and Q2)
And the complete circuit is shown in figure 7.10.

Logic Design Unit 7
Problem 2: Design the ripple counter whose output sequence is

represented by the state diagram shown in figure 7.13.
Figure 7.13: State diagram for problem 2

Solution: As we can see that it is a down counter so we’ll be using Q bar of
all flip-flops as clock to next flip-flops (negative edged FFs). We draw the
table as shown in the table 7.9.
Table 7.9: Truth table for Problem 2
And using K-map (refer figure 7.14)
Figure 7.14: K-map for Problem 2

Logic Design Unit 7
And the equation we get is

Output = Q2 + Q1
The circuit is shown in figure 7.15.
Figure 7.15: Logic circuit diagram for problem 2
Problems on Synchronous counter design

Problem 3: Design a Mod-5 synchronous counter
Solution: To design a mod-5 counter, the number of flip-flops required are
found by the equation 2n ≥ N ≥ 2n-1 where n is the number of flip-flops
required and N is the number of states present in the counter. Now N=5,
then n=3. So three flip flops are required to design a Mod-5 counter.
The state diagram for mod-5 counter is shown n figure 7.16.
Figure 7.16: State diagram for Mod-5 counter

Logic Design Unit 7
The state table for the counter is given in the table 7.10 and table 7.11 gives
its excitation table.
Table 7.10: State table for the counter
Table 7.11: Excitation table for Mod-5 counter
The figure 7.17 shows the Karnaugh Map for Mod-5 Counter.

Logic Design Unit 7
Figure 7.17: Karnaugh Map for Mod-5 counter
The figure 7.18 shows the logic circuit diagram for Mod-5 counter.
Figure 7.18: Logic diagram of a Mod-5 counter

Logic Design Unit 7
Problem 4: Design a counter for the sequence of states shown in figure

7.19.
Figure 7.19: State diagram of a 3-bit binary counter.
Solution: The circuit has no inputs other than the clock pulse and no
outputs other than its internal state (outputs are taken off each flip-flop in the
counter). The next state of the counter depends entirely on its present state,
and the state transition occurs every time the clock pulse occurs.
Once the sequential circuit is defined by the state diagram, the next step is
to obtain the next-state table, which is derived from the state diagram in
figure 7.19 and is shown in table 7.12.
Table 7.12: State table
Since there are eight states, the number of flip-flops required would be
three. Now we want to implement the counter design using JK flip-flops.

Logic Design Unit 7
Next step is to develop an excitation table from the state table, which is
shown in table 7.13.
Table 7.13: Excitation table
Now transfer the JK states of the flip-flop inputs from the excitation table to
Karnaugh maps to derive a simplified Boolean expression for each flip-flop
input. This is shown in figure 7.20.
Figure 7.20: Karnaugh maps

Logic Design Unit 7
The 1s in the Karnaugh maps of figure 7.20 are grouped with "don't cares"
and the following expressions for the J and K inputs of each flip-flop are
obtained:
J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1 * Q0
The final step is to implement the combinational logic from the equations
and connect the flip-flops to form the sequential circuit. The complete logic
of a 3-bit binary counter is shown in figure 7.21.
Figure 7.21: Logic of a 3-bit binary counter
Problem 5: Design a counter using T flip-flop as specified by the state

diagram shown in figure in 7.22.
Figure 7.22: State diagram of a 3-bit binary counter.

Logic Design Unit 7
Now derive the excitation table from the state table, which is shown in
table 7.14.
Table 7.14: Excitation table for problem 5
Next step is to transfer the flip-flop input functions to Karnaugh maps to

derive simplified Boolean expressions, which is shown in figure 7.23.
Figure 7.23: Karnaugh maps for problem 5
The following expressions are obtained:

T0 = 1; T1 = Q0; T2 = Q1 * Q0
Finally, draw the logic diagram of the circuit from the expressions obtained.
The complete logic diagram of the counter is shown in figure 7.24.

Logic Design Unit 7
Figure 7.24: Karnaugh maps for problem 5
7.5 Summary
 In asynchronous or ripple counters, all the flip-flops are not clocked by
the same clock and all flip-flops do not change their state in exact
synchronism with the applied clock pulses.
 Modulus of a counter is the number of different states that a counter can
go through before it comes back to initial state to repeat the count
sequence.
 With ‘n’ flip-flops a mod-2n counting is possible either of ascending or of
descending type.
 The Johnson counter has an even-numbered cycle length of 2N where
N is the number of stages in the register.
 The ring counter continuously circulates a stream of bits, all of which
have same state except one bit. The differing bit may be 1 or 0. Hence
possible 4 bit ring counter sequences are 0001, 0010, 0100, 1000, and
the sequence is repeated.
1. Counters are designed using basic storage elements such as
__________________.
2. The counting range of a BCD counter is from __________ to _______.
3. The valid states of 3 bit ring counter with differing bit having a value of
logic 1 are _____ , ________ and ___________.
4. The length of a cycle of an n bit Johnson counter is _____________.

Logic Design Unit 7
5. A counter that follows the binary sequence is called a _____________

counter.
6. The ________________ counter counts from 0 through 5.

1. Explain the working of 4 bit Johnson counter with the help of neat
diagram.
2. Explain the working of 4-bit ring counter. Draw the timing diagram.
3. Write a short note on design of modulo-N counters.
4. Design a Mod-5 synchronous counter
7.7 Answers
1. Flip-flops
2. 0 to 9
3. 001, 010 and 100
4. 2n
5. Binary
6. Mod-6
Terminal Questions

Logic Design Unit 8
Unit 8 Design of Real World Logic Circuits

Structure:
8.1 Introduction
Objectives
8.2 Traffic Signal Systems
8.3 Two Way Switches
8.4 Electronic Tennis Scoring System
8.5 Temperature & Weather Forecast Systems
8.6 Summary
8.8 Answers
8.1 Introduction
In the previous unit we studied about different types of counters and design
of counters. With the advent of large and very-large-scale integration,
systems of reasonable complexity are realized on a single chip. Reductions
in the number of elements required to realize each function makes it
possible to use fewer chips or to do more on a given chip. In high-
performance systems, eliminating redundant gates not only frees up chip
area, but also reduces power dissipation, often the limiting factor. There are
of course factors that were not present in the days of discrete logic
elements, such as the value of regularity in the arrangement of elements on
a chip. But the need of powerful methods for generating efficient logic
circuits has indeed returned. A major consequence of the larger scale of
integration is the enormous size and complexity of our systems, and the
increased importance of testing. In this unit you will study some real world
logic circuits and their design.
Objectives:
By the end of Unit 8 the learners will be able to
 explain traffic signal systems
 explain the functions of switches
 electronic tennis scoring system
 discuss on temperature & weather forecast systems

Logic Design Unit 8
8.2 Traffic Signal Systems

This is an automatic traffic light controller and can be implemented by
programming any gate array based logic (GAL) device such as FPGA. The
important features of this design are as follows.
1. The density of traffic is assumed to be same on all the roads.
2. The free left turn is regulated to enable safe crossing for the pedestrians
during peak hours.
3. The implementation can be done using digital ICs.
4. The design is generic and can be customized to suit different type of
road junctions with minor changes.
5. Manual operation and control is permitted if required.
The basic light signals red, green and yellow are given uniform importance
in terms of time. Let us keep the duration for which these signals remain ‘on’
to be 8 seconds and its multiples. The figure 8.1 shown indicates the
movement of traffic in all permitted directions in a cycle that covers all the
four roads. We have 8 such signal combinations, each with 8 seconds
duration. The traffic which takes left or right turns and all the pedestrian
crossings are controlled by only two signals – red and green lights.
The table 8.1 displays status of all the signal lights for all the traffic
conditions. Every row in the table indicates the status of each light for 8
seconds. We can see that for the traffic that moves straight, the ratio of red,
yellow and green signal lights is 40:8:16. For the traffic that takes left or right
turns, the ratio of red and green lights is 56:8. Similarly for the pedestrian
crossing the ratio is 48:16.
In the table 8.1 each of the 8 rows is assigned a binary number that
uniquely identifies it. Since we have 8 distinct combinations of signal lights,
we need minimum of 3 bits to represent each state. Each of these bits is
named as variable X, Y and Z respectively in table 8.1 and 8.2. As indicated
in figure. 8.1, the two halves of each of the four roads are denoted by the
alphabets A through H. The alphabet pairs with a single dash line between
them represent valid directions of traffic movements. Also note that
St, Lt and Rt mean straight direction, left turn and right turn respectively.

Logic Design Unit 8
Figure 8.1: Flow of traffic in all possible directions
Table 8.1: States of Signals for All the Traffic

Logic Design Unit 8
Table 8.2 lists the Boolean functions for all the signal lights, in terms of
Boolean variables X, Y and Z.
Table 8.2: Boolean Functions for All the Signal conditions
From the table 8.2, we can note that both the left and right turn signals have
similar switching pattern and hence they have identical functions. Hence
these signals can be controlled by a single block of control logic.
Figure 8.2 shows the logic diagram that generates all the control signals
which can be used to activate all the signal lights according to the Boolean
functions listed in table 8.2.
The IC1 is a 555 timer and is used to generate the clock signal for the
counter IC2. Note that the timer IC is configured as an astable multivibrator.
The duration T for which the IC1 output (clock to IC2) remains HIGH is
given by,
T = 0.695 C2(R1+R2)
Hence we can vary T by varying the values of R1, R2 or C2.

Logic Design Unit 8
The 4 bit counter IC2 works like a 3 bit counter. The connection to reset
pin 1 from the output Q3 via inverter N1 achieves this. The remaining
counter outputs Q2, Q1 and Q0 map to the variables X, Y and Z
respectively.
Figure 8.2: The circuit diagram for traffic light signaling
We can check the working of the traffic light controller by connecting the
light control outputs to red, yellow and green LED’s which represent the
actual signal lights. To limit the current through the LED’s, we can connect a
resistor (typical value 470 Ohms) in series with each. As we stated before,
only. If in a particular junction, some direction of movement is restricted,
then signals can be suitably merged with the next state.
Logic Design Unit 8
For the manual control of the traffic lights, one can load the desired binary
state code (indicated by X, Y, Z variable values) into the counter IC. For this
purpose the counter must be wired in a pre-settable mode. We can also
reset the signal lights to the initial state (XYZ = 000), by resetting the
counter. This can be achieved by having an external switch which can feed
a LOW (0) to reset pin (pin 1) of IC2. A computer program in C language
which can simulate the traffic light controller circuit on a PC is shown in
figure 8.3. Table 8.3 shows the results of execution of the program.
Figure 8.3: C program for simulate the traffic light controller

Logic Design Unit 8
Table 8.3: Execution Results of Software Program
8.3 Two Way Switches

In applications where multiple switching options are required (e.g., a
telephone service), mechanical switches have long been replaced by
electronic switching devices which can be automated and intelligently
controlled.
We can define a switch in terms of its operation and use. In general, a
switch is a device that can be used to either establish or remove (also called
make or break) connections between at least two points in an electric or
electronic circuit.
The figure 8.4 shows ON-OFF switch along with its symbol.
(a)
(b)
Figure 8.4: Switch (a) ON-OFF switch (b) Circuit symbol

Logic Design Unit 8
The most common type of switches is the one that we use to turn our lights
on and off. Depending on the power that is switched, size and physical
nature we have a wide range of switches, ranging from sub-micron
transistors to big switches that can switch megawatts of power. Although
there are many types of switches, we are more accustomed to one-way and
two-way electrical switches. The main difference between them lies in the
number of contacts they have. A one-way switch only has two contacts and
a two-way switch has three.
A one-way switch basically operates as a make or break switch. So when it
is turned on, the two terminals are connected, and when it is turned off, the
contact between the two is broken. In contrast, a two-way switch is basically
two, one-way switches combined into one. Here one of the terminals can be
connected to either of the remaining two but not both at the same time.
When we make a connection with one terminal, the connection with the
other is broken.
A switch can be considered to be a ‘gate’ which either allows or disallows
certain entity. When such a switch can be operated using some logic, then
we can call this switch as a ‘logic gate’. Electronic hardware technology
provides us with miniature logic gates which can be put together in large
numbers (several millions) on a single chip, which can function as a system
of logic. A computer is a classic example of such an electronic system
composed of electronic logic gates.
On the other side we have mechanical arrangements that can switch the
track of a train from one to another.
A regular electric switch that can be used to control power to domestic
appliances has small metallic pieces called contacts. And these contacts
are made to physically touch each other to make a circuit, while separation
between them breaks it. The desirable properties of these metallic contacts
are low resistance, very good electrical conductivity, resistance to corrosion,
mechanical strength to name a few. To achieve the desirable properties,
sometimes the contacts may be plated with metals such a gold, copper etc.
Actuator
The mechanical or electromechanical part which helps the contacts to
physically touch and separate are called actuators. These could be a spring
loaded toggle, a rocker, electrically operated relay, a push-button etc.

Logic Design Unit 8
Contact arrangements
A switch is said to be ‘closed’ if the contacts of the switch are in physically
touching each other, which allows electric current flow through it. When the
contacts are separated with a gap, current cannot flow through the switch.
Now the switch is said to be ‘open’.
Generally electric switches can be classified according to the number of
contacts and mechanical movements required to operate them. A SPST
switch means, single pole (contact) - single throw (movement). But electrical
power supply industry and wiring technicians also have alternate
nomenclature like ‘one-way’ switch; ‘three-way’ switch etc.
The figure 8.5 shows the some of the types of switches based on their
method of contacts.
(a) (b)
(c) (d)
Figure 8.5: Types of Switches

(a) SPST (Single Pole, Single Throw)
(b) SPDT (Single Pole, Double Throw)
(c) DPST (Double Pole, Single Throw)
(d) DPST (Double Pole, Double Throw)

Logic Design Unit 8
A normally open (‘NO’) switch has its contacts open by default and the
contacts close only when the switch is operated. Similarly a normally closed
(‘NC’) switch has closed contacts until opened by operating the switch.
These are shown in figure 8.6. The nomenclatures are normally used in
logic and wiring diagrams to enhance the clarity of operation. This helps in
minimizing assembly line errors and troubleshooting faults. A switch with
both types of contacts is called a changeover switch or "make-before-break"
switch contact, whereas most switches have a spring loaded action which
momentarily disconnect the load and so are "break-before-make" types by
contrast.
Figure 8.6: (i) Normally Open (‘NO’) switch (ii) Normally Close (‘NO’) switch
The type of switch to be used depends on particular application. For

example, if interruption of power to a load is not acceptable, then a “make-
before-break” switch could be used to select an alternate power source to
the load. The terms pole and throw are also used to describe switch contact
variations. A pole is a set of contacts, the switch's electrical terminals that
are connected to and belong to a single circuit, usually a load. A throw is
one of two or more positions that the switch can adopt, which normally, but
not always correspond to the number positions the switch handle or rotor
can take when connecting between the common lead of the switch and a
pole or poles. A throw position which connects no terminals (poles), has a
mismatch between positions and positions which connect terminals, but are
quite useful to turn things "Off" or for example, alternatively select between
two scaled modes of operation. (e.g. Bright illumination, moderate
illumination, no illumination). Switching a load on or off from two locations
(for instance, turning a light on or off from either end of a flight of stairs)
requires two SPDT switches.

Logic Design Unit 8
8.4 Electronic Tennis Scoring System

The present tennis scoring system includes input devices for each player to
indicate whether one player or the other has won a particular point. These
input devices for each player may be in the form of transmitters each having
two recessed pushbutton switches, one to indicate that one player has won
the point and the other to indicate that the opposing player has won the
particular point.
The input device may take the form of a belt buckle size unit worn at the
waist or on the wrist. Electronic scoring circuitry provided is responsive to
the concurrent depressing of buttons by both players indicating who has
won a particular point. Electronic scoring equipment keeps track of the
points, games, sets and matches won by each player and each side.
Suitable electronic equipment is provided to accommodate slight differences
in the timing of the pressing of input switches by the two players. Special
logic circuitry is provided for accommodating the tennis scoring situation
involving deuce games. Transmitters with unique signals to indicate who
has won a point are provided. A common display and annunciator unit may
be used which receives signals from input devices of each player.
Alternatively, small LED displays may be provided on each of the input units
to display the points, games, sets and matches won by each player and
each team. The annunciator may provide a unique sound to indicate points
won by one player as compared with a different sound for points won by the
other player.
A league and tournament system is disclosed which includes a centralized
league machine that transmits data to one or more of a plurality of electronic
dart games via modem or using a wireless portable data storage device.
The electronic dart machines are configured to receive and utilize league
and tournament database information from the league machine for a variety
of purposes, including automatic implementation of player handicaps,
automatic control of match play, and team and player registration using the
dart machine. The dart machine has a monitor that displays context
sensitive menus using information obtained from the league or tournament
database. The dart machine includes a barcode card reader that permits
identification of league and tournament participants using barcode cards.
The dart machine can also respond to other types of barcode cards for such
purposes as crediting games and providing access to machine performance
Logic Design Unit 8
data and certain machine servicing functions. Inter-game communication

within an establishment is provided either by hardwiring the dart machines
or using infrared communication.
8.5 Temperature and Weather Forecast Systems

We consider here weather forecasting. Weather is the state of the
atmosphere like it is hot or cold, wet or dry, calm or stormy, clear or cloudy.
Weather forecasting is predicting the state of the atmosphere for a future
time and a given location. A barometer is a scientific instrument used in
meteorology to measure atmospheric pressure. When atmospheric pressure
is measured by a barometer, the pressure is also referred to as the
barometric pressure. Now let us study 1-wire Barometer.
1-wire Barometer:
Assumptions/Design Criteria
 The barometer will be operated indoors. This will minimize output
variations caused by temperature and will lengthen the calibration
intervals. It also means the circuit board will not have to be
weatherproofed.
 Will be easy to calibrate. Maximum of 1 calibration adjustment.
 The operating range will be from 28.00 inHg to 32.00 inHg
 Resolution will be greater than .01 inHg from sea level to 10,000 feet.
 The interface will be standard Dallas Semiconductor 1-wire.
 Unit will be designed for indoor operation, so it can be externally
powered.
 Will utilize the Motorola MPX4115A pressure transducer.

Logic Design Unit 8
Based on these assumptions, table 8.4 is generated.

Table 8.4: Station Pressure & Actual Pressure
This table 8.4 calculates the station pressure for both the minimum (28.00)
and the maximum (32.00) pressures for altitudes from sea level to 10,000
feet in 1000 foot increments. The station pressure is then converted to
MPX4115A pressure sensor volts. Looking at the table, you can see the
predominant change in altitude in the offset voltage of the pressure sensor.
The OA Offset column is the op amp offset voltage that compensates for
altitude. This will be the only calibration variable. Since the instrumentation
amplifier is a rail-to-rail device, in theory it will operate down to 0 volts.
However, to provide some margin, the offsets were chosen to allow a
minimum of 0 .2 volts at the lowest pressure. The gain of 10 was chosen to
allow maximum output voltage swing for all altitudes. The resulting op amp
output voltages are listed in OA Output column. This is the voltage applied
to the DS2438 Vad input.

Logic Design Unit 8
Circuit Design:
The following circuit design satisfies requirements (refer figure 8.7). INA122
instrumentation amplifier was selected as it eliminated several external
resistors and it provides a very stable gain over a wide temperature. It also
provides excellent rail-to-rail operation allowing full use of the 10 volt input
range of the DS2438. The 40.2K ohm resistor sets the gain to 10. The
variable resistor allows adjustment of the offset voltage from 2.0v to 4.0v.
Figure 8.7: Circuit for 1-wire Barometer
Calibration:
Hardware calibration is simply a matter of setting the offset voltage to the
value listed in table 8.4 for your altitude. A jumper on the input of the
DS2438 allows the use of the DS2438 to measure the offset. Put the jumper
in the A-C position and using the iButton Viewer for the DS2438, set the

Logic Design Unit 8
voltage to the table value using the 25-turn pot. Once it is set, put the
jumper in the A-B position to read pressure.
For altitudes in between the values listed in the table, simple interpolation
will give accurate results. An Excel spreadsheet can be used to calculate
intermediate values.
Routines currently exist to measure the DS2438s Vad voltage. Once this
voltage is measured, the pressure is calculated using:
Press = slope * Vad + intercept
Where the slope and intercept are the values listed in table 8.1 for your
altitude. The prototype code had an external text file to store the slope and
intercept values. This allows the user to edit the file to fine-tune the
calibration if desired.
Fine-tuning can be accomplished by monitoring the pressure and comparing
it with a known reference source, such as a nearby airport or national
weather service. Start by adjusting the intercept. When the reference station
indicates a pressure near mid-scale (30.00 inHg), adjust the software
intercept value until your weather station matches. Now monitor the
pressure extremes to determine if the slope needs adjustment.
Future Options:
A fixed resistor could replace the variable resistor. This would eliminate any
hardware adjustments. The value would have to be calculated for a given
altitude. Another possibility is to use several DS2406 1-wire switches or a
programmable potentiometer to set the offset programmatically.
8.6 Summary
In this unit some example of real world electronic design were presented. All
the designs require clear understanding of application requirements, and
accordingly design decisions are taken. While the traffic light controller was
purely digital, temperature and weather forecast system design included use
of sensors and analog components. We also learnt about various types of
switches and the terminology associated with them.

Logic Design Unit 8

 Traffic Signal Systems is an automatic traffic light controller and can be
implemented by programming any gate array based logic (GAL) device
such as FPGA.
 Switch is a device that can be used to either establish or remove (also
called make or break) connections between at least two points in an
electric or electronic circuit.
 Actuator is the mechanical or electromechanical part which helps the
contacts to physically touch and separate.
 A normally open (‘NO’) switch has its contacts open by default and the
contacts close only when the switch is operated.
 Electronic scoring circuitry provided is responsive to the concurrent
depressing of buttons by both players indicating who has won a
particular point.
 1-wire barometer design will utilize the Motorola MPX4115A pressure
transducer
1. The mechanical or electromechanical part which helps the contacts to
physically touch and separate are called ______________.
2. All control signals that drive traffic lights can be mapped into
_____________functions.
3. A switch can be considered to be a _________which either allows or
disallows certain entity.
4. Electronic scoring equipment keeps track of the points, games, sets and
matches won by each player and each side (True or false).
5. ________________is pressure transducer.

1. Design a traffic light controller for a three road junction.
2. Describe various types of electrical switches.
3. Explain the design of an electronic tennis scoring system.

Logic Design Unit 8
8.8 Answers
Self-Assessment Questions
1. Actuators
2. Boolean
3. Gate
4. True
5. Motorola MPX4115A
Terminal Questions

Logic Design Unit 9
Unit 9 Digital Equipments

Structure:
9.1 Introduction
Objectives
9.2 MODEM
9.3 Digital Multi-meter
9.4 Digital Versatile Disks
9.5 Summary
9.7 Answers
9.1 Introduction
In the previous unit you studied about some real world logic circuits like
traffic signal systems, tennis scoring system, switches, temperature &
weather forecast systems and their design. Multiplexing equipment used by
the news services in the year 1920s are not commonly counted in the
history of modems as the modem function was incidental to the multiplexing
function. In 1940, George Stibitz connected a new Hampshire teletype to a
computer system in New York City through phone lines. In United States,
modems were part of the SAGE air-defense system in 1950s for connecting
terminals to various radar sites, airbases and command-and-control centers
to the SAGE director present all over the US and Canada. SAGE had
dedicated lines for communication, but the terminal devices at every end
were installed with a king of today’s modem.
Later, when CEO of American Airlines and a region manager of IBM had a
chance of meeting; this led to the development of “mini-SAGE” as an
automatic airline ticketing system. It worked in the lines as sage like ticket
office scattered across the nation had the terminals which are tied to the
central computer that took care of availability and scheduling. This system
known as SABRE is the primitive version of today’s Sabre system.
AT&T maintained a monopoly in the US for many years by letting only AT&T
devices to be connected to the network. AT&T introduced two digital
sub-sets in 1958 for the growing group of computers – Wideband device
and low-speed modem.

Logic Design Unit 9
Data-phone was introduced in 1960 to replace the term digital subset. The
202 Data-phone which was market extensively in 1960 was a half-duplex
asynchronous service. The 201A operated half-duplex at 2000 bit/s over
normal phone lines, while the 201B provided full duplex 2400 bit/s service
on four-wire leased lines, they sent and received channels running on their
own set of two wires each.
In 1962, the famous 103A was introduced. Over the normal phone lines, it
provided full-duplex service up to 300 baud. Call originators transmitting at
1070 or 1270 Hz and the answering device transmitting at 2025 or 2225 Hz
used Frequency-shift keying. The readily available 103A2 gave an important
boost to the use of remote low-speed terminals such as the KSR33, the
ASR33, and the IBM 2741. By introducing the originate-only 113D and
answer-only 113B/C modems, AT&T reduced modem costs considerably.
As radio receivers and vacuum tube electronic devices became more
common in 1920s, multimeters were invented. Multimeter became more
complex or may be supplemented by more specialized equipment in
technician’s toolkit as the modern systems became more complex. A
modern technician uses a hand-held analyzer to test several parameters in
order to verify the performance of a network cable, where a general-purpose
mulitmeter can test only short-circuits, conductor resistance and measure of
insulation quality.
DVD (also known as "Digital Versatile Disc" or "Digital Video Disc") – is a
popular optical disc storage media format. Its main uses are video and data
storage. In this unit you will study about the some digital equipments. Here
you will mainly study MODEM, Digital Multi-meter and Digital Versatile Disks
Objectives:
 explain the function of MODEM.
 explain the working of Digital Multi-meter
 list the uses of DVD
9.2 MODEM
MODEM stands for modulator-demodulator. It is a device which modulates
an analog carrier signal for encoding digital information and performs the
function of demodulating such a carrier signal to decipher the digital
Logic Design Unit 9
information encoded in it. The goal is the generation of a signal that can
easily be transmitted and decoded to regenerate the actual digital data.
Modems can be used over any means of transmitting analog signals, from
light emitting diodes to radio. Voice band modem is one example that
converts digital 0s and 1s from a personal computer into sound signals
which could be transmitted over telephone lines of Plain Old Telephone
Systems (POTS) which on the other side receives the sound signal and
converts it back to the corresponding digital information.
Classification of modems is done on the basis of rate of data transmission,
normally measured in bits/second or bps. Classification can also be done
based on the rate at which the modem switches its transmission speed per
second, termed Baud. Baud is measured in symbols/sec. Based on the
modulation technique used, baud rate changes. A state change of
300 times/sec was observed in original Bell 103 modems. If a modem
transmitted 1-bit every baud, it’s a 300bit/sec modem or 300-baud modem.
Only modem whose bit rate matched with the baud rate is 300 bits/sec. A
modem that switches its state 600 times/sec and for each baud if it
transmits 4 bits, it is said to be a 2400 bit/sec modem.
Cable modems and Asymmetric digital subscriber line (ADSL) modems are
some faster modems used by internet users daily. Repeating frames of data
is transmitted at very high rates over microwave radio links in “radio
modems” used in telecommunications. There are modems that transmit
more than hundred million bits/sec. Optical modems use optical fibers to
transmit data. Undersea optical fibers are used in most of the present
intercontinental data links. Optical modems consistently have data rates in
excess of a billion bits/sec. One kilobit/sec in this context refers to
1000bits/sec and not 1024bits/sec. For example, a 48k modem transfers
data at rates up to 48,000 bits (6kB)/sec.
The Smartmodem and the rise of Bulletin Board Systems
Smartmodem introduced by Hayes Communications in 1981 is the next
major breakthrough in modems. It is a standard 103A 300-bits/sec modem,
along with a controller; because of which computer can send commands to
it and enable it use the phone line. Picking up and hanging up calls, dialing
numbers etc. can be done through commands. Most of the modern modems
still use the basic Hayes command set.

Logic Design Unit 9
Modems before the Hayes Smartmodem required a two-step sequence to

activate the connection: primarily, the user will have to dial the number on
the standard phone and the then secondarily, phone is plugged into an
acoustic coupler. In order to emulate dialing a handset, hardware add-ons
like dialers are used in special circumstances.
Using Smartmodem, computer can directly dial the phone using
corresponding commands. Hence the separate phone and acoustic coupler
is no more required. Smartmodem is plugged directly into the phone line.
This reduced the setup and operation effort significantly. Terminal programs
that stored a list of phone numbers and sending commands to dial became
common.
Bulletin board systems (BBSs) spread was aided by the Smartmodem and
its clones. Previously on the client side, call-only, acoustically coupled
models were used. Whereas on the server side, more expensive answer-
only models are were employed. Smartmodem works in any mode
depending on the computer sent out commands. Currently, there are low-
cost server-side modems available in the market and BBSs flourished.
Soft modem (dumb modem)
During the second half of the 1990s, GeoPort modem released by Apple
was similar one. Even though the theory is a clever one, i.e. enabling
creation of powerful telephony application, in reality only programs
developed were mere answering-machine and fax software, little improvised
than their physical-world counterparts and more prone to error. The
software was fussy and consumed majority of processor time and is no
more operates in the present operating systems.
Most of the present day modems works secondarily as fax machine as well.
In 1980’s when digital faxes were introduced, an image format was sent
over a high-speed modem (9600/1200 bit/sec). Computer can convert an
image into fax-format which was then sent through modem. Once, this
function was just an add-on, but it has become universal now.
Softmodem or winmodem is a stripped-down modem that takes up most of
the tasks in to software, which was traditionally performed in hardware.
Here, modem acts a digital signal process that creates sounds or voltage
fluctuations on the telephone line. Because of the lesser hardware
components, it is cheaper than traditional modems. Software generating the
Logic Design Unit 9
modem tones is complex and the performance of the computer as a whole

gets affected when it is used. This is one disadvantage. This is becomes a
real concern when it comes to online gaming. Lack of portability to operating
systems(Oss) like Linux which may not have equivalent driver to operate the
modem is another down-side. If the driver is incompatible with later version
of windows, Winmodem may not work properly then.
Narrowband/phone-line dialup modems
Modems that are used currently are composed of an analog part and a
digital part - analog part for generating signals and operating the phone,
whereas the digital part for setup and control. Both the components are
incorporated into a single chip even though there is division theoretically.
Modem essentially works in two modes – command mode and data mode.
Command mode is the one wherein the modem accepts the commands
from the system and executes them. In data mode, data is sent to and from
the computer over the phone lines. After powering up, modem enters
command mode and then system sends it the command for dialing a
number. Once the connection is established with the remote modem, it can
switch to data mode and then send and receive data. When the user is done
with data transfer, an escape sequence “+++” followed by a break of about
one second is sent to the modem to let it know and return it to command
mode, and the command ATH to hang up the phone is sent.
The commands themselves are typically from the Hayes command set,
although that term is somewhat misleading. Only for the operations which
work at 300 bps Hayes commands are used and for 1200bps operations
these commands are extended. As new commands are required for faster
speeds of operation, in 1990 there was rapid growth of command sets. By
second half of 1990s, chip sets are used to construct the modem. We call
this the Hayes command set even today, although it has three or four times
the numbers of commands as the actual standard.
Increasing speeds (V.21 V.22 V.22bis)
In order to send the data using 300bps modems, frequency shift keying is
used. In the above systems, the sounds which can be transmitted easily on
phone lines is generated from the stream of 1s and 0s. In Bell 103 system,
1070 Hz and 1270 Hz tones are played to send 0s and 1s respectively from
the originating modem, and 0s and 1s are putted on to 2025 Hz and

Logic Design Unit 9
2225 Hz respectively. As these frequencies are not harmonics to each other

and can suffer from the distortion on the system, they should be chosen
very carefully.
Phase shift keying is used in the systems whose speed is equal to or more
than 1200bps. Similar to 300bps systems, same frequencies are used to
send the tones, but these signals will be out of phase with each other. The
values of the stream can be determined by comparing the phases of the two
signals, An 90 degree out of phase signals represent “1,0”, and an
180 degree out of phase signals represent “1, 1”. It can be observed that
instead of one digit, two digits are represented by using above method.
In mid 1980s, 300bps (V.21) and 1200bps (V.22) modems are used in
voiceband modems. A different version of V.22b is 2400bps is introduced in
Europe, but a system which is similar to Bell 212 (1200bps) is introduced in
US. 2400bps modems operations became common by late 1980s and they
could support all the standards.
Increasing speeds (one-way proprietary standards)
In order to use low speed channels and high speed channels for
transmitting and receiving, many standards have been introduced. In the
French Minitel systems, 1200bps and 75bps have been used for receiving
and transmitting respectively.
By introducing high speed versions of above concept 2 companies in US
became famous. The Trailblazer modem which has been introduced by
Telebit, can send the data at a rate of 1800 bps. The direction of the
communication can be changed by the modem depending upon how much
data is waiting on each side; this was done by an additional single channel
which is connected in reverse direction. The UUCP “g” protocol which is
used to send e-mail on Unix systems can spoofed by the special feature on
Trailblazer modem and because of the there was tremendous amount of
speed up. As the speed was improved, till 1990s Trailblazer became
common on Unix systems.
HST modems which was for larger backchannels supplied only 9600bps
was introduced by U.S. Robotics (USR). Instead of offering spoof, for fast
file transfers USR offered its modem to BBs sysops (system operators) at
lower price to create a large market. Similar to Telebit’s PEP, Express 96
was introduced by Hayes which used 9600 bps standard. These modems
Logic Design Unit 9
which are high speed were rare, because neither spoofing nor sysop
discounts was not offered by Hayes.
4800 and 9600 (V.27ter, V.32)
Another major advancement in the modem design was Echo cancellation. In
order to receive and send the data, same wires are used by the telephone
lines, because of which the amount of bouncing back will be small. But the
modem can get confused by this signal. Is the signal it is "hearing" a data
transmission from the remote modem, or its own transmission bouncing
back? In earlier systems, in order to originate and answer, the signal
frequencies are split into two so that modem can avoid hearing its own
originating frequencies; the speed of the modems has been limited to its half
speed because of splitting of the bandwidth.
Echo cancellation got around this problem. The modems were able to
decide whether the signal is from remote modem or from itself by measuring
the delays and magnitudes of the echo and cancel the signals if it is from
itself. By cancelling the echoes, the speed of the modems was increased
and was able to send and receive the data at full speed which led to the
development of 9600bps and 4800bps modems.
A complicated theory of communication has been used to increase the
speed of modems. PSK technique was used in 2400 bps and 1200bs
modems where 2 or 3 bits per symbol can be transmitted. Then Quadrature
Amplitude Modulation (QAM) is used to get the combination of phase and
amplitude by encoding four bits. A constellation diagram can be used for the
best visualization, this diagram has two coordinates x(real) and
y (quadrature) and the bits which are transmitted over the carrier are
mapped on to the points on the graph. The new V.27ter and V.32 standards
were able to transmit 4 bits per symbol, at a rate of 1200 or 2400 baud,
giving an effective bit rate of 4800 or 9600 bits per second. The carrier
frequency was 1650 Hz.
Error correction and compression
The limitation of the phone lines has been increased because of operations
at high speeds which resulted in high error rates. In order to reduce the
error rates, modems with inbuilt error corrections mechanism has been built
and became famous with Micorcom’s MNP systems. By minimizing
overheads, the effective data rate has been increased from 75% (in MNP1)

Logic Design Unit 9
to 95% (MNP 4) the data rate in MNP 5 has been further increased by
introducing the data compression mechanism to the systems. Generally the
user could expect an MNP5 modem to transfer at about 130% the normal
data rate of the modem. MNP was later "opened" and became popular on a
series of 2400-bit/s modems, and ultimately led to the development of
V.42 and V.42bis ITU standards. V.42 and V.42bis were non-compatible
with MNP but were similar in concept: Error correction and compression.
In high speed modems, the concept of fallback is the used very commonly.
Because of this concept high speed modem can speak to a modem which is
less capable. At the time of call initiation, modem would wait for the
response from remote modem once after sending a series of signals into the
telephone line. During this process, till the modem hears from remote
modem, it would reduce its speed progressively. Because of above method
at a speed of 9600bps 2 USR modems were able to communicate, but the
2400bps modem would fall back to its normal speed. As the HST and
V.32 modems used different standard at 9600bps, they also fall back to its
normal standard (2400 bps), if the above method is employed. The same
applies to V.32bis and 14400 bit/s HST modem.
Breaking the 9.6k barrier
In 1980 Gottfried Ungerboeck from IBM Zurich Research Laboratory applied
powerful channel coding techniques to search for new ways to increase the
speed of modems. His results were astonishing but only conveyed to a few
colleagues. Finally in 1982, he agreed to publish what is now a landmark
paper in the theory of information coding. By applying powerful parity check
coding to the bits in each symbol, and mapping the encoded bits into a two
dimensional "diamond pattern", Ungerboeck showed that it was possible to
increase the speed by a factor of two with the same error rate. The new
technique was called "mapping by set partitions" (now known as trellis
modulation).
The industry was galvanized into new research and development. More
powerful coding techniques were developed, commercial firms rolled out
new product lines, and the standards organizations rapidly adopted to new
technology. The "tipping point" occurred with the introduction of the
SupraFAXModem 14400 in 1991. Rockwell had introduced a new chipset
supporting not only V.32 and MNP, but the newer 14,400 bit/s V.32bis and

Logic Design Unit 9
the higher-compression V.42bis as well and even included 9600 bit/s fax
capability. Supra, then known primarily for their hard drive systems, used
this chip set to build a low-priced 14,400 bit/s modem which cost the same
as a 2400 bit/s modem from a year or two earlier (about US$300). The
product was a runaway best-seller, and it was months before the company
could keep up with demand.
V.32bis was so successful that the older high-speed standards had little to
recommend them. USR fought back with a 16,800 bit/s version of HST,
while AT&T introduced a one-off 19,200 bit/s method they referred to as
V.32ter (also known as V.32 terbo), but neither non-standard modem sold
well.
V.34 / 28.8k and 33.6k
An ISA modem manufactured to conform to the V.34 protocol. Any interest
in these systems was destroyed during the lengthy introduction of the
28,800 bit/s V.34 standard. While waiting, several companies decided to
"jump the gun" and introduced modems they referred to as "V.FAST". In
order to guarantee compatibility with V.34 modems once the standard was
ratified (1994), the manufacturers were forced to use more "flexible" parts,
generally a DSP and microcontroller, as opposed to purpose-designed
"modem chips".
Today the ITU standard V.34 represents the culmination of the joint efforts.
The most powerful coding techniques are employed including channel
encoding and shape encoding. From 4 bits per symbol (9.6 kbit/s), the new
standards used the functional equivalent of 6 to 10 bits per symbol, plus
increasing baud rates from 2400 to 3429, to create 14.4, 28.8, and
33.8 kbit/s modems. This rate is near the theoretical Shannon limit.
When calculated, the Shannon capacity of a narrowband line is
Bandwidth * log2(1 + Pu / Pn), with Pu / Pn the signal-to-noise ratio.
Narrowband phone lines have a bandwidth from 300-3100 Hz, so using
Pu / Pn = 100,000: capacity is approximately 35 kbit/s.
Without the discovery and eventual application of trellis modulation,
maximum telephone rates would have been limited to
3429 baud * 4 bits/symbol = approximately 14 kilobits per second using
traditional QAM.

Logic Design Unit 9
Using digital lines and PCM (V.90/92)

In the late 1990s Rockwell and U.S. Robotics introduced new technology
based upon the digital transmission used in modern telephony networks.
The standard digital transmission in modern networks is 64 kbit/s but some
networks use a part of the bandwidth for remote office signaling (eg to hang
up the phone), limiting the effective rate to 56 kbit/s Digital Signal 0 (DS0).
This new technology was adopted into ITU standards V.90 and is common
in modern computers. The 56 kbit/s rate is only possible from the central
office to the user site (downlink) and in the United States; government
regulation limits the maximum power output to only 53.3 kbit/s. The uplink
(from the user to the central office) still uses V.34 technology at 33.6k.
Later in V.92, the digital PCM technique was applied to increase the upload
speed to a maximum of 48 kbit/s, but at the expense of download rates. For
example a 48 kbit/s upstream rate would reduce the downstream as low as
40 kbit/s, due to echo on the telephone line. To avoid this problem,
V.92 modems offer the option to turn off the digital upstream and instead
use a 33.6 kbit/s analog connection, in order to maintain a high digital
downstream of 50 kbit/s or higher. V.92 also adds two other features. The
first is the ability for users who have a call waiting to put their dial-up
Internet connection on hold for extended periods of time while they answer
a call. The second feature is the ability to "quick connect" to one's ISP. This
is achieved by remembering the analog and digital characteristics of the
telephone line, and using this saved information to reconnect at a fast pace.
Using compression to exceed 56k
Today's V.42, V.42bis and V.44 standards allow the modem to transmit data
faster than its basic rate would imply. For instance, a 53.3 kbit/s connection
with V.44 can transmit up to 53.3*6 == 320 kbit/s using pure text. However,
the compression ratio tends to vary due to noise on the line, or due to the
transfer of already-compressed files (ZIP files, JPEG images, MP3 audio,
MPEG video). At some points the modem will be sending compressed files
at approximately 50 kbit/s, uncompressed files at 160 kbit/s, and pure text at
320 kbit/s, or any value in between.
In such situations a small amount of memory in the modem, a buffer, is
used to hold the data while it is being compressed and sent across the
phone line, but in order to prevent overflow of the buffer, it sometimes

Logic Design Unit 9
becomes necessary to tell the computer to pause the data stream. This is
accomplished through hardware flow control using extra lines on the
modem–computer connection. The computer is then set to supply the
modem at some higher rate, such as 320 kbit/s, and the modem will tell the
computer when to start or stop sending data.
Compression by the ISP
As telephone-based 56k modems began losing popularity, some Internet
Service Providers (ISPs) such as Netzero and Juno started using
pre-compression to increase the throughput & maintain their customer base.
As an example, the Netscape ISP uses a compression program that
squeezes images, text, and other objects at the server, just prior to sending
them across the phone line. The server-side compression operates much
more efficiently than the "on-the-fly" compression of V.44-enabled modems.
Typically website text is compacted to 4% thus increasing effective
throughput to approximately 1300 kbit/s. The accelerator also
precompresses Flash executables and images to approximately 30% and
12%, respectively.
The drawback of this approach is a loss in quality, where the graphics
become heavily compacted and smeared, but the speed is dramatically
improved such that web pages load in less than 5 seconds, and the user
can manually choose to view the uncompressed images at any time. The
ISPs employing this approach advertise it as "DSL speeds over regular
phone lines" or simply "high speed dial-up".
List of dialup speeds
Note that the values given are maximum values, and actual values may be
slower under certain conditions (for example, noisy phone lines). For a
complete list see the companion article List of device bandwidths.
Connection Bitrate
Modem 110 baud 0.1 kbit/s
Modem 300 (300 baud) (Bell 103 or V.21) 0.3 kbit/s
Modem 1200 (600 baud) (Bell 212A or V.22) 1.2 kbit/s
Modem 2400 (600 baud) (V.22bis) 2.4 kbit/s
Modem 2400 (1200 baud) (V.26bis) 2.4 kbit/s
Modem 4800 (1600 baud) (V.27ter) 4.8 kbit/s
Modem 9600 (2400 baud) (V.32) 9.6 kbit/s

Logic Design Unit 9
Modem 14.4 (2400 baud) (V.32bis) 14.4 kbit/s

Modem 28.8 (3200 baud) (V.34) 28.8 kbit/s
Modem 33.6 (3429 baud) (V.34) 33.8 kbit/s
Modem 56k (8000/3429 baud) (V.90) 56.0/33.6 kbit/s
Modem 56k (8000/8000 baud) (V.92) 56.0/48.0 kbit/s
Bonding Modem (two 56k modems)) (V.92) 112.0/96.0kbit/s
Hardware compression (variable) (V.90/V.42bis) 56.0-220.0kbit/s
Hardware compression (variable) (V.92/V.44) 56.0-320.0 kbit/s
Server-side web compression(variable) (Netscape ISP) 100.0-1000.0 kbit/s
Radio modems
Direct broadcast satellite, WiFi, and mobile phones all use modems to
communicate. Modern telecommunications and data networks also make
extensive use of radio modems where long distance data links are required.
Such systems are an important part of the PSTN, and are also in common
use for high-speed computer network links to outlying areas where fiber is
not economical.
Even where a cable is installed, it is often possible to get better performance
or make other parts of the system simpler by using radio frequencies and
modulation techniques through a cable. Coaxial cable has a very large
bandwidth; however signal attenuation becomes a major problem at high
data rates if a digital signal is used. By using a modem, a much larger
amount of digital data can be transmitted through a single piece of wire.
Digital cable television and cable Internet services use radio frequency
modems to provide the increasing bandwidth needs of modern households.
Using a modem also allows for frequency-division multiple access to be
used, making full-duplex digital communication with many users possible
using a single wire.
Wireless modems come in a variety of types, bandwidths, and speeds.
Wireless modems are often referred to as transparent or smart. They
transmit information that is modulated onto a carrier frequency to allow
many simultaneous wireless communication links to work simultaneously on
different frequencies.
Transparent modems operate in a manner similar to their phone line modem
cousins. Typically, they were half duplex, meaning that they could not send
and receive data at the same time. Typically transparent modems are polled

Logic Design Unit 9
in a round robin manner to collect small amounts of data from scattered

locations that do not have easy access to wired infrastructure. Transparent
modems are most commonly used by utility companies for data collection.
Smart modems come with a media access controller inside which prevents
random data from colliding and resends data that is not correctly received.
Smart modems typically require more bandwidth than transparent modems,
and typically achieve higher data rates.
WiFi and WiMax
The WiFi and WiMax standards use wireless mobile broadband modems
operating at microwave frequencies.
Mobile modems & Routers
Mobile modems are the modems which use mobile phone lines like GPRS,
UMTS, EVDO, etc. For a laptop or any appliance, these modems can be
embedded inside them. Datacards and cellular routers are the external
modems which can be connected to any appliance. The datacard is a PC
card or ExpressCard which slides into a PCMCIA/PC card/ExpressCard slot
on a computer. AirCard made by Sierra Wireless is the most famous brand
of modem datacards. Instead of PC cards, now a day’s USB modems are
used to connect to the laptop. An external datacard may or may not be
present in the cellular router. The cellular modem is usually made for single
connection and but multiple people are allowed to connect to a cellular
routers.
There will be integrated SIM cardholder for the GSM based cellular router
i.e., Huawei E220, Sierra 881, etc, but the CDMA routers will not use
SIM cards, instead they use Electronic Serial Numbers. From region to
region, there is a variation in the cost of using the modems. For unlimited
data transfers some providers implement a flat rate, whereas some have
maximum limit on the data transfers in a month. Some countries charge per
Megabyte or Kilobyte of downloaded data. The faster data rates of the
newest cellular modem technologies (UMTS, HSPA, EVDO, WiMax) are
also considered to be "Broadband Cellular Modems" and compete with
other Broadband modems below.

Logic Design Unit 9
Broadband
ADSL modem
ADSL (asymmetric digital subscriber line) modems, a more recent
development, are not limited to the telephone's "voiceband" audio
frequencies. Some ADSL modems used discrete multi-tone(DMT) also
called coded orthogonal frequency division modulation (COFDM)
A range of frequencies which are intended to carry radio frequency
TV channels can be used by cable modems. The same frequency band can
be used by many cable modems which are connected to a single cable, in
order to allow multiple cable modems to work together within the channel, a
low level media access protocol can be used. By using FDMA, up and down
signal are kept apart.
Power line modems and double way satellite modems are new types of
latest broadband modems.
As the broadband modems uses complex waveform to carry the data, they
are still called as modems. When compared to the normal dial up modems,
these broadband modems are more advanced. Broadband modems can
modulate or demodulate 100s of channels. Many functions of a router and
features like DHCP, firewall features and NAT are included in broadband
modems.
Since consumers were unfamiliar with routers and networking when the
technology of broadband was introduced manufacturers instead of selling
broadband devices as adapter or transceivers, they started selling with the
term modem. Before a broadband modem using a router, they should be
configured in a bridge mode.
Deep-space telecommunications
Many modern modems have their origin in deep space telecommunications
systems from the 1960s. Differences between deep space telecom modems
and landline modems digital modulation include:
 digital modulation formats that have high doppler immunity are typically
used
 waveform complexity tends to be low-typically binary phase shift keying
 error correction varies mission to mission, but is typically much stronger
than most landline modems

Logic Design Unit 9
Voice modem
The recording or playing audio over the telephone line can be done using a
voice modem and are used in telephony applications. This type of modem
can be used as FXO card for Private branch exchange systems.
9.3 Digital Multi-meter

Digital multi meter (DMM) or multitester is a measuring device which
combines multiple functions in one unit. It is also known as VOM (Volt-Ohm
meter). Generally the voltage, current and resistance measuring features
are included in the multimeter. The figure 9.1 shows the digital multimeter.
Figure 9.1: Digital multimeter
Analog multimeters and digital multimeters are the two categories of the
multimeters. Digital multimeters are abbreviated as DMM or DVOM.
A multimeter can be used to find the faults, field work service with high
accuracy and for troubleshooting of both household and industrial devices.
Quantities measured
Many of the following quantities can be measured using multimeters. The
common ones are:
 Voltage (both Alternating and Direct) in Volts.
 Current( both Alternating and Direct) in amperes
 Resistance in ohms

Logic Design Unit 9
 Capacitance in farads.
 Conductance in siemens.
 Decibels for audio signal levels
 Duty cycle as a percentage.
 Frequency in hertz.
 Inductance in henrys.
Digital multimeters may also include circuits for:
 Continuity that beeps when a circuit conducts.
 Diodes and Transistors
Various sensors can be attached to multimeters to take measurements such
as:
 light level
 Acidity/Alkalinity(pH)
 Wind speed
 Relative humidity
Resolution
The resolution of a multimeter is the smallest part of the scale which can be
shown and is a scale dependent.
Digital
The resolution of a multimeter is often specified in the number of decimal
digits resolved and displayed. For example, the term 5½ digit refers to the
number of digits displayed on the readout of a multimeter.
A number greater than 1 and less than 9 can be displayed using 3 quarters
digit and only zero or one can be displayed by a half digit. Maximum value
of 3 or 5 can be referred to a three quarters digit. The most significant digit
in the display is always the fractional digit. In a 5½ digit multimeter values
from 0 to 9 can be represented using 5 full digits, and only zero or one can
be displayed using half digit. Thus a 5½ digit multimeter can have range
from 0 to 199999 to show the positive or negative values. Depending the
manufacturing company, values from 0 to 3999 or 5999 can be displayed
using a 3¾ digit meter. If the analog portion of the multimeter is not
designed with proper care and calibration, the extra digits which are used to
extend the precision will not have any value. A good traceability of the
calibration, good controllability of the measurement conditions, and goof

Logic Design Unit 9
understanding of the specification of the instruments are required for high

resolution measurements.
The resolution can be also specified using another way called “display
counts”. The largest number that can be displayed by multimeter can be
determined from the display counts and these display counts ignore the
decimal separator. For example, a 5½ digit multimeter can also be specified
as a 199999 display count or 200000 display count multimeter. In
multimeter specification the display count is just referred as count.
Analog
The width of the scale pointer, accuracy of scales, zero calibration, no of
ranges, pointer vibration and errors because of non-horizontal usage of
display limits the analog multiplier’s resolution. Accuracy of readings
obtained is also often compromised by miscounting division markings,
errors in mental arithmetic, parallax observation errors, and less than
perfect eyesight. In order to improve the resolution, a large meter
movements and mirrored scales are used; the resolution of two and half to 3
digits is sufficient.
The resistance measurement circuit compress the scale at higher
resistances, because of this of the precision of the circuit is low.
Accuracy
The accuracy of the digital multimeters is better when compared to the
analog meters. The accuracy of the digital multimeters is 0.5% on current
scales and DC voltage; whereas the analog meters have accuracy of
3 to 5%.The accuracy up to ±0.01% can be achieved by using mainstream
bench top multimeters. The accuracy of Laboratory grade instruments will
be in parts of million.
Sensitivity and input impedance
The accuracy of the mutlimeter can be affected by testing the current load.
Precise measurements are required to calculate the small current drawn. A
multimeter can get damaged with too much of current load or with improper
usage of device.
The digital and analog meters, which performs the amplification using
transistor, has high input impedance so that it will not disturb the most
circuits. The input impedance will be in order of million or ten million ohms.

Logic Design Unit 9
The range of direct current measurement can be done up to tens of

thousands of volts by using the standard input impedance.
The analog meters are said to be unbuffered if they are of moving pointer
type and in order to deflect the meter it will draw the current circuit which is
being tested. Depending upon the selected range of the meter and its
sensitivity, the impedance of the meter varies. The impedance will be
2,000,000 ohms for the meter whose sensitivity is 20,000 ohm/volt. In
testing of power circuits (where meter impedance > source impedance) – a
low sensitivity meters are used. The meter impedance should not be load in
measuring the signal circuits which requires high sensitivity.
Occasionally resolution of the meter confused with the sensitivity of the
meter. The general purpose meters should have a 100 millivolts AC or DC
in the full scale range, but the meter should have 100 milliamps in current’s
full scale range. The accuracy of measurements below few tens of ohms by
the general purpose meters will be low because, these meters have a two
wire resistance measurements and the effect of the lead wire resistance is
not compensated. Depending upon the manufacturers the upper end of
measurement range varies; a specialized test instrument is required for
measurements ove 10 amps, 100 megaohms or 1000 volts.
Alternating current sensing
In order to measure alternating current, an AC to DC converter is included in
the multimeter. To calculate the average value of the sine wave, a rectifier
circuit can be included in the meter and can be calibrated to evaluate the
value. In order to determine the correct RMS value for average responding
meter, correction factors for simple waveforms will be given in meter’s user
guide. To calculate the RMS values of a waveform, few meters include an
AC to DC conversion circuit, but these meters will be expensive. For non-
sinusoidal quantities like audio signals, the measurement of RMS sensing is
required.
Digital Multimeters (DMM or DVOM)
Many features are provided in the digital meters with inclusion of wide
variety of solid state electronics. Commonly available measurement
enhancements include:
 Auto-ranging, which selects the correct range for the quantity under test
so that the most significant digits are shown. For example, a four-digit

Logic Design Unit 9
multimeter would automatically select an appropriate range to display

1.234 instead of 0.012, or overloading. Auto-ranging meters usually
include a facility to 'freeze' the meter to a particular range, because a
measurement that causes frequent range changes is distracting to the
user.
 Auto-polarity for direct-current readings, shows if the applied voltage is
positive (agrees with meter lead labels) or negative (opposite polarity to
meter leads).
 Sample and hold, which will latch the most recent reading for
examination after the instrument is removed from the circuit under test.
 Current-limited tests for voltage drop across semiconductor junctions.
While not a replacement for a transistor tester, this facilitates testing
diodes and a variety of transistor types.
 A graphic representation of the quantity under test, as a bar graph. This
makes go/no-go testing easy, and also allows spotting of fast-moving
trends.
 A low-bandwidth oscilloscope.
 Automotive circuit testers, including tests for automotive timing and
dwell signals.
 Simple data acquisition features to record maximum and minimum
readings over a given period, or to take a number of samples at fixed
intervals.
 A miniature digital multimeter integrated with tweezers for surface-mount
technology.
By using RS232 cables, or by IrDA links or USB or an instrument bus, a
personal computer can be connected to the modern meters. Thus the
recording of the measurements can be done using personal computers.
Few digital multimeters can first store the measurements when are made
and later upload them to a computer. In 1955, Non Linear systems
manufactured the first DMM.
Analog Multimeters
Even though the analog multimeters are used commonly, the cost of a
quality analog instrument will be same as that of DMM. The analog
multimeters cannot have the same accuracy as that of DMM because of the
Logic Design Unit 9
limitations on precision and reading accuracy. The figure 9.2 shows the
analog multimeter with galvanometer needle display.
Figure 9.2: Analog multimeter with galvanometer needle display.
Sometimes for better detection of rate of change of a reading, an analog

meter can be used; fast responding bar graph display is used in few DMM’s
to detect the rate of change of reading. When compared to DMM the analog
multimeters are less susceptible to radio frequency interference.
The basic part of analog meter is called a meter movement. The meter
movement in a moving pointer analog multimeter is practically always a
moving-coil galvanometer of the d'Arsonval type, using either jeweled pivots
or taut bands to support the moving coil. Generally the analog multimeters
draw the current from the circuit being measured in order to deflect the
pointer and the coil; reducing the current drawn from the circuit being tested
will be an advantage. The unit for sensitivity of an analog meter is ohms/v.
The sensitivity the inexpensive analog meter at full scale measure voltage
can be 100ohms/v, which can draw 1mA from a circuit. The sensitivity of the
expensive analog meter at full scale measure voltage can be 20,000 ohms/v

Logic Design Unit 9
or more, and the upper limit for general purpose, portable and non-amplified
meters is 50,000 ohms/v.
An amplifier is inserted between the meter movement and the measuring
circuit in order to minimize the current drawn for meter movement and avoid
loading on the circuit. But the adding of an amplifier increased the
complexity and cost of the meter and power supply which is required by the
amplifier., Independent of the current required to meter movement, the input
resistance can be made high by using vaccum tubes and Field Effect
Transistors. Such amplified multimeters are called VTVM (vacuum tube
voltmeters) TVM (transistor volt meter), FET-VOM, and similar names.
Probes
In order to connect the circuit to a multimeter, different kinds of probes can
be used. The most 3 commons probes used are pointed probes, crocodile
clips, and retractable hook clips. The connectors are attached to flexible,
thickly-insulated leads that are terminated with connectors appropriate for
the meter. Shrouded or recessed banana jacks are used for handheld
multimeters, but BNC connectors or banana jacks can be used for benchtop
meters. Occasionally binding posts and 2mm plugs are also used.
For accuracy and for safety, non-contact attachment mechanism is used in
meter which measures high currents or high voltages. To determine the
current flowing through the conductor, a coil that clamps around it is
provided by the clamp multimeters.
Safety
In order to prevent the damage to the multimeter when it is overloaded, a
fuse is provided by few multimeters. But fuses usually protect only high
current range on the meter. During the operations, setting the meter to
measure the current or resistance and then connecting to a voltage source
which has low impedance would damage the meter and sometimes it can
explode the device.
Depending upon the intended application of the digital meters DMM are
categorized into 4 types:
 Category I: used where current levels are low.
 Category II: used on residential branch circuits.

Logic Design Unit 9
 Category III: used on permanently installed loads such as distribution

panels, motors, and appliance outlets.
 Category IV: used on locations where current levels are high, such as
service entrances, main panels, and house meters.
For selected measuring range in the DMM, maximum transient voltages are
also specified for each category. Protection from over current faults is
provided by the category based meters.
9.4 Digital Versatile Disks

Digital versatile disk (DVD) is a digital optical disc storage format, invented
and developed by Philips, Sony, Toshiba, and Panasonic in 1995. Most
DVDs are of the same dimensions as compact discs (CDs) but store more
than six times as much data.
The figure 9.3 shows the typical DVD.
Figure 9.3: DVD- read/write side
DVD was never defined in the original DVD specification. Now-a-days the
most common usages are “DVD”, “Digital Versatile Disc”, and “Digital Video
Disc”. A DVD can store video’s, audio and other data and access all on one
disc. Variations of the term DVD often describe the way data is stored on
the discs: For example in DVD-ROM, data can only be read and not written,
DVD-R and DVD+R can only record data once and then function as a
DVD-ROM. DVD-RW, DVD+RW and DVD-RAM can both record and erase
data multiple times. The wavelength used by standard DVD lasers is
650 nm, and thus has a red color. The types of DVD are referred by its

Logic Design Unit 9
storage capacity. The table 9.1 shows the capacity of DVD along with
nomenclature.
Table 9.1: Capacity of DVD and nomenclature
Designation Sides Layers (total) Diameter Capacity
(cm) (GB) (GiB)
DVD-1 SS SL 1 1 8 1.46 1.36
DVD-2 SS DL 1 2 8 2.66 2.47
DVD-3 DS SL 2 2 8 2.92 2.72
DVD-4 DS DL 2 4 8 5.32 4.95
DVD-5 SS SL 1 1 12 4.70 4.37
DVD-9 SS DL 1 2 12 8.54 7.95
DVD-10 DS SL 2 2 12 9.40 8.74
DVD-14DS DL/SL 2 3 12 13.24 12.32
DVD-18DS DL 2 4 12 17.08 15.90
SS = single-sided, DS = double-sided, SL = single-layer, DL = dual-layer
Standard DVD is of 12cm and mini DVD is of 8cm. These are the same
sizes as a standard CD and a mini-CD, respectively. The capacity by
surface (MiB/cm²) differs from 6.92MiB/cm² in the DVD-1 to 18.0 MiB/cm² in
the DVD-18.
Note: The capacity of DVD is represented by symbol GB (gigabyte). In
order to show the distinction, Kilobyte, Megabyte and Gigabyte are the
labels used to represent the files sizes in present day computers.
Among 2418 bytes of data that is contained in a sector of DVD, the user
data will be 2048 bytes. There is a small difference in storage space
between ‘+’ and ‘-’ formats. Capacity differences of writable DVD formats is
shown in table 9.2.
Table 9.2: Capacity differences of writable DVD formats

Type Sectors Bytes GB GiB
DVD−R SL 2,298,496 4,707,319,808 4.71 4.384
DVD+R SL 2,295,104 4,700,372,992 4.70 4.378
DVD−R DL 4,171,712 8,543,666,176 8.54 7.957
DVD+R DL 4,173,824 8,547,991,552 8.55 7.961

Logic Design Unit 9
Technology
Internal mechanism of a DVD-ROM Drive.
CD’s uses 780nm wavelength laser diode light, HD-DVD uses 405nm
wavelength laser diode light and DVD uses 650nm wavelength laser diode
light. As DVD uses lesser wavelength laser diode light than CD, on the
media surface it is possible to etch a smaller pit.
The writing speed of the first media and the drive model was 1x (1318
KiBps) and the recent models have the speed of 18x or 20x. The writing
speed of CD is 1x (153.6 KiBps) and it is 9 times slower than DVD.
DVD drive speeds
Drive speed Data rate ~Write time (min)
(Mibit/s) (MB/s) SL DL
1× 10.55 1.35 61 107
2× 21.09 2.70 30 54
2.6× 27.43 3.51 24 42
4× 42.19 5.40 15 27
6× 63.30 8.10 11 18
8× 84.38 10.80 8 14
12× 126.60 16.20 6 11
16× 168.75 21.60 4 7
18× 189.90 24.30 3 5
20× 211.00 27.00 3 4
DVD recordable and rewritable

In order to store the information for transport and back up, a recordable
DVD was developed by HP.
For the purpose of video and audio recording, the recordable DVD’s are
used. DVD-RAM, DVD-R/RW (minus), and DVD+R/RW (plus) are the three
formats for recording purpose.
Dual layer recording
Storing of more data in DVD-R and DVD+R disc can be done by using dual
layer recording. With this method data up to 8.5 GB per side can be stored
on a disc. But with single layer recording, only 4.7GB of data can be stored.
Pioneer Corporation developed DVD-R DL for DVD forum, Philips and
Logic Design Unit 9
Mitsubishi Kagaku Media (MKM) developed DVD+R DL for DVD+RW

Alliance.
When compared to the usual DVD a dual layer disc has a second physical
layer in it. By shining the laser though the first semitransparent layer second
layer can be accessed by the drive. The noticeable pause in DVD players
indicate the change of layer in the disc, some DVD players will pause for
several seconds. Because of this effect, viewers were worried that their
discs are defective or damaged., as a result on dual layer packed discs the
messages were listed explaining the pausing effect due to layer change
DVD recordable discs supporting this technology are backward compatible
with some existing DVD players and DVD-ROM drives. Now a day the dual
layer technology is supported by the modern DVD, and even though the
empty disc is expensive, the cost of both single layer drives and dual layer
drives are comparable. But dual layer drive recording speed is well below
the recording speed of single layer drive.
For dual layer orientation, Parallel track path (PTP) and outer track path
(OTP) are the two modes. With PTP, inside diameter (ID) will be beginning
point for both layers and with lead out at outer diameter (OD) both layers
end. With OTP, at ID lower layer begins and at OD the upper layer begins,
the lead in and lead out are shared at the point where the other layer ends.
DVD-Video
IDVD-Video is a standard for storing and distributing video/audio content on
DVD media. In 1997, the sale of DVD players and videos was started in
U.S. Now a day for worldwide distribution of home video, DVD video is used
as dominant form. Either 16:9 aspect ratio MPEG 2 video or 4:3 aspect ratio
is used in many DVD-video discs, which are stored at 720x576 (PAL) or
720x480 (NTSC) at 25 FPS or 29.97 FPS. Audio is commonly stored using
the Dolby Digital (AC-3) or Digital Theater System (DTS) formats, ranging
from 16-bits/48 kHz to 24-bits/96 kHz format with monaural to 7.1 channel
"Surround Sound" presentation, and/or MPEG-1 Layer 2. Almost all possible
formats are supported by the current DVD players even though there audio
and video requirement specification changes from region to region. Different
features like multiple camera angles, and audio tracks, different subtitles
which can be selectable and menus are supported by the DVD video.

Logic Design Unit 9
DVD-Audio
In order to deliver high quality audio content, DVD audio format is used. At
various frequencies (up to 192 kHz), many channel configuration options
are offered. Higher audio quality and more music can be included in the
higher capacity DVD audio when compared with CD.
Despite DVD-Audio's superior technical specifications, there is debate as to
whether the resulting audio enhancements are distinguishable in typical
listening environments. DVD-Audio currently forms a niche market, probably
due to the very sort of format war with rival standard SACD that DVD-Video
avoided.
Security
DVD-Audio discs employ a copy prevention mechanism, called Content
Protection for Prerecorded Media (CPPM) developed by the 4C group (IBM,
Intel, Matsushita, and Toshiba).
To date, CPPM has not been "broken" in the sense that DVD-Video's CSS
has been broken, but ways to circumvent it have been developed. By
modifying commercial DVD(-Audio) playback software to write the decrypted
and decoded audio streams to the hard disk, users can, essentially, extract
content from DVD-Audio discs much in the same way they can from DVD-
Video discs.
1. ___________was introduced in 1960 to replace the term digital subset.
2. _________________ is a device which modulates an analog carrier
signal for encoding digital information and performs the function of
demodulating such a carrier signal to decipher the digital information
encoded in it.
3. POTS stands for________________________.
4. The WiFi and WiMax standards use wireless mobile broadband
modems operating at __________________frequencies.
5. ADSL stands for ________________________.
6. ________________is a measuring device which combines multiple
functions in one unit.
7. The resolution of a multimeter is often specified in the number of
decimal digits resolved and displayed (True or False).
8. The unit for sensitivity of an analog meter is_______________.

Logic Design Unit 9
9. The meter movement in a moving pointer digital multimeter is always a

moving-coil galvanometer of the d'Arsonval type (True or False?).
10. A _______________can store video’s, audio and other data and access
all on one disc.
11. __________________is a standard for storing and distributing
video/audio content on DVD media.
12. CPPM stands for ___________________________________.
9.5 Summary
 Modem which stands for modulator-demodulator. It is a device which
modulates an analog carrier signal for encoding digital information.
 Cable modems and Asymmetric digital subscriber line (ADSL) modems
are some faster modems used by internet users daily.
 Softmodem or winmodem is a stripped-down modem that takes up
most of the tasks in to software, which was traditionally performed in
hardware.
 In order to send the data using 300bps modems, frequency shift keying
is used.
 Modern telecommunications and data networks also make extensive
use of radio modems where long distance data links are required.
 Digital cable television and cable Internet services use radio frequency
modems to provide the increasing bandwidth needs of modern
households.
 Mobile modems are the modems which use mobile phone lines like
GPRS, UMTS, EVDO, etc.
 Digital multi meter (DMM) or multitester is a measuring device which
combines multiple functions in one unit. It is also known as VOM (Volt-
Ohm meter).
 The resolution of a multimeter is the smallest part of the scale which
can be shown and is a scale dependent.
 When compared to DMM the analog multimeters are less susceptible to
radio frequency interference.

Logic Design Unit 9
 A DVD can store video’s, audio and other data and access all on one
disc.
 The recordable DVD’s are used for the purpose of video and audio
recording.
 DVD-RAM, DVD-R/RW (minus), and DVD+R/RW (plus) are the three
formats for recording purpose.

1. Explain the working of MODEM.
2. Write a note on smartmodem.
3. Explain the functioning of Digital Multi-meter.
4. Write a short note on Digital Versatile Disk.
9.7 Answers
1. Data-phone
2. MODEM
3. Plain Old Telephone Systems
4. Microwave
5. Asymmetric digital subscriber line
6. Digital multi meter (DMM)
7. True
8. Ohms/v
9. False
10. DVD
11. IDVD-Video
12. Content Protection for Prerecorded Media
Terminal Questions

Logic Design Unit 10
Unit 10 Data Converter: DAC/ADC
Structure:
10.1 Introduction
Objectives
10.2 Working Principle & Circuits of Analog to Digital Converters
10.3 Digital to Analog Converters
10.4 Summary
10.6 Answers
10.1 Introduction
In the previous unit, we studied about the MODEM, digital multimeter and
digital versatile disks. An electronic circuit that transforms a continuous
analog signal into digital samples is termed an analog-to-digital converter
(ADC). The other-way conversion is done by the circuit named digital-to-
analog converter (DAC). An ADC takes in analog continuous signal and
converts it into corresponding digital signal. DAC’s convert digital sampled
values to a continuous physical entity, mostly an analogue voltage. In this
unit we will study about the working principles of analog-to-digital converter
and digital-to-analog converter.
Objectives:
 explain the working principle of ADCs.
 explain the working of DACs
 define monotonicity and resolution of DAC
10.2 Working Principle & Circuits of Analog to Digital Converters

An analog-to-digital converter is a device that converts a continuous
physical quantity (usually voltage) to a digital number that represents the
quantity's amplitude.
The analog-to-digital conversion involves quantization of the input, so it
introduces a small amount of error. Instead of doing a single conversion, an
ADC often performs the conversions ("samples" the input) periodically. The
result obtained is a sequence of digital values (i.e. digital signal) which is
discrete both in time and amplitude.

Now let us study some important concepts.
Resolution
The resolution of the converter is the number of discrete values it can
produce over the range of analog values. In other words, the count of
samples that the circuit can generate over a range of analog values is
indicated by the measure called resolution. The sampled values are usually
shown in bits as it is stored in binary format electronically. The count of the
samples available is normally a power of two. For example, an 8-bit
resolution ADC can sample an input signal into 28 = 256 distinct levels. The
values can represent the ranges from 0 to 255.
Resolution is often specified electrically and represented in volts. In this
term, resolution can be defined as voltage range divided by the count of
distinct intervals as mentioned in the formula below:
E FSR E FSR
Q 
M N
2
Where,
Q stands for resolution (volts per output code or step)
EFSR is the reference voltage range, which is equal to VRefHi – VrefLo and M is
the resolution of the circuit in bits.
Count of the distinct intervals is depended number of levels available, which
is N = 2M.
Examples below illustrates better:
Example 1:
Reference voltage measurement range = 0 to 5 volts
Resolution of the ADC: 10 bits (Quantization levels: 210 = 1024)
Voltage resolution of the ADC is: (5v - 0v)/1024 levels = 5/1024 = 0.00488
volts /code or 4.88mV/code.
Example 2:
Reference voltage measurement range = -5 to 5 volts
Resolution of the ADC: 12 bits (Quantization levels: 212 = 4096)
Voltage resolution of the ADC is: (5v – (-5v))/4096 levels = 10/4096 =
0.00244 volts /code or 2.44mV/code
Example 3:
Reference voltage measurement range = 0 to 8 volts
Resolution of the ADC: 3 bits (Quantization levels: 23= 8)
Voltage resolution of the ADC is: (8v – 0v))/8 levels = 8/8 = 1 volts /code or
1000mV/code.
In practice, the smallest output code ("0" in an unsigned system) represents
a voltage range which is 0.5X (half-wide) of the ADC voltage resolution (Q)
and the largest output code represents a voltage range which is 1.5X (50%
wider) of the ADC voltage resolution. The other N-2 codes are all equal in
width and represent the ADC voltage resolution (Q) calculated above. Doing
this centers the code on an input voltage that represents the Mth division of
the input voltage range. For example, with the 3-bit ADC for an 8V range,
each of the N divisions represent 1V, except the 1st ("0" code) which is 0.5V
wide, and the last ("7" code) which is 1.5V wide. Doing this the "1" code
spans a voltage range from 0.5 to 1.5V, the "2" code spans a voltage range
from 1.5 to 2.5V, etc. Thus, if the input signal is at 3/8ths of the full-scale
voltage, then the ADC outputs the "3" code, and will do so as long as the
voltage stays within the range of 2.5/8ths and 3.5/8ths. This is called "Mid-
Tread" operation. This type of ADC can be modeled mathematically as:
The exception to this convention seems to be the Microchip PIC processor,

where all M steps are equal width. This practice is called "Mid-Rise with
Offset" operation. Since signal-to-noise ratio determines resolution of ADC,
If there is too much noise present in the analog input, it will be impossible to
accurately resolve beyond a certain number of bits of resolution, the
"effective number of bits" (ENOB). In case a preamplifier is used before
ADC, the noise injected by the amplifier plays a major role in overall signal-
to-noise ratio. Hence the result produced by ADC will be inaccurate as the
lower bits will simple be measuring noise. Advised signal-to-noise ratio is
around 6dB per bit of resolution required.

Response type:
Linear Analog-to-Digital converters
Even though analog-to-digital conversion process is a non-linear process,
majority of the conversion circuits are known as of the type linear. The
reason why the processor is non-linear is because sampling and mapping of
continuous space into discrete digital space is a piecewise operation. Linear
as used here to refer the type of the ADC, stands for the linear relationship
between the output values to the corresponding input value. In other words,
an output value p is supposed to be from a range of input values:
n(p+b) to n(p+1+b),
where, n and b are constants. Here b is typically 0 or −0.5. When b = 0, the
ADC is referred to as mid-rise, and when b = −0.5 it is referred to as mid-
tread
Non-linear Analog-to-Digital Converters
Signal-to-noise ratio with respect to quantization noise takes the best value
in case the probability density function (PDF) of a signal is uniform. Hence,
normally, the signal is made to pass through the cumulative distribution
function (CDF) of it before quantization. As a result, regions which are more
relevant get better resolution quantization. An inverse CDF will be required
in the dequantisation process. This concept is the same that is employed in
companders used in communication systems and tape recorders and is
related to maximization of entropy.
For example, a voice signal having Laplacian distribution denotes that the
region around 0 carries more information than the regions with higher
amplitudes. Because of the same reason, voice communication systems
widely uses logarithmic ADCs to boost the dynamic range of value that can
be represented by keeping the fine-fidelity in the regions with low amplitude.
An 8 bit a-law or the μ-law logarithmic ADC covers the wide dynamic range
and has a high resolution in the critical low-amplitude region that would
otherwise require a 12-bit linear ADC.
Accuracy
ADC’s are vulnerable to various kinds of errors. Quantization error and non-
linearity comes with very nature of any ADC. Clock jitter causing errors
called aperture error comes in light when digitizing a signal. The unit called

least significant bit (LSB) used to measure these errors. In a 10-bit ADC,
one LSB error is 1/1024 of the full reference signal range, which is about
0.097%.
Quantization error
Quantization error is due to the finite resolution of the ADC, and is an
unavoidable imperfection in all types of ADC. Quantization error ranges
from 0 to half of one LSB. Generally, actual signal is larger than one LSB.
During this, quantization error is not correlated and has a consistent
distribution. Standard deviation of the distribution gives the RMS value as
mentioned below:
For the 10-bit ADC discussed above, this represents 0.0282% of the signal.
Quantization error becomes more dependent on the input signal in lower
levels causing disturbances. This distortion is created after the anti-aliasing
filter, and if these distortions are above 1/2 the sample rate they will alias
back into the audio band. A noise with an amplitude 1 quantization step is
included to the signal in order to make the quantization error independent of
the input signal. This reduces signal-to-noise ratio slightly and eliminates the
distortion completely. It is also known as Dither.
Non-linearity
Physical implementation imperfections cause all the ADCs to suffer from
non-linearity errors resulting in deviation of the output from the linear
relationship (or whatever relationship in case of non-linear type) with the
corresponding input. Alleviation and prevention of these errors can be done
by calibration and testing. Integral non-linearity (INL) and differential non-
linearity (DNL) are important arguments for linearity.
Imagine that we are digitizing a sine wave x(t) = Asin2πf0t. Provided that the
actual sampling time uncertainty due to the clock jitter is Δt, the error
caused by this phenomenon can be estimated as
One can see that the error is relatively small at low frequencies, but can
become significant at high frequencies. This effect can be ignored if it is

relatively small as compared with quantizing error. Jitter requirements can

be calculated using the following formula:
Where q is a number of ADC bits.

Sampling rate
ADC has to convert the analog signal which is continuous in time into a flow
of digital values. Hence the sampling rate of the analog signal plays a major
role. Sampling rate or sampling frequency is the rate at which new digital
values are sampled from the analog signal. The rate of new values is called
the sampling rate or sampling frequency of the converter. If the sampling
rate is higher than double the maximum frequency of the signal, a reliable
faithful reproduction is possible which is based on Shannon-Nyquist
sampling theorem.
Due to finite amount of delay that an ADC takes in converting a signal, the
input is expected to remain constant over the time of conversion (termed
conversion time). So, a sample and hold circuit performs this function –
essentially, using a switch to connect the analog input signal to the
capacitor where it is stored. Sample and hold sub-module is incorporated in
almost all ADC integrated circuits.
Aliasing
Sampling input signals at regular intervals of time, is the way ADCs work.
So, the output of an ADC can be pictured as an abstract representation of
the input behavior. No information about the input signal between the two
sampling instants is available. This depends on the input signal
characteristic, i.e. if the input signal is a slowly changing one with respect to
the sampling rate, then the value between the two sampling points could be
almost the same as either of them. However, if the input change is faster
compared to sampling rate, then the assumption no longer holds valid.
Output produced by the ADC is always expected to be well enough to be
reconstructed back to the original input analog signals, if at all in some later
stage it is made to undergo a digital to analog conversion. But, as discussed
above, if the rate of change of input analog signals is much faster than the
sampling rate, exact regeneration fails and unauthentic signals termed

aliases are produced at the output analog signal of a DAC. In this case,
frequency of the output analog signal (aliased signal) will be difference
between the input signal frequency and the sampling frequency. For
example, a 5kHz sine wave sampled at 4kHz may be reconstructed as 1kHz
sine wave. This is what is known as aliasing.
Aliasing is better resolved by making the input signal low pass filtered
before passing it into the ADC so that the high frequency components
above half of the sampling rate are filtered out. Because of this functionality,
the filter is called anti-aliasing filter. This is an essential component for a real
time ADC especially the ones that work on high frequency signals.
Aliasing, an undesired phenomenon in most of the systems may be used to
provide down-mixing of a band limited high frequency signal.
Oversampling
As the quantization introduces white noise which is spread all over the pass
band of the converter, signals are sampled at the minimum required rate. If
the input signal is sampled at frequency higher than the Nyquist frequency
and then filtered to limit it to the bandwidth of the signal, three main
advantages results:
 Digital filters can have better properties like sharper roll off, phase etc.
than analogue filters, so a sharper anti-aliasing filter can be implemented
and the signal can be down sampled to give a better result
 A 20-bit ADC can be made to act as a 24bit ADC with 256x oversampling
 The signal-to-noise ratio due to quantization noise will be higher than if
the whole available band had been used. So effective resolution larger
than what is provided by ADC can be achieved with this technique.
Dither
You can increase the ADCs, performance by using dither. This is a very
small amount of random noise (white noise), which is added to the input
before conversion. Amplitude of the noise is set to be about half of the LSB.
This mainly cause oscillating the state of LSB to switch between 0 and 1 in
case of very low levels of input, rather than sticking at one constant value. It
improves the effective range of signals that the ADC can convert rather than
signal getting cut off at the low level with the trade-off of slight increase in
noise – essentially, quantization error is included in across a series of noise

values which far more bearable than a cutoff. More accurate representation
of the signal over time is possible with this. A filter at the output tuned
properly can recover the small variations caused.
Without dither, a sampled audio signal of low level becomes unpleasant and
disturbed. Low level always yields a ’1’ from the analog to digital if done
without dithering. With dithering, the true level of the audio may be
calculated by averaging the actual quantized sample with a series of other
samples that are recorded over time. A process similar to dithering is often
employed in photographic image quantization to a lesser number of bits per
pixel. Even though the image becomes noisier, eye fails in recognizing
those and hence sees the original realistic picture which is otherwise
banded. Similar effect is what is happening in case of analogue audio that is
converted to digital.
Integrating systems like electricity meters also makes use of dithering. Since
the values are added together, the dithering produces more reliable results
than the LSB of ADC.
Dither improves only the resolution of the sampler, it doesn’t affect linearity
and hence accuracy doesn’t seem to improve.
ADC structures
Most common ADC implementation ways are the following:
 Flash ADCs or Direct conversion ADCs has a bank of comparators each
firing for their decoded voltage range. A logic circuit follows this
comparator bank which generates a code for each voltage range created.
These converters are faster, but normally have only 8-bits resolution (i.e.
255 comparators as 2n-1 is the number of comparators required) or lesser
since it needs a big and expensive circuit. This type demands a large die
size, high input capacitance and are prone to have glitches in the output
(as outputting is out of sequence). As device mismatch is a dominant
design limitation, scaling to newer submicron technologies doesn’t do any
better. Direct conversion ADCs are mainly employed in applications like
video, wideband communications and other fast signals.
 Successive approximation ADCs makes use of comparators to eliminate
the ranges of voltages, gradually settling on a final voltage range.
Successive approximation continuously compares the input voltage to the

analog output voltage of the inbuilt DAC (working on the current value of
approximation) until the right approximation is obtained. In every single
step in the process, approximation is stored in a successive
approximation register (SAR) in binary format. A reference voltage is
used by the SAR for the comparison. For example, if the input voltage is
6V and the reference voltage is 10v, during the first cycle the comparison
of the input voltage is done with the value 5V, (i.e. the half the value of
the reference voltage: This is the voltage at the output of the inbuilt DAC
when the input is a ‘1’ followed by zeros) and the voltage output from the
comparator is positive as 6V is greater than 5V. The first binary digit is set
to ‘1’ at this point. In the next clock cycle, the input voltage is compared
with 7.5V (which is half value between 5V and 10V: This is the output of
the inbuilt DAC when its input is ‘11’ followed by zeros) and as 6V is
lesser than 7.5V, the comparator output becomes negative. Second
binary digit is therefore set to ‘0’. In the next clock cycle, input voltage is
compared with 6.25V (half value between 5V and 7.5V: This is the output
voltage of the inbuilt DAC when its input is ‘101’ followed by zeros). Now
the output of the comparator becomes negative as 6V is less than 6.25V
and the third bit is set to ‘0’.So on, next clock cycle comparison happens
with 5.625, and the fourth bit goes to ‘1’ as 6V is greater than 5.625.
Hence the result in the binary form would be 1001. This process is also
termed as bit-weighting conversion. This is kind of rounding an analog
signal into a binary form. As the approximations are not successive, each
bit resolution will require one clock cycle. Hence clock frequency will have
to be same as the value obtained by multiplying the number of bits of
resolution and sampling frequency. For example, to sample audio at 44.1
kHz with 32 bit resolution, a clock frequency of over 1.4 MHz would be
required. This type of ADC has better resolution and wide ranges. But it is
more complex than other implementations.
 Ramp-compare ADC which is also known as dual-slope or integrating or
multi-slope ADC produces a saw-tooth signal. A counter starts counting
as the ramp starts. When the ramping voltage matches with the input
voltage, comparator flags and the timer value is recorded. Timed ramp
converters demands least number of transistors. The ramp time is
sensitive to temperature because the circuit generating the ramp is often
just some simple oscillator. There are two solutions for this: using a

clocked counter for DAC and then a comparator to store the counter
value or improving the timed ramp. For the comparison of a second
signal, just another comparator is what is required and another register
to store the voltage value. This is one major advantage of the ramp-
compare system. Implementation of ramp-converter can be as simple as
a combination of a microcontroller, a resistor and a capacitor. A filled
capacitor can be taken from an integrator, time-amplitude converter,
sample and hold circuit or peak and hold circuit and discharged. As slow
comparator cannot be disturbed by fast input changed, this is the major
advantage of this system.
 Delta encoded ADC employs an up-down counter that feeds a DAC.
Both the input signal and the DAC go to the comparator and then it is
this comparator that controls the counter. This converter has a wide
ranges and high resolution. Conversion time often depends on the input
signal and hence it will have a guaranteed worst-case. This type of
converter is a good option to deal with real-world signals. Signals in
physical systems don’t change abruptly. Delta and successive
approximation properties are combined in some kind of converters and
can very well be employed when high frequencies are known to be small
in magnitude.
 Pipeline ADC make use of subranging in two or more steps. Primarily a
rough conversion is performed. Then the difference from the input signal
is determined using a DAC. The difference obtained is used for finer
conversion and the results are combined at the end. This is a kind of
refined successive approximation ADC where, interim conversion of a
whole range of bits is contained in the feedback reference signal, rather
than next MSB. Due to the combined merit of both the converters, this
converter is faster, has got higher resolution and only requires a little die
size.
 Sigma delta ADC which is also termed as Delta-Sigma ADC samples
the input signal by a large factor and filters out only the required signal
band. A flash ADC is placed after the filter which is used to convert
smaller number of bits than that is actually required. The output signal
which contains the error generated by the Flash is fed back and
subtracted from the input. Due to the negative feedback, noise shaping
of the error due to Flash happens and hence it doesn’t appear in the
expected signal frequencies. A digital filter follows the ADC which

reduces the sampling rate, filters off unwanted noise signal and
increases the resolution of the output (sigma-delta modulation, also
called delta-sigma modulation).
Nonelectric ADCs usually use some scheme similar to one of the above.
Commercial analog-to-digital converters
ADCs are mainly integrated circuits. 6 – 24 bits of resolution is used by
many converters to sample and generate lesser than 1 mega sample per
second. Thermal noise generated by the passive components limit the
resolution to a maximum value of 24-bits. In room temperature and for
application like audio, this noise is normally less than 1 μV of noise. If the
Most Significant Bit corresponds to a standard 2 volts of output signal, this
translates to a noise-limited performance that is less than 20~21 bits, and
obviates the need for any dithering. Full speed analog video to digital
conversion in digital video cameras, TV tuner cards and video capture cards
are done with mega sample converters. Commercial converters usually
have ±0.5 to ±1.5 LSB error in their output.
Pins are the most expensive part of an integrated circuit, as the package
size depends on them and each pin has to be connected to the silicon chip.
In order to save pins, ADC’s are slowed down to send the transfer data
serially one bit at a time to the computer with the next bit coming out when a
clock signal state change happens from 0V to 5V. Hence quite a few pins
on the ADC package are reduced and mostly it doesn’t affect the complexity
of the design. An analog multiplexer is used to feed the same converter
from the ADCs that have several inputs. Sample and hold circuits,
instrumentation amplifiers or differential inputs are included in different
models of ADCs, where the quantity measured is the difference between
two voltages.
Applications
Application to music recording
Music reproduction technology uses ADCs extensively. Most of the present
music production happens in computer. And hence, the PCM data stream
that is sent to the disc is obtained by converting the analog recorded signal
using an ADC. Sample rates up to 192kilohertz can be achieved utilizing the
current crop of the ADCs. Due to Nyquist-Shannon sampling theorem, many

people consider this a capability and pure marketing hype. Typically,

recording techniques of high-fidelity is sampled at 44.1kHz for standard CD
or 48kHz for radio/TV broadcast and analog waveform is said to have
enough information in it to necessitate such high sampling rates. Cheaper or
faster anti-aliasing filters of less severe filtering slopes can be used because
of this kind of bandwidth headroom. Because of the gentler slopes of
shallower anti-aliasing, it produces less hampering effect on sound quality.
Few support on avoiding filter with ADC stating that aliasing cause lesser
trouble on sound perception than pre-conversion filter. Even though, there is
enough literature works on this matter, commercial considerations always
overrule. Most high-profile recording studios record in 24-bit/192-176.4 kHz
PCM or in DSD formats and then down sample or decimate the signal for
Red-Book CD production.
10.3 Digital to Analog Converters

A digital-to-analog converter (also known as DAC, D/A, D2A or D-to-A)
converts digital data (usually binary) into an analog signal (current, voltage,
or electric charge). DACs are commonly used in music players to convert
digital data streams into analog audio signals and in televisions and mobile
phones to convert digital video data into analog video signals which connect
to the screen drivers to display monochrome or color images. As per the
Nyquist–Shannon sampling theorem, a DAC can reconstruct the original
signal from the sampled data provided that its bandwidth meets certain
requirements (e.g., a baseband signal with bandwidth less than the Nyquist
frequency). Digital sampling introduces quantization error that manifests as
low-level noise added to the reconstructed signal.
Practical operation
Usually the sequences of numbers update the analog voltage at steady
sampling intervals instead of impulses. A clock signal is used a reference to
write the numbers in to the DAC. These numbers are latched in sequence
and during which the output voltage of the DAC changed rapidly from
previous value to the value corresponding to the currently latched number.
Resulting waveform as shown in figure 10.1 is a piecewise constant or
staircase shaped as the output voltage is held in time until the next input
number is latched. This affects the frequency response of the reconstructed
signal and is equivalent to a zero-order hold operation.

Figure 10.1 Piecewise constant output of an idealized DAC
The fact that DACs output a sequence of piecewise constant values (known
as zero-order hold) or rectangular pulses causes multiple harmonics above
the Nyquist frequency. So a low pass filter placed at the output removes this
and hence it acts as a reconstruction filter. This filter indicates that there is
an inbuilt effect of the zero-order hold over the overall frequency response
of the DAC causing mild roll-off of gain at the higher frequencies and
depending on the phase distortion and filter. High frequency roll-off is not
the property of the sampled data but the output characteristic of DAC.
Applications
Audio
Presently audio signals are stored in digital form and it has to be converted
to analog signal in order to hear it through speakers. Hence DAC’s are
employed in digital music player, PC sound cards and CD players.
The figure 10.2 shows the Top-loading CD player and external digital-to-
analog converter.
Figure 10.2: Top-loading CD player and external digital-to-analog converter.
High-end hi-fi systems make use of specialized stand-alone DAC’s as well.

The digital output of a CD player is taken in and converted to a line-level

output that can then be fed to the pre-amplifier to drive speakers. Such kind
of DACs can be found in USB speakers and in sound cards.
Video
Before a video signal that is stored in a digital storage such as computer is
to be displayed, it has to be converted back to analog form. Until the year
2007, analog inputs were more widely used than digital, but as flat panel
displays with DVI and HDMI port came up digital inputs started dominating.
Device called RAMDAC combines DAC with a memory (RAM) which stores
the conversion tables for contrast, brightness and gamma corrections.
Digitally controlled potentiometer which is used to digitally control an analog
signal is one device that is similar to DAC
DAC types
The most common types of electronic DACs are:
 Pulse Width Modulator is the simplest type of DAC. A stable current or
voltage is switched into a low-pass analog filter and duration is
determined by the digital input code. This is a commonly used technique
in speed control of electric motor and is now commonly used in high
fidelity audio applications.
 Oversampling DACs or Interpolating DACs such as the Delta-Sigma
DAC, use a technique termed pulse density conversion. Use of lower
resolution DAC is allowed because of the usage of the oversampling
technique. As the oversampled result is inherently linear, a simple 1-bit
DAC is often selected. In a technique named delta-sigma modulation,
DAC is driven with a pulse density modulated signal which is created
with step non-linearity, negative feedback loop and a low pass filter. In
effect, quantization noise gets high pass filtered and thus driving the
noise out of the low frequencies in to the high frequency which is of little
interest. This technique is called noise shaping. An analog low-pass
filter at the output removes the quantization noise at the high
frequencies. Due to high linearity and low cost, most of the very high
resolution DACs is of this type. Increased oversampling rate can reduce
the specification overhead on the low pass filter and support further
reduction of the quantization noise. Delta sigma DACs make resolution
of 24-bits and speed greater than 100 thousand samples per second is
achievable.

 Binary weighted DAC is constructed with one resistor and a current

source for bit of the DAC connected to a summing point. Correct output
value is the sum of these precise voltages and currents. This is one of
the fastest converters but this has got poor accuracy. This is because of
the high precision required for each individual voltage or current. This
type of converter is normally limited to 8-bit resolution or less as the
high-precision resistors and current sources are expensive.
 R-2R Ladder ADC is a binary weighted DAC in which resistors of values
R and 2R are repeatedly cascaded. Due to the easiness in producing
equal valued resistors (or current sources), precision is high for this kind
type of converters. But as RC-constants increases for each R-2R link,
converter performance is slow.
 The Successive-Approximation or Cyclic DAC successively
onstructs the output during each cycle. Note that individual bits of the
digital input are processed each cycle until the entire input is accounted
for.
 Thermometer coded DAC makes use of equal resistor or current
source segment for each of the values the DAC output can possibly
take. A 10-bit thermometer will have 1024 segments and a 5-bit
thermometer will have 32 segments. Even though it is costly, this may
be the fastest and highest precision DAC implementation.
 Hybrid DACs combines above techniques in a single implementation. In
order to achieve low cost, high speed and high precision in one device,
mostly DACs are implemented in this fashion.
o Segmented DAC combines binary weighted principle for the LSBs
and thermometer coded principle for MSBs. Hence, a compromise is
reached between the resister or current source count and precision.
DAC performance
DACs are very important for the system performance. The important
features of these devices are:
 Resolution: This is number of possible output levels the DAC is
designed to reproduce. It is represented as the base two logarithm of
the number of levels and is stated as the number of bits it uses. A 5-bit
DAC reproduce 32 levels whereas a 10 bit DAC is developed for 1024

levels. Actual resolution attained by the DAC is measured in terms of

Effective Number of Bits (ENOB).
 Maximum sampling frequency: This is maximum speed at which the
DACs operate and still produce the correct output. Shannon-Nyquist
sampling theorem says a signal must be samples at a frequency greater
than or equal to twice the highest frequency value of the signal. In order
to reproduce signals of frequency 30 kHz, DACs should operate at a
minimum of 60 kHz. Standard CD samples audio at 44.1 kHz (audio
frequency comes in the range of 20 kHz) and thus DACs of this
frequency are used.
 Monotonicity: This is the ability of the analog output of DAC to increase
with increase in digital code or vice versa. This feature is crucial for
DACs used as a low frequency signal source or as a digitally
programmable trim element.
 THD+N: This is the measure that projects the noise and distortions
introduced into the signal by the DAC. It is expressed as a percentage of
the noise and total power of undesired harmonics in the signal. This
feature plays a major role for dynamic and small signal applications.
 Dynamic range: This is a measurement of the difference between the
largest and smallest signals the DAC can reproduce and is expressed in
Decibels. This is usually related to DAC resolution and noise floor.
DAC figures of merit
DAC contains characteristics like
 Static performance:
o DNL (Differential Non-Linearity) shows how much two adjacent code
analog values deviate from the ideal 1LSB step.
o INL (Integral Non-Linearity) shows how much the DAC transfer
characteristic deviates from an ideal one. That is, the ideal
characteristic is usually a straight line; INL shows how much the
actual voltage at a given code value differs from that line, in LSBs
(1LSB steps).
o Gain
o Offset
o Noise is ultimately limited by the thermal noise generated by passive
components such as resistors. For audio applications and in room

temperatures, such noise is usually a little less than 1 μV (microVolt)

of white noise. This limits performance to less than 20~21 bits even
in 24-bit DACs, and cannot be corrected unless one resorts to
extremely low temperatures to create superconductivity: clearly an
impractical proposition.
 Frequency domain performance
o SFDR (Spurious Free Dynamic Range) indicates in dB the ratio
between the powers of the converted main signal and the greatest
undesired spur
o SNDR (Signal to Noise and Distortion Ratio) indicates in dB the ratio
between the powers of the converted main signal and the sum of the
noise and the generated harmonic spurs
o HDi (i-th Harmonic Distortion) indicates the power of the i-th
harmonic of the converted main signal
o THD (Total harmonic distortion) is the sum of the powers of all HDi
o If the maximum DNL error is less than 1 LSB, then a D/A converter
is guaranteed to be monotonic. However many monotonic
converters may have a maximum DNL greater than 1 LSB.
 Time domain performance
o Glitch Energy or Glitch impulse area
o Response Uncertainty
o TNL (Time Non-Linearity)

1. The errors which occur due to physical imperfections are known as
__________ errors.
2. _____________causing errors called aperture error comes in light
when digitizing a signal.
3. Delta encoded ADC employs an __________counter that feeds a DAC.
4. Use of lower resolution DAC is by usage of the oversampling technique
called _______________________.
5. The ___________ has poor accuracy and need high precision
resistors.
6. Actual resolution attained by the DAC is measured in terms of
________.

7. Noise is ultimately limited by the thermal noise generated by active

components such as diodes.(True or False ?).
8. SFDR stands for ______________________________________.
10.4 Summary
 An analog-to-digital converter is a device that converts a continuous
physical quantity (usually voltage) to a digital number that represents the
quantity's amplitude.
 The resolution of an ADC is the number of discrete values it can
produce over the range of analog values.
 Even though analog-to-digital conversion process is a non-linear
process, majority of the conversion circuits are known as of the type
linear.
 Due to finite amount of delay that an ADC takes in converting a signal,
the input is expected to remain constant over the time of conversion
 Aliasing, an undesired phenomenon in most of the systems may be
used to provide down-mixing of a band limited high frequency signal.
 Dither is a very small amount of random noise (white noise), which is
added to the input before conversion.
 Ramp-compare ADC which is also known as dual-slope or integrating or
multi-slope ADC produces a saw-tooth signal.
 A digital-to-analog convert converts digital data (usually binary) into an
analog signal (current, voltage, or electric charge).
 Oversampling DACs or Interpolating DACs such as the Delta-Sigma
DAC, use a technique termed pulse density conversion.
 R-2R Ladder ADC is a binary weighted DAC in which resisters of values
R and 2R are repeatedly cascaded.
 Resolution of a DAC is number of possible output levels the DAC is
designed to reproduce.
 Monotonicity is the ability of the analog output of DAC to increase with
increase in digital code or vice versa.


1. Explain the following as applied to ADC.
a) Resolution
b) Quantization error
c) Dither
2. Write a short note on DAC Types.
3. Explain the following as applied to DAC.
(i) Monotonicity
(ii) THD+N
(iii) Dynamic range
10.6 Answers
1. Nonlinearity
2. Clock jitter
3. Up-down
4. Pulse density conversion
5. Binary weighted DAC
6. ENOB
7. False
8. Spurious Free Dynamic Range
Terminal Question

References:
 Mano M. Morris. “Digital Logic and Computer Design”. PHI Private
Limited.
 Unger H Stephen. “The Essence of Logic Circuits” Second Edition, S.
Chand & Company.
 Roth Jr H. Charles. “Fundamentals of Logic Design. Fifth Edition,
Thomson India Edition,.
 Malvino and Leach. “Digital Principles and Applications”. Fifth Edition,
Tata McGraw-Hill.
____________________

Digital Logi

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Digital Logi

Uploaded by

Copyright:

Available Formats

Logic Design Unit 1

Unit 1 Number Systems

Manipal University Jaipur B0948 Page No. 1

carried similar to the normal day to day computation. Enormous numbers of

1.2 Decimal Number Systems

Manipal University Jaipur B0948 Page No. 2

This number is represented as

1.3 Binary Number Systems

Manipal University Jaipur B0948 Page No. 3

1.4 Octal Number Systems

1.5 Hexadecimal Number Systems

Manipal University Jaipur B0948 Page No. 4

Example 1.7: How to represent the Hexadecimal value “1A3F” in decimal

Manipal University Jaipur B0948 Page No. 5

Table 1.3: Little Endian Method

1.6 Negative Number Representation

Manipal University Jaipur B0948 Page No. 6

Table 1.4: Comparisons of Negative Number Systems

1.7 Conversion from one number system to other number

Manipal University Jaipur B0948 Page No. 7

Manipal University Jaipur B0948 Page No. 8

Manipal University Jaipur B0948 Page No. 9

Table 1.6: Comparison of decimal values with other number formats

Example 1.14: Convert 1A2C.3B4D16 into Binary Value.

1.8 Complements Arithmetic

Value 1 Value 2 Carry Sum

Table 1.8: Subtraction

Value 1 Value 2 Borrow Difference

Manipal University Jaipur B0948 Page No. 11

Number Excess Number Bit Pattern

Manipal University Jaipur B0948 Page No. 13

The excess notation representation however takes longer to compute than

3. The range of values represented by an 8-bit binary number is _____.

1.10 Terminal Questions

3. Convert the following hexadecimal numbers to base 10:

Manipal University Jaipur B0948 Page No. 16

Manipal University Jaipur B0948 Page No. 17

Unit 2 Boolean Algebra

Manipal University Jaipur B0948 Page No. 18

2.2 Rules & Laws of Boolean Algebra with Derivations

Manipal University Jaipur B0948 Page No. 19

a+1=1 Dominance Laws

a + bc = (a + b)(a + c) Distributive Laws

(ab)' = a' + b' DeMorgans Laws

a + (ab) = a Absorption Laws

a + a'b = a + b Redundancy Laws

ab + a'c + bc = ab + a'c Consensus Laws

Table 2.1: Distributive law

A proof of the absorption law x (x + y) = x using identities:

Manipal University Jaipur B0948 Page No. 21

Table 2.2: Boolean expression

From the above table of values, the function F is 1 when y = z = 1 and x = 0.

Manipal University Jaipur B0948 Page No. 22

Table 2.3: Duality

2.3 Basic Gates (NOT, AND & OR)

Manipal University Jaipur B0948 Page No. 23

 Closure. The Boolean system is said to be closed with respect to a

Manipal University Jaipur B0948 Page No. 25

Manipal University Jaipur B0948 Page No. 26

The table 2.7 shows the truth table for OR function.

Manipal University Jaipur B0948 Page No. 27

Table 2.9: Truth Table for a Function with Four Variables

Manipal University Jaipur B0948 Page No. 28

Manipal University Jaipur B0948 Page No. 29