COUNTER_4_BIT_AT_4HZ_SPEED (FROM 100MHZ SPEED)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter_4_bit is

Port ( clk : in STD_LOGIC;

clock1 : inout STD_LOGIC;

reset : in STD_LOGIC;

dir : in STD_LOGIC;

count : out STD_LOGIC_VECTOR (3 downto 0));

end counter_4_bit;

architecture Behavioral of counter_4_bit is

component clock_div is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

clout : inout STD_LOGIC);

end component;

signal count_int:std_logic_vector (3 downto 0);

begin

clk1: clock_div port map(clk,reset,clock1);

process (clock1,reset)

begin

if(reset='1') then

count_int<="0000";
elsif clock1='1' and clock1'event then

if dir='1' then

count_int <= count_int + 1;

else

count_int <= count_int - 1;

end if;

end if;

end process;

count<=count_int;

end Behavioral;

4HZ_SPEED (FROM 100MHZ SPEED)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock_div is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

clout : inout STD_LOGIC);

end clock_div;

architecture Behavioral of clock_div is

signal count:integer;

begin
process(reset,clk)

begin

if reset='1' then

count<=0;

clout<='0';

elsif clk='1' and clk'event then

count<=count + 1;

if count=50000000 then

clout<=not clout;

count<=0;

end if;

end if;

end process;

end Behavioral;