Digital Electronics & Logic Design

(EC 104)

Dr. Vivek Garg

Department of Electronics Engineering
S. V. National Institute of Technology (SVNIT)
Surat

email: vivekg@eced.svnit.ac.in; vivekgarg0101@gmail.com

 Course Outline

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 Course Outline

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 Course Text and Materials

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 Digital Logic Circuits
Shift Registers

• An array of flip flop is used to store a group of bits.

• To store n bits, n flip flops are cascaded.
• Types: 1. Based on input and outputs
Serial In Serial Out
Serial in Parallel Out
Parallel in Serial Out
Parallel in Parallel Out
2. Based on application
Shift Register
Storage Register

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Serial In Serial Out

• For n bit storage n clock pulse is required.

• It provides n clock pulse delay
• To get n bit serial out, n-1 clock pulses are required.

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Serial In Serial Out

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Serial In Serial Out

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Serial In Serial Out

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Serial In Parallel Out

• For n bit storage n clock pulse is required.

• For Parallel output, it requires 0 clock pulses.
• It is used as serial to parallel convertor

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Serial In Parallel Out

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Parallel In Parallel Out

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Parallel In Serial Out

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Parallel/Serial Input and Serial Output

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Bi-Directional Shift Registers

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Universal Shift Registers

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Shift Registers : Time Delay

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Shift Registers : Time Delay

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 Digital Logic Circuits
Counters
• Used to count number of clock pulse is applied.
• Frequency divider
• Time/Frequency measurement
• Pulse Width
• Waveform Generator
• With ‘n’ FF, maximum possible stages are 2n.
• Types of counters: (Based on the wav of clock pulse is applied):
a) Asynchronous
b) Synchronous

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Asynchronous

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Synchronous

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Ripple/Asynchronous/Serial Counter

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 Digital Logic Circuits
Ripple/Asynchronous/Serial Counter

• For given modulus value, number of flip flops required:

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Ripple/Asynchronous/Serial Counter

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Ripple/Asynchronous/Serial Counter
2 Bit Negative Edge Triggered UP Counter

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Ripple/Asynchronous/Serial Counter
3 Bit Negative Edge Triggered UP Counter

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Ripple/Asynchronous/Serial Counter
2 Bit Negative Edge Triggered Down Counter

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Ripple/Asynchronous/Serial Counter
3 Bit Negative Edge Triggered Down Counter

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Ripple/Asynchronous/Serial Counter (UP/Down Counter)

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 Digital Logic Circuits
Ripple/Asynchronous/Serial Counter
2 Bit Positive Edge Triggered Up Counter

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Ripple/Asynchronous/Serial Counter
2 Bit Positive Edge Triggered Down Counter

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Ripple/Asynchronous/Serial Counter
2 Bit Positive Edge Triggered UP/Down Counter

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Ripple/Asynchronous/Serial Counter
Mod 6 Counter Design

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Ripple/Asynchronous/Serial Counter
Mod 10 Asynchronous Counter Design

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Synchronous Counter
4 Bit UP Counter Design

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Synchronous Counter
4 Bit Down Counter Design

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Ripple/Asynchronous/Serial Counter
4 Bit UP/Down Counter Design

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Ripple/Asynchronous/Serial Counter

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Sequential circuit analysis

• Behavior of the sequential circuit is determined from the i/ps, o/ps

and present state of the circuit.
• O/ps and next state function of i/ps and the present state.
• Analysis: Obtain proper description of the time sequence of i/ps,
o/ps and states.
– State table or state diagram
– Or Boolean expressions (time sequence must be included
directly or indirectly)

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 Digital Logic Circuits
State Table

Mealy Model circuits: O/p depends on the i/ps as well as the present state

Moore Model circuits: O/p depends on the present state only. One dimensional
state table is enough.
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 Digital Logic Circuits
State Table, Diagram, and Equations

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State Table, Diagram, and Equations

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State Reduction
• Any design process must consider the problem of minimizing
the cost of the final circuit.
• Cost reductions: Reductions in the number of FFs and gates.
• Reduction of number of FFs in sequential circuits: state
reduction (m FFs: 2m states)
• State reduction algorithms concerned with the reduction of
number of states in the state table keeping the external i/p and
o/p requirements unchanged.

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State Reduction

• Only in the i/p and o/p sequences are

important.
• Internal states are used merely to
provide the required sequences and
hence represented by alphabets
instead of binary values (as you will
see in counters).

• Consider the i/p sequence:

01010110100 starting from initial
state ‘a’

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State Reduction

• Two states are

equivalent if for each
i/p, they give exactly
the same o/p and send
the circuit either to the
same state or to an
equivalent state.
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Excitation Table

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Sequential Circuit Design
• Starts with specification and ends with the logic diagram or set of
Boolean functions from which the logic diagram can be obtained.
• A combinational circuit could be fully specified by a truth table.
• A sequential circuit requires a state table or a state diagram.
• The design involves
• Choosing the FF
• Finding a combination circuit which along with the FFs fulfills the
specifications.
• n FFs can represent 2n states.
• Combination circuit derived from the state table by finding- FF i/p
and o/p equations.
• After assignment of states by binary combinations, a sequential
problem translates to combinational problem.

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 Digital Logic Circuits
Sequential Circuit Design
• Specification
• Formulations: State diagram or State table.
• State reduction if sequential circuit characterized by the i/p-o/p relationships
independent of the number of states.
• State Assignment: Assign binary codes to the states in the table.
• Determine the number of FFs needed and assign a letter symbol
• Choose the type of FF. (SR or D for transfer of data, T for applications
involving complementation (binary counters) and JK for general applications.)
• From the state table, derive the circuit excitation and output tables.
• Using the map or any other simplification method, derive the circuit output
functions and FF i/p functions.
• Draw the logic diagram.
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Design with unused states

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Unused States

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State Diagram

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MOD 6 Counter

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MOD 6 Counter

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MOD 6 Counter

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3 Bit UP Counter

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3 Bit UP Counter

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3 Bit Down Counter

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3 Bit Down Counter

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Check for lockout

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Check for lockout

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Check for lockout

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Ring Counter

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Ring Counter

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 Digital Logic Circuits
Ring Counter

• Only one FF is high in a clock pulse

• A n-bit ring counter circulates a single
bit among the FFs to provide n
distinguishable states.
• Output Frequency: fo = f/n
• Number of unused states: 2n-n
• For decoding no logic gate is required.

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 Digital Logic Circuits
Johnson Counter or Twisted Ring Counter

• A n-bit Johnson counter

circulates a single bit
among the FFs to provide
2n distinguishable states.
• For decoding two input
AND/NOR gate is used

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• A switch-tail ring counter is a circular shift register with the complement

output of the last FF connected to the input of the first FF.
• The number of states can be doubled if the shift register is connected as a
switch-tail ring counter.
• Sequence of eight states (4-bit switch-tail Ring counter).
• Total number of unused states: 2n-2n
• Also called as mobies counter, creeping counter, walking counter, and
switch tail counter
• fo = f/2n
• Disadvantage: lock out may occur when counter entered into to unused
states.

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Problems:

1.

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Problems:

1.

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Problems:

2. Draw state diagram of the circuit given below:

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Problems:

2. Draw state diagram of the circuit given below:

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Problems:

3.

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Problems:
4.

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Problems:
4.

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Problems:
5.

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Problems:
6.

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Problems:
7.

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Problems:
8.

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Problems:
8.

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Problems:
9. Assuming initial state as 000, what should be the output for next 4 clocks?

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Number Systems

Depending on the base or radix, number systems can be classified into the
following four major types −

• Decimal
• Binary
• Octal
• Hexadecimal

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Number Systems

Depending on the base or radix, number systems can be classified into the
following four major types −

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Number Systems

Conversion of one number system to other:

• Decimal to others

a) 87 : 1010111

b) 25.625 :

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Number Systems

Conversion of one number system to other:

• Decimal to others

a). (43)10 : ( )16, ( )2

b). (187)10 : ( )2
c) Convert binary 111111110010 to hexadecimal.
d) Convert the binary number 1001.00102 to decimal.

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Number Systems

Conversion of one number system to other:

• Decimal to others

a). (43)10 : ( )16, ( )2 2B, 0100 0011

b). (187)10 : ( )2 10111011

c) Convert binary 111111110010 to hexadecimal. FF2

d) Convert the binary number 1001.00102 to decimal. 9.125

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Number Systems
Conversion of one number system to other:
• Others to decimal

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Number Systems
Conversion of one number system to other:
• Octal to binary and binary to octal

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Number Systems
Conversion of one number system to other:
• Hexadecimal to binary and binary to Hexadecimal

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Arithmetic Operations
• Binary

• Octal

• Hexadecimal

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