Digital Logic Design

(EC 104)

Dr. Vivek Garg

Department of Electronics Engineering
S. V. National Institute of Technology (SVNIT)
Surat

email: vivekg@eced.svnit.ac.in; vivekgarg0101@gmail.com

 Course Outline

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 Course Outline

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 Course Text and Materials

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 Digital Logic Circuits

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 Digital Logic Circuits

NAND Gate SR Latch

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NAND Gate SR Latch

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NOR Gate SR Latch

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Pulse triggering

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Edge triggering

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Setup and Hold time

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Clocked SR Flip Flop

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Problem

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Negative Edge triggered SR Flip Flop

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Internal Circuit of Clocked SR Flip Flop

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Generation of Positive Edge Triggering

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Generation of Negative Edge Triggering

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Clocked RS Flip Flop

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D-Flip Flop

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Jack-Kibly (JK) Flip Flop

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T Flip Flop

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T Flip Flop

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D Flip Flop from JK Flip Flop

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T Flip Flop from JK Flip Flop

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Concept of Frequency Division

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Preset and Clear

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SR Flip Flop

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D Flip Flop

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T Flip Flop

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T Flip Flop from JK Flip Flop

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Example

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Effect of Propagation Delays

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Race Around Condition

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Elimination of Race Around Condition

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Master Slave Arrangement

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Excitation Tables

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Excitation Table

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Steps for converting one flip-flop to the other:

• Consider the characteristic table of desired flip-flop.

• Fill the excitation values inputs of given flip-flop for each combination
of present state and next state.
• Get the simplified expressions for each excitation input. If necessary, use
K-maps for simplifying.
• Draw the circuit diagram of desired flip-flop according to the simplified
expressions using given flip-flop and necessary logic gates.

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SR flip-flop to D flip-flop conversion

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SR to JK flip-flop
• JK to SR flip-flop
• JK to D FF
• JK to T FF
• SR to D FF
• SR to T FF
• SR to JK
• D to SR FF
• D to JK FF
• D to T FF
• T to SR FF
• T to JK FF
• T to D FF
SR to T flip-flop
JK to T flip-flop
JK to SR flip-flop